twl4030.c 66 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  116. };
  117. /* codec private data */
  118. struct twl4030_priv {
  119. unsigned int bypass_state;
  120. unsigned int codec_powered;
  121. unsigned int codec_muted;
  122. struct snd_pcm_substream *master_substream;
  123. struct snd_pcm_substream *slave_substream;
  124. unsigned int configured;
  125. unsigned int rate;
  126. unsigned int sample_bits;
  127. unsigned int channels;
  128. unsigned int sysclk;
  129. /* Headset output state handling */
  130. unsigned int hsl_enabled;
  131. unsigned int hsr_enabled;
  132. };
  133. /*
  134. * read twl4030 register cache
  135. */
  136. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  137. unsigned int reg)
  138. {
  139. if (reg >= TWL4030_CACHEREGNUM)
  140. return -EIO;
  141. return cache[reg];
  142. }
  143. /*
  144. * write twl4030 register cache
  145. */
  146. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  147. u8 reg, u8 value)
  148. {
  149. u8 *cache = codec->reg_cache;
  150. if (reg >= TWL4030_CACHEREGNUM)
  151. return;
  152. cache[reg] = value;
  153. }
  154. /*
  155. * write to the twl4030 register space
  156. */
  157. static int twl4030_write(struct snd_soc_codec *codec,
  158. unsigned int reg, unsigned int value)
  159. {
  160. twl4030_write_reg_cache(codec, reg, value);
  161. if (likely(reg < TWL4030_REG_SW_SHADOW))
  162. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
  163. reg);
  164. else
  165. return 0;
  166. }
  167. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  168. {
  169. struct twl4030_priv *twl4030 = codec->private_data;
  170. u8 mode;
  171. if (enable == twl4030->codec_powered)
  172. return;
  173. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  174. if (enable)
  175. mode |= TWL4030_CODECPDZ;
  176. else
  177. mode &= ~TWL4030_CODECPDZ;
  178. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  179. twl4030->codec_powered = enable;
  180. /* REVISIT: this delay is present in TI sample drivers */
  181. /* but there seems to be no TRM requirement for it */
  182. udelay(10);
  183. }
  184. static void twl4030_init_chip(struct snd_soc_codec *codec)
  185. {
  186. u8 *cache = codec->reg_cache;
  187. int i;
  188. /* clear CODECPDZ prior to setting register defaults */
  189. twl4030_codec_enable(codec, 0);
  190. /* set all audio section registers to reasonable defaults */
  191. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  192. twl4030_write(codec, i, cache[i]);
  193. }
  194. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  195. {
  196. struct twl4030_priv *twl4030 = codec->private_data;
  197. u8 reg_val;
  198. if (mute == twl4030->codec_muted)
  199. return;
  200. if (mute) {
  201. /* Bypass the reg_cache and mute the volumes
  202. * Headset mute is done in it's own event handler
  203. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  204. */
  205. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  206. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  207. reg_val & (~TWL4030_EAR_GAIN),
  208. TWL4030_REG_EAR_CTL);
  209. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  210. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  211. reg_val & (~TWL4030_PREDL_GAIN),
  212. TWL4030_REG_PREDL_CTL);
  213. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  214. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  215. reg_val & (~TWL4030_PREDR_GAIN),
  216. TWL4030_REG_PREDL_CTL);
  217. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  218. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  219. reg_val & (~TWL4030_PRECKL_GAIN),
  220. TWL4030_REG_PRECKL_CTL);
  221. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  222. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  223. reg_val & (~TWL4030_PRECKR_GAIN),
  224. TWL4030_REG_PRECKR_CTL);
  225. /* Disable PLL */
  226. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  227. reg_val &= ~TWL4030_APLL_EN;
  228. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  229. } else {
  230. /* Restore the volumes
  231. * Headset mute is done in it's own event handler
  232. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  233. */
  234. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  235. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  236. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  237. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  238. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  239. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  240. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  241. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  242. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  243. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  244. /* Enable PLL */
  245. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  246. reg_val |= TWL4030_APLL_EN;
  247. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  248. }
  249. twl4030->codec_muted = mute;
  250. }
  251. static void twl4030_power_up(struct snd_soc_codec *codec)
  252. {
  253. struct twl4030_priv *twl4030 = codec->private_data;
  254. u8 anamicl, regmisc1, byte;
  255. int i = 0;
  256. if (twl4030->codec_powered)
  257. return;
  258. /* set CODECPDZ to turn on codec */
  259. twl4030_codec_enable(codec, 1);
  260. /* initiate offset cancellation */
  261. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  262. twl4030_write(codec, TWL4030_REG_ANAMICL,
  263. anamicl | TWL4030_CNCL_OFFSET_START);
  264. /* wait for offset cancellation to complete */
  265. do {
  266. /* this takes a little while, so don't slam i2c */
  267. udelay(2000);
  268. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  269. TWL4030_REG_ANAMICL);
  270. } while ((i++ < 100) &&
  271. ((byte & TWL4030_CNCL_OFFSET_START) ==
  272. TWL4030_CNCL_OFFSET_START));
  273. /* Make sure that the reg_cache has the same value as the HW */
  274. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  275. /* anti-pop when changing analog gain */
  276. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  277. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  278. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  279. /* toggle CODECPDZ as per TRM */
  280. twl4030_codec_enable(codec, 0);
  281. twl4030_codec_enable(codec, 1);
  282. }
  283. /*
  284. * Unconditional power down
  285. */
  286. static void twl4030_power_down(struct snd_soc_codec *codec)
  287. {
  288. /* power down */
  289. twl4030_codec_enable(codec, 0);
  290. }
  291. /* Earpiece */
  292. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  293. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  294. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  295. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  296. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  297. };
  298. /* PreDrive Left */
  299. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  300. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  301. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  302. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  303. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  304. };
  305. /* PreDrive Right */
  306. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  307. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  308. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  309. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  310. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  311. };
  312. /* Headset Left */
  313. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  314. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  315. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  316. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  317. };
  318. /* Headset Right */
  319. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  320. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  321. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  322. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  323. };
  324. /* Carkit Left */
  325. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  326. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  327. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  328. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  329. };
  330. /* Carkit Right */
  331. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  332. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  333. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  334. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  335. };
  336. /* Handsfree Left */
  337. static const char *twl4030_handsfreel_texts[] =
  338. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  339. static const struct soc_enum twl4030_handsfreel_enum =
  340. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  341. ARRAY_SIZE(twl4030_handsfreel_texts),
  342. twl4030_handsfreel_texts);
  343. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  344. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  345. /* Handsfree Left virtual mute */
  346. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  347. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  348. /* Handsfree Right */
  349. static const char *twl4030_handsfreer_texts[] =
  350. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  351. static const struct soc_enum twl4030_handsfreer_enum =
  352. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  353. ARRAY_SIZE(twl4030_handsfreer_texts),
  354. twl4030_handsfreer_texts);
  355. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  356. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  357. /* Handsfree Right virtual mute */
  358. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  359. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  360. /* Vibra */
  361. /* Vibra audio path selection */
  362. static const char *twl4030_vibra_texts[] =
  363. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  364. static const struct soc_enum twl4030_vibra_enum =
  365. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  366. ARRAY_SIZE(twl4030_vibra_texts),
  367. twl4030_vibra_texts);
  368. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  369. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  370. /* Vibra path selection: local vibrator (PWM) or audio driven */
  371. static const char *twl4030_vibrapath_texts[] =
  372. {"Local vibrator", "Audio"};
  373. static const struct soc_enum twl4030_vibrapath_enum =
  374. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  375. ARRAY_SIZE(twl4030_vibrapath_texts),
  376. twl4030_vibrapath_texts);
  377. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  378. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  379. /* Left analog microphone selection */
  380. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  381. SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
  382. SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
  383. SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
  384. SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
  385. };
  386. /* Right analog microphone selection */
  387. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  388. SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
  389. SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
  390. };
  391. /* TX1 L/R Analog/Digital microphone selection */
  392. static const char *twl4030_micpathtx1_texts[] =
  393. {"Analog", "Digimic0"};
  394. static const struct soc_enum twl4030_micpathtx1_enum =
  395. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  396. ARRAY_SIZE(twl4030_micpathtx1_texts),
  397. twl4030_micpathtx1_texts);
  398. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  399. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  400. /* TX2 L/R Analog/Digital microphone selection */
  401. static const char *twl4030_micpathtx2_texts[] =
  402. {"Analog", "Digimic1"};
  403. static const struct soc_enum twl4030_micpathtx2_enum =
  404. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  405. ARRAY_SIZE(twl4030_micpathtx2_texts),
  406. twl4030_micpathtx2_texts);
  407. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  408. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  409. /* Analog bypass for AudioR1 */
  410. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  411. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  412. /* Analog bypass for AudioL1 */
  413. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  414. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  415. /* Analog bypass for AudioR2 */
  416. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  417. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  418. /* Analog bypass for AudioL2 */
  419. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  420. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  421. /* Analog bypass for Voice */
  422. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  423. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  424. /* Digital bypass gain, 0 mutes the bypass */
  425. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  426. TLV_DB_RANGE_HEAD(2),
  427. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  428. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  429. };
  430. /* Digital bypass left (TX1L -> RX2L) */
  431. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  432. SOC_DAPM_SINGLE_TLV("Volume",
  433. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  434. twl4030_dapm_dbypass_tlv);
  435. /* Digital bypass right (TX1R -> RX2R) */
  436. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  437. SOC_DAPM_SINGLE_TLV("Volume",
  438. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  439. twl4030_dapm_dbypass_tlv);
  440. /*
  441. * Voice Sidetone GAIN volume control:
  442. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  443. */
  444. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  445. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  446. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  447. SOC_DAPM_SINGLE_TLV("Volume",
  448. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  449. twl4030_dapm_dbypassv_tlv);
  450. static int micpath_event(struct snd_soc_dapm_widget *w,
  451. struct snd_kcontrol *kcontrol, int event)
  452. {
  453. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  454. unsigned char adcmicsel, micbias_ctl;
  455. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  456. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  457. /* Prepare the bits for the given TX path:
  458. * shift_l == 0: TX1 microphone path
  459. * shift_l == 2: TX2 microphone path */
  460. if (e->shift_l) {
  461. /* TX2 microphone path */
  462. if (adcmicsel & TWL4030_TX2IN_SEL)
  463. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  464. else
  465. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  466. } else {
  467. /* TX1 microphone path */
  468. if (adcmicsel & TWL4030_TX1IN_SEL)
  469. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  470. else
  471. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  472. }
  473. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  474. return 0;
  475. }
  476. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  477. {
  478. unsigned char hs_ctl;
  479. hs_ctl = twl4030_read_reg_cache(codec, reg);
  480. if (ramp) {
  481. /* HF ramp-up */
  482. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  483. twl4030_write(codec, reg, hs_ctl);
  484. udelay(10);
  485. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  486. twl4030_write(codec, reg, hs_ctl);
  487. udelay(40);
  488. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  489. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  490. twl4030_write(codec, reg, hs_ctl);
  491. } else {
  492. /* HF ramp-down */
  493. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  494. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  495. twl4030_write(codec, reg, hs_ctl);
  496. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  497. twl4030_write(codec, reg, hs_ctl);
  498. udelay(40);
  499. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  500. twl4030_write(codec, reg, hs_ctl);
  501. }
  502. }
  503. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  504. struct snd_kcontrol *kcontrol, int event)
  505. {
  506. switch (event) {
  507. case SND_SOC_DAPM_POST_PMU:
  508. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  509. break;
  510. case SND_SOC_DAPM_POST_PMD:
  511. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  512. break;
  513. }
  514. return 0;
  515. }
  516. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  517. struct snd_kcontrol *kcontrol, int event)
  518. {
  519. switch (event) {
  520. case SND_SOC_DAPM_POST_PMU:
  521. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  522. break;
  523. case SND_SOC_DAPM_POST_PMD:
  524. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  525. break;
  526. }
  527. return 0;
  528. }
  529. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  530. {
  531. unsigned char hs_gain, hs_pop;
  532. struct twl4030_priv *twl4030 = codec->private_data;
  533. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  534. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  535. 8388608, 16777216, 33554432, 67108864};
  536. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  537. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  538. if (ramp) {
  539. /* Headset ramp-up according to the TRM */
  540. hs_pop |= TWL4030_VMID_EN;
  541. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  542. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  543. hs_pop |= TWL4030_RAMP_EN;
  544. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  545. } else {
  546. /* Headset ramp-down _not_ according to
  547. * the TRM, but in a way that it is working */
  548. hs_pop &= ~TWL4030_RAMP_EN;
  549. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  550. /* Wait ramp delay time + 1, so the VMID can settle */
  551. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  552. twl4030->sysclk) + 1);
  553. /* Bypass the reg_cache to mute the headset */
  554. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  555. hs_gain & (~0x0f),
  556. TWL4030_REG_HS_GAIN_SET);
  557. hs_pop &= ~TWL4030_VMID_EN;
  558. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  559. }
  560. }
  561. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  562. struct snd_kcontrol *kcontrol, int event)
  563. {
  564. struct twl4030_priv *twl4030 = w->codec->private_data;
  565. switch (event) {
  566. case SND_SOC_DAPM_POST_PMU:
  567. /* Do the ramp-up only once */
  568. if (!twl4030->hsr_enabled)
  569. headset_ramp(w->codec, 1);
  570. twl4030->hsl_enabled = 1;
  571. break;
  572. case SND_SOC_DAPM_POST_PMD:
  573. /* Do the ramp-down only if both headsetL/R is disabled */
  574. if (!twl4030->hsr_enabled)
  575. headset_ramp(w->codec, 0);
  576. twl4030->hsl_enabled = 0;
  577. break;
  578. }
  579. return 0;
  580. }
  581. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  582. struct snd_kcontrol *kcontrol, int event)
  583. {
  584. struct twl4030_priv *twl4030 = w->codec->private_data;
  585. switch (event) {
  586. case SND_SOC_DAPM_POST_PMU:
  587. /* Do the ramp-up only once */
  588. if (!twl4030->hsl_enabled)
  589. headset_ramp(w->codec, 1);
  590. twl4030->hsr_enabled = 1;
  591. break;
  592. case SND_SOC_DAPM_POST_PMD:
  593. /* Do the ramp-down only if both headsetL/R is disabled */
  594. if (!twl4030->hsl_enabled)
  595. headset_ramp(w->codec, 0);
  596. twl4030->hsr_enabled = 0;
  597. break;
  598. }
  599. return 0;
  600. }
  601. static int bypass_event(struct snd_soc_dapm_widget *w,
  602. struct snd_kcontrol *kcontrol, int event)
  603. {
  604. struct soc_mixer_control *m =
  605. (struct soc_mixer_control *)w->kcontrols->private_value;
  606. struct twl4030_priv *twl4030 = w->codec->private_data;
  607. unsigned char reg, misc;
  608. reg = twl4030_read_reg_cache(w->codec, m->reg);
  609. if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  610. /* Analog bypass */
  611. if (reg & (1 << m->shift))
  612. twl4030->bypass_state |=
  613. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  614. else
  615. twl4030->bypass_state &=
  616. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  617. } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
  618. /* Analog voice bypass */
  619. if (reg & (1 << m->shift))
  620. twl4030->bypass_state |= (1 << 4);
  621. else
  622. twl4030->bypass_state &= ~(1 << 4);
  623. } else if (m->reg == TWL4030_REG_VSTPGA) {
  624. /* Voice digital bypass */
  625. if (reg)
  626. twl4030->bypass_state |= (1 << 5);
  627. else
  628. twl4030->bypass_state &= ~(1 << 5);
  629. } else {
  630. /* Digital bypass */
  631. if (reg & (0x7 << m->shift))
  632. twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
  633. else
  634. twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
  635. }
  636. /* Enable master analog loopback mode if any analog switch is enabled*/
  637. misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
  638. if (twl4030->bypass_state & 0x1F)
  639. misc |= TWL4030_FMLOOP_EN;
  640. else
  641. misc &= ~TWL4030_FMLOOP_EN;
  642. twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
  643. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  644. if (twl4030->bypass_state)
  645. twl4030_codec_mute(w->codec, 0);
  646. else
  647. twl4030_codec_mute(w->codec, 1);
  648. }
  649. return 0;
  650. }
  651. /*
  652. * Some of the gain controls in TWL (mostly those which are associated with
  653. * the outputs) are implemented in an interesting way:
  654. * 0x0 : Power down (mute)
  655. * 0x1 : 6dB
  656. * 0x2 : 0 dB
  657. * 0x3 : -6 dB
  658. * Inverting not going to help with these.
  659. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  660. */
  661. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  662. xinvert, tlv_array) \
  663. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  664. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  665. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  666. .tlv.p = (tlv_array), \
  667. .info = snd_soc_info_volsw, \
  668. .get = snd_soc_get_volsw_twl4030, \
  669. .put = snd_soc_put_volsw_twl4030, \
  670. .private_value = (unsigned long)&(struct soc_mixer_control) \
  671. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  672. .max = xmax, .invert = xinvert} }
  673. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  674. xinvert, tlv_array) \
  675. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  676. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  677. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  678. .tlv.p = (tlv_array), \
  679. .info = snd_soc_info_volsw_2r, \
  680. .get = snd_soc_get_volsw_r2_twl4030,\
  681. .put = snd_soc_put_volsw_r2_twl4030, \
  682. .private_value = (unsigned long)&(struct soc_mixer_control) \
  683. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  684. .rshift = xshift, .max = xmax, .invert = xinvert} }
  685. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  686. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  687. xinvert, tlv_array)
  688. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  689. struct snd_ctl_elem_value *ucontrol)
  690. {
  691. struct soc_mixer_control *mc =
  692. (struct soc_mixer_control *)kcontrol->private_value;
  693. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  694. unsigned int reg = mc->reg;
  695. unsigned int shift = mc->shift;
  696. unsigned int rshift = mc->rshift;
  697. int max = mc->max;
  698. int mask = (1 << fls(max)) - 1;
  699. ucontrol->value.integer.value[0] =
  700. (snd_soc_read(codec, reg) >> shift) & mask;
  701. if (ucontrol->value.integer.value[0])
  702. ucontrol->value.integer.value[0] =
  703. max + 1 - ucontrol->value.integer.value[0];
  704. if (shift != rshift) {
  705. ucontrol->value.integer.value[1] =
  706. (snd_soc_read(codec, reg) >> rshift) & mask;
  707. if (ucontrol->value.integer.value[1])
  708. ucontrol->value.integer.value[1] =
  709. max + 1 - ucontrol->value.integer.value[1];
  710. }
  711. return 0;
  712. }
  713. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  714. struct snd_ctl_elem_value *ucontrol)
  715. {
  716. struct soc_mixer_control *mc =
  717. (struct soc_mixer_control *)kcontrol->private_value;
  718. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  719. unsigned int reg = mc->reg;
  720. unsigned int shift = mc->shift;
  721. unsigned int rshift = mc->rshift;
  722. int max = mc->max;
  723. int mask = (1 << fls(max)) - 1;
  724. unsigned short val, val2, val_mask;
  725. val = (ucontrol->value.integer.value[0] & mask);
  726. val_mask = mask << shift;
  727. if (val)
  728. val = max + 1 - val;
  729. val = val << shift;
  730. if (shift != rshift) {
  731. val2 = (ucontrol->value.integer.value[1] & mask);
  732. val_mask |= mask << rshift;
  733. if (val2)
  734. val2 = max + 1 - val2;
  735. val |= val2 << rshift;
  736. }
  737. return snd_soc_update_bits(codec, reg, val_mask, val);
  738. }
  739. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  740. struct snd_ctl_elem_value *ucontrol)
  741. {
  742. struct soc_mixer_control *mc =
  743. (struct soc_mixer_control *)kcontrol->private_value;
  744. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  745. unsigned int reg = mc->reg;
  746. unsigned int reg2 = mc->rreg;
  747. unsigned int shift = mc->shift;
  748. int max = mc->max;
  749. int mask = (1<<fls(max))-1;
  750. ucontrol->value.integer.value[0] =
  751. (snd_soc_read(codec, reg) >> shift) & mask;
  752. ucontrol->value.integer.value[1] =
  753. (snd_soc_read(codec, reg2) >> shift) & mask;
  754. if (ucontrol->value.integer.value[0])
  755. ucontrol->value.integer.value[0] =
  756. max + 1 - ucontrol->value.integer.value[0];
  757. if (ucontrol->value.integer.value[1])
  758. ucontrol->value.integer.value[1] =
  759. max + 1 - ucontrol->value.integer.value[1];
  760. return 0;
  761. }
  762. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  763. struct snd_ctl_elem_value *ucontrol)
  764. {
  765. struct soc_mixer_control *mc =
  766. (struct soc_mixer_control *)kcontrol->private_value;
  767. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  768. unsigned int reg = mc->reg;
  769. unsigned int reg2 = mc->rreg;
  770. unsigned int shift = mc->shift;
  771. int max = mc->max;
  772. int mask = (1 << fls(max)) - 1;
  773. int err;
  774. unsigned short val, val2, val_mask;
  775. val_mask = mask << shift;
  776. val = (ucontrol->value.integer.value[0] & mask);
  777. val2 = (ucontrol->value.integer.value[1] & mask);
  778. if (val)
  779. val = max + 1 - val;
  780. if (val2)
  781. val2 = max + 1 - val2;
  782. val = val << shift;
  783. val2 = val2 << shift;
  784. err = snd_soc_update_bits(codec, reg, val_mask, val);
  785. if (err < 0)
  786. return err;
  787. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  788. return err;
  789. }
  790. /* Codec operation modes */
  791. static const char *twl4030_op_modes_texts[] = {
  792. "Option 2 (voice/audio)", "Option 1 (audio)"
  793. };
  794. static const struct soc_enum twl4030_op_modes_enum =
  795. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  796. ARRAY_SIZE(twl4030_op_modes_texts),
  797. twl4030_op_modes_texts);
  798. int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  799. struct snd_ctl_elem_value *ucontrol)
  800. {
  801. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  802. struct twl4030_priv *twl4030 = codec->private_data;
  803. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  804. unsigned short val;
  805. unsigned short mask, bitmask;
  806. if (twl4030->configured) {
  807. printk(KERN_ERR "twl4030 operation mode cannot be "
  808. "changed on-the-fly\n");
  809. return -EBUSY;
  810. }
  811. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  812. ;
  813. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  814. return -EINVAL;
  815. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  816. mask = (bitmask - 1) << e->shift_l;
  817. if (e->shift_l != e->shift_r) {
  818. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  819. return -EINVAL;
  820. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  821. mask |= (bitmask - 1) << e->shift_r;
  822. }
  823. return snd_soc_update_bits(codec, e->reg, mask, val);
  824. }
  825. /*
  826. * FGAIN volume control:
  827. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  828. */
  829. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  830. /*
  831. * CGAIN volume control:
  832. * 0 dB to 12 dB in 6 dB steps
  833. * value 2 and 3 means 12 dB
  834. */
  835. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  836. /*
  837. * Voice Downlink GAIN volume control:
  838. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  839. */
  840. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  841. /*
  842. * Analog playback gain
  843. * -24 dB to 12 dB in 2 dB steps
  844. */
  845. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  846. /*
  847. * Gain controls tied to outputs
  848. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  849. */
  850. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  851. /*
  852. * Gain control for earpiece amplifier
  853. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  854. */
  855. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  856. /*
  857. * Capture gain after the ADCs
  858. * from 0 dB to 31 dB in 1 dB steps
  859. */
  860. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  861. /*
  862. * Gain control for input amplifiers
  863. * 0 dB to 30 dB in 6 dB steps
  864. */
  865. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  866. static const char *twl4030_rampdelay_texts[] = {
  867. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  868. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  869. "3495/2581/1748 ms"
  870. };
  871. static const struct soc_enum twl4030_rampdelay_enum =
  872. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  873. ARRAY_SIZE(twl4030_rampdelay_texts),
  874. twl4030_rampdelay_texts);
  875. /* Vibra H-bridge direction mode */
  876. static const char *twl4030_vibradirmode_texts[] = {
  877. "Vibra H-bridge direction", "Audio data MSB",
  878. };
  879. static const struct soc_enum twl4030_vibradirmode_enum =
  880. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  881. ARRAY_SIZE(twl4030_vibradirmode_texts),
  882. twl4030_vibradirmode_texts);
  883. /* Vibra H-bridge direction */
  884. static const char *twl4030_vibradir_texts[] = {
  885. "Positive polarity", "Negative polarity",
  886. };
  887. static const struct soc_enum twl4030_vibradir_enum =
  888. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  889. ARRAY_SIZE(twl4030_vibradir_texts),
  890. twl4030_vibradir_texts);
  891. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  892. /* Codec operation mode control */
  893. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  894. snd_soc_get_enum_double,
  895. snd_soc_put_twl4030_opmode_enum_double),
  896. /* Common playback gain controls */
  897. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  898. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  899. 0, 0x3f, 0, digital_fine_tlv),
  900. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  901. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  902. 0, 0x3f, 0, digital_fine_tlv),
  903. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  904. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  905. 6, 0x2, 0, digital_coarse_tlv),
  906. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  907. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  908. 6, 0x2, 0, digital_coarse_tlv),
  909. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  910. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  911. 3, 0x12, 1, analog_tlv),
  912. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  913. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  914. 3, 0x12, 1, analog_tlv),
  915. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  916. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  917. 1, 1, 0),
  918. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  919. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  920. 1, 1, 0),
  921. /* Common voice downlink gain controls */
  922. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  923. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  924. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  925. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  926. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  927. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  928. /* Separate output gain controls */
  929. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  930. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  931. 4, 3, 0, output_tvl),
  932. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  933. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  934. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  935. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  936. 4, 3, 0, output_tvl),
  937. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  938. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  939. /* Common capture gain controls */
  940. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  941. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  942. 0, 0x1f, 0, digital_capture_tlv),
  943. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  944. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  945. 0, 0x1f, 0, digital_capture_tlv),
  946. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  947. 0, 3, 5, 0, input_gain_tlv),
  948. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  949. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  950. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  951. };
  952. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  953. /* Left channel inputs */
  954. SND_SOC_DAPM_INPUT("MAINMIC"),
  955. SND_SOC_DAPM_INPUT("HSMIC"),
  956. SND_SOC_DAPM_INPUT("AUXL"),
  957. SND_SOC_DAPM_INPUT("CARKITMIC"),
  958. /* Right channel inputs */
  959. SND_SOC_DAPM_INPUT("SUBMIC"),
  960. SND_SOC_DAPM_INPUT("AUXR"),
  961. /* Digital microphones (Stereo) */
  962. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  963. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  964. /* Outputs */
  965. SND_SOC_DAPM_OUTPUT("OUTL"),
  966. SND_SOC_DAPM_OUTPUT("OUTR"),
  967. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  968. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  969. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  970. SND_SOC_DAPM_OUTPUT("HSOL"),
  971. SND_SOC_DAPM_OUTPUT("HSOR"),
  972. SND_SOC_DAPM_OUTPUT("CARKITL"),
  973. SND_SOC_DAPM_OUTPUT("CARKITR"),
  974. SND_SOC_DAPM_OUTPUT("HFL"),
  975. SND_SOC_DAPM_OUTPUT("HFR"),
  976. SND_SOC_DAPM_OUTPUT("VIBRA"),
  977. /* DACs */
  978. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  979. SND_SOC_NOPM, 0, 0),
  980. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  981. SND_SOC_NOPM, 0, 0),
  982. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  983. SND_SOC_NOPM, 0, 0),
  984. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  985. SND_SOC_NOPM, 0, 0),
  986. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  987. SND_SOC_NOPM, 0, 0),
  988. /* Analog bypasses */
  989. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  990. &twl4030_dapm_abypassr1_control, bypass_event,
  991. SND_SOC_DAPM_POST_REG),
  992. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  993. &twl4030_dapm_abypassl1_control,
  994. bypass_event, SND_SOC_DAPM_POST_REG),
  995. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  996. &twl4030_dapm_abypassr2_control,
  997. bypass_event, SND_SOC_DAPM_POST_REG),
  998. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  999. &twl4030_dapm_abypassl2_control,
  1000. bypass_event, SND_SOC_DAPM_POST_REG),
  1001. SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1002. &twl4030_dapm_abypassv_control,
  1003. bypass_event, SND_SOC_DAPM_POST_REG),
  1004. /* Digital bypasses */
  1005. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1006. &twl4030_dapm_dbypassl_control, bypass_event,
  1007. SND_SOC_DAPM_POST_REG),
  1008. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1009. &twl4030_dapm_dbypassr_control, bypass_event,
  1010. SND_SOC_DAPM_POST_REG),
  1011. SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1012. &twl4030_dapm_dbypassv_control, bypass_event,
  1013. SND_SOC_DAPM_POST_REG),
  1014. /* Digital mixers, power control for the physical DACs */
  1015. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1016. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1017. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1018. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1019. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1020. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1021. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1022. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1023. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1024. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1025. /* Analog mixers, power control for the physical PGAs */
  1026. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1027. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1028. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1029. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1030. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1031. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1032. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1033. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1034. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1035. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1036. /* Output MIXER controls */
  1037. /* Earpiece */
  1038. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1039. &twl4030_dapm_earpiece_controls[0],
  1040. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1041. /* PreDrivL/R */
  1042. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1043. &twl4030_dapm_predrivel_controls[0],
  1044. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1045. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1046. &twl4030_dapm_predriver_controls[0],
  1047. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1048. /* HeadsetL/R */
  1049. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1050. &twl4030_dapm_hsol_controls[0],
  1051. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1052. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1053. 0, 0, NULL, 0, headsetlpga_event,
  1054. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1055. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1056. &twl4030_dapm_hsor_controls[0],
  1057. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1058. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1059. 0, 0, NULL, 0, headsetrpga_event,
  1060. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1061. /* CarkitL/R */
  1062. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1063. &twl4030_dapm_carkitl_controls[0],
  1064. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1065. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1066. &twl4030_dapm_carkitr_controls[0],
  1067. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1068. /* Output MUX controls */
  1069. /* HandsfreeL/R */
  1070. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1071. &twl4030_dapm_handsfreel_control),
  1072. SND_SOC_DAPM_SWITCH("HandsfreeL Switch", SND_SOC_NOPM, 0, 0,
  1073. &twl4030_dapm_handsfreelmute_control),
  1074. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1075. 0, 0, NULL, 0, handsfreelpga_event,
  1076. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1077. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1078. &twl4030_dapm_handsfreer_control),
  1079. SND_SOC_DAPM_SWITCH("HandsfreeR Switch", SND_SOC_NOPM, 0, 0,
  1080. &twl4030_dapm_handsfreermute_control),
  1081. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1082. 0, 0, NULL, 0, handsfreerpga_event,
  1083. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1084. /* Vibra */
  1085. SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1086. &twl4030_dapm_vibra_control),
  1087. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1088. &twl4030_dapm_vibrapath_control),
  1089. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1090. capture */
  1091. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1092. SND_SOC_NOPM, 0, 0),
  1093. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1094. SND_SOC_NOPM, 0, 0),
  1095. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1096. SND_SOC_NOPM, 0, 0),
  1097. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1098. SND_SOC_NOPM, 0, 0),
  1099. /* Analog/Digital mic path selection.
  1100. TX1 Left/Right: either analog Left/Right or Digimic0
  1101. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1102. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1103. &twl4030_dapm_micpathtx1_control, micpath_event,
  1104. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1105. SND_SOC_DAPM_POST_REG),
  1106. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1107. &twl4030_dapm_micpathtx2_control, micpath_event,
  1108. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1109. SND_SOC_DAPM_POST_REG),
  1110. /* Analog input mixers for the capture amplifiers */
  1111. SND_SOC_DAPM_MIXER("Analog Left Capture Route",
  1112. TWL4030_REG_ANAMICL, 4, 0,
  1113. &twl4030_dapm_analoglmic_controls[0],
  1114. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1115. SND_SOC_DAPM_MIXER("Analog Right Capture Route",
  1116. TWL4030_REG_ANAMICR, 4, 0,
  1117. &twl4030_dapm_analogrmic_controls[0],
  1118. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1119. SND_SOC_DAPM_PGA("ADC Physical Left",
  1120. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1121. SND_SOC_DAPM_PGA("ADC Physical Right",
  1122. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1123. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1124. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1125. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1126. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1127. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1128. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1129. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1130. };
  1131. static const struct snd_soc_dapm_route intercon[] = {
  1132. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1133. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1134. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1135. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1136. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1137. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1138. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1139. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1140. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1141. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1142. /* Internal playback routings */
  1143. /* Earpiece */
  1144. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1145. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1146. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1147. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1148. /* PreDrivL */
  1149. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1150. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1151. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1152. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1153. /* PreDrivR */
  1154. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1155. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1156. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1157. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1158. /* HeadsetL */
  1159. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1160. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1161. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1162. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1163. /* HeadsetR */
  1164. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1165. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1166. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1167. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1168. /* CarkitL */
  1169. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1170. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1171. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1172. /* CarkitR */
  1173. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1174. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1175. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1176. /* HandsfreeL */
  1177. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1178. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1179. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1180. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1181. {"HandsfreeL Switch", "Switch", "HandsfreeL Mux"},
  1182. {"HandsfreeL PGA", NULL, "HandsfreeL Switch"},
  1183. /* HandsfreeR */
  1184. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1185. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1186. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1187. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1188. {"HandsfreeR Switch", "Switch", "HandsfreeR Mux"},
  1189. {"HandsfreeR PGA", NULL, "HandsfreeR Switch"},
  1190. /* Vibra */
  1191. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1192. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1193. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1194. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1195. /* outputs */
  1196. {"OUTL", NULL, "Analog L2 Playback Mixer"},
  1197. {"OUTR", NULL, "Analog R2 Playback Mixer"},
  1198. {"EARPIECE", NULL, "Earpiece Mixer"},
  1199. {"PREDRIVEL", NULL, "PredriveL Mixer"},
  1200. {"PREDRIVER", NULL, "PredriveR Mixer"},
  1201. {"HSOL", NULL, "HeadsetL PGA"},
  1202. {"HSOR", NULL, "HeadsetR PGA"},
  1203. {"CARKITL", NULL, "CarkitL Mixer"},
  1204. {"CARKITR", NULL, "CarkitR Mixer"},
  1205. {"HFL", NULL, "HandsfreeL PGA"},
  1206. {"HFR", NULL, "HandsfreeR PGA"},
  1207. {"Vibra Route", "Audio", "Vibra Mux"},
  1208. {"VIBRA", NULL, "Vibra Route"},
  1209. /* Capture path */
  1210. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  1211. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  1212. {"Analog Left Capture Route", "AUXL", "AUXL"},
  1213. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  1214. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  1215. {"Analog Right Capture Route", "AUXR", "AUXR"},
  1216. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  1217. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  1218. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1219. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1220. /* TX1 Left capture path */
  1221. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1222. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1223. /* TX1 Right capture path */
  1224. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1225. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1226. /* TX2 Left capture path */
  1227. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1228. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1229. /* TX2 Right capture path */
  1230. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1231. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1232. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1233. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1234. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1235. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1236. /* Analog bypass routes */
  1237. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1238. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1239. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1240. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1241. {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
  1242. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1243. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1244. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1245. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1246. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1247. /* Digital bypass routes */
  1248. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1249. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1250. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1251. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1252. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1253. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1254. };
  1255. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1256. {
  1257. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1258. ARRAY_SIZE(twl4030_dapm_widgets));
  1259. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1260. snd_soc_dapm_new_widgets(codec);
  1261. return 0;
  1262. }
  1263. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1264. enum snd_soc_bias_level level)
  1265. {
  1266. struct twl4030_priv *twl4030 = codec->private_data;
  1267. switch (level) {
  1268. case SND_SOC_BIAS_ON:
  1269. twl4030_codec_mute(codec, 0);
  1270. break;
  1271. case SND_SOC_BIAS_PREPARE:
  1272. twl4030_power_up(codec);
  1273. if (twl4030->bypass_state)
  1274. twl4030_codec_mute(codec, 0);
  1275. else
  1276. twl4030_codec_mute(codec, 1);
  1277. break;
  1278. case SND_SOC_BIAS_STANDBY:
  1279. twl4030_power_up(codec);
  1280. if (twl4030->bypass_state)
  1281. twl4030_codec_mute(codec, 0);
  1282. else
  1283. twl4030_codec_mute(codec, 1);
  1284. break;
  1285. case SND_SOC_BIAS_OFF:
  1286. twl4030_power_down(codec);
  1287. break;
  1288. }
  1289. codec->bias_level = level;
  1290. return 0;
  1291. }
  1292. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1293. struct snd_pcm_substream *mst_substream)
  1294. {
  1295. struct snd_pcm_substream *slv_substream;
  1296. /* Pick the stream, which need to be constrained */
  1297. if (mst_substream == twl4030->master_substream)
  1298. slv_substream = twl4030->slave_substream;
  1299. else if (mst_substream == twl4030->slave_substream)
  1300. slv_substream = twl4030->master_substream;
  1301. else /* This should not happen.. */
  1302. return;
  1303. /* Set the constraints according to the already configured stream */
  1304. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1305. SNDRV_PCM_HW_PARAM_RATE,
  1306. twl4030->rate,
  1307. twl4030->rate);
  1308. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1309. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1310. twl4030->sample_bits,
  1311. twl4030->sample_bits);
  1312. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1313. SNDRV_PCM_HW_PARAM_CHANNELS,
  1314. twl4030->channels,
  1315. twl4030->channels);
  1316. }
  1317. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1318. * capture has to be enabled/disabled. */
  1319. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1320. int enable)
  1321. {
  1322. u8 reg, mask;
  1323. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1324. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1325. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1326. else
  1327. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1328. if (enable)
  1329. reg |= mask;
  1330. else
  1331. reg &= ~mask;
  1332. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1333. }
  1334. static int twl4030_startup(struct snd_pcm_substream *substream,
  1335. struct snd_soc_dai *dai)
  1336. {
  1337. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1338. struct snd_soc_device *socdev = rtd->socdev;
  1339. struct snd_soc_codec *codec = socdev->card->codec;
  1340. struct twl4030_priv *twl4030 = codec->private_data;
  1341. if (twl4030->master_substream) {
  1342. twl4030->slave_substream = substream;
  1343. /* The DAI has one configuration for playback and capture, so
  1344. * if the DAI has been already configured then constrain this
  1345. * substream to match it. */
  1346. if (twl4030->configured)
  1347. twl4030_constraints(twl4030, twl4030->master_substream);
  1348. } else {
  1349. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1350. TWL4030_OPTION_1)) {
  1351. /* In option2 4 channel is not supported, set the
  1352. * constraint for the first stream for channels, the
  1353. * second stream will 'inherit' this cosntraint */
  1354. snd_pcm_hw_constraint_minmax(substream->runtime,
  1355. SNDRV_PCM_HW_PARAM_CHANNELS,
  1356. 2, 2);
  1357. }
  1358. twl4030->master_substream = substream;
  1359. }
  1360. return 0;
  1361. }
  1362. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1363. struct snd_soc_dai *dai)
  1364. {
  1365. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1366. struct snd_soc_device *socdev = rtd->socdev;
  1367. struct snd_soc_codec *codec = socdev->card->codec;
  1368. struct twl4030_priv *twl4030 = codec->private_data;
  1369. if (twl4030->master_substream == substream)
  1370. twl4030->master_substream = twl4030->slave_substream;
  1371. twl4030->slave_substream = NULL;
  1372. /* If all streams are closed, or the remaining stream has not yet
  1373. * been configured than set the DAI as not configured. */
  1374. if (!twl4030->master_substream)
  1375. twl4030->configured = 0;
  1376. else if (!twl4030->master_substream->runtime->channels)
  1377. twl4030->configured = 0;
  1378. /* If the closing substream had 4 channel, do the necessary cleanup */
  1379. if (substream->runtime->channels == 4)
  1380. twl4030_tdm_enable(codec, substream->stream, 0);
  1381. }
  1382. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1383. struct snd_pcm_hw_params *params,
  1384. struct snd_soc_dai *dai)
  1385. {
  1386. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1387. struct snd_soc_device *socdev = rtd->socdev;
  1388. struct snd_soc_codec *codec = socdev->card->codec;
  1389. struct twl4030_priv *twl4030 = codec->private_data;
  1390. u8 mode, old_mode, format, old_format;
  1391. /* If the substream has 4 channel, do the necessary setup */
  1392. if (params_channels(params) == 4) {
  1393. /* Safety check: are we in the correct operating mode? */
  1394. if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1395. TWL4030_OPTION_1))
  1396. twl4030_tdm_enable(codec, substream->stream, 1);
  1397. else
  1398. return -EINVAL;
  1399. }
  1400. if (twl4030->configured)
  1401. /* Ignoring hw_params for already configured DAI */
  1402. return 0;
  1403. /* bit rate */
  1404. old_mode = twl4030_read_reg_cache(codec,
  1405. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1406. mode = old_mode & ~TWL4030_APLL_RATE;
  1407. switch (params_rate(params)) {
  1408. case 8000:
  1409. mode |= TWL4030_APLL_RATE_8000;
  1410. break;
  1411. case 11025:
  1412. mode |= TWL4030_APLL_RATE_11025;
  1413. break;
  1414. case 12000:
  1415. mode |= TWL4030_APLL_RATE_12000;
  1416. break;
  1417. case 16000:
  1418. mode |= TWL4030_APLL_RATE_16000;
  1419. break;
  1420. case 22050:
  1421. mode |= TWL4030_APLL_RATE_22050;
  1422. break;
  1423. case 24000:
  1424. mode |= TWL4030_APLL_RATE_24000;
  1425. break;
  1426. case 32000:
  1427. mode |= TWL4030_APLL_RATE_32000;
  1428. break;
  1429. case 44100:
  1430. mode |= TWL4030_APLL_RATE_44100;
  1431. break;
  1432. case 48000:
  1433. mode |= TWL4030_APLL_RATE_48000;
  1434. break;
  1435. case 96000:
  1436. mode |= TWL4030_APLL_RATE_96000;
  1437. break;
  1438. default:
  1439. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1440. params_rate(params));
  1441. return -EINVAL;
  1442. }
  1443. if (mode != old_mode) {
  1444. /* change rate and set CODECPDZ */
  1445. twl4030_codec_enable(codec, 0);
  1446. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1447. twl4030_codec_enable(codec, 1);
  1448. }
  1449. /* sample size */
  1450. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1451. format = old_format;
  1452. format &= ~TWL4030_DATA_WIDTH;
  1453. switch (params_format(params)) {
  1454. case SNDRV_PCM_FORMAT_S16_LE:
  1455. format |= TWL4030_DATA_WIDTH_16S_16W;
  1456. break;
  1457. case SNDRV_PCM_FORMAT_S24_LE:
  1458. format |= TWL4030_DATA_WIDTH_32S_24W;
  1459. break;
  1460. default:
  1461. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1462. params_format(params));
  1463. return -EINVAL;
  1464. }
  1465. if (format != old_format) {
  1466. /* clear CODECPDZ before changing format (codec requirement) */
  1467. twl4030_codec_enable(codec, 0);
  1468. /* change format */
  1469. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1470. /* set CODECPDZ afterwards */
  1471. twl4030_codec_enable(codec, 1);
  1472. }
  1473. /* Store the important parameters for the DAI configuration and set
  1474. * the DAI as configured */
  1475. twl4030->configured = 1;
  1476. twl4030->rate = params_rate(params);
  1477. twl4030->sample_bits = hw_param_interval(params,
  1478. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1479. twl4030->channels = params_channels(params);
  1480. /* If both playback and capture streams are open, and one of them
  1481. * is setting the hw parameters right now (since we are here), set
  1482. * constraints to the other stream to match the current one. */
  1483. if (twl4030->slave_substream)
  1484. twl4030_constraints(twl4030, substream);
  1485. return 0;
  1486. }
  1487. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1488. int clk_id, unsigned int freq, int dir)
  1489. {
  1490. struct snd_soc_codec *codec = codec_dai->codec;
  1491. struct twl4030_priv *twl4030 = codec->private_data;
  1492. u8 infreq;
  1493. switch (freq) {
  1494. case 19200000:
  1495. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1496. twl4030->sysclk = 19200;
  1497. break;
  1498. case 26000000:
  1499. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1500. twl4030->sysclk = 26000;
  1501. break;
  1502. case 38400000:
  1503. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1504. twl4030->sysclk = 38400;
  1505. break;
  1506. default:
  1507. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1508. freq);
  1509. return -EINVAL;
  1510. }
  1511. infreq |= TWL4030_APLL_EN;
  1512. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1513. return 0;
  1514. }
  1515. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1516. unsigned int fmt)
  1517. {
  1518. struct snd_soc_codec *codec = codec_dai->codec;
  1519. u8 old_format, format;
  1520. /* get format */
  1521. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1522. format = old_format;
  1523. /* set master/slave audio interface */
  1524. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1525. case SND_SOC_DAIFMT_CBM_CFM:
  1526. format &= ~(TWL4030_AIF_SLAVE_EN);
  1527. format &= ~(TWL4030_CLK256FS_EN);
  1528. break;
  1529. case SND_SOC_DAIFMT_CBS_CFS:
  1530. format |= TWL4030_AIF_SLAVE_EN;
  1531. format |= TWL4030_CLK256FS_EN;
  1532. break;
  1533. default:
  1534. return -EINVAL;
  1535. }
  1536. /* interface format */
  1537. format &= ~TWL4030_AIF_FORMAT;
  1538. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1539. case SND_SOC_DAIFMT_I2S:
  1540. format |= TWL4030_AIF_FORMAT_CODEC;
  1541. break;
  1542. case SND_SOC_DAIFMT_DSP_A:
  1543. format |= TWL4030_AIF_FORMAT_TDM;
  1544. break;
  1545. default:
  1546. return -EINVAL;
  1547. }
  1548. if (format != old_format) {
  1549. /* clear CODECPDZ before changing format (codec requirement) */
  1550. twl4030_codec_enable(codec, 0);
  1551. /* change format */
  1552. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1553. /* set CODECPDZ afterwards */
  1554. twl4030_codec_enable(codec, 1);
  1555. }
  1556. return 0;
  1557. }
  1558. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1559. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1560. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1561. int enable)
  1562. {
  1563. u8 reg, mask;
  1564. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1565. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1566. mask = TWL4030_ARXL1_VRX_EN;
  1567. else
  1568. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1569. if (enable)
  1570. reg |= mask;
  1571. else
  1572. reg &= ~mask;
  1573. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1574. }
  1575. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1576. struct snd_soc_dai *dai)
  1577. {
  1578. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1579. struct snd_soc_device *socdev = rtd->socdev;
  1580. struct snd_soc_codec *codec = socdev->card->codec;
  1581. u8 infreq;
  1582. u8 mode;
  1583. /* If the system master clock is not 26MHz, the voice PCM interface is
  1584. * not avilable.
  1585. */
  1586. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1587. & TWL4030_APLL_INFREQ;
  1588. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1589. printk(KERN_ERR "TWL4030 voice startup: "
  1590. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1591. return -EINVAL;
  1592. }
  1593. /* If the codec mode is not option2, the voice PCM interface is not
  1594. * avilable.
  1595. */
  1596. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1597. & TWL4030_OPT_MODE;
  1598. if (mode != TWL4030_OPTION_2) {
  1599. printk(KERN_ERR "TWL4030 voice startup: "
  1600. "the codec mode is not option2\n");
  1601. return -EINVAL;
  1602. }
  1603. return 0;
  1604. }
  1605. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1606. struct snd_soc_dai *dai)
  1607. {
  1608. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1609. struct snd_soc_device *socdev = rtd->socdev;
  1610. struct snd_soc_codec *codec = socdev->card->codec;
  1611. /* Enable voice digital filters */
  1612. twl4030_voice_enable(codec, substream->stream, 0);
  1613. }
  1614. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1615. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1616. {
  1617. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1618. struct snd_soc_device *socdev = rtd->socdev;
  1619. struct snd_soc_codec *codec = socdev->card->codec;
  1620. u8 old_mode, mode;
  1621. /* Enable voice digital filters */
  1622. twl4030_voice_enable(codec, substream->stream, 1);
  1623. /* bit rate */
  1624. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1625. & ~(TWL4030_CODECPDZ);
  1626. mode = old_mode;
  1627. switch (params_rate(params)) {
  1628. case 8000:
  1629. mode &= ~(TWL4030_SEL_16K);
  1630. break;
  1631. case 16000:
  1632. mode |= TWL4030_SEL_16K;
  1633. break;
  1634. default:
  1635. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1636. params_rate(params));
  1637. return -EINVAL;
  1638. }
  1639. if (mode != old_mode) {
  1640. /* change rate and set CODECPDZ */
  1641. twl4030_codec_enable(codec, 0);
  1642. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1643. twl4030_codec_enable(codec, 1);
  1644. }
  1645. return 0;
  1646. }
  1647. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1648. int clk_id, unsigned int freq, int dir)
  1649. {
  1650. struct snd_soc_codec *codec = codec_dai->codec;
  1651. u8 infreq;
  1652. switch (freq) {
  1653. case 26000000:
  1654. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1655. break;
  1656. default:
  1657. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1658. freq);
  1659. return -EINVAL;
  1660. }
  1661. infreq |= TWL4030_APLL_EN;
  1662. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1663. return 0;
  1664. }
  1665. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1666. unsigned int fmt)
  1667. {
  1668. struct snd_soc_codec *codec = codec_dai->codec;
  1669. u8 old_format, format;
  1670. /* get format */
  1671. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1672. format = old_format;
  1673. /* set master/slave audio interface */
  1674. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1675. case SND_SOC_DAIFMT_CBS_CFM:
  1676. format &= ~(TWL4030_VIF_SLAVE_EN);
  1677. break;
  1678. case SND_SOC_DAIFMT_CBS_CFS:
  1679. format |= TWL4030_VIF_SLAVE_EN;
  1680. break;
  1681. default:
  1682. return -EINVAL;
  1683. }
  1684. /* clock inversion */
  1685. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1686. case SND_SOC_DAIFMT_IB_NF:
  1687. format &= ~(TWL4030_VIF_FORMAT);
  1688. break;
  1689. case SND_SOC_DAIFMT_NB_IF:
  1690. format |= TWL4030_VIF_FORMAT;
  1691. break;
  1692. default:
  1693. return -EINVAL;
  1694. }
  1695. if (format != old_format) {
  1696. /* change format and set CODECPDZ */
  1697. twl4030_codec_enable(codec, 0);
  1698. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1699. twl4030_codec_enable(codec, 1);
  1700. }
  1701. return 0;
  1702. }
  1703. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1704. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1705. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1706. .startup = twl4030_startup,
  1707. .shutdown = twl4030_shutdown,
  1708. .hw_params = twl4030_hw_params,
  1709. .set_sysclk = twl4030_set_dai_sysclk,
  1710. .set_fmt = twl4030_set_dai_fmt,
  1711. };
  1712. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1713. .startup = twl4030_voice_startup,
  1714. .shutdown = twl4030_voice_shutdown,
  1715. .hw_params = twl4030_voice_hw_params,
  1716. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1717. .set_fmt = twl4030_voice_set_dai_fmt,
  1718. };
  1719. struct snd_soc_dai twl4030_dai[] = {
  1720. {
  1721. .name = "twl4030",
  1722. .playback = {
  1723. .stream_name = "HiFi Playback",
  1724. .channels_min = 2,
  1725. .channels_max = 4,
  1726. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1727. .formats = TWL4030_FORMATS,},
  1728. .capture = {
  1729. .stream_name = "Capture",
  1730. .channels_min = 2,
  1731. .channels_max = 4,
  1732. .rates = TWL4030_RATES,
  1733. .formats = TWL4030_FORMATS,},
  1734. .ops = &twl4030_dai_ops,
  1735. },
  1736. {
  1737. .name = "twl4030 Voice",
  1738. .playback = {
  1739. .stream_name = "Voice Playback",
  1740. .channels_min = 1,
  1741. .channels_max = 1,
  1742. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1743. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1744. .capture = {
  1745. .stream_name = "Capture",
  1746. .channels_min = 1,
  1747. .channels_max = 2,
  1748. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1749. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1750. .ops = &twl4030_dai_voice_ops,
  1751. },
  1752. };
  1753. EXPORT_SYMBOL_GPL(twl4030_dai);
  1754. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1755. {
  1756. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1757. struct snd_soc_codec *codec = socdev->card->codec;
  1758. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1759. return 0;
  1760. }
  1761. static int twl4030_resume(struct platform_device *pdev)
  1762. {
  1763. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1764. struct snd_soc_codec *codec = socdev->card->codec;
  1765. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1766. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1767. return 0;
  1768. }
  1769. /*
  1770. * initialize the driver
  1771. * register the mixer and dsp interfaces with the kernel
  1772. */
  1773. static int twl4030_init(struct snd_soc_device *socdev)
  1774. {
  1775. struct snd_soc_codec *codec = socdev->card->codec;
  1776. struct twl4030_setup_data *setup = socdev->codec_data;
  1777. struct twl4030_priv *twl4030 = codec->private_data;
  1778. int ret = 0;
  1779. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1780. codec->name = "twl4030";
  1781. codec->owner = THIS_MODULE;
  1782. codec->read = twl4030_read_reg_cache;
  1783. codec->write = twl4030_write;
  1784. codec->set_bias_level = twl4030_set_bias_level;
  1785. codec->dai = twl4030_dai;
  1786. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1787. codec->reg_cache_size = sizeof(twl4030_reg);
  1788. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1789. GFP_KERNEL);
  1790. if (codec->reg_cache == NULL)
  1791. return -ENOMEM;
  1792. /* Configuration for headset ramp delay from setup data */
  1793. if (setup) {
  1794. unsigned char hs_pop;
  1795. if (setup->sysclk)
  1796. twl4030->sysclk = setup->sysclk;
  1797. else
  1798. twl4030->sysclk = 26000;
  1799. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  1800. hs_pop &= ~TWL4030_RAMP_DELAY;
  1801. hs_pop |= (setup->ramp_delay_value << 2);
  1802. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  1803. } else {
  1804. twl4030->sysclk = 26000;
  1805. }
  1806. /* register pcms */
  1807. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1808. if (ret < 0) {
  1809. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1810. goto pcm_err;
  1811. }
  1812. twl4030_init_chip(codec);
  1813. /* power on device */
  1814. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1815. snd_soc_add_controls(codec, twl4030_snd_controls,
  1816. ARRAY_SIZE(twl4030_snd_controls));
  1817. twl4030_add_widgets(codec);
  1818. ret = snd_soc_init_card(socdev);
  1819. if (ret < 0) {
  1820. printk(KERN_ERR "twl4030: failed to register card\n");
  1821. goto card_err;
  1822. }
  1823. return ret;
  1824. card_err:
  1825. snd_soc_free_pcms(socdev);
  1826. snd_soc_dapm_free(socdev);
  1827. pcm_err:
  1828. kfree(codec->reg_cache);
  1829. return ret;
  1830. }
  1831. static struct snd_soc_device *twl4030_socdev;
  1832. static int twl4030_probe(struct platform_device *pdev)
  1833. {
  1834. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1835. struct snd_soc_codec *codec;
  1836. struct twl4030_priv *twl4030;
  1837. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1838. if (codec == NULL)
  1839. return -ENOMEM;
  1840. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1841. if (twl4030 == NULL) {
  1842. kfree(codec);
  1843. return -ENOMEM;
  1844. }
  1845. codec->private_data = twl4030;
  1846. socdev->card->codec = codec;
  1847. mutex_init(&codec->mutex);
  1848. INIT_LIST_HEAD(&codec->dapm_widgets);
  1849. INIT_LIST_HEAD(&codec->dapm_paths);
  1850. twl4030_socdev = socdev;
  1851. twl4030_init(socdev);
  1852. return 0;
  1853. }
  1854. static int twl4030_remove(struct platform_device *pdev)
  1855. {
  1856. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1857. struct snd_soc_codec *codec = socdev->card->codec;
  1858. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1859. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1860. snd_soc_free_pcms(socdev);
  1861. snd_soc_dapm_free(socdev);
  1862. kfree(codec->private_data);
  1863. kfree(codec);
  1864. return 0;
  1865. }
  1866. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1867. .probe = twl4030_probe,
  1868. .remove = twl4030_remove,
  1869. .suspend = twl4030_suspend,
  1870. .resume = twl4030_resume,
  1871. };
  1872. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1873. static int __init twl4030_modinit(void)
  1874. {
  1875. return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1876. }
  1877. module_init(twl4030_modinit);
  1878. static void __exit twl4030_exit(void)
  1879. {
  1880. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1881. }
  1882. module_exit(twl4030_exit);
  1883. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1884. MODULE_AUTHOR("Steve Sakoman");
  1885. MODULE_LICENSE("GPL");