patch_ca0132.c 28 KB

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  1. /*
  2. * HD audio interface patch for Creative CA0132 chip
  3. *
  4. * Copyright (c) 2011, Creative Technology Ltd.
  5. *
  6. * Based on patch_ca0110.c
  7. * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
  8. *
  9. * This driver is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This driver is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/slab.h>
  26. #include <linux/pci.h>
  27. #include <linux/mutex.h>
  28. #include <sound/core.h>
  29. #include "hda_codec.h"
  30. #include "hda_local.h"
  31. #define WIDGET_CHIP_CTRL 0x15
  32. #define WIDGET_DSP_CTRL 0x16
  33. #define WUH_MEM_CONNID 10
  34. #define DSP_MEM_CONNID 16
  35. enum hda_cmd_vendor_io {
  36. /* for DspIO node */
  37. VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
  38. VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
  39. VENDOR_DSPIO_STATUS = 0xF01,
  40. VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
  41. VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
  42. VENDOR_DSPIO_DSP_INIT = 0x703,
  43. VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
  44. VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
  45. /* for ChipIO node */
  46. VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
  47. VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
  48. VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
  49. VENDOR_CHIPIO_DATA_LOW = 0x300,
  50. VENDOR_CHIPIO_DATA_HIGH = 0x400,
  51. VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
  52. VENDOR_CHIPIO_STATUS = 0xF01,
  53. VENDOR_CHIPIO_HIC_POST_READ = 0x702,
  54. VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
  55. VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
  56. VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
  57. VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
  58. VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
  59. VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
  60. VENDOR_CHIPIO_FLAG_SET = 0x70F,
  61. VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
  62. VENDOR_CHIPIO_PARAMETER_SET = 0x710,
  63. VENDOR_CHIPIO_PARAMETER_GET = 0xF10,
  64. VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
  65. VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
  66. VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
  67. VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
  68. VENDOR_CHIPIO_PARAMETER_EX_ID_GET = 0xF17,
  69. VENDOR_CHIPIO_PARAMETER_EX_ID_SET = 0x717,
  70. VENDOR_CHIPIO_PARAMETER_EX_VALUE_GET = 0xF18,
  71. VENDOR_CHIPIO_PARAMETER_EX_VALUE_SET = 0x718
  72. };
  73. /*
  74. * Control flag IDs
  75. */
  76. enum control_flag_id {
  77. /* Connection manager stream setup is bypassed/enabled */
  78. CONTROL_FLAG_C_MGR = 0,
  79. /* DSP DMA is bypassed/enabled */
  80. CONTROL_FLAG_DMA = 1,
  81. /* 8051 'idle' mode is disabled/enabled */
  82. CONTROL_FLAG_IDLE_ENABLE = 2,
  83. /* Tracker for the SPDIF-in path is bypassed/enabled */
  84. CONTROL_FLAG_TRACKER = 3,
  85. /* DigitalOut to Spdif2Out connection is disabled/enabled */
  86. CONTROL_FLAG_SPDIF2OUT = 4,
  87. /* Digital Microphone is disabled/enabled */
  88. CONTROL_FLAG_DMIC = 5,
  89. /* ADC_B rate is 48 kHz/96 kHz */
  90. CONTROL_FLAG_ADC_B_96KHZ = 6,
  91. /* ADC_C rate is 48 kHz/96 kHz */
  92. CONTROL_FLAG_ADC_C_96KHZ = 7,
  93. /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
  94. CONTROL_FLAG_DAC_96KHZ = 8,
  95. /* DSP rate is 48 kHz/96 kHz */
  96. CONTROL_FLAG_DSP_96KHZ = 9,
  97. /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
  98. CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
  99. /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
  100. CONTROL_FLAG_SRC_RATE_96KHZ = 11,
  101. /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
  102. CONTROL_FLAG_DECODE_LOOP = 12,
  103. /* De-emphasis filter on DAC-1 disabled/enabled */
  104. CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
  105. /* De-emphasis filter on DAC-2 disabled/enabled */
  106. CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
  107. /* De-emphasis filter on DAC-3 disabled/enabled */
  108. CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
  109. /* High-pass filter on ADC_B disabled/enabled */
  110. CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
  111. /* High-pass filter on ADC_C disabled/enabled */
  112. CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
  113. /* Common mode on Port_A disabled/enabled */
  114. CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
  115. /* Common mode on Port_D disabled/enabled */
  116. CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
  117. /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
  118. CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
  119. /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
  120. CONTROL_FLAG_PORT_D_10K0HM_LOAD = 21,
  121. /* ASI rate is 48kHz/96kHz */
  122. CONTROL_FLAG_ASI_96KHZ = 22,
  123. /* DAC power settings able to control attached ports no/yes */
  124. CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
  125. /* Clock Stop OK reporting is disabled/enabled */
  126. CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
  127. /* Number of control flags */
  128. CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
  129. };
  130. /*
  131. * Control parameter IDs
  132. */
  133. enum control_parameter_id {
  134. /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
  135. CONTROL_PARAM_SPDIF1_SOURCE = 2,
  136. /* Stream Control */
  137. /* Select stream with the given ID */
  138. CONTROL_PARAM_STREAM_ID = 24,
  139. /* Source connection point for the selected stream */
  140. CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
  141. /* Destination connection point for the selected stream */
  142. CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
  143. /* Number of audio channels in the selected stream */
  144. CONTROL_PARAM_STREAMS_CHANNELS = 27,
  145. /*Enable control for the selected stream */
  146. CONTROL_PARAM_STREAM_CONTROL = 28,
  147. /* Connection Point Control */
  148. /* Select connection point with the given ID */
  149. CONTROL_PARAM_CONN_POINT_ID = 29,
  150. /* Connection point sample rate */
  151. CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
  152. /* Node Control */
  153. /* Select HDA node with the given ID */
  154. CONTROL_PARAM_NODE_ID = 31
  155. };
  156. /*
  157. * Dsp Io Status codes
  158. */
  159. enum hda_vendor_status_dspio {
  160. /* Success */
  161. VENDOR_STATUS_DSPIO_OK = 0x00,
  162. /* Busy, unable to accept new command, the host must retry */
  163. VENDOR_STATUS_DSPIO_BUSY = 0x01,
  164. /* SCP command queue is full */
  165. VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
  166. /* SCP response queue is empty */
  167. VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
  168. };
  169. /*
  170. * Chip Io Status codes
  171. */
  172. enum hda_vendor_status_chipio {
  173. /* Success */
  174. VENDOR_STATUS_CHIPIO_OK = 0x00,
  175. /* Busy, unable to accept new command, the host must retry */
  176. VENDOR_STATUS_CHIPIO_BUSY = 0x01
  177. };
  178. /*
  179. * CA0132 sample rate
  180. */
  181. enum ca0132_sample_rate {
  182. SR_6_000 = 0x00,
  183. SR_8_000 = 0x01,
  184. SR_9_600 = 0x02,
  185. SR_11_025 = 0x03,
  186. SR_16_000 = 0x04,
  187. SR_22_050 = 0x05,
  188. SR_24_000 = 0x06,
  189. SR_32_000 = 0x07,
  190. SR_44_100 = 0x08,
  191. SR_48_000 = 0x09,
  192. SR_88_200 = 0x0A,
  193. SR_96_000 = 0x0B,
  194. SR_144_000 = 0x0C,
  195. SR_176_400 = 0x0D,
  196. SR_192_000 = 0x0E,
  197. SR_384_000 = 0x0F,
  198. SR_COUNT = 0x10,
  199. SR_RATE_UNKNOWN = 0x1F
  200. };
  201. /*
  202. * Scp Helper function
  203. */
  204. enum get_set {
  205. IS_SET = 0,
  206. IS_GET = 1,
  207. };
  208. /*
  209. * Duplicated from ca0110 codec
  210. */
  211. static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
  212. {
  213. if (pin) {
  214. snd_hda_codec_write(codec, pin, 0,
  215. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP);
  216. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  217. snd_hda_codec_write(codec, pin, 0,
  218. AC_VERB_SET_AMP_GAIN_MUTE,
  219. AMP_OUT_UNMUTE);
  220. }
  221. if (dac)
  222. snd_hda_codec_write(codec, dac, 0,
  223. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
  224. }
  225. static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
  226. {
  227. if (pin) {
  228. snd_hda_codec_write(codec, pin, 0,
  229. AC_VERB_SET_PIN_WIDGET_CONTROL,
  230. PIN_VREF80);
  231. if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
  232. snd_hda_codec_write(codec, pin, 0,
  233. AC_VERB_SET_AMP_GAIN_MUTE,
  234. AMP_IN_UNMUTE(0));
  235. }
  236. if (adc)
  237. snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  238. AMP_IN_UNMUTE(0));
  239. }
  240. static char *dirstr[2] = { "Playback", "Capture" };
  241. static int _add_switch(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
  242. int chan, int dir)
  243. {
  244. char namestr[44];
  245. int type = dir ? HDA_INPUT : HDA_OUTPUT;
  246. struct snd_kcontrol_new knew =
  247. HDA_CODEC_MUTE_MONO(namestr, nid, chan, 0, type);
  248. sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
  249. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  250. }
  251. static int _add_volume(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
  252. int chan, int dir)
  253. {
  254. char namestr[44];
  255. int type = dir ? HDA_INPUT : HDA_OUTPUT;
  256. struct snd_kcontrol_new knew =
  257. HDA_CODEC_VOLUME_MONO(namestr, nid, chan, 0, type);
  258. sprintf(namestr, "%s %s Volume", pfx, dirstr[dir]);
  259. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  260. }
  261. #define add_out_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 0)
  262. #define add_out_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 0)
  263. #define add_in_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 1)
  264. #define add_in_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 1)
  265. #define add_mono_switch(codec, nid, pfx, chan) \
  266. _add_switch(codec, nid, pfx, chan, 0)
  267. #define add_mono_volume(codec, nid, pfx, chan) \
  268. _add_volume(codec, nid, pfx, chan, 0)
  269. #define add_in_mono_switch(codec, nid, pfx, chan) \
  270. _add_switch(codec, nid, pfx, chan, 1)
  271. #define add_in_mono_volume(codec, nid, pfx, chan) \
  272. _add_volume(codec, nid, pfx, chan, 1)
  273. /*
  274. * CA0132 specific
  275. */
  276. struct ca0132_spec {
  277. struct auto_pin_cfg autocfg;
  278. struct hda_multi_out multiout;
  279. hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
  280. hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
  281. hda_nid_t hp_dac;
  282. hda_nid_t input_pins[AUTO_PIN_LAST];
  283. hda_nid_t adcs[AUTO_PIN_LAST];
  284. hda_nid_t dig_out;
  285. hda_nid_t dig_in;
  286. unsigned int num_inputs;
  287. long curr_hp_switch;
  288. long curr_hp_volume[2];
  289. long curr_speaker_switch;
  290. struct mutex chipio_mutex;
  291. const char *input_labels[AUTO_PIN_LAST];
  292. struct hda_pcm pcm_rec[2]; /* PCM information */
  293. };
  294. /* Chip access helper function */
  295. static int chipio_send(struct hda_codec *codec,
  296. unsigned int reg,
  297. unsigned int data)
  298. {
  299. unsigned int res;
  300. int retry = 50;
  301. /* send bits of data specified by reg */
  302. do {
  303. res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
  304. reg, data);
  305. if (res == VENDOR_STATUS_CHIPIO_OK)
  306. return 0;
  307. } while (--retry);
  308. return -EIO;
  309. }
  310. /*
  311. * Write chip address through the vendor widget -- NOT protected by the Mutex!
  312. */
  313. static int chipio_write_address(struct hda_codec *codec,
  314. unsigned int chip_addx)
  315. {
  316. int res;
  317. /* send low 16 bits of the address */
  318. res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
  319. chip_addx & 0xffff);
  320. if (res != -EIO) {
  321. /* send high 16 bits of the address */
  322. res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
  323. chip_addx >> 16);
  324. }
  325. return res;
  326. }
  327. /*
  328. * Write data through the vendor widget -- NOT protected by the Mutex!
  329. */
  330. static int chipio_write_data(struct hda_codec *codec, unsigned int data)
  331. {
  332. int res;
  333. /* send low 16 bits of the data */
  334. res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
  335. if (res != -EIO) {
  336. /* send high 16 bits of the data */
  337. res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
  338. data >> 16);
  339. }
  340. return res;
  341. }
  342. /*
  343. * Read data through the vendor widget -- NOT protected by the Mutex!
  344. */
  345. static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
  346. {
  347. int res;
  348. /* post read */
  349. res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
  350. if (res != -EIO) {
  351. /* read status */
  352. res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
  353. }
  354. if (res != -EIO) {
  355. /* read data */
  356. *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
  357. VENDOR_CHIPIO_HIC_READ_DATA,
  358. 0);
  359. }
  360. return res;
  361. }
  362. /*
  363. * Write given value to the given address through the chip I/O widget.
  364. * protected by the Mutex
  365. */
  366. static int chipio_write(struct hda_codec *codec,
  367. unsigned int chip_addx, const unsigned int data)
  368. {
  369. struct ca0132_spec *spec = codec->spec;
  370. int err;
  371. mutex_lock(&spec->chipio_mutex);
  372. /* write the address, and if successful proceed to write data */
  373. err = chipio_write_address(codec, chip_addx);
  374. if (err < 0)
  375. goto exit;
  376. err = chipio_write_data(codec, data);
  377. if (err < 0)
  378. goto exit;
  379. exit:
  380. mutex_unlock(&spec->chipio_mutex);
  381. return err;
  382. }
  383. /*
  384. * Read the given address through the chip I/O widget
  385. * protected by the Mutex
  386. */
  387. static int chipio_read(struct hda_codec *codec,
  388. unsigned int chip_addx, unsigned int *data)
  389. {
  390. struct ca0132_spec *spec = codec->spec;
  391. int err;
  392. mutex_lock(&spec->chipio_mutex);
  393. /* write the address, and if successful proceed to write data */
  394. err = chipio_write_address(codec, chip_addx);
  395. if (err < 0)
  396. goto exit;
  397. err = chipio_read_data(codec, data);
  398. if (err < 0)
  399. goto exit;
  400. exit:
  401. mutex_unlock(&spec->chipio_mutex);
  402. return err;
  403. }
  404. /*
  405. * PCM stuffs
  406. */
  407. static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
  408. u32 stream_tag,
  409. int channel_id, int format)
  410. {
  411. unsigned int oldval, newval;
  412. if (!nid)
  413. return;
  414. snd_printdd("ca0132_setup_stream: "
  415. "NID=0x%x, stream=0x%x, channel=%d, format=0x%x\n",
  416. nid, stream_tag, channel_id, format);
  417. /* update the format-id if changed */
  418. oldval = snd_hda_codec_read(codec, nid, 0,
  419. AC_VERB_GET_STREAM_FORMAT,
  420. 0);
  421. if (oldval != format) {
  422. msleep(20);
  423. snd_hda_codec_write(codec, nid, 0,
  424. AC_VERB_SET_STREAM_FORMAT,
  425. format);
  426. }
  427. oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
  428. newval = (stream_tag << 4) | channel_id;
  429. if (oldval != newval) {
  430. snd_hda_codec_write(codec, nid, 0,
  431. AC_VERB_SET_CHANNEL_STREAMID,
  432. newval);
  433. }
  434. }
  435. static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
  436. {
  437. snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
  438. snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  439. }
  440. /*
  441. * PCM callbacks
  442. */
  443. static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  444. struct hda_codec *codec,
  445. unsigned int stream_tag,
  446. unsigned int format,
  447. struct snd_pcm_substream *substream)
  448. {
  449. struct ca0132_spec *spec = codec->spec;
  450. ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
  451. return 0;
  452. }
  453. static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  454. struct hda_codec *codec,
  455. struct snd_pcm_substream *substream)
  456. {
  457. struct ca0132_spec *spec = codec->spec;
  458. ca0132_cleanup_stream(codec, spec->dacs[0]);
  459. return 0;
  460. }
  461. /*
  462. * Digital out
  463. */
  464. static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  465. struct hda_codec *codec,
  466. unsigned int stream_tag,
  467. unsigned int format,
  468. struct snd_pcm_substream *substream)
  469. {
  470. struct ca0132_spec *spec = codec->spec;
  471. ca0132_setup_stream(codec, spec->dig_out, stream_tag, 0, format);
  472. return 0;
  473. }
  474. static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  475. struct hda_codec *codec,
  476. struct snd_pcm_substream *substream)
  477. {
  478. struct ca0132_spec *spec = codec->spec;
  479. ca0132_cleanup_stream(codec, spec->dig_out);
  480. return 0;
  481. }
  482. /*
  483. * Analog capture
  484. */
  485. static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
  486. struct hda_codec *codec,
  487. unsigned int stream_tag,
  488. unsigned int format,
  489. struct snd_pcm_substream *substream)
  490. {
  491. struct ca0132_spec *spec = codec->spec;
  492. ca0132_setup_stream(codec, spec->adcs[substream->number],
  493. stream_tag, 0, format);
  494. return 0;
  495. }
  496. static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
  497. struct hda_codec *codec,
  498. struct snd_pcm_substream *substream)
  499. {
  500. struct ca0132_spec *spec = codec->spec;
  501. ca0132_cleanup_stream(codec, spec->adcs[substream->number]);
  502. return 0;
  503. }
  504. /*
  505. * Digital capture
  506. */
  507. static int ca0132_dig_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
  508. struct hda_codec *codec,
  509. unsigned int stream_tag,
  510. unsigned int format,
  511. struct snd_pcm_substream *substream)
  512. {
  513. struct ca0132_spec *spec = codec->spec;
  514. ca0132_setup_stream(codec, spec->dig_in, stream_tag, 0, format);
  515. return 0;
  516. }
  517. static int ca0132_dig_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
  518. struct hda_codec *codec,
  519. struct snd_pcm_substream *substream)
  520. {
  521. struct ca0132_spec *spec = codec->spec;
  522. ca0132_cleanup_stream(codec, spec->dig_in);
  523. return 0;
  524. }
  525. /*
  526. */
  527. static struct hda_pcm_stream ca0132_pcm_analog_playback = {
  528. .substreams = 1,
  529. .channels_min = 2,
  530. .channels_max = 2,
  531. .ops = {
  532. .prepare = ca0132_playback_pcm_prepare,
  533. .cleanup = ca0132_playback_pcm_cleanup
  534. },
  535. };
  536. static struct hda_pcm_stream ca0132_pcm_analog_capture = {
  537. .substreams = 1,
  538. .channels_min = 2,
  539. .channels_max = 2,
  540. .ops = {
  541. .prepare = ca0132_capture_pcm_prepare,
  542. .cleanup = ca0132_capture_pcm_cleanup
  543. },
  544. };
  545. static struct hda_pcm_stream ca0132_pcm_digital_playback = {
  546. .substreams = 1,
  547. .channels_min = 2,
  548. .channels_max = 2,
  549. .ops = {
  550. .prepare = ca0132_dig_playback_pcm_prepare,
  551. .cleanup = ca0132_dig_playback_pcm_cleanup
  552. },
  553. };
  554. static struct hda_pcm_stream ca0132_pcm_digital_capture = {
  555. .substreams = 1,
  556. .channels_min = 2,
  557. .channels_max = 2,
  558. .ops = {
  559. .prepare = ca0132_dig_capture_pcm_prepare,
  560. .cleanup = ca0132_dig_capture_pcm_cleanup
  561. },
  562. };
  563. static int ca0132_build_pcms(struct hda_codec *codec)
  564. {
  565. struct ca0132_spec *spec = codec->spec;
  566. struct hda_pcm *info = spec->pcm_rec;
  567. codec->pcm_info = info;
  568. codec->num_pcms = 0;
  569. info->name = "CA0132 Analog";
  570. info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
  571. info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
  572. info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
  573. spec->multiout.max_channels;
  574. info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
  575. info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_inputs;
  576. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
  577. codec->num_pcms++;
  578. if (!spec->dig_out && !spec->dig_in)
  579. return 0;
  580. info++;
  581. info->name = "CA0132 Digital";
  582. info->pcm_type = HDA_PCM_TYPE_SPDIF;
  583. if (spec->dig_out) {
  584. info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
  585. ca0132_pcm_digital_playback;
  586. info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
  587. }
  588. if (spec->dig_in) {
  589. info->stream[SNDRV_PCM_STREAM_CAPTURE] =
  590. ca0132_pcm_digital_capture;
  591. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
  592. }
  593. codec->num_pcms++;
  594. return 0;
  595. }
  596. #define REG_CODEC_MUTE 0x18b014
  597. #define REG_CODEC_HP_VOL_L 0x18b070
  598. #define REG_CODEC_HP_VOL_R 0x18b074
  599. static int ca0132_hp_switch_get(struct snd_kcontrol *kcontrol,
  600. struct snd_ctl_elem_value *ucontrol)
  601. {
  602. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  603. struct ca0132_spec *spec = codec->spec;
  604. long *valp = ucontrol->value.integer.value;
  605. *valp = spec->curr_hp_switch;
  606. return 0;
  607. }
  608. static int ca0132_hp_switch_put(struct snd_kcontrol *kcontrol,
  609. struct snd_ctl_elem_value *ucontrol)
  610. {
  611. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  612. struct ca0132_spec *spec = codec->spec;
  613. long *valp = ucontrol->value.integer.value;
  614. unsigned int data;
  615. int err;
  616. /* any change? */
  617. if (spec->curr_hp_switch == *valp)
  618. return 0;
  619. snd_hda_power_up(codec);
  620. err = chipio_read(codec, REG_CODEC_MUTE, &data);
  621. if (err < 0)
  622. return err;
  623. /* *valp 0 is mute, 1 is unmute */
  624. data = (data & 0x7f) | (*valp ? 0 : 0x80);
  625. chipio_write(codec, REG_CODEC_MUTE, data);
  626. if (err < 0)
  627. return err;
  628. spec->curr_hp_switch = *valp;
  629. snd_hda_power_down(codec);
  630. return 1;
  631. }
  632. static int ca0132_speaker_switch_get(struct snd_kcontrol *kcontrol,
  633. struct snd_ctl_elem_value *ucontrol)
  634. {
  635. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  636. struct ca0132_spec *spec = codec->spec;
  637. long *valp = ucontrol->value.integer.value;
  638. *valp = spec->curr_speaker_switch;
  639. return 0;
  640. }
  641. static int ca0132_speaker_switch_put(struct snd_kcontrol *kcontrol,
  642. struct snd_ctl_elem_value *ucontrol)
  643. {
  644. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  645. struct ca0132_spec *spec = codec->spec;
  646. long *valp = ucontrol->value.integer.value;
  647. unsigned int data;
  648. int err;
  649. /* any change? */
  650. if (spec->curr_speaker_switch == *valp)
  651. return 0;
  652. snd_hda_power_up(codec);
  653. err = chipio_read(codec, REG_CODEC_MUTE, &data);
  654. if (err < 0)
  655. return err;
  656. /* *valp 0 is mute, 1 is unmute */
  657. data = (data & 0xef) | (*valp ? 0 : 0x10);
  658. chipio_write(codec, REG_CODEC_MUTE, data);
  659. if (err < 0)
  660. return err;
  661. spec->curr_speaker_switch = *valp;
  662. snd_hda_power_down(codec);
  663. return 1;
  664. }
  665. static int ca0132_hp_volume_get(struct snd_kcontrol *kcontrol,
  666. struct snd_ctl_elem_value *ucontrol)
  667. {
  668. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  669. struct ca0132_spec *spec = codec->spec;
  670. long *valp = ucontrol->value.integer.value;
  671. *valp++ = spec->curr_hp_volume[0];
  672. *valp = spec->curr_hp_volume[1];
  673. return 0;
  674. }
  675. static int ca0132_hp_volume_put(struct snd_kcontrol *kcontrol,
  676. struct snd_ctl_elem_value *ucontrol)
  677. {
  678. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  679. struct ca0132_spec *spec = codec->spec;
  680. long *valp = ucontrol->value.integer.value;
  681. long left_vol, right_vol;
  682. unsigned int data;
  683. int val;
  684. int err;
  685. left_vol = *valp++;
  686. right_vol = *valp;
  687. /* any change? */
  688. if ((spec->curr_hp_volume[0] == left_vol) &&
  689. (spec->curr_hp_volume[1] == right_vol))
  690. return 0;
  691. snd_hda_power_up(codec);
  692. err = chipio_read(codec, REG_CODEC_HP_VOL_L, &data);
  693. if (err < 0)
  694. return err;
  695. val = 31 - left_vol;
  696. data = (data & 0xe0) | val;
  697. chipio_write(codec, REG_CODEC_HP_VOL_L, data);
  698. if (err < 0)
  699. return err;
  700. val = 31 - right_vol;
  701. data = (data & 0xe0) | val;
  702. chipio_write(codec, REG_CODEC_HP_VOL_R, data);
  703. if (err < 0)
  704. return err;
  705. spec->curr_hp_volume[0] = left_vol;
  706. spec->curr_hp_volume[1] = right_vol;
  707. snd_hda_power_down(codec);
  708. return 1;
  709. }
  710. static int add_hp_switch(struct hda_codec *codec, hda_nid_t nid)
  711. {
  712. struct snd_kcontrol_new knew =
  713. HDA_CODEC_MUTE_MONO("Headphone Playback Switch",
  714. nid, 1, 0, HDA_OUTPUT);
  715. knew.get = ca0132_hp_switch_get;
  716. knew.put = ca0132_hp_switch_put;
  717. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  718. }
  719. static int add_hp_volume(struct hda_codec *codec, hda_nid_t nid)
  720. {
  721. struct snd_kcontrol_new knew =
  722. HDA_CODEC_VOLUME_MONO("Headphone Playback Volume",
  723. nid, 3, 0, HDA_OUTPUT);
  724. knew.get = ca0132_hp_volume_get;
  725. knew.put = ca0132_hp_volume_put;
  726. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  727. }
  728. static int add_speaker_switch(struct hda_codec *codec, hda_nid_t nid)
  729. {
  730. struct snd_kcontrol_new knew =
  731. HDA_CODEC_MUTE_MONO("Speaker Playback Switch",
  732. nid, 1, 0, HDA_OUTPUT);
  733. knew.get = ca0132_speaker_switch_get;
  734. knew.put = ca0132_speaker_switch_put;
  735. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  736. }
  737. static void ca0132_fix_hp_caps(struct hda_codec *codec)
  738. {
  739. struct ca0132_spec *spec = codec->spec;
  740. struct auto_pin_cfg *cfg = &spec->autocfg;
  741. unsigned int caps;
  742. /* set mute-capable, 1db step, 32 steps, ofs 6 */
  743. caps = 0x80031f06;
  744. snd_hda_override_amp_caps(codec, cfg->hp_pins[0], HDA_OUTPUT, caps);
  745. }
  746. static int ca0132_build_controls(struct hda_codec *codec)
  747. {
  748. struct ca0132_spec *spec = codec->spec;
  749. struct auto_pin_cfg *cfg = &spec->autocfg;
  750. int i, err;
  751. if (spec->multiout.num_dacs) {
  752. err = add_speaker_switch(codec, spec->out_pins[0]);
  753. if (err < 0)
  754. return err;
  755. }
  756. if (cfg->hp_outs) {
  757. ca0132_fix_hp_caps(codec);
  758. err = add_hp_switch(codec, cfg->hp_pins[0]);
  759. if (err < 0)
  760. return err;
  761. err = add_hp_volume(codec, cfg->hp_pins[0]);
  762. if (err < 0)
  763. return err;
  764. }
  765. for (i = 0; i < spec->num_inputs; i++) {
  766. const char *label = spec->input_labels[i];
  767. err = add_in_switch(codec, spec->adcs[i], label);
  768. if (err < 0)
  769. return err;
  770. err = add_in_volume(codec, spec->adcs[i], label);
  771. if (err < 0)
  772. return err;
  773. if (cfg->inputs[i].type == AUTO_PIN_MIC) {
  774. /* add Mic-Boost */
  775. err = add_in_mono_volume(codec, spec->input_pins[i],
  776. "Mic Boost", 1);
  777. if (err < 0)
  778. return err;
  779. }
  780. }
  781. if (spec->dig_out) {
  782. err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
  783. spec->dig_out);
  784. if (err < 0)
  785. return err;
  786. err = add_out_volume(codec, spec->dig_out, "IEC958");
  787. if (err < 0)
  788. return err;
  789. }
  790. if (spec->dig_in) {
  791. err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
  792. if (err < 0)
  793. return err;
  794. err = add_in_volume(codec, spec->dig_in, "IEC958");
  795. }
  796. return 0;
  797. }
  798. static void ca0132_set_ct_ext(struct hda_codec *codec, int enable)
  799. {
  800. /* Set Creative extension */
  801. snd_printdd("SET CREATIVE EXTENSION\n");
  802. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  803. VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE,
  804. enable);
  805. msleep(20);
  806. }
  807. static void ca0132_config(struct hda_codec *codec)
  808. {
  809. struct ca0132_spec *spec = codec->spec;
  810. struct auto_pin_cfg *cfg = &spec->autocfg;
  811. /* line-outs */
  812. cfg->line_outs = 1;
  813. cfg->line_out_pins[0] = 0x0b; /* front */
  814. cfg->line_out_type = AUTO_PIN_LINE_OUT;
  815. spec->dacs[0] = 0x02;
  816. spec->out_pins[0] = 0x0b;
  817. spec->multiout.dac_nids = spec->dacs;
  818. spec->multiout.num_dacs = 1;
  819. spec->multiout.max_channels = 2;
  820. /* headphone */
  821. cfg->hp_outs = 1;
  822. cfg->hp_pins[0] = 0x0f;
  823. spec->hp_dac = 0;
  824. spec->multiout.hp_nid = 0;
  825. /* inputs */
  826. cfg->num_inputs = 2; /* Mic-in and line-in */
  827. cfg->inputs[0].pin = 0x12;
  828. cfg->inputs[0].type = AUTO_PIN_MIC;
  829. cfg->inputs[1].pin = 0x11;
  830. cfg->inputs[1].type = AUTO_PIN_LINE_IN;
  831. /* Mic-in */
  832. spec->input_pins[0] = 0x12;
  833. spec->input_labels[0] = "Mic-In";
  834. spec->adcs[0] = 0x07;
  835. /* Line-In */
  836. spec->input_pins[1] = 0x11;
  837. spec->input_labels[1] = "Line-In";
  838. spec->adcs[1] = 0x08;
  839. spec->num_inputs = 2;
  840. }
  841. static void ca0132_init_chip(struct hda_codec *codec)
  842. {
  843. struct ca0132_spec *spec = codec->spec;
  844. mutex_init(&spec->chipio_mutex);
  845. }
  846. static void ca0132_exit_chip(struct hda_codec *codec)
  847. {
  848. /* put any chip cleanup stuffs here. */
  849. }
  850. static int ca0132_init(struct hda_codec *codec)
  851. {
  852. struct ca0132_spec *spec = codec->spec;
  853. struct auto_pin_cfg *cfg = &spec->autocfg;
  854. int i;
  855. for (i = 0; i < spec->multiout.num_dacs; i++) {
  856. init_output(codec, spec->out_pins[i],
  857. spec->multiout.dac_nids[i]);
  858. }
  859. init_output(codec, cfg->hp_pins[0], spec->hp_dac);
  860. init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
  861. for (i = 0; i < spec->num_inputs; i++)
  862. init_input(codec, spec->input_pins[i], spec->adcs[i]);
  863. init_input(codec, cfg->dig_in_pin, spec->dig_in);
  864. ca0132_set_ct_ext(codec, 1);
  865. return 0;
  866. }
  867. static void ca0132_free(struct hda_codec *codec)
  868. {
  869. ca0132_set_ct_ext(codec, 0);
  870. ca0132_exit_chip(codec);
  871. kfree(codec->spec);
  872. }
  873. static struct hda_codec_ops ca0132_patch_ops = {
  874. .build_controls = ca0132_build_controls,
  875. .build_pcms = ca0132_build_pcms,
  876. .init = ca0132_init,
  877. .free = ca0132_free,
  878. };
  879. static int patch_ca0132(struct hda_codec *codec)
  880. {
  881. struct ca0132_spec *spec;
  882. snd_printdd("patch_ca0132\n");
  883. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  884. if (!spec)
  885. return -ENOMEM;
  886. codec->spec = spec;
  887. ca0132_init_chip(codec);
  888. ca0132_config(codec);
  889. codec->patch_ops = ca0132_patch_ops;
  890. return 0;
  891. }
  892. /*
  893. * patch entries
  894. */
  895. static struct hda_codec_preset snd_hda_preset_ca0132[] = {
  896. { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
  897. {} /* terminator */
  898. };
  899. MODULE_ALIAS("snd-hda-codec-id:11020011");
  900. MODULE_LICENSE("GPL");
  901. MODULE_DESCRIPTION("Creative CA0132, CA0132 HD-audio codec");
  902. static struct hda_codec_preset_list ca0132_list = {
  903. .preset = snd_hda_preset_ca0132,
  904. .owner = THIS_MODULE,
  905. };
  906. static int __init patch_ca0132_init(void)
  907. {
  908. return snd_hda_add_codec_preset(&ca0132_list);
  909. }
  910. static void __exit patch_ca0132_exit(void)
  911. {
  912. snd_hda_delete_codec_preset(&ca0132_list);
  913. }
  914. module_init(patch_ca0132_init)
  915. module_exit(patch_ca0132_exit)