langwell_otg.c 59 KB

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  1. /*
  2. * Intel Langwell USB OTG transceiver driver
  3. * Copyright (C) 2008 - 2010, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. /* This driver helps to switch Langwell OTG controller function between host
  20. * and peripheral. It works with EHCI driver and Langwell client controller
  21. * driver together.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/pci.h>
  26. #include <linux/errno.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/kernel.h>
  29. #include <linux/device.h>
  30. #include <linux/moduleparam.h>
  31. #include <linux/usb/ch9.h>
  32. #include <linux/usb/gadget.h>
  33. #include <linux/usb.h>
  34. #include <linux/usb/otg.h>
  35. #include <linux/usb/hcd.h>
  36. #include <linux/notifier.h>
  37. #include <linux/delay.h>
  38. #include <asm/intel_scu_ipc.h>
  39. #include <linux/usb/langwell_otg.h>
  40. #define DRIVER_DESC "Intel Langwell USB OTG transceiver driver"
  41. #define DRIVER_VERSION "July 10, 2010"
  42. MODULE_DESCRIPTION(DRIVER_DESC);
  43. MODULE_AUTHOR("Henry Yuan <hang.yuan@intel.com>, Hao Wu <hao.wu@intel.com>");
  44. MODULE_VERSION(DRIVER_VERSION);
  45. MODULE_LICENSE("GPL");
  46. static const char driver_name[] = "langwell_otg";
  47. static int langwell_otg_probe(struct pci_dev *pdev,
  48. const struct pci_device_id *id);
  49. static void langwell_otg_remove(struct pci_dev *pdev);
  50. static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message);
  51. static int langwell_otg_resume(struct pci_dev *pdev);
  52. static int langwell_otg_set_host(struct otg_transceiver *otg,
  53. struct usb_bus *host);
  54. static int langwell_otg_set_peripheral(struct otg_transceiver *otg,
  55. struct usb_gadget *gadget);
  56. static int langwell_otg_start_srp(struct otg_transceiver *otg);
  57. static const struct pci_device_id pci_ids[] = {{
  58. .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
  59. .class_mask = ~0,
  60. .vendor = 0x8086,
  61. .device = 0x0811,
  62. .subvendor = PCI_ANY_ID,
  63. .subdevice = PCI_ANY_ID,
  64. }, { /* end: all zeroes */ }
  65. };
  66. static struct pci_driver otg_pci_driver = {
  67. .name = (char *) driver_name,
  68. .id_table = pci_ids,
  69. .probe = langwell_otg_probe,
  70. .remove = langwell_otg_remove,
  71. .suspend = langwell_otg_suspend,
  72. .resume = langwell_otg_resume,
  73. };
  74. /* HSM timers */
  75. static inline struct langwell_otg_timer *otg_timer_initializer
  76. (void (*function)(unsigned long), unsigned long expires, unsigned long data)
  77. {
  78. struct langwell_otg_timer *timer;
  79. timer = kmalloc(sizeof(struct langwell_otg_timer), GFP_KERNEL);
  80. if (timer == NULL)
  81. return timer;
  82. timer->function = function;
  83. timer->expires = expires;
  84. timer->data = data;
  85. return timer;
  86. }
  87. static struct langwell_otg_timer *a_wait_vrise_tmr, *a_aidl_bdis_tmr,
  88. *b_se0_srp_tmr, *b_srp_init_tmr;
  89. static struct list_head active_timers;
  90. static struct langwell_otg *the_transceiver;
  91. /* host/client notify transceiver when event affects HNP state */
  92. void langwell_update_transceiver(void)
  93. {
  94. struct langwell_otg *lnw = the_transceiver;
  95. dev_dbg(lnw->dev, "transceiver is updated\n");
  96. if (!lnw->qwork)
  97. return ;
  98. queue_work(lnw->qwork, &lnw->work);
  99. }
  100. EXPORT_SYMBOL(langwell_update_transceiver);
  101. static int langwell_otg_set_host(struct otg_transceiver *otg,
  102. struct usb_bus *host)
  103. {
  104. otg->host = host;
  105. return 0;
  106. }
  107. static int langwell_otg_set_peripheral(struct otg_transceiver *otg,
  108. struct usb_gadget *gadget)
  109. {
  110. otg->gadget = gadget;
  111. return 0;
  112. }
  113. static int langwell_otg_set_power(struct otg_transceiver *otg,
  114. unsigned mA)
  115. {
  116. return 0;
  117. }
  118. /* A-device drives vbus, controlled through IPC commands */
  119. static int langwell_otg_set_vbus(struct otg_transceiver *otg, bool enabled)
  120. {
  121. struct langwell_otg *lnw = the_transceiver;
  122. u8 sub_id;
  123. dev_dbg(lnw->dev, "%s <--- %s\n", __func__, enabled ? "on" : "off");
  124. if (enabled)
  125. sub_id = 0x8; /* Turn on the VBus */
  126. else
  127. sub_id = 0x9; /* Turn off the VBus */
  128. if (intel_scu_ipc_simple_command(0xef, sub_id)) {
  129. dev_dbg(lnw->dev, "Failed to set Vbus via IPC commands\n");
  130. return -EBUSY;
  131. }
  132. dev_dbg(lnw->dev, "%s --->\n", __func__);
  133. return 0;
  134. }
  135. /* charge vbus or discharge vbus through a resistor to ground */
  136. static void langwell_otg_chrg_vbus(int on)
  137. {
  138. struct langwell_otg *lnw = the_transceiver;
  139. u32 val;
  140. val = readl(lnw->iotg.base + CI_OTGSC);
  141. if (on)
  142. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VC,
  143. lnw->iotg.base + CI_OTGSC);
  144. else
  145. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VD,
  146. lnw->iotg.base + CI_OTGSC);
  147. }
  148. /* Start SRP */
  149. static int langwell_otg_start_srp(struct otg_transceiver *otg)
  150. {
  151. struct langwell_otg *lnw = the_transceiver;
  152. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  153. u32 val;
  154. dev_dbg(lnw->dev, "%s --->\n", __func__);
  155. val = readl(iotg->base + CI_OTGSC);
  156. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HADP,
  157. iotg->base + CI_OTGSC);
  158. /* Check if the data plus is finished or not */
  159. msleep(8);
  160. val = readl(iotg->base + CI_OTGSC);
  161. if (val & (OTGSC_HADP | OTGSC_DP))
  162. dev_dbg(lnw->dev, "DataLine SRP Error\n");
  163. /* Disable interrupt - b_sess_vld */
  164. val = readl(iotg->base + CI_OTGSC);
  165. val &= (~(OTGSC_BSVIE | OTGSC_BSEIE));
  166. writel(val, iotg->base + CI_OTGSC);
  167. /* Start VBus SRP, drive vbus to generate VBus pulse */
  168. iotg->otg.set_vbus(&iotg->otg, true);
  169. msleep(15);
  170. iotg->otg.set_vbus(&iotg->otg, false);
  171. /* Enable interrupt - b_sess_vld*/
  172. val = readl(iotg->base + CI_OTGSC);
  173. dev_dbg(lnw->dev, "after VBUS pulse otgsc = %x\n", val);
  174. val |= (OTGSC_BSVIE | OTGSC_BSEIE);
  175. writel(val, iotg->base + CI_OTGSC);
  176. /* If Vbus is valid, then update the hsm */
  177. if (val & OTGSC_BSV) {
  178. dev_dbg(lnw->dev, "no b_sess_vld interrupt\n");
  179. lnw->iotg.hsm.b_sess_vld = 1;
  180. langwell_update_transceiver();
  181. }
  182. dev_dbg(lnw->dev, "%s <---\n", __func__);
  183. return 0;
  184. }
  185. /* stop SOF via bus_suspend */
  186. static void langwell_otg_loc_sof(int on)
  187. {
  188. struct langwell_otg *lnw = the_transceiver;
  189. struct usb_hcd *hcd;
  190. int err;
  191. dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "suspend" : "resume");
  192. hcd = bus_to_hcd(lnw->iotg.otg.host);
  193. if (on)
  194. err = hcd->driver->bus_resume(hcd);
  195. else
  196. err = hcd->driver->bus_suspend(hcd);
  197. if (err)
  198. dev_dbg(lnw->dev, "Fail to resume/suspend USB bus - %d\n", err);
  199. dev_dbg(lnw->dev, "%s <---\n", __func__);
  200. }
  201. static int langwell_otg_check_otgsc(void)
  202. {
  203. struct langwell_otg *lnw = the_transceiver;
  204. u32 otgsc, usbcfg;
  205. dev_dbg(lnw->dev, "check sync OTGSC and USBCFG registers\n");
  206. otgsc = readl(lnw->iotg.base + CI_OTGSC);
  207. usbcfg = readl(lnw->usbcfg);
  208. dev_dbg(lnw->dev, "OTGSC = %08x, USBCFG = %08x\n",
  209. otgsc, usbcfg);
  210. dev_dbg(lnw->dev, "OTGSC_AVV = %d\n", !!(otgsc & OTGSC_AVV));
  211. dev_dbg(lnw->dev, "USBCFG.VBUSVAL = %d\n",
  212. !!(usbcfg & USBCFG_VBUSVAL));
  213. dev_dbg(lnw->dev, "OTGSC_ASV = %d\n", !!(otgsc & OTGSC_ASV));
  214. dev_dbg(lnw->dev, "USBCFG.AVALID = %d\n",
  215. !!(usbcfg & USBCFG_AVALID));
  216. dev_dbg(lnw->dev, "OTGSC_BSV = %d\n", !!(otgsc & OTGSC_BSV));
  217. dev_dbg(lnw->dev, "USBCFG.BVALID = %d\n",
  218. !!(usbcfg & USBCFG_BVALID));
  219. dev_dbg(lnw->dev, "OTGSC_BSE = %d\n", !!(otgsc & OTGSC_BSE));
  220. dev_dbg(lnw->dev, "USBCFG.SESEND = %d\n",
  221. !!(usbcfg & USBCFG_SESEND));
  222. /* Check USBCFG VBusValid/AValid/BValid/SessEnd */
  223. if (!!(otgsc & OTGSC_AVV) ^ !!(usbcfg & USBCFG_VBUSVAL)) {
  224. dev_dbg(lnw->dev, "OTGSC.AVV != USBCFG.VBUSVAL\n");
  225. goto err;
  226. }
  227. if (!!(otgsc & OTGSC_ASV) ^ !!(usbcfg & USBCFG_AVALID)) {
  228. dev_dbg(lnw->dev, "OTGSC.ASV != USBCFG.AVALID\n");
  229. goto err;
  230. }
  231. if (!!(otgsc & OTGSC_BSV) ^ !!(usbcfg & USBCFG_BVALID)) {
  232. dev_dbg(lnw->dev, "OTGSC.BSV != USBCFG.BVALID\n");
  233. goto err;
  234. }
  235. if (!!(otgsc & OTGSC_BSE) ^ !!(usbcfg & USBCFG_SESEND)) {
  236. dev_dbg(lnw->dev, "OTGSC.BSE != USBCFG.SESSEN\n");
  237. goto err;
  238. }
  239. dev_dbg(lnw->dev, "OTGSC and USBCFG are synced\n");
  240. return 0;
  241. err:
  242. dev_warn(lnw->dev, "OTGSC isn't equal to USBCFG\n");
  243. return -EPIPE;
  244. }
  245. static void langwell_otg_phy_low_power(int on)
  246. {
  247. struct langwell_otg *lnw = the_transceiver;
  248. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  249. u8 val, phcd;
  250. int retval;
  251. dev_dbg(lnw->dev, "%s ---> %s mode\n",
  252. __func__, on ? "Low power" : "Normal");
  253. phcd = 0x40;
  254. val = readb(iotg->base + CI_HOSTPC1 + 2);
  255. if (on) {
  256. /* Due to hardware issue, after set PHCD, sync will failed
  257. * between USBCFG and OTGSC, so before set PHCD, check if
  258. * sync is in process now. If the answer is "yes", then do
  259. * not touch PHCD bit */
  260. retval = langwell_otg_check_otgsc();
  261. if (retval) {
  262. dev_dbg(lnw->dev, "Skip PHCD programming..\n");
  263. return ;
  264. }
  265. writeb(val | phcd, iotg->base + CI_HOSTPC1 + 2);
  266. } else
  267. writeb(val & ~phcd, iotg->base + CI_HOSTPC1 + 2);
  268. dev_dbg(lnw->dev, "%s <--- done\n", __func__);
  269. }
  270. /* After drv vbus, add 5 ms delay to set PHCD */
  271. static void langwell_otg_phy_low_power_wait(int on)
  272. {
  273. struct langwell_otg *lnw = the_transceiver;
  274. dev_dbg(lnw->dev, "add 5ms delay before programing PHCD\n");
  275. mdelay(5);
  276. langwell_otg_phy_low_power(on);
  277. }
  278. /* Enable/Disable OTG interrupt */
  279. static void langwell_otg_intr(int on)
  280. {
  281. struct langwell_otg *lnw = the_transceiver;
  282. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  283. u32 val;
  284. dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off");
  285. val = readl(iotg->base + CI_OTGSC);
  286. /* OTGSC_INT_MASK doesn't contains 1msInt */
  287. if (on) {
  288. val = val | (OTGSC_INT_MASK);
  289. writel(val, iotg->base + CI_OTGSC);
  290. } else {
  291. val = val & ~(OTGSC_INT_MASK);
  292. writel(val, iotg->base + CI_OTGSC);
  293. }
  294. dev_dbg(lnw->dev, "%s <---\n", __func__);
  295. }
  296. /* set HAAR: Hardware Assist Auto-Reset */
  297. static void langwell_otg_HAAR(int on)
  298. {
  299. struct langwell_otg *lnw = the_transceiver;
  300. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  301. u32 val;
  302. dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off");
  303. val = readl(iotg->base + CI_OTGSC);
  304. if (on)
  305. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HAAR,
  306. iotg->base + CI_OTGSC);
  307. else
  308. writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HAAR,
  309. iotg->base + CI_OTGSC);
  310. dev_dbg(lnw->dev, "%s <---\n", __func__);
  311. }
  312. /* set HABA: Hardware Assist B-Disconnect to A-Connect */
  313. static void langwell_otg_HABA(int on)
  314. {
  315. struct langwell_otg *lnw = the_transceiver;
  316. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  317. u32 val;
  318. dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off");
  319. val = readl(iotg->base + CI_OTGSC);
  320. if (on)
  321. writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HABA,
  322. iotg->base + CI_OTGSC);
  323. else
  324. writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HABA,
  325. iotg->base + CI_OTGSC);
  326. dev_dbg(lnw->dev, "%s <---\n", __func__);
  327. }
  328. static int langwell_otg_check_se0_srp(int on)
  329. {
  330. struct langwell_otg *lnw = the_transceiver;
  331. int delay_time = TB_SE0_SRP * 10;
  332. u32 val;
  333. dev_dbg(lnw->dev, "%s --->\n", __func__);
  334. do {
  335. udelay(100);
  336. if (!delay_time--)
  337. break;
  338. val = readl(lnw->iotg.base + CI_PORTSC1);
  339. val &= PORTSC_LS;
  340. } while (!val);
  341. dev_dbg(lnw->dev, "%s <---\n", __func__);
  342. return val;
  343. }
  344. /* The timeout callback function to set time out bit */
  345. static void set_tmout(unsigned long indicator)
  346. {
  347. *(int *)indicator = 1;
  348. }
  349. void langwell_otg_nsf_msg(unsigned long indicator)
  350. {
  351. struct langwell_otg *lnw = the_transceiver;
  352. switch (indicator) {
  353. case 2:
  354. case 4:
  355. case 6:
  356. case 7:
  357. dev_warn(lnw->dev,
  358. "OTG:NSF-%lu - deivce not responding\n", indicator);
  359. break;
  360. case 3:
  361. dev_warn(lnw->dev,
  362. "OTG:NSF-%lu - deivce not supported\n", indicator);
  363. break;
  364. default:
  365. dev_warn(lnw->dev, "Do not have this kind of NSF\n");
  366. break;
  367. }
  368. }
  369. /* Initialize timers */
  370. static int langwell_otg_init_timers(struct otg_hsm *hsm)
  371. {
  372. /* HSM used timers */
  373. a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
  374. (unsigned long)&hsm->a_wait_vrise_tmout);
  375. if (a_wait_vrise_tmr == NULL)
  376. return -ENOMEM;
  377. a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
  378. (unsigned long)&hsm->a_aidl_bdis_tmout);
  379. if (a_aidl_bdis_tmr == NULL)
  380. return -ENOMEM;
  381. b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
  382. (unsigned long)&hsm->b_se0_srp);
  383. if (b_se0_srp_tmr == NULL)
  384. return -ENOMEM;
  385. b_srp_init_tmr = otg_timer_initializer(&set_tmout, TB_SRP_INIT,
  386. (unsigned long)&hsm->b_srp_init_tmout);
  387. if (b_srp_init_tmr == NULL)
  388. return -ENOMEM;
  389. return 0;
  390. }
  391. /* Free timers */
  392. static void langwell_otg_free_timers(void)
  393. {
  394. kfree(a_wait_vrise_tmr);
  395. kfree(a_aidl_bdis_tmr);
  396. kfree(b_se0_srp_tmr);
  397. kfree(b_srp_init_tmr);
  398. }
  399. /* The timeout callback function to set time out bit */
  400. static void langwell_otg_timer_fn(unsigned long indicator)
  401. {
  402. struct langwell_otg *lnw = the_transceiver;
  403. *(int *)indicator = 1;
  404. dev_dbg(lnw->dev, "kernel timer - timeout\n");
  405. langwell_update_transceiver();
  406. }
  407. /* kernel timer used instead of HW based interrupt */
  408. static void langwell_otg_add_ktimer(enum langwell_otg_timer_type timers)
  409. {
  410. struct langwell_otg *lnw = the_transceiver;
  411. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  412. unsigned long j = jiffies;
  413. unsigned long data, time;
  414. switch (timers) {
  415. case TA_WAIT_VRISE_TMR:
  416. iotg->hsm.a_wait_vrise_tmout = 0;
  417. data = (unsigned long)&iotg->hsm.a_wait_vrise_tmout;
  418. time = TA_WAIT_VRISE;
  419. break;
  420. case TA_WAIT_BCON_TMR:
  421. iotg->hsm.a_wait_bcon_tmout = 0;
  422. data = (unsigned long)&iotg->hsm.a_wait_bcon_tmout;
  423. time = TA_WAIT_BCON;
  424. break;
  425. case TA_AIDL_BDIS_TMR:
  426. iotg->hsm.a_aidl_bdis_tmout = 0;
  427. data = (unsigned long)&iotg->hsm.a_aidl_bdis_tmout;
  428. time = TA_AIDL_BDIS;
  429. break;
  430. case TB_ASE0_BRST_TMR:
  431. iotg->hsm.b_ase0_brst_tmout = 0;
  432. data = (unsigned long)&iotg->hsm.b_ase0_brst_tmout;
  433. time = TB_ASE0_BRST;
  434. break;
  435. case TB_SRP_INIT_TMR:
  436. iotg->hsm.b_srp_init_tmout = 0;
  437. data = (unsigned long)&iotg->hsm.b_srp_init_tmout;
  438. time = TB_SRP_INIT;
  439. break;
  440. case TB_SRP_FAIL_TMR:
  441. iotg->hsm.b_srp_fail_tmout = 0;
  442. data = (unsigned long)&iotg->hsm.b_srp_fail_tmout;
  443. time = TB_SRP_FAIL;
  444. break;
  445. case TB_BUS_SUSPEND_TMR:
  446. iotg->hsm.b_bus_suspend_tmout = 0;
  447. data = (unsigned long)&iotg->hsm.b_bus_suspend_tmout;
  448. time = TB_BUS_SUSPEND;
  449. break;
  450. default:
  451. dev_dbg(lnw->dev, "unknown timer, cannot enable it\n");
  452. return;
  453. }
  454. lnw->hsm_timer.data = data;
  455. lnw->hsm_timer.function = langwell_otg_timer_fn;
  456. lnw->hsm_timer.expires = j + time * HZ / 1000; /* milliseconds */
  457. add_timer(&lnw->hsm_timer);
  458. dev_dbg(lnw->dev, "add timer successfully\n");
  459. }
  460. /* Add timer to timer list */
  461. static void langwell_otg_add_timer(void *gtimer)
  462. {
  463. struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer;
  464. struct langwell_otg_timer *tmp_timer;
  465. struct intel_mid_otg_xceiv *iotg = &the_transceiver->iotg;
  466. u32 val32;
  467. /* Check if the timer is already in the active list,
  468. * if so update timer count
  469. */
  470. list_for_each_entry(tmp_timer, &active_timers, list)
  471. if (tmp_timer == timer) {
  472. timer->count = timer->expires;
  473. return;
  474. }
  475. timer->count = timer->expires;
  476. if (list_empty(&active_timers)) {
  477. val32 = readl(iotg->base + CI_OTGSC);
  478. writel(val32 | OTGSC_1MSE, iotg->base + CI_OTGSC);
  479. }
  480. list_add_tail(&timer->list, &active_timers);
  481. }
  482. /* Remove timer from the timer list; clear timeout status */
  483. static void langwell_otg_del_timer(void *gtimer)
  484. {
  485. struct langwell_otg *lnw = the_transceiver;
  486. struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer;
  487. struct langwell_otg_timer *tmp_timer, *del_tmp;
  488. u32 val32;
  489. list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
  490. if (tmp_timer == timer)
  491. list_del(&timer->list);
  492. if (list_empty(&active_timers)) {
  493. val32 = readl(lnw->iotg.base + CI_OTGSC);
  494. writel(val32 & ~OTGSC_1MSE, lnw->iotg.base + CI_OTGSC);
  495. }
  496. }
  497. /* Reduce timer count by 1, and find timeout conditions.*/
  498. static int langwell_otg_tick_timer(u32 *int_sts)
  499. {
  500. struct langwell_otg *lnw = the_transceiver;
  501. struct langwell_otg_timer *tmp_timer, *del_tmp;
  502. int expired = 0;
  503. list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
  504. tmp_timer->count--;
  505. /* check if timer expires */
  506. if (!tmp_timer->count) {
  507. list_del(&tmp_timer->list);
  508. tmp_timer->function(tmp_timer->data);
  509. expired = 1;
  510. }
  511. }
  512. if (list_empty(&active_timers)) {
  513. dev_dbg(lnw->dev, "tick timer: disable 1ms int\n");
  514. *int_sts = *int_sts & ~OTGSC_1MSE;
  515. }
  516. return expired;
  517. }
  518. static void reset_otg(void)
  519. {
  520. struct langwell_otg *lnw = the_transceiver;
  521. int delay_time = 1000;
  522. u32 val;
  523. dev_dbg(lnw->dev, "reseting OTG controller ...\n");
  524. val = readl(lnw->iotg.base + CI_USBCMD);
  525. writel(val | USBCMD_RST, lnw->iotg.base + CI_USBCMD);
  526. do {
  527. udelay(100);
  528. if (!delay_time--)
  529. dev_dbg(lnw->dev, "reset timeout\n");
  530. val = readl(lnw->iotg.base + CI_USBCMD);
  531. val &= USBCMD_RST;
  532. } while (val != 0);
  533. dev_dbg(lnw->dev, "reset done.\n");
  534. }
  535. static void set_host_mode(void)
  536. {
  537. struct langwell_otg *lnw = the_transceiver;
  538. u32 val;
  539. reset_otg();
  540. val = readl(lnw->iotg.base + CI_USBMODE);
  541. val = (val & (~USBMODE_CM)) | USBMODE_HOST;
  542. writel(val, lnw->iotg.base + CI_USBMODE);
  543. }
  544. static void set_client_mode(void)
  545. {
  546. struct langwell_otg *lnw = the_transceiver;
  547. u32 val;
  548. reset_otg();
  549. val = readl(lnw->iotg.base + CI_USBMODE);
  550. val = (val & (~USBMODE_CM)) | USBMODE_DEVICE;
  551. writel(val, lnw->iotg.base + CI_USBMODE);
  552. }
  553. static void init_hsm(void)
  554. {
  555. struct langwell_otg *lnw = the_transceiver;
  556. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  557. u32 val32;
  558. /* read OTGSC after reset */
  559. val32 = readl(lnw->iotg.base + CI_OTGSC);
  560. dev_dbg(lnw->dev, "%s: OTGSC init value = 0x%x\n", __func__, val32);
  561. /* set init state */
  562. if (val32 & OTGSC_ID) {
  563. iotg->hsm.id = 1;
  564. iotg->otg.default_a = 0;
  565. set_client_mode();
  566. iotg->otg.state = OTG_STATE_B_IDLE;
  567. } else {
  568. iotg->hsm.id = 0;
  569. iotg->otg.default_a = 1;
  570. set_host_mode();
  571. iotg->otg.state = OTG_STATE_A_IDLE;
  572. }
  573. /* set session indicator */
  574. if (val32 & OTGSC_BSE)
  575. iotg->hsm.b_sess_end = 1;
  576. if (val32 & OTGSC_BSV)
  577. iotg->hsm.b_sess_vld = 1;
  578. if (val32 & OTGSC_ASV)
  579. iotg->hsm.a_sess_vld = 1;
  580. if (val32 & OTGSC_AVV)
  581. iotg->hsm.a_vbus_vld = 1;
  582. /* defautly power the bus */
  583. iotg->hsm.a_bus_req = 1;
  584. iotg->hsm.a_bus_drop = 0;
  585. /* defautly don't request bus as B device */
  586. iotg->hsm.b_bus_req = 0;
  587. /* no system error */
  588. iotg->hsm.a_clr_err = 0;
  589. langwell_otg_phy_low_power_wait(1);
  590. }
  591. static void update_hsm(void)
  592. {
  593. struct langwell_otg *lnw = the_transceiver;
  594. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  595. u32 val32;
  596. /* read OTGSC */
  597. val32 = readl(lnw->iotg.base + CI_OTGSC);
  598. dev_dbg(lnw->dev, "%s: OTGSC value = 0x%x\n", __func__, val32);
  599. iotg->hsm.id = !!(val32 & OTGSC_ID);
  600. iotg->hsm.b_sess_end = !!(val32 & OTGSC_BSE);
  601. iotg->hsm.b_sess_vld = !!(val32 & OTGSC_BSV);
  602. iotg->hsm.a_sess_vld = !!(val32 & OTGSC_ASV);
  603. iotg->hsm.a_vbus_vld = !!(val32 & OTGSC_AVV);
  604. }
  605. static irqreturn_t otg_dummy_irq(int irq, void *_dev)
  606. {
  607. struct langwell_otg *lnw = the_transceiver;
  608. void __iomem *reg_base = _dev;
  609. u32 val;
  610. u32 int_mask = 0;
  611. val = readl(reg_base + CI_USBMODE);
  612. if ((val & USBMODE_CM) != USBMODE_DEVICE)
  613. return IRQ_NONE;
  614. val = readl(reg_base + CI_USBSTS);
  615. int_mask = val & INTR_DUMMY_MASK;
  616. if (int_mask == 0)
  617. return IRQ_NONE;
  618. /* clear hsm.b_conn here since host driver can't detect it
  619. * otg_dummy_irq called means B-disconnect happened.
  620. */
  621. if (lnw->iotg.hsm.b_conn) {
  622. lnw->iotg.hsm.b_conn = 0;
  623. if (spin_trylock(&lnw->wq_lock)) {
  624. langwell_update_transceiver();
  625. spin_unlock(&lnw->wq_lock);
  626. }
  627. }
  628. /* Clear interrupts */
  629. writel(int_mask, reg_base + CI_USBSTS);
  630. return IRQ_HANDLED;
  631. }
  632. static irqreturn_t otg_irq(int irq, void *_dev)
  633. {
  634. struct langwell_otg *lnw = _dev;
  635. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  636. u32 int_sts, int_en;
  637. u32 int_mask = 0;
  638. int flag = 0;
  639. int_sts = readl(lnw->iotg.base + CI_OTGSC);
  640. int_en = (int_sts & OTGSC_INTEN_MASK) >> 8;
  641. int_mask = int_sts & int_en;
  642. if (int_mask == 0)
  643. return IRQ_NONE;
  644. if (int_mask & OTGSC_IDIS) {
  645. dev_dbg(lnw->dev, "%s: id change int\n", __func__);
  646. iotg->hsm.id = (int_sts & OTGSC_ID) ? 1 : 0;
  647. dev_dbg(lnw->dev, "id = %d\n", iotg->hsm.id);
  648. flag = 1;
  649. }
  650. if (int_mask & OTGSC_DPIS) {
  651. dev_dbg(lnw->dev, "%s: data pulse int\n", __func__);
  652. iotg->hsm.a_srp_det = (int_sts & OTGSC_DPS) ? 1 : 0;
  653. dev_dbg(lnw->dev, "data pulse = %d\n", iotg->hsm.a_srp_det);
  654. flag = 1;
  655. }
  656. if (int_mask & OTGSC_BSEIS) {
  657. dev_dbg(lnw->dev, "%s: b session end int\n", __func__);
  658. iotg->hsm.b_sess_end = (int_sts & OTGSC_BSE) ? 1 : 0;
  659. dev_dbg(lnw->dev, "b_sess_end = %d\n", iotg->hsm.b_sess_end);
  660. flag = 1;
  661. }
  662. if (int_mask & OTGSC_BSVIS) {
  663. dev_dbg(lnw->dev, "%s: b session valid int\n", __func__);
  664. iotg->hsm.b_sess_vld = (int_sts & OTGSC_BSV) ? 1 : 0;
  665. dev_dbg(lnw->dev, "b_sess_vld = %d\n", iotg->hsm.b_sess_end);
  666. flag = 1;
  667. }
  668. if (int_mask & OTGSC_ASVIS) {
  669. dev_dbg(lnw->dev, "%s: a session valid int\n", __func__);
  670. iotg->hsm.a_sess_vld = (int_sts & OTGSC_ASV) ? 1 : 0;
  671. dev_dbg(lnw->dev, "a_sess_vld = %d\n", iotg->hsm.a_sess_vld);
  672. flag = 1;
  673. }
  674. if (int_mask & OTGSC_AVVIS) {
  675. dev_dbg(lnw->dev, "%s: a vbus valid int\n", __func__);
  676. iotg->hsm.a_vbus_vld = (int_sts & OTGSC_AVV) ? 1 : 0;
  677. dev_dbg(lnw->dev, "a_vbus_vld = %d\n", iotg->hsm.a_vbus_vld);
  678. flag = 1;
  679. }
  680. if (int_mask & OTGSC_1MSS) {
  681. /* need to schedule otg_work if any timer is expired */
  682. if (langwell_otg_tick_timer(&int_sts))
  683. flag = 1;
  684. }
  685. writel((int_sts & ~OTGSC_INTSTS_MASK) | int_mask,
  686. lnw->iotg.base + CI_OTGSC);
  687. if (flag)
  688. langwell_update_transceiver();
  689. return IRQ_HANDLED;
  690. }
  691. static int langwell_otg_iotg_notify(struct notifier_block *nb,
  692. unsigned long action, void *data)
  693. {
  694. struct langwell_otg *lnw = the_transceiver;
  695. struct intel_mid_otg_xceiv *iotg = data;
  696. int flag = 0;
  697. if (iotg == NULL)
  698. return NOTIFY_BAD;
  699. if (lnw == NULL)
  700. return NOTIFY_BAD;
  701. switch (action) {
  702. case MID_OTG_NOTIFY_CONNECT:
  703. dev_dbg(lnw->dev, "Lnw OTG Notify Connect Event\n");
  704. if (iotg->otg.default_a == 1)
  705. iotg->hsm.b_conn = 1;
  706. else
  707. iotg->hsm.a_conn = 1;
  708. flag = 1;
  709. break;
  710. case MID_OTG_NOTIFY_DISCONN:
  711. dev_dbg(lnw->dev, "Lnw OTG Notify Disconnect Event\n");
  712. if (iotg->otg.default_a == 1)
  713. iotg->hsm.b_conn = 0;
  714. else
  715. iotg->hsm.a_conn = 0;
  716. flag = 1;
  717. break;
  718. case MID_OTG_NOTIFY_HSUSPEND:
  719. dev_dbg(lnw->dev, "Lnw OTG Notify Host Bus suspend Event\n");
  720. if (iotg->otg.default_a == 1)
  721. iotg->hsm.a_suspend_req = 1;
  722. else
  723. iotg->hsm.b_bus_req = 0;
  724. flag = 1;
  725. break;
  726. case MID_OTG_NOTIFY_HRESUME:
  727. dev_dbg(lnw->dev, "Lnw OTG Notify Host Bus resume Event\n");
  728. if (iotg->otg.default_a == 1)
  729. iotg->hsm.b_bus_resume = 1;
  730. flag = 1;
  731. break;
  732. case MID_OTG_NOTIFY_CSUSPEND:
  733. dev_dbg(lnw->dev, "Lnw OTG Notify Client Bus suspend Event\n");
  734. if (iotg->otg.default_a == 1) {
  735. if (iotg->hsm.b_bus_suspend_vld == 2) {
  736. iotg->hsm.b_bus_suspend = 1;
  737. iotg->hsm.b_bus_suspend_vld = 0;
  738. flag = 1;
  739. } else {
  740. iotg->hsm.b_bus_suspend_vld++;
  741. flag = 0;
  742. }
  743. } else {
  744. if (iotg->hsm.a_bus_suspend == 0) {
  745. iotg->hsm.a_bus_suspend = 1;
  746. flag = 1;
  747. }
  748. }
  749. break;
  750. case MID_OTG_NOTIFY_CRESUME:
  751. dev_dbg(lnw->dev, "Lnw OTG Notify Client Bus resume Event\n");
  752. if (iotg->otg.default_a == 0)
  753. iotg->hsm.a_bus_suspend = 0;
  754. flag = 0;
  755. break;
  756. case MID_OTG_NOTIFY_HOSTADD:
  757. dev_dbg(lnw->dev, "Lnw OTG Nofity Host Driver Add\n");
  758. flag = 1;
  759. break;
  760. case MID_OTG_NOTIFY_HOSTREMOVE:
  761. dev_dbg(lnw->dev, "Lnw OTG Nofity Host Driver remove\n");
  762. flag = 1;
  763. break;
  764. case MID_OTG_NOTIFY_CLIENTADD:
  765. dev_dbg(lnw->dev, "Lnw OTG Nofity Client Driver Add\n");
  766. flag = 1;
  767. break;
  768. case MID_OTG_NOTIFY_CLIENTREMOVE:
  769. dev_dbg(lnw->dev, "Lnw OTG Nofity Client Driver remove\n");
  770. flag = 1;
  771. break;
  772. default:
  773. dev_dbg(lnw->dev, "Lnw OTG Nofity unknown notify message\n");
  774. return NOTIFY_DONE;
  775. }
  776. if (flag)
  777. langwell_update_transceiver();
  778. return NOTIFY_OK;
  779. }
  780. static void langwell_otg_work(struct work_struct *work)
  781. {
  782. struct langwell_otg *lnw;
  783. struct intel_mid_otg_xceiv *iotg;
  784. int retval;
  785. struct pci_dev *pdev;
  786. lnw = container_of(work, struct langwell_otg, work);
  787. iotg = &lnw->iotg;
  788. pdev = to_pci_dev(lnw->dev);
  789. dev_dbg(lnw->dev, "%s: old state = %s\n", __func__,
  790. otg_state_string(iotg->otg.state));
  791. switch (iotg->otg.state) {
  792. case OTG_STATE_UNDEFINED:
  793. case OTG_STATE_B_IDLE:
  794. if (!iotg->hsm.id) {
  795. langwell_otg_del_timer(b_srp_init_tmr);
  796. del_timer_sync(&lnw->hsm_timer);
  797. iotg->otg.default_a = 1;
  798. iotg->hsm.a_srp_det = 0;
  799. langwell_otg_chrg_vbus(0);
  800. set_host_mode();
  801. langwell_otg_phy_low_power(1);
  802. iotg->otg.state = OTG_STATE_A_IDLE;
  803. langwell_update_transceiver();
  804. } else if (iotg->hsm.b_sess_vld) {
  805. langwell_otg_del_timer(b_srp_init_tmr);
  806. del_timer_sync(&lnw->hsm_timer);
  807. iotg->hsm.b_sess_end = 0;
  808. iotg->hsm.a_bus_suspend = 0;
  809. langwell_otg_chrg_vbus(0);
  810. if (lnw->iotg.start_peripheral) {
  811. lnw->iotg.start_peripheral(&lnw->iotg);
  812. iotg->otg.state = OTG_STATE_B_PERIPHERAL;
  813. } else
  814. dev_dbg(lnw->dev, "client driver not loaded\n");
  815. } else if (iotg->hsm.b_srp_init_tmout) {
  816. iotg->hsm.b_srp_init_tmout = 0;
  817. dev_warn(lnw->dev, "SRP init timeout\n");
  818. } else if (iotg->hsm.b_srp_fail_tmout) {
  819. iotg->hsm.b_srp_fail_tmout = 0;
  820. iotg->hsm.b_bus_req = 0;
  821. /* No silence failure */
  822. langwell_otg_nsf_msg(6);
  823. } else if (iotg->hsm.b_bus_req && iotg->hsm.b_sess_end) {
  824. del_timer_sync(&lnw->hsm_timer);
  825. /* workaround for b_se0_srp detection */
  826. retval = langwell_otg_check_se0_srp(0);
  827. if (retval) {
  828. iotg->hsm.b_bus_req = 0;
  829. dev_dbg(lnw->dev, "LS isn't SE0, try later\n");
  830. } else {
  831. /* clear the PHCD before start srp */
  832. langwell_otg_phy_low_power(0);
  833. /* Start SRP */
  834. langwell_otg_add_timer(b_srp_init_tmr);
  835. iotg->otg.start_srp(&iotg->otg);
  836. langwell_otg_del_timer(b_srp_init_tmr);
  837. langwell_otg_add_ktimer(TB_SRP_FAIL_TMR);
  838. /* reset PHY low power mode here */
  839. langwell_otg_phy_low_power_wait(1);
  840. }
  841. }
  842. break;
  843. case OTG_STATE_B_SRP_INIT:
  844. if (!iotg->hsm.id) {
  845. iotg->otg.default_a = 1;
  846. iotg->hsm.a_srp_det = 0;
  847. /* Turn off VBus */
  848. iotg->otg.set_vbus(&iotg->otg, false);
  849. langwell_otg_chrg_vbus(0);
  850. set_host_mode();
  851. langwell_otg_phy_low_power(1);
  852. iotg->otg.state = OTG_STATE_A_IDLE;
  853. langwell_update_transceiver();
  854. } else if (iotg->hsm.b_sess_vld) {
  855. langwell_otg_chrg_vbus(0);
  856. if (lnw->iotg.start_peripheral) {
  857. lnw->iotg.start_peripheral(&lnw->iotg);
  858. iotg->otg.state = OTG_STATE_B_PERIPHERAL;
  859. } else
  860. dev_dbg(lnw->dev, "client driver not loaded\n");
  861. }
  862. break;
  863. case OTG_STATE_B_PERIPHERAL:
  864. if (!iotg->hsm.id) {
  865. iotg->otg.default_a = 1;
  866. iotg->hsm.a_srp_det = 0;
  867. langwell_otg_chrg_vbus(0);
  868. if (lnw->iotg.stop_peripheral)
  869. lnw->iotg.stop_peripheral(&lnw->iotg);
  870. else
  871. dev_dbg(lnw->dev,
  872. "client driver has been removed.\n");
  873. set_host_mode();
  874. langwell_otg_phy_low_power(1);
  875. iotg->otg.state = OTG_STATE_A_IDLE;
  876. langwell_update_transceiver();
  877. } else if (!iotg->hsm.b_sess_vld) {
  878. iotg->hsm.b_hnp_enable = 0;
  879. if (lnw->iotg.stop_peripheral)
  880. lnw->iotg.stop_peripheral(&lnw->iotg);
  881. else
  882. dev_dbg(lnw->dev,
  883. "client driver has been removed.\n");
  884. iotg->otg.state = OTG_STATE_B_IDLE;
  885. } else if (iotg->hsm.b_bus_req && iotg->otg.gadget &&
  886. iotg->otg.gadget->b_hnp_enable &&
  887. iotg->hsm.a_bus_suspend) {
  888. if (lnw->iotg.stop_peripheral)
  889. lnw->iotg.stop_peripheral(&lnw->iotg);
  890. else
  891. dev_dbg(lnw->dev,
  892. "client driver has been removed.\n");
  893. langwell_otg_HAAR(1);
  894. iotg->hsm.a_conn = 0;
  895. if (lnw->iotg.start_host) {
  896. lnw->iotg.start_host(&lnw->iotg);
  897. iotg->otg.state = OTG_STATE_B_WAIT_ACON;
  898. } else
  899. dev_dbg(lnw->dev,
  900. "host driver not loaded.\n");
  901. iotg->hsm.a_bus_resume = 0;
  902. langwell_otg_add_ktimer(TB_ASE0_BRST_TMR);
  903. }
  904. break;
  905. case OTG_STATE_B_WAIT_ACON:
  906. if (!iotg->hsm.id) {
  907. /* delete hsm timer for b_ase0_brst_tmr */
  908. del_timer_sync(&lnw->hsm_timer);
  909. iotg->otg.default_a = 1;
  910. iotg->hsm.a_srp_det = 0;
  911. langwell_otg_chrg_vbus(0);
  912. langwell_otg_HAAR(0);
  913. if (lnw->iotg.stop_host)
  914. lnw->iotg.stop_host(&lnw->iotg);
  915. else
  916. dev_dbg(lnw->dev,
  917. "host driver has been removed.\n");
  918. set_host_mode();
  919. langwell_otg_phy_low_power(1);
  920. iotg->otg.state = OTG_STATE_A_IDLE;
  921. langwell_update_transceiver();
  922. } else if (!iotg->hsm.b_sess_vld) {
  923. /* delete hsm timer for b_ase0_brst_tmr */
  924. del_timer_sync(&lnw->hsm_timer);
  925. iotg->hsm.b_hnp_enable = 0;
  926. iotg->hsm.b_bus_req = 0;
  927. langwell_otg_chrg_vbus(0);
  928. langwell_otg_HAAR(0);
  929. if (lnw->iotg.stop_host)
  930. lnw->iotg.stop_host(&lnw->iotg);
  931. else
  932. dev_dbg(lnw->dev,
  933. "host driver has been removed.\n");
  934. set_client_mode();
  935. langwell_otg_phy_low_power(1);
  936. iotg->otg.state = OTG_STATE_B_IDLE;
  937. } else if (iotg->hsm.a_conn) {
  938. /* delete hsm timer for b_ase0_brst_tmr */
  939. del_timer_sync(&lnw->hsm_timer);
  940. langwell_otg_HAAR(0);
  941. iotg->otg.state = OTG_STATE_B_HOST;
  942. langwell_update_transceiver();
  943. } else if (iotg->hsm.a_bus_resume ||
  944. iotg->hsm.b_ase0_brst_tmout) {
  945. /* delete hsm timer for b_ase0_brst_tmr */
  946. del_timer_sync(&lnw->hsm_timer);
  947. langwell_otg_HAAR(0);
  948. langwell_otg_nsf_msg(7);
  949. if (lnw->iotg.stop_host)
  950. lnw->iotg.stop_host(&lnw->iotg);
  951. else
  952. dev_dbg(lnw->dev,
  953. "host driver has been removed.\n");
  954. iotg->hsm.a_bus_suspend = 0;
  955. iotg->hsm.b_bus_req = 0;
  956. if (lnw->iotg.start_peripheral)
  957. lnw->iotg.start_peripheral(&lnw->iotg);
  958. else
  959. dev_dbg(lnw->dev,
  960. "client driver not loaded.\n");
  961. iotg->otg.state = OTG_STATE_B_PERIPHERAL;
  962. }
  963. break;
  964. case OTG_STATE_B_HOST:
  965. if (!iotg->hsm.id) {
  966. iotg->otg.default_a = 1;
  967. iotg->hsm.a_srp_det = 0;
  968. langwell_otg_chrg_vbus(0);
  969. if (lnw->iotg.stop_host)
  970. lnw->iotg.stop_host(&lnw->iotg);
  971. else
  972. dev_dbg(lnw->dev,
  973. "host driver has been removed.\n");
  974. set_host_mode();
  975. langwell_otg_phy_low_power(1);
  976. iotg->otg.state = OTG_STATE_A_IDLE;
  977. langwell_update_transceiver();
  978. } else if (!iotg->hsm.b_sess_vld) {
  979. iotg->hsm.b_hnp_enable = 0;
  980. iotg->hsm.b_bus_req = 0;
  981. langwell_otg_chrg_vbus(0);
  982. if (lnw->iotg.stop_host)
  983. lnw->iotg.stop_host(&lnw->iotg);
  984. else
  985. dev_dbg(lnw->dev,
  986. "host driver has been removed.\n");
  987. set_client_mode();
  988. langwell_otg_phy_low_power(1);
  989. iotg->otg.state = OTG_STATE_B_IDLE;
  990. } else if ((!iotg->hsm.b_bus_req) ||
  991. (!iotg->hsm.a_conn)) {
  992. iotg->hsm.b_bus_req = 0;
  993. langwell_otg_loc_sof(0);
  994. if (lnw->iotg.stop_host)
  995. lnw->iotg.stop_host(&lnw->iotg);
  996. else
  997. dev_dbg(lnw->dev,
  998. "host driver has been removed.\n");
  999. iotg->hsm.a_bus_suspend = 0;
  1000. if (lnw->iotg.start_peripheral)
  1001. lnw->iotg.start_peripheral(&lnw->iotg);
  1002. else
  1003. dev_dbg(lnw->dev,
  1004. "client driver not loaded.\n");
  1005. iotg->otg.state = OTG_STATE_B_PERIPHERAL;
  1006. }
  1007. break;
  1008. case OTG_STATE_A_IDLE:
  1009. iotg->otg.default_a = 1;
  1010. if (iotg->hsm.id) {
  1011. iotg->otg.default_a = 0;
  1012. iotg->hsm.b_bus_req = 0;
  1013. iotg->hsm.vbus_srp_up = 0;
  1014. langwell_otg_chrg_vbus(0);
  1015. set_client_mode();
  1016. langwell_otg_phy_low_power(1);
  1017. iotg->otg.state = OTG_STATE_B_IDLE;
  1018. langwell_update_transceiver();
  1019. } else if (!iotg->hsm.a_bus_drop &&
  1020. (iotg->hsm.a_srp_det || iotg->hsm.a_bus_req)) {
  1021. langwell_otg_phy_low_power(0);
  1022. /* Turn on VBus */
  1023. iotg->otg.set_vbus(&iotg->otg, true);
  1024. iotg->hsm.vbus_srp_up = 0;
  1025. iotg->hsm.a_wait_vrise_tmout = 0;
  1026. langwell_otg_add_timer(a_wait_vrise_tmr);
  1027. iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
  1028. langwell_update_transceiver();
  1029. } else if (!iotg->hsm.a_bus_drop && iotg->hsm.a_sess_vld) {
  1030. iotg->hsm.vbus_srp_up = 1;
  1031. } else if (!iotg->hsm.a_sess_vld && iotg->hsm.vbus_srp_up) {
  1032. msleep(10);
  1033. langwell_otg_phy_low_power(0);
  1034. /* Turn on VBus */
  1035. iotg->otg.set_vbus(&iotg->otg, true);
  1036. iotg->hsm.a_srp_det = 1;
  1037. iotg->hsm.vbus_srp_up = 0;
  1038. iotg->hsm.a_wait_vrise_tmout = 0;
  1039. langwell_otg_add_timer(a_wait_vrise_tmr);
  1040. iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
  1041. langwell_update_transceiver();
  1042. } else if (!iotg->hsm.a_sess_vld &&
  1043. !iotg->hsm.vbus_srp_up) {
  1044. langwell_otg_phy_low_power(1);
  1045. }
  1046. break;
  1047. case OTG_STATE_A_WAIT_VRISE:
  1048. if (iotg->hsm.id) {
  1049. langwell_otg_del_timer(a_wait_vrise_tmr);
  1050. iotg->hsm.b_bus_req = 0;
  1051. iotg->otg.default_a = 0;
  1052. /* Turn off VBus */
  1053. iotg->otg.set_vbus(&iotg->otg, false);
  1054. set_client_mode();
  1055. langwell_otg_phy_low_power_wait(1);
  1056. iotg->otg.state = OTG_STATE_B_IDLE;
  1057. } else if (iotg->hsm.a_vbus_vld) {
  1058. langwell_otg_del_timer(a_wait_vrise_tmr);
  1059. iotg->hsm.b_conn = 0;
  1060. if (lnw->iotg.start_host)
  1061. lnw->iotg.start_host(&lnw->iotg);
  1062. else {
  1063. dev_dbg(lnw->dev, "host driver not loaded.\n");
  1064. break;
  1065. }
  1066. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1067. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1068. } else if (iotg->hsm.a_wait_vrise_tmout) {
  1069. iotg->hsm.b_conn = 0;
  1070. if (iotg->hsm.a_vbus_vld) {
  1071. if (lnw->iotg.start_host)
  1072. lnw->iotg.start_host(&lnw->iotg);
  1073. else {
  1074. dev_dbg(lnw->dev,
  1075. "host driver not loaded.\n");
  1076. break;
  1077. }
  1078. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1079. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1080. } else {
  1081. /* Turn off VBus */
  1082. iotg->otg.set_vbus(&iotg->otg, false);
  1083. langwell_otg_phy_low_power_wait(1);
  1084. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1085. }
  1086. }
  1087. break;
  1088. case OTG_STATE_A_WAIT_BCON:
  1089. if (iotg->hsm.id) {
  1090. /* delete hsm timer for a_wait_bcon_tmr */
  1091. del_timer_sync(&lnw->hsm_timer);
  1092. iotg->otg.default_a = 0;
  1093. iotg->hsm.b_bus_req = 0;
  1094. if (lnw->iotg.stop_host)
  1095. lnw->iotg.stop_host(&lnw->iotg);
  1096. else
  1097. dev_dbg(lnw->dev,
  1098. "host driver has been removed.\n");
  1099. /* Turn off VBus */
  1100. iotg->otg.set_vbus(&iotg->otg, false);
  1101. set_client_mode();
  1102. langwell_otg_phy_low_power_wait(1);
  1103. iotg->otg.state = OTG_STATE_B_IDLE;
  1104. langwell_update_transceiver();
  1105. } else if (!iotg->hsm.a_vbus_vld) {
  1106. /* delete hsm timer for a_wait_bcon_tmr */
  1107. del_timer_sync(&lnw->hsm_timer);
  1108. if (lnw->iotg.stop_host)
  1109. lnw->iotg.stop_host(&lnw->iotg);
  1110. else
  1111. dev_dbg(lnw->dev,
  1112. "host driver has been removed.\n");
  1113. /* Turn off VBus */
  1114. iotg->otg.set_vbus(&iotg->otg, false);
  1115. langwell_otg_phy_low_power_wait(1);
  1116. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1117. } else if (iotg->hsm.a_bus_drop ||
  1118. (iotg->hsm.a_wait_bcon_tmout &&
  1119. !iotg->hsm.a_bus_req)) {
  1120. /* delete hsm timer for a_wait_bcon_tmr */
  1121. del_timer_sync(&lnw->hsm_timer);
  1122. if (lnw->iotg.stop_host)
  1123. lnw->iotg.stop_host(&lnw->iotg);
  1124. else
  1125. dev_dbg(lnw->dev,
  1126. "host driver has been removed.\n");
  1127. /* Turn off VBus */
  1128. iotg->otg.set_vbus(&iotg->otg, false);
  1129. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1130. } else if (iotg->hsm.b_conn) {
  1131. /* delete hsm timer for a_wait_bcon_tmr */
  1132. del_timer_sync(&lnw->hsm_timer);
  1133. iotg->hsm.a_suspend_req = 0;
  1134. iotg->otg.state = OTG_STATE_A_HOST;
  1135. if (iotg->hsm.a_srp_det && iotg->otg.host &&
  1136. !iotg->otg.host->b_hnp_enable) {
  1137. /* SRP capable peripheral-only device */
  1138. iotg->hsm.a_bus_req = 1;
  1139. iotg->hsm.a_srp_det = 0;
  1140. } else if (!iotg->hsm.a_bus_req && iotg->otg.host &&
  1141. iotg->otg.host->b_hnp_enable) {
  1142. /* It is not safe enough to do a fast
  1143. * transition from A_WAIT_BCON to
  1144. * A_SUSPEND */
  1145. msleep(10000);
  1146. if (iotg->hsm.a_bus_req)
  1147. break;
  1148. if (request_irq(pdev->irq,
  1149. otg_dummy_irq, IRQF_SHARED,
  1150. driver_name, iotg->base) != 0) {
  1151. dev_dbg(lnw->dev,
  1152. "request interrupt %d fail\n",
  1153. pdev->irq);
  1154. }
  1155. langwell_otg_HABA(1);
  1156. iotg->hsm.b_bus_resume = 0;
  1157. iotg->hsm.a_aidl_bdis_tmout = 0;
  1158. langwell_otg_loc_sof(0);
  1159. /* clear PHCD to enable HW timer */
  1160. langwell_otg_phy_low_power(0);
  1161. langwell_otg_add_timer(a_aidl_bdis_tmr);
  1162. iotg->otg.state = OTG_STATE_A_SUSPEND;
  1163. } else if (!iotg->hsm.a_bus_req && iotg->otg.host &&
  1164. !iotg->otg.host->b_hnp_enable) {
  1165. if (lnw->iotg.stop_host)
  1166. lnw->iotg.stop_host(&lnw->iotg);
  1167. else
  1168. dev_dbg(lnw->dev,
  1169. "host driver removed.\n");
  1170. /* Turn off VBus */
  1171. iotg->otg.set_vbus(&iotg->otg, false);
  1172. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1173. }
  1174. }
  1175. break;
  1176. case OTG_STATE_A_HOST:
  1177. if (iotg->hsm.id) {
  1178. iotg->otg.default_a = 0;
  1179. iotg->hsm.b_bus_req = 0;
  1180. if (lnw->iotg.stop_host)
  1181. lnw->iotg.stop_host(&lnw->iotg);
  1182. else
  1183. dev_dbg(lnw->dev,
  1184. "host driver has been removed.\n");
  1185. /* Turn off VBus */
  1186. iotg->otg.set_vbus(&iotg->otg, false);
  1187. set_client_mode();
  1188. langwell_otg_phy_low_power_wait(1);
  1189. iotg->otg.state = OTG_STATE_B_IDLE;
  1190. langwell_update_transceiver();
  1191. } else if (iotg->hsm.a_bus_drop ||
  1192. (iotg->otg.host &&
  1193. !iotg->otg.host->b_hnp_enable &&
  1194. !iotg->hsm.a_bus_req)) {
  1195. if (lnw->iotg.stop_host)
  1196. lnw->iotg.stop_host(&lnw->iotg);
  1197. else
  1198. dev_dbg(lnw->dev,
  1199. "host driver has been removed.\n");
  1200. /* Turn off VBus */
  1201. iotg->otg.set_vbus(&iotg->otg, false);
  1202. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1203. } else if (!iotg->hsm.a_vbus_vld) {
  1204. if (lnw->iotg.stop_host)
  1205. lnw->iotg.stop_host(&lnw->iotg);
  1206. else
  1207. dev_dbg(lnw->dev,
  1208. "host driver has been removed.\n");
  1209. /* Turn off VBus */
  1210. iotg->otg.set_vbus(&iotg->otg, false);
  1211. langwell_otg_phy_low_power_wait(1);
  1212. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1213. } else if (iotg->otg.host &&
  1214. iotg->otg.host->b_hnp_enable &&
  1215. !iotg->hsm.a_bus_req) {
  1216. /* Set HABA to enable hardware assistance to signal
  1217. * A-connect after receiver B-disconnect. Hardware
  1218. * will then set client mode and enable URE, SLE and
  1219. * PCE after the assistance. otg_dummy_irq is used to
  1220. * clean these ints when client driver is not resumed.
  1221. */
  1222. if (request_irq(pdev->irq, otg_dummy_irq, IRQF_SHARED,
  1223. driver_name, iotg->base) != 0) {
  1224. dev_dbg(lnw->dev,
  1225. "request interrupt %d failed\n",
  1226. pdev->irq);
  1227. }
  1228. /* set HABA */
  1229. langwell_otg_HABA(1);
  1230. iotg->hsm.b_bus_resume = 0;
  1231. iotg->hsm.a_aidl_bdis_tmout = 0;
  1232. langwell_otg_loc_sof(0);
  1233. /* clear PHCD to enable HW timer */
  1234. langwell_otg_phy_low_power(0);
  1235. langwell_otg_add_timer(a_aidl_bdis_tmr);
  1236. iotg->otg.state = OTG_STATE_A_SUSPEND;
  1237. } else if (!iotg->hsm.b_conn || !iotg->hsm.a_bus_req) {
  1238. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1239. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1240. }
  1241. break;
  1242. case OTG_STATE_A_SUSPEND:
  1243. if (iotg->hsm.id) {
  1244. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1245. langwell_otg_HABA(0);
  1246. free_irq(pdev->irq, iotg->base);
  1247. iotg->otg.default_a = 0;
  1248. iotg->hsm.b_bus_req = 0;
  1249. if (lnw->iotg.stop_host)
  1250. lnw->iotg.stop_host(&lnw->iotg);
  1251. else
  1252. dev_dbg(lnw->dev,
  1253. "host driver has been removed.\n");
  1254. /* Turn off VBus */
  1255. iotg->otg.set_vbus(&iotg->otg, false);
  1256. set_client_mode();
  1257. langwell_otg_phy_low_power(1);
  1258. iotg->otg.state = OTG_STATE_B_IDLE;
  1259. langwell_update_transceiver();
  1260. } else if (iotg->hsm.a_bus_req ||
  1261. iotg->hsm.b_bus_resume) {
  1262. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1263. langwell_otg_HABA(0);
  1264. free_irq(pdev->irq, iotg->base);
  1265. iotg->hsm.a_suspend_req = 0;
  1266. langwell_otg_loc_sof(1);
  1267. iotg->otg.state = OTG_STATE_A_HOST;
  1268. } else if (iotg->hsm.a_aidl_bdis_tmout ||
  1269. iotg->hsm.a_bus_drop) {
  1270. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1271. langwell_otg_HABA(0);
  1272. free_irq(pdev->irq, iotg->base);
  1273. if (lnw->iotg.stop_host)
  1274. lnw->iotg.stop_host(&lnw->iotg);
  1275. else
  1276. dev_dbg(lnw->dev,
  1277. "host driver has been removed.\n");
  1278. /* Turn off VBus */
  1279. iotg->otg.set_vbus(&iotg->otg, false);
  1280. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1281. } else if (!iotg->hsm.b_conn && iotg->otg.host &&
  1282. iotg->otg.host->b_hnp_enable) {
  1283. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1284. langwell_otg_HABA(0);
  1285. free_irq(pdev->irq, iotg->base);
  1286. if (lnw->iotg.stop_host)
  1287. lnw->iotg.stop_host(&lnw->iotg);
  1288. else
  1289. dev_dbg(lnw->dev,
  1290. "host driver has been removed.\n");
  1291. iotg->hsm.b_bus_suspend = 0;
  1292. iotg->hsm.b_bus_suspend_vld = 0;
  1293. /* msleep(200); */
  1294. if (lnw->iotg.start_peripheral)
  1295. lnw->iotg.start_peripheral(&lnw->iotg);
  1296. else
  1297. dev_dbg(lnw->dev,
  1298. "client driver not loaded.\n");
  1299. langwell_otg_add_ktimer(TB_BUS_SUSPEND_TMR);
  1300. iotg->otg.state = OTG_STATE_A_PERIPHERAL;
  1301. break;
  1302. } else if (!iotg->hsm.a_vbus_vld) {
  1303. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1304. langwell_otg_HABA(0);
  1305. free_irq(pdev->irq, iotg->base);
  1306. if (lnw->iotg.stop_host)
  1307. lnw->iotg.stop_host(&lnw->iotg);
  1308. else
  1309. dev_dbg(lnw->dev,
  1310. "host driver has been removed.\n");
  1311. /* Turn off VBus */
  1312. iotg->otg.set_vbus(&iotg->otg, false);
  1313. langwell_otg_phy_low_power_wait(1);
  1314. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1315. }
  1316. break;
  1317. case OTG_STATE_A_PERIPHERAL:
  1318. if (iotg->hsm.id) {
  1319. /* delete hsm timer for b_bus_suspend_tmr */
  1320. del_timer_sync(&lnw->hsm_timer);
  1321. iotg->otg.default_a = 0;
  1322. iotg->hsm.b_bus_req = 0;
  1323. if (lnw->iotg.stop_peripheral)
  1324. lnw->iotg.stop_peripheral(&lnw->iotg);
  1325. else
  1326. dev_dbg(lnw->dev,
  1327. "client driver has been removed.\n");
  1328. /* Turn off VBus */
  1329. iotg->otg.set_vbus(&iotg->otg, false);
  1330. set_client_mode();
  1331. langwell_otg_phy_low_power_wait(1);
  1332. iotg->otg.state = OTG_STATE_B_IDLE;
  1333. langwell_update_transceiver();
  1334. } else if (!iotg->hsm.a_vbus_vld) {
  1335. /* delete hsm timer for b_bus_suspend_tmr */
  1336. del_timer_sync(&lnw->hsm_timer);
  1337. if (lnw->iotg.stop_peripheral)
  1338. lnw->iotg.stop_peripheral(&lnw->iotg);
  1339. else
  1340. dev_dbg(lnw->dev,
  1341. "client driver has been removed.\n");
  1342. /* Turn off VBus */
  1343. iotg->otg.set_vbus(&iotg->otg, false);
  1344. langwell_otg_phy_low_power_wait(1);
  1345. iotg->otg.state = OTG_STATE_A_VBUS_ERR;
  1346. } else if (iotg->hsm.a_bus_drop) {
  1347. /* delete hsm timer for b_bus_suspend_tmr */
  1348. del_timer_sync(&lnw->hsm_timer);
  1349. if (lnw->iotg.stop_peripheral)
  1350. lnw->iotg.stop_peripheral(&lnw->iotg);
  1351. else
  1352. dev_dbg(lnw->dev,
  1353. "client driver has been removed.\n");
  1354. /* Turn off VBus */
  1355. iotg->otg.set_vbus(&iotg->otg, false);
  1356. iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
  1357. } else if (iotg->hsm.b_bus_suspend) {
  1358. /* delete hsm timer for b_bus_suspend_tmr */
  1359. del_timer_sync(&lnw->hsm_timer);
  1360. if (lnw->iotg.stop_peripheral)
  1361. lnw->iotg.stop_peripheral(&lnw->iotg);
  1362. else
  1363. dev_dbg(lnw->dev,
  1364. "client driver has been removed.\n");
  1365. if (lnw->iotg.start_host)
  1366. lnw->iotg.start_host(&lnw->iotg);
  1367. else
  1368. dev_dbg(lnw->dev,
  1369. "host driver not loaded.\n");
  1370. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1371. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1372. } else if (iotg->hsm.b_bus_suspend_tmout) {
  1373. u32 val;
  1374. val = readl(lnw->iotg.base + CI_PORTSC1);
  1375. if (!(val & PORTSC_SUSP))
  1376. break;
  1377. if (lnw->iotg.stop_peripheral)
  1378. lnw->iotg.stop_peripheral(&lnw->iotg);
  1379. else
  1380. dev_dbg(lnw->dev,
  1381. "client driver has been removed.\n");
  1382. if (lnw->iotg.start_host)
  1383. lnw->iotg.start_host(&lnw->iotg);
  1384. else
  1385. dev_dbg(lnw->dev,
  1386. "host driver not loaded.\n");
  1387. langwell_otg_add_ktimer(TA_WAIT_BCON_TMR);
  1388. iotg->otg.state = OTG_STATE_A_WAIT_BCON;
  1389. }
  1390. break;
  1391. case OTG_STATE_A_VBUS_ERR:
  1392. if (iotg->hsm.id) {
  1393. iotg->otg.default_a = 0;
  1394. iotg->hsm.a_clr_err = 0;
  1395. iotg->hsm.a_srp_det = 0;
  1396. set_client_mode();
  1397. langwell_otg_phy_low_power(1);
  1398. iotg->otg.state = OTG_STATE_B_IDLE;
  1399. langwell_update_transceiver();
  1400. } else if (iotg->hsm.a_clr_err) {
  1401. iotg->hsm.a_clr_err = 0;
  1402. iotg->hsm.a_srp_det = 0;
  1403. reset_otg();
  1404. init_hsm();
  1405. if (iotg->otg.state == OTG_STATE_A_IDLE)
  1406. langwell_update_transceiver();
  1407. } else {
  1408. /* FW will clear PHCD bit when any VBus
  1409. * event detected. Reset PHCD to 1 again */
  1410. langwell_otg_phy_low_power(1);
  1411. }
  1412. break;
  1413. case OTG_STATE_A_WAIT_VFALL:
  1414. if (iotg->hsm.id) {
  1415. iotg->otg.default_a = 0;
  1416. set_client_mode();
  1417. langwell_otg_phy_low_power(1);
  1418. iotg->otg.state = OTG_STATE_B_IDLE;
  1419. langwell_update_transceiver();
  1420. } else if (iotg->hsm.a_bus_req) {
  1421. /* Turn on VBus */
  1422. iotg->otg.set_vbus(&iotg->otg, true);
  1423. iotg->hsm.a_wait_vrise_tmout = 0;
  1424. langwell_otg_add_timer(a_wait_vrise_tmr);
  1425. iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
  1426. } else if (!iotg->hsm.a_sess_vld) {
  1427. iotg->hsm.a_srp_det = 0;
  1428. set_host_mode();
  1429. langwell_otg_phy_low_power(1);
  1430. iotg->otg.state = OTG_STATE_A_IDLE;
  1431. }
  1432. break;
  1433. default:
  1434. ;
  1435. }
  1436. dev_dbg(lnw->dev, "%s: new state = %s\n", __func__,
  1437. otg_state_string(iotg->otg.state));
  1438. }
  1439. static ssize_t
  1440. show_registers(struct device *_dev, struct device_attribute *attr, char *buf)
  1441. {
  1442. struct langwell_otg *lnw = the_transceiver;
  1443. char *next;
  1444. unsigned size, t;
  1445. next = buf;
  1446. size = PAGE_SIZE;
  1447. t = scnprintf(next, size,
  1448. "\n"
  1449. "USBCMD = 0x%08x\n"
  1450. "USBSTS = 0x%08x\n"
  1451. "USBINTR = 0x%08x\n"
  1452. "ASYNCLISTADDR = 0x%08x\n"
  1453. "PORTSC1 = 0x%08x\n"
  1454. "HOSTPC1 = 0x%08x\n"
  1455. "OTGSC = 0x%08x\n"
  1456. "USBMODE = 0x%08x\n",
  1457. readl(lnw->iotg.base + 0x30),
  1458. readl(lnw->iotg.base + 0x34),
  1459. readl(lnw->iotg.base + 0x38),
  1460. readl(lnw->iotg.base + 0x48),
  1461. readl(lnw->iotg.base + 0x74),
  1462. readl(lnw->iotg.base + 0xb4),
  1463. readl(lnw->iotg.base + 0xf4),
  1464. readl(lnw->iotg.base + 0xf8)
  1465. );
  1466. size -= t;
  1467. next += t;
  1468. return PAGE_SIZE - size;
  1469. }
  1470. static DEVICE_ATTR(registers, S_IRUGO, show_registers, NULL);
  1471. static ssize_t
  1472. show_hsm(struct device *_dev, struct device_attribute *attr, char *buf)
  1473. {
  1474. struct langwell_otg *lnw = the_transceiver;
  1475. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1476. char *next;
  1477. unsigned size, t;
  1478. next = buf;
  1479. size = PAGE_SIZE;
  1480. if (iotg->otg.host)
  1481. iotg->hsm.a_set_b_hnp_en = iotg->otg.host->b_hnp_enable;
  1482. if (iotg->otg.gadget)
  1483. iotg->hsm.b_hnp_enable = iotg->otg.gadget->b_hnp_enable;
  1484. t = scnprintf(next, size,
  1485. "\n"
  1486. "current state = %s\n"
  1487. "a_bus_resume = \t%d\n"
  1488. "a_bus_suspend = \t%d\n"
  1489. "a_conn = \t%d\n"
  1490. "a_sess_vld = \t%d\n"
  1491. "a_srp_det = \t%d\n"
  1492. "a_vbus_vld = \t%d\n"
  1493. "b_bus_resume = \t%d\n"
  1494. "b_bus_suspend = \t%d\n"
  1495. "b_conn = \t%d\n"
  1496. "b_se0_srp = \t%d\n"
  1497. "b_sess_end = \t%d\n"
  1498. "b_sess_vld = \t%d\n"
  1499. "id = \t%d\n"
  1500. "a_set_b_hnp_en = \t%d\n"
  1501. "b_srp_done = \t%d\n"
  1502. "b_hnp_enable = \t%d\n"
  1503. "a_wait_vrise_tmout = \t%d\n"
  1504. "a_wait_bcon_tmout = \t%d\n"
  1505. "a_aidl_bdis_tmout = \t%d\n"
  1506. "b_ase0_brst_tmout = \t%d\n"
  1507. "a_bus_drop = \t%d\n"
  1508. "a_bus_req = \t%d\n"
  1509. "a_clr_err = \t%d\n"
  1510. "a_suspend_req = \t%d\n"
  1511. "b_bus_req = \t%d\n"
  1512. "b_bus_suspend_tmout = \t%d\n"
  1513. "b_bus_suspend_vld = \t%d\n",
  1514. otg_state_string(iotg->otg.state),
  1515. iotg->hsm.a_bus_resume,
  1516. iotg->hsm.a_bus_suspend,
  1517. iotg->hsm.a_conn,
  1518. iotg->hsm.a_sess_vld,
  1519. iotg->hsm.a_srp_det,
  1520. iotg->hsm.a_vbus_vld,
  1521. iotg->hsm.b_bus_resume,
  1522. iotg->hsm.b_bus_suspend,
  1523. iotg->hsm.b_conn,
  1524. iotg->hsm.b_se0_srp,
  1525. iotg->hsm.b_sess_end,
  1526. iotg->hsm.b_sess_vld,
  1527. iotg->hsm.id,
  1528. iotg->hsm.a_set_b_hnp_en,
  1529. iotg->hsm.b_srp_done,
  1530. iotg->hsm.b_hnp_enable,
  1531. iotg->hsm.a_wait_vrise_tmout,
  1532. iotg->hsm.a_wait_bcon_tmout,
  1533. iotg->hsm.a_aidl_bdis_tmout,
  1534. iotg->hsm.b_ase0_brst_tmout,
  1535. iotg->hsm.a_bus_drop,
  1536. iotg->hsm.a_bus_req,
  1537. iotg->hsm.a_clr_err,
  1538. iotg->hsm.a_suspend_req,
  1539. iotg->hsm.b_bus_req,
  1540. iotg->hsm.b_bus_suspend_tmout,
  1541. iotg->hsm.b_bus_suspend_vld
  1542. );
  1543. size -= t;
  1544. next += t;
  1545. return PAGE_SIZE - size;
  1546. }
  1547. static DEVICE_ATTR(hsm, S_IRUGO, show_hsm, NULL);
  1548. static ssize_t
  1549. get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
  1550. {
  1551. struct langwell_otg *lnw = the_transceiver;
  1552. char *next;
  1553. unsigned size, t;
  1554. next = buf;
  1555. size = PAGE_SIZE;
  1556. t = scnprintf(next, size, "%d", lnw->iotg.hsm.a_bus_req);
  1557. size -= t;
  1558. next += t;
  1559. return PAGE_SIZE - size;
  1560. }
  1561. static ssize_t
  1562. set_a_bus_req(struct device *dev, struct device_attribute *attr,
  1563. const char *buf, size_t count)
  1564. {
  1565. struct langwell_otg *lnw = the_transceiver;
  1566. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1567. if (!iotg->otg.default_a)
  1568. return -1;
  1569. if (count > 2)
  1570. return -1;
  1571. if (buf[0] == '0') {
  1572. iotg->hsm.a_bus_req = 0;
  1573. dev_dbg(lnw->dev, "User request: a_bus_req = 0\n");
  1574. } else if (buf[0] == '1') {
  1575. /* If a_bus_drop is TRUE, a_bus_req can't be set */
  1576. if (iotg->hsm.a_bus_drop)
  1577. return -1;
  1578. iotg->hsm.a_bus_req = 1;
  1579. dev_dbg(lnw->dev, "User request: a_bus_req = 1\n");
  1580. }
  1581. if (spin_trylock(&lnw->wq_lock)) {
  1582. langwell_update_transceiver();
  1583. spin_unlock(&lnw->wq_lock);
  1584. }
  1585. return count;
  1586. }
  1587. static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req, set_a_bus_req);
  1588. static ssize_t
  1589. get_a_bus_drop(struct device *dev, struct device_attribute *attr, char *buf)
  1590. {
  1591. struct langwell_otg *lnw = the_transceiver;
  1592. char *next;
  1593. unsigned size, t;
  1594. next = buf;
  1595. size = PAGE_SIZE;
  1596. t = scnprintf(next, size, "%d", lnw->iotg.hsm.a_bus_drop);
  1597. size -= t;
  1598. next += t;
  1599. return PAGE_SIZE - size;
  1600. }
  1601. static ssize_t
  1602. set_a_bus_drop(struct device *dev, struct device_attribute *attr,
  1603. const char *buf, size_t count)
  1604. {
  1605. struct langwell_otg *lnw = the_transceiver;
  1606. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1607. if (!iotg->otg.default_a)
  1608. return -1;
  1609. if (count > 2)
  1610. return -1;
  1611. if (buf[0] == '0') {
  1612. iotg->hsm.a_bus_drop = 0;
  1613. dev_dbg(lnw->dev, "User request: a_bus_drop = 0\n");
  1614. } else if (buf[0] == '1') {
  1615. iotg->hsm.a_bus_drop = 1;
  1616. iotg->hsm.a_bus_req = 0;
  1617. dev_dbg(lnw->dev, "User request: a_bus_drop = 1\n");
  1618. dev_dbg(lnw->dev, "User request: and a_bus_req = 0\n");
  1619. }
  1620. if (spin_trylock(&lnw->wq_lock)) {
  1621. langwell_update_transceiver();
  1622. spin_unlock(&lnw->wq_lock);
  1623. }
  1624. return count;
  1625. }
  1626. static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR, get_a_bus_drop, set_a_bus_drop);
  1627. static ssize_t
  1628. get_b_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
  1629. {
  1630. struct langwell_otg *lnw = the_transceiver;
  1631. char *next;
  1632. unsigned size, t;
  1633. next = buf;
  1634. size = PAGE_SIZE;
  1635. t = scnprintf(next, size, "%d", lnw->iotg.hsm.b_bus_req);
  1636. size -= t;
  1637. next += t;
  1638. return PAGE_SIZE - size;
  1639. }
  1640. static ssize_t
  1641. set_b_bus_req(struct device *dev, struct device_attribute *attr,
  1642. const char *buf, size_t count)
  1643. {
  1644. struct langwell_otg *lnw = the_transceiver;
  1645. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1646. if (iotg->otg.default_a)
  1647. return -1;
  1648. if (count > 2)
  1649. return -1;
  1650. if (buf[0] == '0') {
  1651. iotg->hsm.b_bus_req = 0;
  1652. dev_dbg(lnw->dev, "User request: b_bus_req = 0\n");
  1653. } else if (buf[0] == '1') {
  1654. iotg->hsm.b_bus_req = 1;
  1655. dev_dbg(lnw->dev, "User request: b_bus_req = 1\n");
  1656. }
  1657. if (spin_trylock(&lnw->wq_lock)) {
  1658. langwell_update_transceiver();
  1659. spin_unlock(&lnw->wq_lock);
  1660. }
  1661. return count;
  1662. }
  1663. static DEVICE_ATTR(b_bus_req, S_IRUGO | S_IWUSR, get_b_bus_req, set_b_bus_req);
  1664. static ssize_t
  1665. set_a_clr_err(struct device *dev, struct device_attribute *attr,
  1666. const char *buf, size_t count)
  1667. {
  1668. struct langwell_otg *lnw = the_transceiver;
  1669. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1670. if (!iotg->otg.default_a)
  1671. return -1;
  1672. if (count > 2)
  1673. return -1;
  1674. if (buf[0] == '1') {
  1675. iotg->hsm.a_clr_err = 1;
  1676. dev_dbg(lnw->dev, "User request: a_clr_err = 1\n");
  1677. }
  1678. if (spin_trylock(&lnw->wq_lock)) {
  1679. langwell_update_transceiver();
  1680. spin_unlock(&lnw->wq_lock);
  1681. }
  1682. return count;
  1683. }
  1684. static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
  1685. static struct attribute *inputs_attrs[] = {
  1686. &dev_attr_a_bus_req.attr,
  1687. &dev_attr_a_bus_drop.attr,
  1688. &dev_attr_b_bus_req.attr,
  1689. &dev_attr_a_clr_err.attr,
  1690. NULL,
  1691. };
  1692. static struct attribute_group debug_dev_attr_group = {
  1693. .name = "inputs",
  1694. .attrs = inputs_attrs,
  1695. };
  1696. static int langwell_otg_probe(struct pci_dev *pdev,
  1697. const struct pci_device_id *id)
  1698. {
  1699. unsigned long resource, len;
  1700. void __iomem *base = NULL;
  1701. int retval;
  1702. u32 val32;
  1703. struct langwell_otg *lnw;
  1704. char qname[] = "langwell_otg_queue";
  1705. retval = 0;
  1706. dev_dbg(&pdev->dev, "\notg controller is detected.\n");
  1707. if (pci_enable_device(pdev) < 0) {
  1708. retval = -ENODEV;
  1709. goto done;
  1710. }
  1711. lnw = kzalloc(sizeof *lnw, GFP_KERNEL);
  1712. if (lnw == NULL) {
  1713. retval = -ENOMEM;
  1714. goto done;
  1715. }
  1716. the_transceiver = lnw;
  1717. /* control register: BAR 0 */
  1718. resource = pci_resource_start(pdev, 0);
  1719. len = pci_resource_len(pdev, 0);
  1720. if (!request_mem_region(resource, len, driver_name)) {
  1721. retval = -EBUSY;
  1722. goto err;
  1723. }
  1724. lnw->region = 1;
  1725. base = ioremap_nocache(resource, len);
  1726. if (base == NULL) {
  1727. retval = -EFAULT;
  1728. goto err;
  1729. }
  1730. lnw->iotg.base = base;
  1731. if (!request_mem_region(USBCFG_ADDR, USBCFG_LEN, driver_name)) {
  1732. retval = -EBUSY;
  1733. goto err;
  1734. }
  1735. lnw->cfg_region = 1;
  1736. /* For the SCCB.USBCFG register */
  1737. base = ioremap_nocache(USBCFG_ADDR, USBCFG_LEN);
  1738. if (base == NULL) {
  1739. retval = -EFAULT;
  1740. goto err;
  1741. }
  1742. lnw->usbcfg = base;
  1743. if (!pdev->irq) {
  1744. dev_dbg(&pdev->dev, "No IRQ.\n");
  1745. retval = -ENODEV;
  1746. goto err;
  1747. }
  1748. lnw->qwork = create_singlethread_workqueue(qname);
  1749. if (!lnw->qwork) {
  1750. dev_dbg(&pdev->dev, "cannot create workqueue %s\n", qname);
  1751. retval = -ENOMEM;
  1752. goto err;
  1753. }
  1754. INIT_WORK(&lnw->work, langwell_otg_work);
  1755. /* OTG common part */
  1756. lnw->dev = &pdev->dev;
  1757. lnw->iotg.otg.dev = lnw->dev;
  1758. lnw->iotg.otg.label = driver_name;
  1759. lnw->iotg.otg.set_host = langwell_otg_set_host;
  1760. lnw->iotg.otg.set_peripheral = langwell_otg_set_peripheral;
  1761. lnw->iotg.otg.set_power = langwell_otg_set_power;
  1762. lnw->iotg.otg.set_vbus = langwell_otg_set_vbus;
  1763. lnw->iotg.otg.start_srp = langwell_otg_start_srp;
  1764. lnw->iotg.otg.state = OTG_STATE_UNDEFINED;
  1765. if (otg_set_transceiver(&lnw->iotg.otg)) {
  1766. dev_dbg(lnw->dev, "can't set transceiver\n");
  1767. retval = -EBUSY;
  1768. goto err;
  1769. }
  1770. reset_otg();
  1771. init_hsm();
  1772. spin_lock_init(&lnw->lock);
  1773. spin_lock_init(&lnw->wq_lock);
  1774. INIT_LIST_HEAD(&active_timers);
  1775. retval = langwell_otg_init_timers(&lnw->iotg.hsm);
  1776. if (retval) {
  1777. dev_dbg(&pdev->dev, "Failed to init timers\n");
  1778. goto err;
  1779. }
  1780. init_timer(&lnw->hsm_timer);
  1781. ATOMIC_INIT_NOTIFIER_HEAD(&lnw->iotg.iotg_notifier);
  1782. lnw->iotg_notifier.notifier_call = langwell_otg_iotg_notify;
  1783. retval = intel_mid_otg_register_notifier(&lnw->iotg,
  1784. &lnw->iotg_notifier);
  1785. if (retval) {
  1786. dev_dbg(lnw->dev, "Failed to register notifier\n");
  1787. goto err;
  1788. }
  1789. if (request_irq(pdev->irq, otg_irq, IRQF_SHARED,
  1790. driver_name, lnw) != 0) {
  1791. dev_dbg(lnw->dev, "request interrupt %d failed\n", pdev->irq);
  1792. retval = -EBUSY;
  1793. goto err;
  1794. }
  1795. /* enable OTGSC int */
  1796. val32 = OTGSC_DPIE | OTGSC_BSEIE | OTGSC_BSVIE |
  1797. OTGSC_ASVIE | OTGSC_AVVIE | OTGSC_IDIE | OTGSC_IDPU;
  1798. writel(val32, lnw->iotg.base + CI_OTGSC);
  1799. retval = device_create_file(&pdev->dev, &dev_attr_registers);
  1800. if (retval < 0) {
  1801. dev_dbg(lnw->dev,
  1802. "Can't register sysfs attribute: %d\n", retval);
  1803. goto err;
  1804. }
  1805. retval = device_create_file(&pdev->dev, &dev_attr_hsm);
  1806. if (retval < 0) {
  1807. dev_dbg(lnw->dev, "Can't hsm sysfs attribute: %d\n", retval);
  1808. goto err;
  1809. }
  1810. retval = sysfs_create_group(&pdev->dev.kobj, &debug_dev_attr_group);
  1811. if (retval < 0) {
  1812. dev_dbg(lnw->dev,
  1813. "Can't register sysfs attr group: %d\n", retval);
  1814. goto err;
  1815. }
  1816. if (lnw->iotg.otg.state == OTG_STATE_A_IDLE)
  1817. langwell_update_transceiver();
  1818. return 0;
  1819. err:
  1820. if (the_transceiver)
  1821. langwell_otg_remove(pdev);
  1822. done:
  1823. return retval;
  1824. }
  1825. static void langwell_otg_remove(struct pci_dev *pdev)
  1826. {
  1827. struct langwell_otg *lnw = the_transceiver;
  1828. if (lnw->qwork) {
  1829. flush_workqueue(lnw->qwork);
  1830. destroy_workqueue(lnw->qwork);
  1831. }
  1832. intel_mid_otg_unregister_notifier(&lnw->iotg, &lnw->iotg_notifier);
  1833. langwell_otg_free_timers();
  1834. /* disable OTGSC interrupt as OTGSC doesn't change in reset */
  1835. writel(0, lnw->iotg.base + CI_OTGSC);
  1836. if (pdev->irq)
  1837. free_irq(pdev->irq, lnw);
  1838. if (lnw->usbcfg)
  1839. iounmap(lnw->usbcfg);
  1840. if (lnw->cfg_region)
  1841. release_mem_region(USBCFG_ADDR, USBCFG_LEN);
  1842. if (lnw->iotg.base)
  1843. iounmap(lnw->iotg.base);
  1844. if (lnw->region)
  1845. release_mem_region(pci_resource_start(pdev, 0),
  1846. pci_resource_len(pdev, 0));
  1847. otg_set_transceiver(NULL);
  1848. pci_disable_device(pdev);
  1849. sysfs_remove_group(&pdev->dev.kobj, &debug_dev_attr_group);
  1850. device_remove_file(&pdev->dev, &dev_attr_hsm);
  1851. device_remove_file(&pdev->dev, &dev_attr_registers);
  1852. kfree(lnw);
  1853. lnw = NULL;
  1854. }
  1855. static void transceiver_suspend(struct pci_dev *pdev)
  1856. {
  1857. pci_save_state(pdev);
  1858. pci_set_power_state(pdev, PCI_D3hot);
  1859. langwell_otg_phy_low_power(1);
  1860. }
  1861. static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message)
  1862. {
  1863. struct langwell_otg *lnw = the_transceiver;
  1864. struct intel_mid_otg_xceiv *iotg = &lnw->iotg;
  1865. int ret = 0;
  1866. /* Disbale OTG interrupts */
  1867. langwell_otg_intr(0);
  1868. if (pdev->irq)
  1869. free_irq(pdev->irq, lnw);
  1870. /* Prevent more otg_work */
  1871. flush_workqueue(lnw->qwork);
  1872. destroy_workqueue(lnw->qwork);
  1873. lnw->qwork = NULL;
  1874. /* start actions */
  1875. switch (iotg->otg.state) {
  1876. case OTG_STATE_A_WAIT_VFALL:
  1877. iotg->otg.state = OTG_STATE_A_IDLE;
  1878. case OTG_STATE_A_IDLE:
  1879. case OTG_STATE_B_IDLE:
  1880. case OTG_STATE_A_VBUS_ERR:
  1881. transceiver_suspend(pdev);
  1882. break;
  1883. case OTG_STATE_A_WAIT_VRISE:
  1884. langwell_otg_del_timer(a_wait_vrise_tmr);
  1885. iotg->hsm.a_srp_det = 0;
  1886. /* Turn off VBus */
  1887. iotg->otg.set_vbus(&iotg->otg, false);
  1888. iotg->otg.state = OTG_STATE_A_IDLE;
  1889. transceiver_suspend(pdev);
  1890. break;
  1891. case OTG_STATE_A_WAIT_BCON:
  1892. del_timer_sync(&lnw->hsm_timer);
  1893. if (lnw->iotg.stop_host)
  1894. lnw->iotg.stop_host(&lnw->iotg);
  1895. else
  1896. dev_dbg(&pdev->dev, "host driver has been removed.\n");
  1897. iotg->hsm.a_srp_det = 0;
  1898. /* Turn off VBus */
  1899. iotg->otg.set_vbus(&iotg->otg, false);
  1900. iotg->otg.state = OTG_STATE_A_IDLE;
  1901. transceiver_suspend(pdev);
  1902. break;
  1903. case OTG_STATE_A_HOST:
  1904. if (lnw->iotg.stop_host)
  1905. lnw->iotg.stop_host(&lnw->iotg);
  1906. else
  1907. dev_dbg(&pdev->dev, "host driver has been removed.\n");
  1908. iotg->hsm.a_srp_det = 0;
  1909. /* Turn off VBus */
  1910. iotg->otg.set_vbus(&iotg->otg, false);
  1911. iotg->otg.state = OTG_STATE_A_IDLE;
  1912. transceiver_suspend(pdev);
  1913. break;
  1914. case OTG_STATE_A_SUSPEND:
  1915. langwell_otg_del_timer(a_aidl_bdis_tmr);
  1916. langwell_otg_HABA(0);
  1917. if (lnw->iotg.stop_host)
  1918. lnw->iotg.stop_host(&lnw->iotg);
  1919. else
  1920. dev_dbg(lnw->dev, "host driver has been removed.\n");
  1921. iotg->hsm.a_srp_det = 0;
  1922. /* Turn off VBus */
  1923. iotg->otg.set_vbus(&iotg->otg, false);
  1924. iotg->otg.state = OTG_STATE_A_IDLE;
  1925. transceiver_suspend(pdev);
  1926. break;
  1927. case OTG_STATE_A_PERIPHERAL:
  1928. del_timer_sync(&lnw->hsm_timer);
  1929. if (lnw->iotg.stop_peripheral)
  1930. lnw->iotg.stop_peripheral(&lnw->iotg);
  1931. else
  1932. dev_dbg(&pdev->dev,
  1933. "client driver has been removed.\n");
  1934. iotg->hsm.a_srp_det = 0;
  1935. /* Turn off VBus */
  1936. iotg->otg.set_vbus(&iotg->otg, false);
  1937. iotg->otg.state = OTG_STATE_A_IDLE;
  1938. transceiver_suspend(pdev);
  1939. break;
  1940. case OTG_STATE_B_HOST:
  1941. if (lnw->iotg.stop_host)
  1942. lnw->iotg.stop_host(&lnw->iotg);
  1943. else
  1944. dev_dbg(&pdev->dev, "host driver has been removed.\n");
  1945. iotg->hsm.b_bus_req = 0;
  1946. iotg->otg.state = OTG_STATE_B_IDLE;
  1947. transceiver_suspend(pdev);
  1948. break;
  1949. case OTG_STATE_B_PERIPHERAL:
  1950. if (lnw->iotg.stop_peripheral)
  1951. lnw->iotg.stop_peripheral(&lnw->iotg);
  1952. else
  1953. dev_dbg(&pdev->dev,
  1954. "client driver has been removed.\n");
  1955. iotg->otg.state = OTG_STATE_B_IDLE;
  1956. transceiver_suspend(pdev);
  1957. break;
  1958. case OTG_STATE_B_WAIT_ACON:
  1959. /* delete hsm timer for b_ase0_brst_tmr */
  1960. del_timer_sync(&lnw->hsm_timer);
  1961. langwell_otg_HAAR(0);
  1962. if (lnw->iotg.stop_host)
  1963. lnw->iotg.stop_host(&lnw->iotg);
  1964. else
  1965. dev_dbg(&pdev->dev, "host driver has been removed.\n");
  1966. iotg->hsm.b_bus_req = 0;
  1967. iotg->otg.state = OTG_STATE_B_IDLE;
  1968. transceiver_suspend(pdev);
  1969. break;
  1970. default:
  1971. dev_dbg(lnw->dev, "error state before suspend\n");
  1972. break;
  1973. }
  1974. return ret;
  1975. }
  1976. static void transceiver_resume(struct pci_dev *pdev)
  1977. {
  1978. pci_restore_state(pdev);
  1979. pci_set_power_state(pdev, PCI_D0);
  1980. }
  1981. static int langwell_otg_resume(struct pci_dev *pdev)
  1982. {
  1983. struct langwell_otg *lnw = the_transceiver;
  1984. int ret = 0;
  1985. transceiver_resume(pdev);
  1986. lnw->qwork = create_singlethread_workqueue("langwell_otg_queue");
  1987. if (!lnw->qwork) {
  1988. dev_dbg(&pdev->dev, "cannot create langwell otg workqueuen");
  1989. ret = -ENOMEM;
  1990. goto error;
  1991. }
  1992. if (request_irq(pdev->irq, otg_irq, IRQF_SHARED,
  1993. driver_name, lnw) != 0) {
  1994. dev_dbg(&pdev->dev, "request interrupt %d failed\n", pdev->irq);
  1995. ret = -EBUSY;
  1996. goto error;
  1997. }
  1998. /* enable OTG interrupts */
  1999. langwell_otg_intr(1);
  2000. update_hsm();
  2001. langwell_update_transceiver();
  2002. return ret;
  2003. error:
  2004. langwell_otg_intr(0);
  2005. transceiver_suspend(pdev);
  2006. return ret;
  2007. }
  2008. static int __init langwell_otg_init(void)
  2009. {
  2010. return pci_register_driver(&otg_pci_driver);
  2011. }
  2012. module_init(langwell_otg_init);
  2013. static void __exit langwell_otg_cleanup(void)
  2014. {
  2015. pci_unregister_driver(&otg_pci_driver);
  2016. }
  2017. module_exit(langwell_otg_cleanup);