omap2430.c 13 KB

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  1. /*
  2. * Copyright (C) 2005-2007 by Texas Instruments
  3. * Some code has been taken from tusb6010.c
  4. * Copyrights for that are attributable to:
  5. * Copyright (C) 2006 Nokia Corporation
  6. * Tony Lindgren <tony@atomide.com>
  7. *
  8. * This file is part of the Inventra Controller Driver for Linux.
  9. *
  10. * The Inventra Controller Driver for Linux is free software; you
  11. * can redistribute it and/or modify it under the terms of the GNU
  12. * General Public License version 2 as published by the Free Software
  13. * Foundation.
  14. *
  15. * The Inventra Controller Driver for Linux is distributed in
  16. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  17. * without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  19. * License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with The Inventra Controller Driver for Linux ; if not,
  23. * write to the Free Software Foundation, Inc., 59 Temple Place,
  24. * Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/sched.h>
  30. #include <linux/init.h>
  31. #include <linux/list.h>
  32. #include <linux/clk.h>
  33. #include <linux/io.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/pm_runtime.h>
  37. #include <linux/err.h>
  38. #include "musb_core.h"
  39. #include "omap2430.h"
  40. struct omap2430_glue {
  41. struct device *dev;
  42. struct platform_device *musb;
  43. };
  44. #define glue_to_musb(g) platform_get_drvdata(g->musb)
  45. static struct timer_list musb_idle_timer;
  46. static void musb_do_idle(unsigned long _musb)
  47. {
  48. struct musb *musb = (void *)_musb;
  49. unsigned long flags;
  50. u8 power;
  51. u8 devctl;
  52. spin_lock_irqsave(&musb->lock, flags);
  53. switch (musb->xceiv->state) {
  54. case OTG_STATE_A_WAIT_BCON:
  55. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  56. if (devctl & MUSB_DEVCTL_BDEVICE) {
  57. musb->xceiv->state = OTG_STATE_B_IDLE;
  58. MUSB_DEV_MODE(musb);
  59. } else {
  60. musb->xceiv->state = OTG_STATE_A_IDLE;
  61. MUSB_HST_MODE(musb);
  62. }
  63. break;
  64. case OTG_STATE_A_SUSPEND:
  65. /* finish RESUME signaling? */
  66. if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
  67. power = musb_readb(musb->mregs, MUSB_POWER);
  68. power &= ~MUSB_POWER_RESUME;
  69. dev_dbg(musb->controller, "root port resume stopped, power %02x\n", power);
  70. musb_writeb(musb->mregs, MUSB_POWER, power);
  71. musb->is_active = 1;
  72. musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
  73. | MUSB_PORT_STAT_RESUME);
  74. musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
  75. usb_hcd_poll_rh_status(musb_to_hcd(musb));
  76. /* NOTE: it might really be A_WAIT_BCON ... */
  77. musb->xceiv->state = OTG_STATE_A_HOST;
  78. }
  79. break;
  80. case OTG_STATE_A_HOST:
  81. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  82. if (devctl & MUSB_DEVCTL_BDEVICE)
  83. musb->xceiv->state = OTG_STATE_B_IDLE;
  84. else
  85. musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  86. default:
  87. break;
  88. }
  89. spin_unlock_irqrestore(&musb->lock, flags);
  90. }
  91. static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
  92. {
  93. unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
  94. static unsigned long last_timer;
  95. if (timeout == 0)
  96. timeout = default_timeout;
  97. /* Never idle if active, or when VBUS timeout is not set as host */
  98. if (musb->is_active || ((musb->a_wait_bcon == 0)
  99. && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
  100. dev_dbg(musb->controller, "%s active, deleting timer\n",
  101. otg_state_string(musb->xceiv->state));
  102. del_timer(&musb_idle_timer);
  103. last_timer = jiffies;
  104. return;
  105. }
  106. if (time_after(last_timer, timeout)) {
  107. if (!timer_pending(&musb_idle_timer))
  108. last_timer = timeout;
  109. else {
  110. dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
  111. return;
  112. }
  113. }
  114. last_timer = timeout;
  115. dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
  116. otg_state_string(musb->xceiv->state),
  117. (unsigned long)jiffies_to_msecs(timeout - jiffies));
  118. mod_timer(&musb_idle_timer, timeout);
  119. }
  120. static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
  121. {
  122. u8 devctl;
  123. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  124. int ret = 1;
  125. /* HDRC controls CPEN, but beware current surges during device
  126. * connect. They can trigger transient overcurrent conditions
  127. * that must be ignored.
  128. */
  129. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  130. if (is_on) {
  131. if (musb->xceiv->state == OTG_STATE_A_IDLE) {
  132. /* start the session */
  133. devctl |= MUSB_DEVCTL_SESSION;
  134. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  135. /*
  136. * Wait for the musb to set as A device to enable the
  137. * VBUS
  138. */
  139. while (musb_readb(musb->mregs, MUSB_DEVCTL) & 0x80) {
  140. cpu_relax();
  141. if (time_after(jiffies, timeout)) {
  142. dev_err(musb->controller,
  143. "configured as A device timeout");
  144. ret = -EINVAL;
  145. break;
  146. }
  147. }
  148. if (ret && musb->xceiv->set_vbus)
  149. otg_set_vbus(musb->xceiv, 1);
  150. } else {
  151. musb->is_active = 1;
  152. musb->xceiv->default_a = 1;
  153. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  154. devctl |= MUSB_DEVCTL_SESSION;
  155. MUSB_HST_MODE(musb);
  156. }
  157. } else {
  158. musb->is_active = 0;
  159. /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
  160. * jumping right to B_IDLE...
  161. */
  162. musb->xceiv->default_a = 0;
  163. musb->xceiv->state = OTG_STATE_B_IDLE;
  164. devctl &= ~MUSB_DEVCTL_SESSION;
  165. MUSB_DEV_MODE(musb);
  166. }
  167. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  168. dev_dbg(musb->controller, "VBUS %s, devctl %02x "
  169. /* otg %3x conf %08x prcm %08x */ "\n",
  170. otg_state_string(musb->xceiv->state),
  171. musb_readb(musb->mregs, MUSB_DEVCTL));
  172. }
  173. static int omap2430_musb_set_mode(struct musb *musb, u8 musb_mode)
  174. {
  175. u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  176. devctl |= MUSB_DEVCTL_SESSION;
  177. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  178. return 0;
  179. }
  180. static inline void omap2430_low_level_exit(struct musb *musb)
  181. {
  182. u32 l;
  183. /* in any role */
  184. l = musb_readl(musb->mregs, OTG_FORCESTDBY);
  185. l |= ENABLEFORCE; /* enable MSTANDBY */
  186. musb_writel(musb->mregs, OTG_FORCESTDBY, l);
  187. }
  188. static inline void omap2430_low_level_init(struct musb *musb)
  189. {
  190. u32 l;
  191. l = musb_readl(musb->mregs, OTG_FORCESTDBY);
  192. l &= ~ENABLEFORCE; /* disable MSTANDBY */
  193. musb_writel(musb->mregs, OTG_FORCESTDBY, l);
  194. }
  195. /* blocking notifier support */
  196. static int musb_otg_notifications(struct notifier_block *nb,
  197. unsigned long event, void *unused)
  198. {
  199. struct musb *musb = container_of(nb, struct musb, nb);
  200. struct device *dev = musb->controller;
  201. struct musb_hdrc_platform_data *pdata = dev->platform_data;
  202. struct omap_musb_board_data *data = pdata->board_data;
  203. switch (event) {
  204. case USB_EVENT_ID:
  205. dev_dbg(musb->controller, "ID GND\n");
  206. if (is_otg_enabled(musb)) {
  207. if (musb->gadget_driver) {
  208. pm_runtime_get_sync(musb->controller);
  209. otg_init(musb->xceiv);
  210. omap2430_musb_set_vbus(musb, 1);
  211. }
  212. } else {
  213. pm_runtime_get_sync(musb->controller);
  214. otg_init(musb->xceiv);
  215. omap2430_musb_set_vbus(musb, 1);
  216. }
  217. break;
  218. case USB_EVENT_VBUS:
  219. dev_dbg(musb->controller, "VBUS Connect\n");
  220. if (musb->gadget_driver)
  221. pm_runtime_get_sync(musb->controller);
  222. otg_init(musb->xceiv);
  223. break;
  224. case USB_EVENT_NONE:
  225. dev_dbg(musb->controller, "VBUS Disconnect\n");
  226. if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
  227. if (musb->gadget_driver) {
  228. pm_runtime_mark_last_busy(musb->controller);
  229. pm_runtime_put_autosuspend(musb->controller);
  230. }
  231. if (data->interface_type == MUSB_INTERFACE_UTMI) {
  232. if (musb->xceiv->set_vbus)
  233. otg_set_vbus(musb->xceiv, 0);
  234. }
  235. otg_shutdown(musb->xceiv);
  236. break;
  237. default:
  238. dev_dbg(musb->controller, "ID float\n");
  239. return NOTIFY_DONE;
  240. }
  241. return NOTIFY_OK;
  242. }
  243. static int omap2430_musb_init(struct musb *musb)
  244. {
  245. u32 l, status = 0;
  246. struct device *dev = musb->controller;
  247. struct musb_hdrc_platform_data *plat = dev->platform_data;
  248. struct omap_musb_board_data *data = plat->board_data;
  249. /* We require some kind of external transceiver, hooked
  250. * up through ULPI. TWL4030-family PMICs include one,
  251. * which needs a driver, drivers aren't always needed.
  252. */
  253. musb->xceiv = otg_get_transceiver();
  254. if (!musb->xceiv) {
  255. pr_err("HS USB OTG: no transceiver configured\n");
  256. return -ENODEV;
  257. }
  258. status = pm_runtime_get_sync(dev);
  259. if (status < 0) {
  260. dev_err(dev, "pm_runtime_get_sync FAILED");
  261. goto err1;
  262. }
  263. l = musb_readl(musb->mregs, OTG_INTERFSEL);
  264. if (data->interface_type == MUSB_INTERFACE_UTMI) {
  265. /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
  266. l &= ~ULPI_12PIN; /* Disable ULPI */
  267. l |= UTMI_8BIT; /* Enable UTMI */
  268. } else {
  269. l |= ULPI_12PIN;
  270. }
  271. musb_writel(musb->mregs, OTG_INTERFSEL, l);
  272. pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
  273. "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
  274. musb_readl(musb->mregs, OTG_REVISION),
  275. musb_readl(musb->mregs, OTG_SYSCONFIG),
  276. musb_readl(musb->mregs, OTG_SYSSTATUS),
  277. musb_readl(musb->mregs, OTG_INTERFSEL),
  278. musb_readl(musb->mregs, OTG_SIMENABLE));
  279. musb->nb.notifier_call = musb_otg_notifications;
  280. status = otg_register_notifier(musb->xceiv, &musb->nb);
  281. if (status)
  282. dev_dbg(musb->controller, "notification register failed\n");
  283. setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
  284. return 0;
  285. err1:
  286. pm_runtime_disable(dev);
  287. return status;
  288. }
  289. static void omap2430_musb_enable(struct musb *musb)
  290. {
  291. u8 devctl;
  292. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  293. struct device *dev = musb->controller;
  294. struct musb_hdrc_platform_data *pdata = dev->platform_data;
  295. struct omap_musb_board_data *data = pdata->board_data;
  296. switch (musb->xceiv->last_event) {
  297. case USB_EVENT_ID:
  298. otg_init(musb->xceiv);
  299. if (data->interface_type == MUSB_INTERFACE_UTMI) {
  300. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  301. /* start the session */
  302. devctl |= MUSB_DEVCTL_SESSION;
  303. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  304. while (musb_readb(musb->mregs, MUSB_DEVCTL) &
  305. MUSB_DEVCTL_BDEVICE) {
  306. cpu_relax();
  307. if (time_after(jiffies, timeout)) {
  308. dev_err(musb->controller,
  309. "configured as A device timeout");
  310. break;
  311. }
  312. }
  313. }
  314. break;
  315. case USB_EVENT_VBUS:
  316. otg_init(musb->xceiv);
  317. break;
  318. default:
  319. break;
  320. }
  321. }
  322. static void omap2430_musb_disable(struct musb *musb)
  323. {
  324. if (musb->xceiv->last_event)
  325. otg_shutdown(musb->xceiv);
  326. }
  327. static int omap2430_musb_exit(struct musb *musb)
  328. {
  329. del_timer_sync(&musb_idle_timer);
  330. omap2430_low_level_exit(musb);
  331. otg_put_transceiver(musb->xceiv);
  332. return 0;
  333. }
  334. static const struct musb_platform_ops omap2430_ops = {
  335. .init = omap2430_musb_init,
  336. .exit = omap2430_musb_exit,
  337. .set_mode = omap2430_musb_set_mode,
  338. .try_idle = omap2430_musb_try_idle,
  339. .set_vbus = omap2430_musb_set_vbus,
  340. .enable = omap2430_musb_enable,
  341. .disable = omap2430_musb_disable,
  342. };
  343. static u64 omap2430_dmamask = DMA_BIT_MASK(32);
  344. static int __init omap2430_probe(struct platform_device *pdev)
  345. {
  346. struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
  347. struct platform_device *musb;
  348. struct omap2430_glue *glue;
  349. int ret = -ENOMEM;
  350. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  351. if (!glue) {
  352. dev_err(&pdev->dev, "failed to allocate glue context\n");
  353. goto err0;
  354. }
  355. musb = platform_device_alloc("musb-hdrc", -1);
  356. if (!musb) {
  357. dev_err(&pdev->dev, "failed to allocate musb device\n");
  358. goto err1;
  359. }
  360. musb->dev.parent = &pdev->dev;
  361. musb->dev.dma_mask = &omap2430_dmamask;
  362. musb->dev.coherent_dma_mask = omap2430_dmamask;
  363. glue->dev = &pdev->dev;
  364. glue->musb = musb;
  365. pdata->platform_ops = &omap2430_ops;
  366. platform_set_drvdata(pdev, glue);
  367. ret = platform_device_add_resources(musb, pdev->resource,
  368. pdev->num_resources);
  369. if (ret) {
  370. dev_err(&pdev->dev, "failed to add resources\n");
  371. goto err2;
  372. }
  373. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  374. if (ret) {
  375. dev_err(&pdev->dev, "failed to add platform_data\n");
  376. goto err2;
  377. }
  378. ret = platform_device_add(musb);
  379. if (ret) {
  380. dev_err(&pdev->dev, "failed to register musb device\n");
  381. goto err2;
  382. }
  383. pm_runtime_enable(&pdev->dev);
  384. return 0;
  385. err2:
  386. platform_device_put(musb);
  387. err1:
  388. kfree(glue);
  389. err0:
  390. return ret;
  391. }
  392. static int __exit omap2430_remove(struct platform_device *pdev)
  393. {
  394. struct omap2430_glue *glue = platform_get_drvdata(pdev);
  395. platform_device_del(glue->musb);
  396. platform_device_put(glue->musb);
  397. pm_runtime_put(&pdev->dev);
  398. pm_runtime_disable(&pdev->dev);
  399. kfree(glue);
  400. return 0;
  401. }
  402. #ifdef CONFIG_PM
  403. static int omap2430_runtime_suspend(struct device *dev)
  404. {
  405. struct omap2430_glue *glue = dev_get_drvdata(dev);
  406. struct musb *musb = glue_to_musb(glue);
  407. omap2430_low_level_exit(musb);
  408. otg_set_suspend(musb->xceiv, 1);
  409. return 0;
  410. }
  411. static int omap2430_runtime_resume(struct device *dev)
  412. {
  413. struct omap2430_glue *glue = dev_get_drvdata(dev);
  414. struct musb *musb = glue_to_musb(glue);
  415. omap2430_low_level_init(musb);
  416. otg_set_suspend(musb->xceiv, 0);
  417. return 0;
  418. }
  419. static struct dev_pm_ops omap2430_pm_ops = {
  420. .runtime_suspend = omap2430_runtime_suspend,
  421. .runtime_resume = omap2430_runtime_resume,
  422. };
  423. #define DEV_PM_OPS (&omap2430_pm_ops)
  424. #else
  425. #define DEV_PM_OPS NULL
  426. #endif
  427. static struct platform_driver omap2430_driver = {
  428. .remove = __exit_p(omap2430_remove),
  429. .driver = {
  430. .name = "musb-omap2430",
  431. .pm = DEV_PM_OPS,
  432. },
  433. };
  434. MODULE_DESCRIPTION("OMAP2PLUS MUSB Glue Layer");
  435. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  436. MODULE_LICENSE("GPL v2");
  437. static int __init omap2430_init(void)
  438. {
  439. return platform_driver_probe(&omap2430_driver, omap2430_probe);
  440. }
  441. subsys_initcall(omap2430_init);
  442. static void __exit omap2430_exit(void)
  443. {
  444. platform_driver_unregister(&omap2430_driver);
  445. }
  446. module_exit(omap2430_exit);