c67x00-sched.c 30 KB

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  1. /*
  2. * c67x00-sched.c: Cypress C67X00 USB Host Controller Driver - TD scheduling
  3. *
  4. * Copyright (C) 2006-2008 Barco N.V.
  5. * Derived from the Cypress cy7c67200/300 ezusb linux driver and
  6. * based on multiple host controller drivers inside the linux kernel.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  21. * MA 02110-1301 USA.
  22. */
  23. #include <linux/kthread.h>
  24. #include <linux/slab.h>
  25. #include "c67x00.h"
  26. #include "c67x00-hcd.h"
  27. /*
  28. * These are the stages for a control urb, they are kept
  29. * in both urb->interval and td->privdata.
  30. */
  31. #define SETUP_STAGE 0
  32. #define DATA_STAGE 1
  33. #define STATUS_STAGE 2
  34. /* -------------------------------------------------------------------------- */
  35. /**
  36. * struct c67x00_ep_data: Host endpoint data structure
  37. */
  38. struct c67x00_ep_data {
  39. struct list_head queue;
  40. struct list_head node;
  41. struct usb_host_endpoint *hep;
  42. struct usb_device *dev;
  43. u16 next_frame; /* For int/isoc transactions */
  44. };
  45. /**
  46. * struct c67x00_td
  47. *
  48. * Hardware parts are little endiannes, SW in CPU endianess.
  49. */
  50. struct c67x00_td {
  51. /* HW specific part */
  52. __le16 ly_base_addr; /* Bytes 0-1 */
  53. __le16 port_length; /* Bytes 2-3 */
  54. u8 pid_ep; /* Byte 4 */
  55. u8 dev_addr; /* Byte 5 */
  56. u8 ctrl_reg; /* Byte 6 */
  57. u8 status; /* Byte 7 */
  58. u8 retry_cnt; /* Byte 8 */
  59. #define TT_OFFSET 2
  60. #define TT_CONTROL 0
  61. #define TT_ISOCHRONOUS 1
  62. #define TT_BULK 2
  63. #define TT_INTERRUPT 3
  64. u8 residue; /* Byte 9 */
  65. __le16 next_td_addr; /* Bytes 10-11 */
  66. /* SW part */
  67. struct list_head td_list;
  68. u16 td_addr;
  69. void *data;
  70. struct urb *urb;
  71. unsigned long privdata;
  72. /* These are needed for handling the toggle bits:
  73. * an urb can be dequeued while a td is in progress
  74. * after checking the td, the toggle bit might need to
  75. * be fixed */
  76. struct c67x00_ep_data *ep_data;
  77. unsigned int pipe;
  78. };
  79. struct c67x00_urb_priv {
  80. struct list_head hep_node;
  81. struct urb *urb;
  82. int port;
  83. int cnt; /* packet number for isoc */
  84. int status;
  85. struct c67x00_ep_data *ep_data;
  86. };
  87. #define td_udev(td) ((td)->ep_data->dev)
  88. #define CY_TD_SIZE 12
  89. #define TD_PIDEP_OFFSET 0x04
  90. #define TD_PIDEPMASK_PID 0xF0
  91. #define TD_PIDEPMASK_EP 0x0F
  92. #define TD_PORTLENMASK_DL 0x02FF
  93. #define TD_PORTLENMASK_PN 0xC000
  94. #define TD_STATUS_OFFSET 0x07
  95. #define TD_STATUSMASK_ACK 0x01
  96. #define TD_STATUSMASK_ERR 0x02
  97. #define TD_STATUSMASK_TMOUT 0x04
  98. #define TD_STATUSMASK_SEQ 0x08
  99. #define TD_STATUSMASK_SETUP 0x10
  100. #define TD_STATUSMASK_OVF 0x20
  101. #define TD_STATUSMASK_NAK 0x40
  102. #define TD_STATUSMASK_STALL 0x80
  103. #define TD_ERROR_MASK (TD_STATUSMASK_ERR | TD_STATUSMASK_TMOUT | \
  104. TD_STATUSMASK_STALL)
  105. #define TD_RETRYCNT_OFFSET 0x08
  106. #define TD_RETRYCNTMASK_ACT_FLG 0x10
  107. #define TD_RETRYCNTMASK_TX_TYPE 0x0C
  108. #define TD_RETRYCNTMASK_RTY_CNT 0x03
  109. #define TD_RESIDUE_OVERFLOW 0x80
  110. #define TD_PID_IN 0x90
  111. /* Residue: signed 8bits, neg -> OVERFLOW, pos -> UNDERFLOW */
  112. #define td_residue(td) ((__s8)(td->residue))
  113. #define td_ly_base_addr(td) (__le16_to_cpu((td)->ly_base_addr))
  114. #define td_port_length(td) (__le16_to_cpu((td)->port_length))
  115. #define td_next_td_addr(td) (__le16_to_cpu((td)->next_td_addr))
  116. #define td_active(td) ((td)->retry_cnt & TD_RETRYCNTMASK_ACT_FLG)
  117. #define td_length(td) (td_port_length(td) & TD_PORTLENMASK_DL)
  118. #define td_sequence_ok(td) (!td->status || \
  119. (!(td->status & TD_STATUSMASK_SEQ) == \
  120. !(td->ctrl_reg & SEQ_SEL)))
  121. #define td_acked(td) (!td->status || \
  122. (td->status & TD_STATUSMASK_ACK))
  123. #define td_actual_bytes(td) (td_length(td) - td_residue(td))
  124. /* -------------------------------------------------------------------------- */
  125. #ifdef DEBUG
  126. /**
  127. * dbg_td - Dump the contents of the TD
  128. */
  129. static void dbg_td(struct c67x00_hcd *c67x00, struct c67x00_td *td, char *msg)
  130. {
  131. struct device *dev = c67x00_hcd_dev(c67x00);
  132. dev_dbg(dev, "### %s at 0x%04x\n", msg, td->td_addr);
  133. dev_dbg(dev, "urb: 0x%p\n", td->urb);
  134. dev_dbg(dev, "endpoint: %4d\n", usb_pipeendpoint(td->pipe));
  135. dev_dbg(dev, "pipeout: %4d\n", usb_pipeout(td->pipe));
  136. dev_dbg(dev, "ly_base_addr: 0x%04x\n", td_ly_base_addr(td));
  137. dev_dbg(dev, "port_length: 0x%04x\n", td_port_length(td));
  138. dev_dbg(dev, "pid_ep: 0x%02x\n", td->pid_ep);
  139. dev_dbg(dev, "dev_addr: 0x%02x\n", td->dev_addr);
  140. dev_dbg(dev, "ctrl_reg: 0x%02x\n", td->ctrl_reg);
  141. dev_dbg(dev, "status: 0x%02x\n", td->status);
  142. dev_dbg(dev, "retry_cnt: 0x%02x\n", td->retry_cnt);
  143. dev_dbg(dev, "residue: 0x%02x\n", td->residue);
  144. dev_dbg(dev, "next_td_addr: 0x%04x\n", td_next_td_addr(td));
  145. dev_dbg(dev, "data:");
  146. print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
  147. td->data, td_length(td), 1);
  148. }
  149. #else /* DEBUG */
  150. static inline void
  151. dbg_td(struct c67x00_hcd *c67x00, struct c67x00_td *td, char *msg) { }
  152. #endif /* DEBUG */
  153. /* -------------------------------------------------------------------------- */
  154. /* Helper functions */
  155. static inline u16 c67x00_get_current_frame_number(struct c67x00_hcd *c67x00)
  156. {
  157. return c67x00_ll_husb_get_frame(c67x00->sie) & HOST_FRAME_MASK;
  158. }
  159. /**
  160. * frame_add
  161. * Software wraparound for framenumbers.
  162. */
  163. static inline u16 frame_add(u16 a, u16 b)
  164. {
  165. return (a + b) & HOST_FRAME_MASK;
  166. }
  167. /**
  168. * frame_after - is frame a after frame b
  169. */
  170. static inline int frame_after(u16 a, u16 b)
  171. {
  172. return ((HOST_FRAME_MASK + a - b) & HOST_FRAME_MASK) <
  173. (HOST_FRAME_MASK / 2);
  174. }
  175. /**
  176. * frame_after_eq - is frame a after or equal to frame b
  177. */
  178. static inline int frame_after_eq(u16 a, u16 b)
  179. {
  180. return ((HOST_FRAME_MASK + 1 + a - b) & HOST_FRAME_MASK) <
  181. (HOST_FRAME_MASK / 2);
  182. }
  183. /* -------------------------------------------------------------------------- */
  184. /**
  185. * c67x00_release_urb - remove link from all tds to this urb
  186. * Disconnects the urb from it's tds, so that it can be given back.
  187. * pre: urb->hcpriv != NULL
  188. */
  189. static void c67x00_release_urb(struct c67x00_hcd *c67x00, struct urb *urb)
  190. {
  191. struct c67x00_td *td;
  192. struct c67x00_urb_priv *urbp;
  193. BUG_ON(!urb);
  194. c67x00->urb_count--;
  195. if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
  196. c67x00->urb_iso_count--;
  197. if (c67x00->urb_iso_count == 0)
  198. c67x00->max_frame_bw = MAX_FRAME_BW_STD;
  199. }
  200. /* TODO this might be not so efficient when we've got many urbs!
  201. * Alternatives:
  202. * * only clear when needed
  203. * * keep a list of tds with each urbp
  204. */
  205. list_for_each_entry(td, &c67x00->td_list, td_list)
  206. if (urb == td->urb)
  207. td->urb = NULL;
  208. urbp = urb->hcpriv;
  209. urb->hcpriv = NULL;
  210. list_del(&urbp->hep_node);
  211. kfree(urbp);
  212. }
  213. /* -------------------------------------------------------------------------- */
  214. static struct c67x00_ep_data *
  215. c67x00_ep_data_alloc(struct c67x00_hcd *c67x00, struct urb *urb)
  216. {
  217. struct usb_host_endpoint *hep = urb->ep;
  218. struct c67x00_ep_data *ep_data;
  219. int type;
  220. c67x00->current_frame = c67x00_get_current_frame_number(c67x00);
  221. /* Check if endpoint already has a c67x00_ep_data struct allocated */
  222. if (hep->hcpriv) {
  223. ep_data = hep->hcpriv;
  224. if (frame_after(c67x00->current_frame, ep_data->next_frame))
  225. ep_data->next_frame =
  226. frame_add(c67x00->current_frame, 1);
  227. return hep->hcpriv;
  228. }
  229. /* Allocate and initialize a new c67x00 endpoint data structure */
  230. ep_data = kzalloc(sizeof(*ep_data), GFP_ATOMIC);
  231. if (!ep_data)
  232. return NULL;
  233. INIT_LIST_HEAD(&ep_data->queue);
  234. INIT_LIST_HEAD(&ep_data->node);
  235. ep_data->hep = hep;
  236. /* hold a reference to udev as long as this endpoint lives,
  237. * this is needed to possibly fix the data toggle */
  238. ep_data->dev = usb_get_dev(urb->dev);
  239. hep->hcpriv = ep_data;
  240. /* For ISOC and INT endpoints, start ASAP: */
  241. ep_data->next_frame = frame_add(c67x00->current_frame, 1);
  242. /* Add the endpoint data to one of the pipe lists; must be added
  243. in order of endpoint address */
  244. type = usb_pipetype(urb->pipe);
  245. if (list_empty(&ep_data->node)) {
  246. list_add(&ep_data->node, &c67x00->list[type]);
  247. } else {
  248. struct c67x00_ep_data *prev;
  249. list_for_each_entry(prev, &c67x00->list[type], node) {
  250. if (prev->hep->desc.bEndpointAddress >
  251. hep->desc.bEndpointAddress) {
  252. list_add(&ep_data->node, prev->node.prev);
  253. break;
  254. }
  255. }
  256. }
  257. return ep_data;
  258. }
  259. static int c67x00_ep_data_free(struct usb_host_endpoint *hep)
  260. {
  261. struct c67x00_ep_data *ep_data = hep->hcpriv;
  262. if (!ep_data)
  263. return 0;
  264. if (!list_empty(&ep_data->queue))
  265. return -EBUSY;
  266. usb_put_dev(ep_data->dev);
  267. list_del(&ep_data->queue);
  268. list_del(&ep_data->node);
  269. kfree(ep_data);
  270. hep->hcpriv = NULL;
  271. return 0;
  272. }
  273. void c67x00_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
  274. {
  275. struct c67x00_hcd *c67x00 = hcd_to_c67x00_hcd(hcd);
  276. unsigned long flags;
  277. if (!list_empty(&ep->urb_list))
  278. dev_warn(c67x00_hcd_dev(c67x00), "error: urb list not empty\n");
  279. spin_lock_irqsave(&c67x00->lock, flags);
  280. /* loop waiting for all transfers in the endpoint queue to complete */
  281. while (c67x00_ep_data_free(ep)) {
  282. /* Drop the lock so we can sleep waiting for the hardware */
  283. spin_unlock_irqrestore(&c67x00->lock, flags);
  284. /* it could happen that we reinitialize this completion, while
  285. * somebody was waiting for that completion. The timeout and
  286. * while loop handle such cases, but this might be improved */
  287. INIT_COMPLETION(c67x00->endpoint_disable);
  288. c67x00_sched_kick(c67x00);
  289. wait_for_completion_timeout(&c67x00->endpoint_disable, 1 * HZ);
  290. spin_lock_irqsave(&c67x00->lock, flags);
  291. }
  292. spin_unlock_irqrestore(&c67x00->lock, flags);
  293. }
  294. /* -------------------------------------------------------------------------- */
  295. static inline int get_root_port(struct usb_device *dev)
  296. {
  297. while (dev->parent->parent)
  298. dev = dev->parent;
  299. return dev->portnum;
  300. }
  301. int c67x00_urb_enqueue(struct usb_hcd *hcd,
  302. struct urb *urb, gfp_t mem_flags)
  303. {
  304. int ret;
  305. unsigned long flags;
  306. struct c67x00_urb_priv *urbp;
  307. struct c67x00_hcd *c67x00 = hcd_to_c67x00_hcd(hcd);
  308. int port = get_root_port(urb->dev)-1;
  309. spin_lock_irqsave(&c67x00->lock, flags);
  310. /* Make sure host controller is running */
  311. if (!HC_IS_RUNNING(hcd->state)) {
  312. ret = -ENODEV;
  313. goto err_not_linked;
  314. }
  315. ret = usb_hcd_link_urb_to_ep(hcd, urb);
  316. if (ret)
  317. goto err_not_linked;
  318. /* Allocate and initialize urb private data */
  319. urbp = kzalloc(sizeof(*urbp), mem_flags);
  320. if (!urbp) {
  321. ret = -ENOMEM;
  322. goto err_urbp;
  323. }
  324. INIT_LIST_HEAD(&urbp->hep_node);
  325. urbp->urb = urb;
  326. urbp->port = port;
  327. urbp->ep_data = c67x00_ep_data_alloc(c67x00, urb);
  328. if (!urbp->ep_data) {
  329. ret = -ENOMEM;
  330. goto err_epdata;
  331. }
  332. /* TODO claim bandwidth with usb_claim_bandwidth?
  333. * also release it somewhere! */
  334. urb->hcpriv = urbp;
  335. urb->actual_length = 0; /* Nothing received/transmitted yet */
  336. switch (usb_pipetype(urb->pipe)) {
  337. case PIPE_CONTROL:
  338. urb->interval = SETUP_STAGE;
  339. break;
  340. case PIPE_INTERRUPT:
  341. break;
  342. case PIPE_BULK:
  343. break;
  344. case PIPE_ISOCHRONOUS:
  345. if (c67x00->urb_iso_count == 0)
  346. c67x00->max_frame_bw = MAX_FRAME_BW_ISO;
  347. c67x00->urb_iso_count++;
  348. /* Assume always URB_ISO_ASAP, FIXME */
  349. if (list_empty(&urbp->ep_data->queue))
  350. urb->start_frame = urbp->ep_data->next_frame;
  351. else {
  352. /* Go right after the last one */
  353. struct urb *last_urb;
  354. last_urb = list_entry(urbp->ep_data->queue.prev,
  355. struct c67x00_urb_priv,
  356. hep_node)->urb;
  357. urb->start_frame =
  358. frame_add(last_urb->start_frame,
  359. last_urb->number_of_packets *
  360. last_urb->interval);
  361. }
  362. urbp->cnt = 0;
  363. break;
  364. }
  365. /* Add the URB to the endpoint queue */
  366. list_add_tail(&urbp->hep_node, &urbp->ep_data->queue);
  367. /* If this is the only URB, kick start the controller */
  368. if (!c67x00->urb_count++)
  369. c67x00_ll_hpi_enable_sofeop(c67x00->sie);
  370. c67x00_sched_kick(c67x00);
  371. spin_unlock_irqrestore(&c67x00->lock, flags);
  372. return 0;
  373. err_epdata:
  374. kfree(urbp);
  375. err_urbp:
  376. usb_hcd_unlink_urb_from_ep(hcd, urb);
  377. err_not_linked:
  378. spin_unlock_irqrestore(&c67x00->lock, flags);
  379. return ret;
  380. }
  381. int c67x00_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  382. {
  383. struct c67x00_hcd *c67x00 = hcd_to_c67x00_hcd(hcd);
  384. unsigned long flags;
  385. int rc;
  386. spin_lock_irqsave(&c67x00->lock, flags);
  387. rc = usb_hcd_check_unlink_urb(hcd, urb, status);
  388. if (rc)
  389. goto done;
  390. c67x00_release_urb(c67x00, urb);
  391. usb_hcd_unlink_urb_from_ep(hcd, urb);
  392. spin_unlock(&c67x00->lock);
  393. usb_hcd_giveback_urb(hcd, urb, status);
  394. spin_lock(&c67x00->lock);
  395. spin_unlock_irqrestore(&c67x00->lock, flags);
  396. return 0;
  397. done:
  398. spin_unlock_irqrestore(&c67x00->lock, flags);
  399. return rc;
  400. }
  401. /* -------------------------------------------------------------------------- */
  402. /*
  403. * pre: c67x00 locked, urb unlocked
  404. */
  405. static void
  406. c67x00_giveback_urb(struct c67x00_hcd *c67x00, struct urb *urb, int status)
  407. {
  408. struct c67x00_urb_priv *urbp;
  409. if (!urb)
  410. return;
  411. urbp = urb->hcpriv;
  412. urbp->status = status;
  413. list_del_init(&urbp->hep_node);
  414. c67x00_release_urb(c67x00, urb);
  415. usb_hcd_unlink_urb_from_ep(c67x00_hcd_to_hcd(c67x00), urb);
  416. spin_unlock(&c67x00->lock);
  417. usb_hcd_giveback_urb(c67x00_hcd_to_hcd(c67x00), urb, urbp->status);
  418. spin_lock(&c67x00->lock);
  419. }
  420. /* -------------------------------------------------------------------------- */
  421. static int c67x00_claim_frame_bw(struct c67x00_hcd *c67x00, struct urb *urb,
  422. int len, int periodic)
  423. {
  424. struct c67x00_urb_priv *urbp = urb->hcpriv;
  425. int bit_time;
  426. /* According to the C67x00 BIOS user manual, page 3-18,19, the
  427. * following calculations provide the full speed bit times for
  428. * a transaction.
  429. *
  430. * FS(in) = 112.5 + 9.36*BC + HOST_DELAY
  431. * FS(in,iso) = 90.5 + 9.36*BC + HOST_DELAY
  432. * FS(out) = 112.5 + 9.36*BC + HOST_DELAY
  433. * FS(out,iso) = 78.4 + 9.36*BC + HOST_DELAY
  434. * LS(in) = 802.4 + 75.78*BC + HOST_DELAY
  435. * LS(out) = 802.6 + 74.67*BC + HOST_DELAY
  436. *
  437. * HOST_DELAY == 106 for the c67200 and c67300.
  438. */
  439. /* make calculations in 1/100 bit times to maintain resolution */
  440. if (urbp->ep_data->dev->speed == USB_SPEED_LOW) {
  441. /* Low speed pipe */
  442. if (usb_pipein(urb->pipe))
  443. bit_time = 80240 + 7578*len;
  444. else
  445. bit_time = 80260 + 7467*len;
  446. } else {
  447. /* FS pipes */
  448. if (usb_pipeisoc(urb->pipe))
  449. bit_time = usb_pipein(urb->pipe) ? 9050 : 7840;
  450. else
  451. bit_time = 11250;
  452. bit_time += 936*len;
  453. }
  454. /* Scale back down to integer bit times. Use a host delay of 106.
  455. * (this is the only place it is used) */
  456. bit_time = ((bit_time+50) / 100) + 106;
  457. if (unlikely(bit_time + c67x00->bandwidth_allocated >=
  458. c67x00->max_frame_bw))
  459. return -EMSGSIZE;
  460. if (unlikely(c67x00->next_td_addr + CY_TD_SIZE >=
  461. c67x00->td_base_addr + SIE_TD_SIZE))
  462. return -EMSGSIZE;
  463. if (unlikely(c67x00->next_buf_addr + len >=
  464. c67x00->buf_base_addr + SIE_TD_BUF_SIZE))
  465. return -EMSGSIZE;
  466. if (periodic) {
  467. if (unlikely(bit_time + c67x00->periodic_bw_allocated >=
  468. MAX_PERIODIC_BW(c67x00->max_frame_bw)))
  469. return -EMSGSIZE;
  470. c67x00->periodic_bw_allocated += bit_time;
  471. }
  472. c67x00->bandwidth_allocated += bit_time;
  473. return 0;
  474. }
  475. /* -------------------------------------------------------------------------- */
  476. /**
  477. * td_addr and buf_addr must be word aligned
  478. */
  479. static int c67x00_create_td(struct c67x00_hcd *c67x00, struct urb *urb,
  480. void *data, int len, int pid, int toggle,
  481. unsigned long privdata)
  482. {
  483. struct c67x00_td *td;
  484. struct c67x00_urb_priv *urbp = urb->hcpriv;
  485. const __u8 active_flag = 1, retry_cnt = 1;
  486. __u8 cmd = 0;
  487. int tt = 0;
  488. if (c67x00_claim_frame_bw(c67x00, urb, len, usb_pipeisoc(urb->pipe)
  489. || usb_pipeint(urb->pipe)))
  490. return -EMSGSIZE; /* Not really an error, but expected */
  491. td = kzalloc(sizeof(*td), GFP_ATOMIC);
  492. if (!td)
  493. return -ENOMEM;
  494. td->pipe = urb->pipe;
  495. td->ep_data = urbp->ep_data;
  496. if ((td_udev(td)->speed == USB_SPEED_LOW) &&
  497. !(c67x00->low_speed_ports & (1 << urbp->port)))
  498. cmd |= PREAMBLE_EN;
  499. switch (usb_pipetype(td->pipe)) {
  500. case PIPE_ISOCHRONOUS:
  501. tt = TT_ISOCHRONOUS;
  502. cmd |= ISO_EN;
  503. break;
  504. case PIPE_CONTROL:
  505. tt = TT_CONTROL;
  506. break;
  507. case PIPE_BULK:
  508. tt = TT_BULK;
  509. break;
  510. case PIPE_INTERRUPT:
  511. tt = TT_INTERRUPT;
  512. break;
  513. }
  514. if (toggle)
  515. cmd |= SEQ_SEL;
  516. cmd |= ARM_EN;
  517. /* SW part */
  518. td->td_addr = c67x00->next_td_addr;
  519. c67x00->next_td_addr = c67x00->next_td_addr + CY_TD_SIZE;
  520. /* HW part */
  521. td->ly_base_addr = __cpu_to_le16(c67x00->next_buf_addr);
  522. td->port_length = __cpu_to_le16((c67x00->sie->sie_num << 15) |
  523. (urbp->port << 14) | (len & 0x3FF));
  524. td->pid_ep = ((pid & 0xF) << TD_PIDEP_OFFSET) |
  525. (usb_pipeendpoint(td->pipe) & 0xF);
  526. td->dev_addr = usb_pipedevice(td->pipe) & 0x7F;
  527. td->ctrl_reg = cmd;
  528. td->status = 0;
  529. td->retry_cnt = (tt << TT_OFFSET) | (active_flag << 4) | retry_cnt;
  530. td->residue = 0;
  531. td->next_td_addr = __cpu_to_le16(c67x00->next_td_addr);
  532. /* SW part */
  533. td->data = data;
  534. td->urb = urb;
  535. td->privdata = privdata;
  536. c67x00->next_buf_addr += (len + 1) & ~0x01; /* properly align */
  537. list_add_tail(&td->td_list, &c67x00->td_list);
  538. return 0;
  539. }
  540. static inline void c67x00_release_td(struct c67x00_td *td)
  541. {
  542. list_del_init(&td->td_list);
  543. kfree(td);
  544. }
  545. /* -------------------------------------------------------------------------- */
  546. static int c67x00_add_data_urb(struct c67x00_hcd *c67x00, struct urb *urb)
  547. {
  548. int remaining;
  549. int toggle;
  550. int pid;
  551. int ret = 0;
  552. int maxps;
  553. int need_empty;
  554. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  555. usb_pipeout(urb->pipe));
  556. remaining = urb->transfer_buffer_length - urb->actual_length;
  557. maxps = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  558. need_empty = (urb->transfer_flags & URB_ZERO_PACKET) &&
  559. usb_pipeout(urb->pipe) && !(remaining % maxps);
  560. while (remaining || need_empty) {
  561. int len;
  562. char *td_buf;
  563. len = (remaining > maxps) ? maxps : remaining;
  564. if (!len)
  565. need_empty = 0;
  566. pid = usb_pipeout(urb->pipe) ? USB_PID_OUT : USB_PID_IN;
  567. td_buf = urb->transfer_buffer + urb->transfer_buffer_length -
  568. remaining;
  569. ret = c67x00_create_td(c67x00, urb, td_buf, len, pid, toggle,
  570. DATA_STAGE);
  571. if (ret)
  572. return ret; /* td wasn't created */
  573. toggle ^= 1;
  574. remaining -= len;
  575. if (usb_pipecontrol(urb->pipe))
  576. break;
  577. }
  578. return 0;
  579. }
  580. /**
  581. * return 0 in case more bandwidth is available, else errorcode
  582. */
  583. static int c67x00_add_ctrl_urb(struct c67x00_hcd *c67x00, struct urb *urb)
  584. {
  585. int ret;
  586. int pid;
  587. switch (urb->interval) {
  588. default:
  589. case SETUP_STAGE:
  590. ret = c67x00_create_td(c67x00, urb, urb->setup_packet,
  591. 8, USB_PID_SETUP, 0, SETUP_STAGE);
  592. if (ret)
  593. return ret;
  594. urb->interval = SETUP_STAGE;
  595. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  596. usb_pipeout(urb->pipe), 1);
  597. break;
  598. case DATA_STAGE:
  599. if (urb->transfer_buffer_length) {
  600. ret = c67x00_add_data_urb(c67x00, urb);
  601. if (ret)
  602. return ret;
  603. break;
  604. } /* else fallthrough */
  605. case STATUS_STAGE:
  606. pid = !usb_pipeout(urb->pipe) ? USB_PID_OUT : USB_PID_IN;
  607. ret = c67x00_create_td(c67x00, urb, NULL, 0, pid, 1,
  608. STATUS_STAGE);
  609. if (ret)
  610. return ret;
  611. break;
  612. }
  613. return 0;
  614. }
  615. /*
  616. * return 0 in case more bandwidth is available, else errorcode
  617. */
  618. static int c67x00_add_int_urb(struct c67x00_hcd *c67x00, struct urb *urb)
  619. {
  620. struct c67x00_urb_priv *urbp = urb->hcpriv;
  621. if (frame_after_eq(c67x00->current_frame, urbp->ep_data->next_frame)) {
  622. urbp->ep_data->next_frame =
  623. frame_add(urbp->ep_data->next_frame, urb->interval);
  624. return c67x00_add_data_urb(c67x00, urb);
  625. }
  626. return 0;
  627. }
  628. static int c67x00_add_iso_urb(struct c67x00_hcd *c67x00, struct urb *urb)
  629. {
  630. struct c67x00_urb_priv *urbp = urb->hcpriv;
  631. if (frame_after_eq(c67x00->current_frame, urbp->ep_data->next_frame)) {
  632. char *td_buf;
  633. int len, pid, ret;
  634. BUG_ON(urbp->cnt >= urb->number_of_packets);
  635. td_buf = urb->transfer_buffer +
  636. urb->iso_frame_desc[urbp->cnt].offset;
  637. len = urb->iso_frame_desc[urbp->cnt].length;
  638. pid = usb_pipeout(urb->pipe) ? USB_PID_OUT : USB_PID_IN;
  639. ret = c67x00_create_td(c67x00, urb, td_buf, len, pid, 0,
  640. urbp->cnt);
  641. if (ret) {
  642. printk(KERN_DEBUG "create failed: %d\n", ret);
  643. urb->iso_frame_desc[urbp->cnt].actual_length = 0;
  644. urb->iso_frame_desc[urbp->cnt].status = ret;
  645. if (urbp->cnt + 1 == urb->number_of_packets)
  646. c67x00_giveback_urb(c67x00, urb, 0);
  647. }
  648. urbp->ep_data->next_frame =
  649. frame_add(urbp->ep_data->next_frame, urb->interval);
  650. urbp->cnt++;
  651. }
  652. return 0;
  653. }
  654. /* -------------------------------------------------------------------------- */
  655. static void c67x00_fill_from_list(struct c67x00_hcd *c67x00, int type,
  656. int (*add)(struct c67x00_hcd *, struct urb *))
  657. {
  658. struct c67x00_ep_data *ep_data;
  659. struct urb *urb;
  660. /* traverse every endpoint on the list */
  661. list_for_each_entry(ep_data, &c67x00->list[type], node) {
  662. if (!list_empty(&ep_data->queue)) {
  663. /* and add the first urb */
  664. /* isochronous transfer rely on this */
  665. urb = list_entry(ep_data->queue.next,
  666. struct c67x00_urb_priv,
  667. hep_node)->urb;
  668. add(c67x00, urb);
  669. }
  670. }
  671. }
  672. static void c67x00_fill_frame(struct c67x00_hcd *c67x00)
  673. {
  674. struct c67x00_td *td, *ttd;
  675. /* Check if we can proceed */
  676. if (!list_empty(&c67x00->td_list)) {
  677. dev_warn(c67x00_hcd_dev(c67x00),
  678. "TD list not empty! This should not happen!\n");
  679. list_for_each_entry_safe(td, ttd, &c67x00->td_list, td_list) {
  680. dbg_td(c67x00, td, "Unprocessed td");
  681. c67x00_release_td(td);
  682. }
  683. }
  684. /* Reinitialize variables */
  685. c67x00->bandwidth_allocated = 0;
  686. c67x00->periodic_bw_allocated = 0;
  687. c67x00->next_td_addr = c67x00->td_base_addr;
  688. c67x00->next_buf_addr = c67x00->buf_base_addr;
  689. /* Fill the list */
  690. c67x00_fill_from_list(c67x00, PIPE_ISOCHRONOUS, c67x00_add_iso_urb);
  691. c67x00_fill_from_list(c67x00, PIPE_INTERRUPT, c67x00_add_int_urb);
  692. c67x00_fill_from_list(c67x00, PIPE_CONTROL, c67x00_add_ctrl_urb);
  693. c67x00_fill_from_list(c67x00, PIPE_BULK, c67x00_add_data_urb);
  694. }
  695. /* -------------------------------------------------------------------------- */
  696. /**
  697. * Get TD from C67X00
  698. */
  699. static inline void
  700. c67x00_parse_td(struct c67x00_hcd *c67x00, struct c67x00_td *td)
  701. {
  702. c67x00_ll_read_mem_le16(c67x00->sie->dev,
  703. td->td_addr, td, CY_TD_SIZE);
  704. if (usb_pipein(td->pipe) && td_actual_bytes(td))
  705. c67x00_ll_read_mem_le16(c67x00->sie->dev, td_ly_base_addr(td),
  706. td->data, td_actual_bytes(td));
  707. }
  708. static int c67x00_td_to_error(struct c67x00_hcd *c67x00, struct c67x00_td *td)
  709. {
  710. if (td->status & TD_STATUSMASK_ERR) {
  711. dbg_td(c67x00, td, "ERROR_FLAG");
  712. return -EILSEQ;
  713. }
  714. if (td->status & TD_STATUSMASK_STALL) {
  715. /* dbg_td(c67x00, td, "STALL"); */
  716. return -EPIPE;
  717. }
  718. if (td->status & TD_STATUSMASK_TMOUT) {
  719. dbg_td(c67x00, td, "TIMEOUT");
  720. return -ETIMEDOUT;
  721. }
  722. return 0;
  723. }
  724. static inline int c67x00_end_of_data(struct c67x00_td *td)
  725. {
  726. int maxps, need_empty, remaining;
  727. struct urb *urb = td->urb;
  728. int act_bytes;
  729. act_bytes = td_actual_bytes(td);
  730. if (unlikely(!act_bytes))
  731. return 1; /* This was an empty packet */
  732. maxps = usb_maxpacket(td_udev(td), td->pipe, usb_pipeout(td->pipe));
  733. if (unlikely(act_bytes < maxps))
  734. return 1; /* Smaller then full packet */
  735. remaining = urb->transfer_buffer_length - urb->actual_length;
  736. need_empty = (urb->transfer_flags & URB_ZERO_PACKET) &&
  737. usb_pipeout(urb->pipe) && !(remaining % maxps);
  738. if (unlikely(!remaining && !need_empty))
  739. return 1;
  740. return 0;
  741. }
  742. /* -------------------------------------------------------------------------- */
  743. /* Remove all td's from the list which come
  744. * after last_td and are meant for the same pipe.
  745. * This is used when a short packet has occurred */
  746. static inline void c67x00_clear_pipe(struct c67x00_hcd *c67x00,
  747. struct c67x00_td *last_td)
  748. {
  749. struct c67x00_td *td, *tmp;
  750. td = last_td;
  751. tmp = last_td;
  752. while (td->td_list.next != &c67x00->td_list) {
  753. td = list_entry(td->td_list.next, struct c67x00_td, td_list);
  754. if (td->pipe == last_td->pipe) {
  755. c67x00_release_td(td);
  756. td = tmp;
  757. }
  758. tmp = td;
  759. }
  760. }
  761. /* -------------------------------------------------------------------------- */
  762. static void c67x00_handle_successful_td(struct c67x00_hcd *c67x00,
  763. struct c67x00_td *td)
  764. {
  765. struct urb *urb = td->urb;
  766. if (!urb)
  767. return;
  768. urb->actual_length += td_actual_bytes(td);
  769. switch (usb_pipetype(td->pipe)) {
  770. /* isochronous tds are handled separately */
  771. case PIPE_CONTROL:
  772. switch (td->privdata) {
  773. case SETUP_STAGE:
  774. urb->interval =
  775. urb->transfer_buffer_length ?
  776. DATA_STAGE : STATUS_STAGE;
  777. /* Don't count setup_packet with normal data: */
  778. urb->actual_length = 0;
  779. break;
  780. case DATA_STAGE:
  781. if (c67x00_end_of_data(td)) {
  782. urb->interval = STATUS_STAGE;
  783. c67x00_clear_pipe(c67x00, td);
  784. }
  785. break;
  786. case STATUS_STAGE:
  787. urb->interval = 0;
  788. c67x00_giveback_urb(c67x00, urb, 0);
  789. break;
  790. }
  791. break;
  792. case PIPE_INTERRUPT:
  793. case PIPE_BULK:
  794. if (unlikely(c67x00_end_of_data(td))) {
  795. c67x00_clear_pipe(c67x00, td);
  796. c67x00_giveback_urb(c67x00, urb, 0);
  797. }
  798. break;
  799. }
  800. }
  801. static void c67x00_handle_isoc(struct c67x00_hcd *c67x00, struct c67x00_td *td)
  802. {
  803. struct urb *urb = td->urb;
  804. struct c67x00_urb_priv *urbp;
  805. int cnt;
  806. if (!urb)
  807. return;
  808. urbp = urb->hcpriv;
  809. cnt = td->privdata;
  810. if (td->status & TD_ERROR_MASK)
  811. urb->error_count++;
  812. urb->iso_frame_desc[cnt].actual_length = td_actual_bytes(td);
  813. urb->iso_frame_desc[cnt].status = c67x00_td_to_error(c67x00, td);
  814. if (cnt + 1 == urb->number_of_packets) /* Last packet */
  815. c67x00_giveback_urb(c67x00, urb, 0);
  816. }
  817. /* -------------------------------------------------------------------------- */
  818. /**
  819. * c67x00_check_td_list - handle tds which have been processed by the c67x00
  820. * pre: current_td == 0
  821. */
  822. static inline void c67x00_check_td_list(struct c67x00_hcd *c67x00)
  823. {
  824. struct c67x00_td *td, *tmp;
  825. struct urb *urb;
  826. int ack_ok;
  827. int clear_endpoint;
  828. list_for_each_entry_safe(td, tmp, &c67x00->td_list, td_list) {
  829. /* get the TD */
  830. c67x00_parse_td(c67x00, td);
  831. urb = td->urb; /* urb can be NULL! */
  832. ack_ok = 0;
  833. clear_endpoint = 1;
  834. /* Handle isochronous transfers separately */
  835. if (usb_pipeisoc(td->pipe)) {
  836. clear_endpoint = 0;
  837. c67x00_handle_isoc(c67x00, td);
  838. goto cont;
  839. }
  840. /* When an error occurs, all td's for that pipe go into an
  841. * inactive state. This state matches successful transfers so
  842. * we must make sure not to service them. */
  843. if (td->status & TD_ERROR_MASK) {
  844. c67x00_giveback_urb(c67x00, urb,
  845. c67x00_td_to_error(c67x00, td));
  846. goto cont;
  847. }
  848. if ((td->status & TD_STATUSMASK_NAK) || !td_sequence_ok(td) ||
  849. !td_acked(td))
  850. goto cont;
  851. /* Sequence ok and acked, don't need to fix toggle */
  852. ack_ok = 1;
  853. if (unlikely(td->status & TD_STATUSMASK_OVF)) {
  854. if (td_residue(td) & TD_RESIDUE_OVERFLOW) {
  855. /* Overflow */
  856. c67x00_giveback_urb(c67x00, urb, -EOVERFLOW);
  857. goto cont;
  858. }
  859. }
  860. clear_endpoint = 0;
  861. c67x00_handle_successful_td(c67x00, td);
  862. cont:
  863. if (clear_endpoint)
  864. c67x00_clear_pipe(c67x00, td);
  865. if (ack_ok)
  866. usb_settoggle(td_udev(td), usb_pipeendpoint(td->pipe),
  867. usb_pipeout(td->pipe),
  868. !(td->ctrl_reg & SEQ_SEL));
  869. /* next in list could have been removed, due to clear_pipe! */
  870. tmp = list_entry(td->td_list.next, typeof(*td), td_list);
  871. c67x00_release_td(td);
  872. }
  873. }
  874. /* -------------------------------------------------------------------------- */
  875. static inline int c67x00_all_tds_processed(struct c67x00_hcd *c67x00)
  876. {
  877. /* If all tds are processed, we can check the previous frame (if
  878. * there was any) and start our next frame.
  879. */
  880. return !c67x00_ll_husb_get_current_td(c67x00->sie);
  881. }
  882. /**
  883. * Send td to C67X00
  884. */
  885. static void c67x00_send_td(struct c67x00_hcd *c67x00, struct c67x00_td *td)
  886. {
  887. int len = td_length(td);
  888. if (len && ((td->pid_ep & TD_PIDEPMASK_PID) != TD_PID_IN))
  889. c67x00_ll_write_mem_le16(c67x00->sie->dev, td_ly_base_addr(td),
  890. td->data, len);
  891. c67x00_ll_write_mem_le16(c67x00->sie->dev,
  892. td->td_addr, td, CY_TD_SIZE);
  893. }
  894. static void c67x00_send_frame(struct c67x00_hcd *c67x00)
  895. {
  896. struct c67x00_td *td;
  897. if (list_empty(&c67x00->td_list))
  898. dev_warn(c67x00_hcd_dev(c67x00),
  899. "%s: td list should not be empty here!\n",
  900. __func__);
  901. list_for_each_entry(td, &c67x00->td_list, td_list) {
  902. if (td->td_list.next == &c67x00->td_list)
  903. td->next_td_addr = 0; /* Last td in list */
  904. c67x00_send_td(c67x00, td);
  905. }
  906. c67x00_ll_husb_set_current_td(c67x00->sie, c67x00->td_base_addr);
  907. }
  908. /* -------------------------------------------------------------------------- */
  909. /**
  910. * c67x00_do_work - Schedulers state machine
  911. */
  912. static void c67x00_do_work(struct c67x00_hcd *c67x00)
  913. {
  914. spin_lock(&c67x00->lock);
  915. /* Make sure all tds are processed */
  916. if (!c67x00_all_tds_processed(c67x00))
  917. goto out;
  918. c67x00_check_td_list(c67x00);
  919. /* no td's are being processed (current == 0)
  920. * and all have been "checked" */
  921. complete(&c67x00->endpoint_disable);
  922. if (!list_empty(&c67x00->td_list))
  923. goto out;
  924. c67x00->current_frame = c67x00_get_current_frame_number(c67x00);
  925. if (c67x00->current_frame == c67x00->last_frame)
  926. goto out; /* Don't send tds in same frame */
  927. c67x00->last_frame = c67x00->current_frame;
  928. /* If no urbs are scheduled, our work is done */
  929. if (!c67x00->urb_count) {
  930. c67x00_ll_hpi_disable_sofeop(c67x00->sie);
  931. goto out;
  932. }
  933. c67x00_fill_frame(c67x00);
  934. if (!list_empty(&c67x00->td_list))
  935. /* TD's have been added to the frame */
  936. c67x00_send_frame(c67x00);
  937. out:
  938. spin_unlock(&c67x00->lock);
  939. }
  940. /* -------------------------------------------------------------------------- */
  941. static void c67x00_sched_tasklet(unsigned long __c67x00)
  942. {
  943. struct c67x00_hcd *c67x00 = (struct c67x00_hcd *)__c67x00;
  944. c67x00_do_work(c67x00);
  945. }
  946. void c67x00_sched_kick(struct c67x00_hcd *c67x00)
  947. {
  948. tasklet_hi_schedule(&c67x00->tasklet);
  949. }
  950. int c67x00_sched_start_scheduler(struct c67x00_hcd *c67x00)
  951. {
  952. tasklet_init(&c67x00->tasklet, c67x00_sched_tasklet,
  953. (unsigned long)c67x00);
  954. return 0;
  955. }
  956. void c67x00_sched_stop_scheduler(struct c67x00_hcd *c67x00)
  957. {
  958. tasklet_kill(&c67x00->tasklet);
  959. }