spi-s3c24xx.c 17 KB

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  1. /*
  2. * Copyright (c) 2006 Ben Dooks
  3. * Copyright 2006-2009 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/init.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/workqueue.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/clk.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/gpio.h>
  21. #include <linux/io.h>
  22. #include <linux/slab.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/spi/spi_bitbang.h>
  25. #include <plat/regs-spi.h>
  26. #include <mach/spi.h>
  27. #include <plat/fiq.h>
  28. #include <asm/fiq.h>
  29. #include "spi-s3c24xx-fiq.h"
  30. /**
  31. * s3c24xx_spi_devstate - per device data
  32. * @hz: Last frequency calculated for @sppre field.
  33. * @mode: Last mode setting for the @spcon field.
  34. * @spcon: Value to write to the SPCON register.
  35. * @sppre: Value to write to the SPPRE register.
  36. */
  37. struct s3c24xx_spi_devstate {
  38. unsigned int hz;
  39. unsigned int mode;
  40. u8 spcon;
  41. u8 sppre;
  42. };
  43. enum spi_fiq_mode {
  44. FIQ_MODE_NONE = 0,
  45. FIQ_MODE_TX = 1,
  46. FIQ_MODE_RX = 2,
  47. FIQ_MODE_TXRX = 3,
  48. };
  49. struct s3c24xx_spi {
  50. /* bitbang has to be first */
  51. struct spi_bitbang bitbang;
  52. struct completion done;
  53. void __iomem *regs;
  54. int irq;
  55. int len;
  56. int count;
  57. struct fiq_handler fiq_handler;
  58. enum spi_fiq_mode fiq_mode;
  59. unsigned char fiq_inuse;
  60. unsigned char fiq_claimed;
  61. void (*set_cs)(struct s3c2410_spi_info *spi,
  62. int cs, int pol);
  63. /* data buffers */
  64. const unsigned char *tx;
  65. unsigned char *rx;
  66. struct clk *clk;
  67. struct resource *ioarea;
  68. struct spi_master *master;
  69. struct spi_device *curdev;
  70. struct device *dev;
  71. struct s3c2410_spi_info *pdata;
  72. };
  73. #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
  74. #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
  75. static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
  76. {
  77. return spi_master_get_devdata(sdev->master);
  78. }
  79. static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
  80. {
  81. gpio_set_value(spi->pin_cs, pol);
  82. }
  83. static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
  84. {
  85. struct s3c24xx_spi_devstate *cs = spi->controller_state;
  86. struct s3c24xx_spi *hw = to_hw(spi);
  87. unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  88. /* change the chipselect state and the state of the spi engine clock */
  89. switch (value) {
  90. case BITBANG_CS_INACTIVE:
  91. hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
  92. writeb(cs->spcon, hw->regs + S3C2410_SPCON);
  93. break;
  94. case BITBANG_CS_ACTIVE:
  95. writeb(cs->spcon | S3C2410_SPCON_ENSCK,
  96. hw->regs + S3C2410_SPCON);
  97. hw->set_cs(hw->pdata, spi->chip_select, cspol);
  98. break;
  99. }
  100. }
  101. static int s3c24xx_spi_update_state(struct spi_device *spi,
  102. struct spi_transfer *t)
  103. {
  104. struct s3c24xx_spi *hw = to_hw(spi);
  105. struct s3c24xx_spi_devstate *cs = spi->controller_state;
  106. unsigned int bpw;
  107. unsigned int hz;
  108. unsigned int div;
  109. unsigned long clk;
  110. bpw = t ? t->bits_per_word : spi->bits_per_word;
  111. hz = t ? t->speed_hz : spi->max_speed_hz;
  112. if (!bpw)
  113. bpw = 8;
  114. if (!hz)
  115. hz = spi->max_speed_hz;
  116. if (bpw != 8) {
  117. dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
  118. return -EINVAL;
  119. }
  120. if (spi->mode != cs->mode) {
  121. u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
  122. if (spi->mode & SPI_CPHA)
  123. spcon |= S3C2410_SPCON_CPHA_FMTB;
  124. if (spi->mode & SPI_CPOL)
  125. spcon |= S3C2410_SPCON_CPOL_HIGH;
  126. cs->mode = spi->mode;
  127. cs->spcon = spcon;
  128. }
  129. if (cs->hz != hz) {
  130. clk = clk_get_rate(hw->clk);
  131. div = DIV_ROUND_UP(clk, hz * 2) - 1;
  132. if (div > 255)
  133. div = 255;
  134. dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
  135. div, hz, clk / (2 * (div + 1)));
  136. cs->hz = hz;
  137. cs->sppre = div;
  138. }
  139. return 0;
  140. }
  141. static int s3c24xx_spi_setupxfer(struct spi_device *spi,
  142. struct spi_transfer *t)
  143. {
  144. struct s3c24xx_spi_devstate *cs = spi->controller_state;
  145. struct s3c24xx_spi *hw = to_hw(spi);
  146. int ret;
  147. ret = s3c24xx_spi_update_state(spi, t);
  148. if (!ret)
  149. writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
  150. return ret;
  151. }
  152. static int s3c24xx_spi_setup(struct spi_device *spi)
  153. {
  154. struct s3c24xx_spi_devstate *cs = spi->controller_state;
  155. struct s3c24xx_spi *hw = to_hw(spi);
  156. int ret;
  157. /* allocate settings on the first call */
  158. if (!cs) {
  159. cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
  160. if (!cs) {
  161. dev_err(&spi->dev, "no memory for controller state\n");
  162. return -ENOMEM;
  163. }
  164. cs->spcon = SPCON_DEFAULT;
  165. cs->hz = -1;
  166. spi->controller_state = cs;
  167. }
  168. /* initialise the state from the device */
  169. ret = s3c24xx_spi_update_state(spi, NULL);
  170. if (ret)
  171. return ret;
  172. spin_lock(&hw->bitbang.lock);
  173. if (!hw->bitbang.busy) {
  174. hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
  175. /* need to ndelay for 0.5 clocktick ? */
  176. }
  177. spin_unlock(&hw->bitbang.lock);
  178. return 0;
  179. }
  180. static void s3c24xx_spi_cleanup(struct spi_device *spi)
  181. {
  182. kfree(spi->controller_state);
  183. }
  184. static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
  185. {
  186. return hw->tx ? hw->tx[count] : 0;
  187. }
  188. #ifdef CONFIG_SPI_S3C24XX_FIQ
  189. /* Support for FIQ based pseudo-DMA to improve the transfer speed.
  190. *
  191. * This code uses the assembly helper in spi_s3c24xx_spi.S which is
  192. * used by the FIQ core to move data between main memory and the peripheral
  193. * block. Since this is code running on the processor, there is no problem
  194. * with cache coherency of the buffers, so we can use any buffer we like.
  195. */
  196. /**
  197. * struct spi_fiq_code - FIQ code and header
  198. * @length: The length of the code fragment, excluding this header.
  199. * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
  200. * @data: The code itself to install as a FIQ handler.
  201. */
  202. struct spi_fiq_code {
  203. u32 length;
  204. u32 ack_offset;
  205. u8 data[0];
  206. };
  207. extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
  208. extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
  209. extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
  210. /**
  211. * ack_bit - turn IRQ into IRQ acknowledgement bit
  212. * @irq: The interrupt number
  213. *
  214. * Returns the bit to write to the interrupt acknowledge register.
  215. */
  216. static inline u32 ack_bit(unsigned int irq)
  217. {
  218. return 1 << (irq - IRQ_EINT0);
  219. }
  220. /**
  221. * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
  222. * @hw: The hardware state.
  223. *
  224. * Claim the FIQ handler (only one can be active at any one time) and
  225. * then setup the correct transfer code for this transfer.
  226. *
  227. * This call updates all the necessary state information if successful,
  228. * so the caller does not need to do anything more than start the transfer
  229. * as normal, since the IRQ will have been re-routed to the FIQ handler.
  230. */
  231. void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
  232. {
  233. struct pt_regs regs;
  234. enum spi_fiq_mode mode;
  235. struct spi_fiq_code *code;
  236. int ret;
  237. if (!hw->fiq_claimed) {
  238. /* try and claim fiq if we haven't got it, and if not
  239. * then return and simply use another transfer method */
  240. ret = claim_fiq(&hw->fiq_handler);
  241. if (ret)
  242. return;
  243. }
  244. if (hw->tx && !hw->rx)
  245. mode = FIQ_MODE_TX;
  246. else if (hw->rx && !hw->tx)
  247. mode = FIQ_MODE_RX;
  248. else
  249. mode = FIQ_MODE_TXRX;
  250. regs.uregs[fiq_rspi] = (long)hw->regs;
  251. regs.uregs[fiq_rrx] = (long)hw->rx;
  252. regs.uregs[fiq_rtx] = (long)hw->tx + 1;
  253. regs.uregs[fiq_rcount] = hw->len - 1;
  254. regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
  255. set_fiq_regs(&regs);
  256. if (hw->fiq_mode != mode) {
  257. u32 *ack_ptr;
  258. hw->fiq_mode = mode;
  259. switch (mode) {
  260. case FIQ_MODE_TX:
  261. code = &s3c24xx_spi_fiq_tx;
  262. break;
  263. case FIQ_MODE_RX:
  264. code = &s3c24xx_spi_fiq_rx;
  265. break;
  266. case FIQ_MODE_TXRX:
  267. code = &s3c24xx_spi_fiq_txrx;
  268. break;
  269. default:
  270. code = NULL;
  271. }
  272. BUG_ON(!code);
  273. ack_ptr = (u32 *)&code->data[code->ack_offset];
  274. *ack_ptr = ack_bit(hw->irq);
  275. set_fiq_handler(&code->data, code->length);
  276. }
  277. s3c24xx_set_fiq(hw->irq, true);
  278. hw->fiq_mode = mode;
  279. hw->fiq_inuse = 1;
  280. }
  281. /**
  282. * s3c24xx_spi_fiqop - FIQ core code callback
  283. * @pw: Data registered with the handler
  284. * @release: Whether this is a release or a return.
  285. *
  286. * Called by the FIQ code when another module wants to use the FIQ, so
  287. * return whether we are currently using this or not and then update our
  288. * internal state.
  289. */
  290. static int s3c24xx_spi_fiqop(void *pw, int release)
  291. {
  292. struct s3c24xx_spi *hw = pw;
  293. int ret = 0;
  294. if (release) {
  295. if (hw->fiq_inuse)
  296. ret = -EBUSY;
  297. /* note, we do not need to unroute the FIQ, as the FIQ
  298. * vector code de-routes it to signal the end of transfer */
  299. hw->fiq_mode = FIQ_MODE_NONE;
  300. hw->fiq_claimed = 0;
  301. } else {
  302. hw->fiq_claimed = 1;
  303. }
  304. return ret;
  305. }
  306. /**
  307. * s3c24xx_spi_initfiq - setup the information for the FIQ core
  308. * @hw: The hardware state.
  309. *
  310. * Setup the fiq_handler block to pass to the FIQ core.
  311. */
  312. static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
  313. {
  314. hw->fiq_handler.dev_id = hw;
  315. hw->fiq_handler.name = dev_name(hw->dev);
  316. hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
  317. }
  318. /**
  319. * s3c24xx_spi_usefiq - return if we should be using FIQ.
  320. * @hw: The hardware state.
  321. *
  322. * Return true if the platform data specifies whether this channel is
  323. * allowed to use the FIQ.
  324. */
  325. static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
  326. {
  327. return hw->pdata->use_fiq;
  328. }
  329. /**
  330. * s3c24xx_spi_usingfiq - return if channel is using FIQ
  331. * @spi: The hardware state.
  332. *
  333. * Return whether the channel is currently using the FIQ (separate from
  334. * whether the FIQ is claimed).
  335. */
  336. static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
  337. {
  338. return spi->fiq_inuse;
  339. }
  340. #else
  341. static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
  342. static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
  343. static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
  344. static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
  345. #endif /* CONFIG_SPI_S3C24XX_FIQ */
  346. static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  347. {
  348. struct s3c24xx_spi *hw = to_hw(spi);
  349. hw->tx = t->tx_buf;
  350. hw->rx = t->rx_buf;
  351. hw->len = t->len;
  352. hw->count = 0;
  353. init_completion(&hw->done);
  354. hw->fiq_inuse = 0;
  355. if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
  356. s3c24xx_spi_tryfiq(hw);
  357. /* send the first byte */
  358. writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
  359. wait_for_completion(&hw->done);
  360. return hw->count;
  361. }
  362. static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
  363. {
  364. struct s3c24xx_spi *hw = dev;
  365. unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
  366. unsigned int count = hw->count;
  367. if (spsta & S3C2410_SPSTA_DCOL) {
  368. dev_dbg(hw->dev, "data-collision\n");
  369. complete(&hw->done);
  370. goto irq_done;
  371. }
  372. if (!(spsta & S3C2410_SPSTA_READY)) {
  373. dev_dbg(hw->dev, "spi not ready for tx?\n");
  374. complete(&hw->done);
  375. goto irq_done;
  376. }
  377. if (!s3c24xx_spi_usingfiq(hw)) {
  378. hw->count++;
  379. if (hw->rx)
  380. hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
  381. count++;
  382. if (count < hw->len)
  383. writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
  384. else
  385. complete(&hw->done);
  386. } else {
  387. hw->count = hw->len;
  388. hw->fiq_inuse = 0;
  389. if (hw->rx)
  390. hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
  391. complete(&hw->done);
  392. }
  393. irq_done:
  394. return IRQ_HANDLED;
  395. }
  396. static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
  397. {
  398. /* for the moment, permanently enable the clock */
  399. clk_enable(hw->clk);
  400. /* program defaults into the registers */
  401. writeb(0xff, hw->regs + S3C2410_SPPRE);
  402. writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
  403. writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
  404. if (hw->pdata) {
  405. if (hw->set_cs == s3c24xx_spi_gpiocs)
  406. gpio_direction_output(hw->pdata->pin_cs, 1);
  407. if (hw->pdata->gpio_setup)
  408. hw->pdata->gpio_setup(hw->pdata, 1);
  409. }
  410. }
  411. static int __init s3c24xx_spi_probe(struct platform_device *pdev)
  412. {
  413. struct s3c2410_spi_info *pdata;
  414. struct s3c24xx_spi *hw;
  415. struct spi_master *master;
  416. struct resource *res;
  417. int err = 0;
  418. master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
  419. if (master == NULL) {
  420. dev_err(&pdev->dev, "No memory for spi_master\n");
  421. err = -ENOMEM;
  422. goto err_nomem;
  423. }
  424. hw = spi_master_get_devdata(master);
  425. memset(hw, 0, sizeof(struct s3c24xx_spi));
  426. hw->master = spi_master_get(master);
  427. hw->pdata = pdata = pdev->dev.platform_data;
  428. hw->dev = &pdev->dev;
  429. if (pdata == NULL) {
  430. dev_err(&pdev->dev, "No platform data supplied\n");
  431. err = -ENOENT;
  432. goto err_no_pdata;
  433. }
  434. platform_set_drvdata(pdev, hw);
  435. init_completion(&hw->done);
  436. /* initialise fiq handler */
  437. s3c24xx_spi_initfiq(hw);
  438. /* setup the master state. */
  439. /* the spi->mode bits understood by this driver: */
  440. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  441. master->num_chipselect = hw->pdata->num_cs;
  442. master->bus_num = pdata->bus_num;
  443. /* setup the state for the bitbang driver */
  444. hw->bitbang.master = hw->master;
  445. hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
  446. hw->bitbang.chipselect = s3c24xx_spi_chipsel;
  447. hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
  448. hw->master->setup = s3c24xx_spi_setup;
  449. hw->master->cleanup = s3c24xx_spi_cleanup;
  450. dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
  451. /* find and map our resources */
  452. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  453. if (res == NULL) {
  454. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  455. err = -ENOENT;
  456. goto err_no_iores;
  457. }
  458. hw->ioarea = request_mem_region(res->start, resource_size(res),
  459. pdev->name);
  460. if (hw->ioarea == NULL) {
  461. dev_err(&pdev->dev, "Cannot reserve region\n");
  462. err = -ENXIO;
  463. goto err_no_iores;
  464. }
  465. hw->regs = ioremap(res->start, resource_size(res));
  466. if (hw->regs == NULL) {
  467. dev_err(&pdev->dev, "Cannot map IO\n");
  468. err = -ENXIO;
  469. goto err_no_iomap;
  470. }
  471. hw->irq = platform_get_irq(pdev, 0);
  472. if (hw->irq < 0) {
  473. dev_err(&pdev->dev, "No IRQ specified\n");
  474. err = -ENOENT;
  475. goto err_no_irq;
  476. }
  477. err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
  478. if (err) {
  479. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  480. goto err_no_irq;
  481. }
  482. hw->clk = clk_get(&pdev->dev, "spi");
  483. if (IS_ERR(hw->clk)) {
  484. dev_err(&pdev->dev, "No clock for device\n");
  485. err = PTR_ERR(hw->clk);
  486. goto err_no_clk;
  487. }
  488. /* setup any gpio we can */
  489. if (!pdata->set_cs) {
  490. if (pdata->pin_cs < 0) {
  491. dev_err(&pdev->dev, "No chipselect pin\n");
  492. goto err_register;
  493. }
  494. err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
  495. if (err) {
  496. dev_err(&pdev->dev, "Failed to get gpio for cs\n");
  497. goto err_register;
  498. }
  499. hw->set_cs = s3c24xx_spi_gpiocs;
  500. gpio_direction_output(pdata->pin_cs, 1);
  501. } else
  502. hw->set_cs = pdata->set_cs;
  503. s3c24xx_spi_initialsetup(hw);
  504. /* register our spi controller */
  505. err = spi_bitbang_start(&hw->bitbang);
  506. if (err) {
  507. dev_err(&pdev->dev, "Failed to register SPI master\n");
  508. goto err_register;
  509. }
  510. return 0;
  511. err_register:
  512. if (hw->set_cs == s3c24xx_spi_gpiocs)
  513. gpio_free(pdata->pin_cs);
  514. clk_disable(hw->clk);
  515. clk_put(hw->clk);
  516. err_no_clk:
  517. free_irq(hw->irq, hw);
  518. err_no_irq:
  519. iounmap(hw->regs);
  520. err_no_iomap:
  521. release_resource(hw->ioarea);
  522. kfree(hw->ioarea);
  523. err_no_iores:
  524. err_no_pdata:
  525. spi_master_put(hw->master);
  526. err_nomem:
  527. return err;
  528. }
  529. static int __exit s3c24xx_spi_remove(struct platform_device *dev)
  530. {
  531. struct s3c24xx_spi *hw = platform_get_drvdata(dev);
  532. platform_set_drvdata(dev, NULL);
  533. spi_bitbang_stop(&hw->bitbang);
  534. clk_disable(hw->clk);
  535. clk_put(hw->clk);
  536. free_irq(hw->irq, hw);
  537. iounmap(hw->regs);
  538. if (hw->set_cs == s3c24xx_spi_gpiocs)
  539. gpio_free(hw->pdata->pin_cs);
  540. release_resource(hw->ioarea);
  541. kfree(hw->ioarea);
  542. spi_master_put(hw->master);
  543. return 0;
  544. }
  545. #ifdef CONFIG_PM
  546. static int s3c24xx_spi_suspend(struct device *dev)
  547. {
  548. struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
  549. if (hw->pdata && hw->pdata->gpio_setup)
  550. hw->pdata->gpio_setup(hw->pdata, 0);
  551. clk_disable(hw->clk);
  552. return 0;
  553. }
  554. static int s3c24xx_spi_resume(struct device *dev)
  555. {
  556. struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
  557. s3c24xx_spi_initialsetup(hw);
  558. return 0;
  559. }
  560. static const struct dev_pm_ops s3c24xx_spi_pmops = {
  561. .suspend = s3c24xx_spi_suspend,
  562. .resume = s3c24xx_spi_resume,
  563. };
  564. #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
  565. #else
  566. #define S3C24XX_SPI_PMOPS NULL
  567. #endif /* CONFIG_PM */
  568. MODULE_ALIAS("platform:s3c2410-spi");
  569. static struct platform_driver s3c24xx_spi_driver = {
  570. .remove = __exit_p(s3c24xx_spi_remove),
  571. .driver = {
  572. .name = "s3c2410-spi",
  573. .owner = THIS_MODULE,
  574. .pm = S3C24XX_SPI_PMOPS,
  575. },
  576. };
  577. static int __init s3c24xx_spi_init(void)
  578. {
  579. return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
  580. }
  581. static void __exit s3c24xx_spi_exit(void)
  582. {
  583. platform_driver_unregister(&s3c24xx_spi_driver);
  584. }
  585. module_init(s3c24xx_spi_init);
  586. module_exit(s3c24xx_spi_exit);
  587. MODULE_DESCRIPTION("S3C24XX SPI Driver");
  588. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  589. MODULE_LICENSE("GPL");