spi-nuc900.c 10 KB

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  1. /*
  2. * Copyright (c) 2009 Nuvoton technology.
  3. * Wan ZongShun <mcuos.com@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/init.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/workqueue.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/delay.h>
  15. #include <linux/errno.h>
  16. #include <linux/err.h>
  17. #include <linux/clk.h>
  18. #include <linux/device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/gpio.h>
  21. #include <linux/io.h>
  22. #include <linux/slab.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/spi/spi_bitbang.h>
  25. #include <mach/nuc900_spi.h>
  26. /* usi registers offset */
  27. #define USI_CNT 0x00
  28. #define USI_DIV 0x04
  29. #define USI_SSR 0x08
  30. #define USI_RX0 0x10
  31. #define USI_TX0 0x10
  32. /* usi register bit */
  33. #define ENINT (0x01 << 17)
  34. #define ENFLG (0x01 << 16)
  35. #define TXNUM (0x03 << 8)
  36. #define TXNEG (0x01 << 2)
  37. #define RXNEG (0x01 << 1)
  38. #define LSB (0x01 << 10)
  39. #define SELECTLEV (0x01 << 2)
  40. #define SELECTPOL (0x01 << 31)
  41. #define SELECTSLAVE 0x01
  42. #define GOBUSY 0x01
  43. struct nuc900_spi {
  44. struct spi_bitbang bitbang;
  45. struct completion done;
  46. void __iomem *regs;
  47. int irq;
  48. int len;
  49. int count;
  50. const unsigned char *tx;
  51. unsigned char *rx;
  52. struct clk *clk;
  53. struct resource *ioarea;
  54. struct spi_master *master;
  55. struct spi_device *curdev;
  56. struct device *dev;
  57. struct nuc900_spi_info *pdata;
  58. spinlock_t lock;
  59. struct resource *res;
  60. };
  61. static inline struct nuc900_spi *to_hw(struct spi_device *sdev)
  62. {
  63. return spi_master_get_devdata(sdev->master);
  64. }
  65. static void nuc900_slave_select(struct spi_device *spi, unsigned int ssr)
  66. {
  67. struct nuc900_spi *hw = to_hw(spi);
  68. unsigned int val;
  69. unsigned int cs = spi->mode & SPI_CS_HIGH ? 1 : 0;
  70. unsigned int cpol = spi->mode & SPI_CPOL ? 1 : 0;
  71. unsigned long flags;
  72. spin_lock_irqsave(&hw->lock, flags);
  73. val = __raw_readl(hw->regs + USI_SSR);
  74. if (!cs)
  75. val &= ~SELECTLEV;
  76. else
  77. val |= SELECTLEV;
  78. if (!ssr)
  79. val &= ~SELECTSLAVE;
  80. else
  81. val |= SELECTSLAVE;
  82. __raw_writel(val, hw->regs + USI_SSR);
  83. val = __raw_readl(hw->regs + USI_CNT);
  84. if (!cpol)
  85. val &= ~SELECTPOL;
  86. else
  87. val |= SELECTPOL;
  88. __raw_writel(val, hw->regs + USI_CNT);
  89. spin_unlock_irqrestore(&hw->lock, flags);
  90. }
  91. static void nuc900_spi_chipsel(struct spi_device *spi, int value)
  92. {
  93. switch (value) {
  94. case BITBANG_CS_INACTIVE:
  95. nuc900_slave_select(spi, 0);
  96. break;
  97. case BITBANG_CS_ACTIVE:
  98. nuc900_slave_select(spi, 1);
  99. break;
  100. }
  101. }
  102. static void nuc900_spi_setup_txnum(struct nuc900_spi *hw,
  103. unsigned int txnum)
  104. {
  105. unsigned int val;
  106. unsigned long flags;
  107. spin_lock_irqsave(&hw->lock, flags);
  108. val = __raw_readl(hw->regs + USI_CNT);
  109. if (!txnum)
  110. val &= ~TXNUM;
  111. else
  112. val |= txnum << 0x08;
  113. __raw_writel(val, hw->regs + USI_CNT);
  114. spin_unlock_irqrestore(&hw->lock, flags);
  115. }
  116. static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw,
  117. unsigned int txbitlen)
  118. {
  119. unsigned int val;
  120. unsigned long flags;
  121. spin_lock_irqsave(&hw->lock, flags);
  122. val = __raw_readl(hw->regs + USI_CNT);
  123. val |= (txbitlen << 0x03);
  124. __raw_writel(val, hw->regs + USI_CNT);
  125. spin_unlock_irqrestore(&hw->lock, flags);
  126. }
  127. static void nuc900_spi_gobusy(struct nuc900_spi *hw)
  128. {
  129. unsigned int val;
  130. unsigned long flags;
  131. spin_lock_irqsave(&hw->lock, flags);
  132. val = __raw_readl(hw->regs + USI_CNT);
  133. val |= GOBUSY;
  134. __raw_writel(val, hw->regs + USI_CNT);
  135. spin_unlock_irqrestore(&hw->lock, flags);
  136. }
  137. static int nuc900_spi_setupxfer(struct spi_device *spi,
  138. struct spi_transfer *t)
  139. {
  140. return 0;
  141. }
  142. static int nuc900_spi_setup(struct spi_device *spi)
  143. {
  144. return 0;
  145. }
  146. static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count)
  147. {
  148. return hw->tx ? hw->tx[count] : 0;
  149. }
  150. static int nuc900_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  151. {
  152. struct nuc900_spi *hw = to_hw(spi);
  153. hw->tx = t->tx_buf;
  154. hw->rx = t->rx_buf;
  155. hw->len = t->len;
  156. hw->count = 0;
  157. __raw_writel(hw_txbyte(hw, 0x0), hw->regs + USI_TX0);
  158. nuc900_spi_gobusy(hw);
  159. wait_for_completion(&hw->done);
  160. return hw->count;
  161. }
  162. static irqreturn_t nuc900_spi_irq(int irq, void *dev)
  163. {
  164. struct nuc900_spi *hw = dev;
  165. unsigned int status;
  166. unsigned int count = hw->count;
  167. status = __raw_readl(hw->regs + USI_CNT);
  168. __raw_writel(status, hw->regs + USI_CNT);
  169. if (status & ENFLG) {
  170. hw->count++;
  171. if (hw->rx)
  172. hw->rx[count] = __raw_readl(hw->regs + USI_RX0);
  173. count++;
  174. if (count < hw->len) {
  175. __raw_writel(hw_txbyte(hw, count), hw->regs + USI_TX0);
  176. nuc900_spi_gobusy(hw);
  177. } else {
  178. complete(&hw->done);
  179. }
  180. return IRQ_HANDLED;
  181. }
  182. complete(&hw->done);
  183. return IRQ_HANDLED;
  184. }
  185. static void nuc900_tx_edge(struct nuc900_spi *hw, unsigned int edge)
  186. {
  187. unsigned int val;
  188. unsigned long flags;
  189. spin_lock_irqsave(&hw->lock, flags);
  190. val = __raw_readl(hw->regs + USI_CNT);
  191. if (edge)
  192. val |= TXNEG;
  193. else
  194. val &= ~TXNEG;
  195. __raw_writel(val, hw->regs + USI_CNT);
  196. spin_unlock_irqrestore(&hw->lock, flags);
  197. }
  198. static void nuc900_rx_edge(struct nuc900_spi *hw, unsigned int edge)
  199. {
  200. unsigned int val;
  201. unsigned long flags;
  202. spin_lock_irqsave(&hw->lock, flags);
  203. val = __raw_readl(hw->regs + USI_CNT);
  204. if (edge)
  205. val |= RXNEG;
  206. else
  207. val &= ~RXNEG;
  208. __raw_writel(val, hw->regs + USI_CNT);
  209. spin_unlock_irqrestore(&hw->lock, flags);
  210. }
  211. static void nuc900_send_first(struct nuc900_spi *hw, unsigned int lsb)
  212. {
  213. unsigned int val;
  214. unsigned long flags;
  215. spin_lock_irqsave(&hw->lock, flags);
  216. val = __raw_readl(hw->regs + USI_CNT);
  217. if (lsb)
  218. val |= LSB;
  219. else
  220. val &= ~LSB;
  221. __raw_writel(val, hw->regs + USI_CNT);
  222. spin_unlock_irqrestore(&hw->lock, flags);
  223. }
  224. static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep)
  225. {
  226. unsigned int val;
  227. unsigned long flags;
  228. spin_lock_irqsave(&hw->lock, flags);
  229. val = __raw_readl(hw->regs + USI_CNT);
  230. if (sleep)
  231. val |= (sleep << 12);
  232. else
  233. val &= ~(0x0f << 12);
  234. __raw_writel(val, hw->regs + USI_CNT);
  235. spin_unlock_irqrestore(&hw->lock, flags);
  236. }
  237. static void nuc900_enable_int(struct nuc900_spi *hw)
  238. {
  239. unsigned int val;
  240. unsigned long flags;
  241. spin_lock_irqsave(&hw->lock, flags);
  242. val = __raw_readl(hw->regs + USI_CNT);
  243. val |= ENINT;
  244. __raw_writel(val, hw->regs + USI_CNT);
  245. spin_unlock_irqrestore(&hw->lock, flags);
  246. }
  247. static void nuc900_set_divider(struct nuc900_spi *hw)
  248. {
  249. __raw_writel(hw->pdata->divider, hw->regs + USI_DIV);
  250. }
  251. static void nuc900_init_spi(struct nuc900_spi *hw)
  252. {
  253. clk_enable(hw->clk);
  254. spin_lock_init(&hw->lock);
  255. nuc900_tx_edge(hw, hw->pdata->txneg);
  256. nuc900_rx_edge(hw, hw->pdata->rxneg);
  257. nuc900_send_first(hw, hw->pdata->lsb);
  258. nuc900_set_sleep(hw, hw->pdata->sleep);
  259. nuc900_spi_setup_txbitlen(hw, hw->pdata->txbitlen);
  260. nuc900_spi_setup_txnum(hw, hw->pdata->txnum);
  261. nuc900_set_divider(hw);
  262. nuc900_enable_int(hw);
  263. }
  264. static int __devinit nuc900_spi_probe(struct platform_device *pdev)
  265. {
  266. struct nuc900_spi *hw;
  267. struct spi_master *master;
  268. int err = 0;
  269. master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
  270. if (master == NULL) {
  271. dev_err(&pdev->dev, "No memory for spi_master\n");
  272. err = -ENOMEM;
  273. goto err_nomem;
  274. }
  275. hw = spi_master_get_devdata(master);
  276. memset(hw, 0, sizeof(struct nuc900_spi));
  277. hw->master = spi_master_get(master);
  278. hw->pdata = pdev->dev.platform_data;
  279. hw->dev = &pdev->dev;
  280. if (hw->pdata == NULL) {
  281. dev_err(&pdev->dev, "No platform data supplied\n");
  282. err = -ENOENT;
  283. goto err_pdata;
  284. }
  285. platform_set_drvdata(pdev, hw);
  286. init_completion(&hw->done);
  287. master->mode_bits = SPI_MODE_0;
  288. master->num_chipselect = hw->pdata->num_cs;
  289. master->bus_num = hw->pdata->bus_num;
  290. hw->bitbang.master = hw->master;
  291. hw->bitbang.setup_transfer = nuc900_spi_setupxfer;
  292. hw->bitbang.chipselect = nuc900_spi_chipsel;
  293. hw->bitbang.txrx_bufs = nuc900_spi_txrx;
  294. hw->bitbang.master->setup = nuc900_spi_setup;
  295. hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  296. if (hw->res == NULL) {
  297. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  298. err = -ENOENT;
  299. goto err_pdata;
  300. }
  301. hw->ioarea = request_mem_region(hw->res->start,
  302. resource_size(hw->res), pdev->name);
  303. if (hw->ioarea == NULL) {
  304. dev_err(&pdev->dev, "Cannot reserve region\n");
  305. err = -ENXIO;
  306. goto err_pdata;
  307. }
  308. hw->regs = ioremap(hw->res->start, resource_size(hw->res));
  309. if (hw->regs == NULL) {
  310. dev_err(&pdev->dev, "Cannot map IO\n");
  311. err = -ENXIO;
  312. goto err_iomap;
  313. }
  314. hw->irq = platform_get_irq(pdev, 0);
  315. if (hw->irq < 0) {
  316. dev_err(&pdev->dev, "No IRQ specified\n");
  317. err = -ENOENT;
  318. goto err_irq;
  319. }
  320. err = request_irq(hw->irq, nuc900_spi_irq, 0, pdev->name, hw);
  321. if (err) {
  322. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  323. goto err_irq;
  324. }
  325. hw->clk = clk_get(&pdev->dev, "spi");
  326. if (IS_ERR(hw->clk)) {
  327. dev_err(&pdev->dev, "No clock for device\n");
  328. err = PTR_ERR(hw->clk);
  329. goto err_clk;
  330. }
  331. mfp_set_groupg(&pdev->dev);
  332. nuc900_init_spi(hw);
  333. err = spi_bitbang_start(&hw->bitbang);
  334. if (err) {
  335. dev_err(&pdev->dev, "Failed to register SPI master\n");
  336. goto err_register;
  337. }
  338. return 0;
  339. err_register:
  340. clk_disable(hw->clk);
  341. clk_put(hw->clk);
  342. err_clk:
  343. free_irq(hw->irq, hw);
  344. err_irq:
  345. iounmap(hw->regs);
  346. err_iomap:
  347. release_mem_region(hw->res->start, resource_size(hw->res));
  348. kfree(hw->ioarea);
  349. err_pdata:
  350. spi_master_put(hw->master);
  351. err_nomem:
  352. return err;
  353. }
  354. static int __devexit nuc900_spi_remove(struct platform_device *dev)
  355. {
  356. struct nuc900_spi *hw = platform_get_drvdata(dev);
  357. free_irq(hw->irq, hw);
  358. platform_set_drvdata(dev, NULL);
  359. spi_bitbang_stop(&hw->bitbang);
  360. clk_disable(hw->clk);
  361. clk_put(hw->clk);
  362. iounmap(hw->regs);
  363. release_mem_region(hw->res->start, resource_size(hw->res));
  364. kfree(hw->ioarea);
  365. spi_master_put(hw->master);
  366. return 0;
  367. }
  368. static struct platform_driver nuc900_spi_driver = {
  369. .probe = nuc900_spi_probe,
  370. .remove = __devexit_p(nuc900_spi_remove),
  371. .driver = {
  372. .name = "nuc900-spi",
  373. .owner = THIS_MODULE,
  374. },
  375. };
  376. static int __init nuc900_spi_init(void)
  377. {
  378. return platform_driver_register(&nuc900_spi_driver);
  379. }
  380. static void __exit nuc900_spi_exit(void)
  381. {
  382. platform_driver_unregister(&nuc900_spi_driver);
  383. }
  384. module_init(nuc900_spi_init);
  385. module_exit(nuc900_spi_exit);
  386. MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
  387. MODULE_DESCRIPTION("nuc900 spi driver!");
  388. MODULE_LICENSE("GPL");
  389. MODULE_ALIAS("platform:nuc900-spi");