qeth_core_main.c 135 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include <asm/sysinfo.h>
  25. #include "qeth_core.h"
  26. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  27. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  28. /* N P A M L V H */
  29. [QETH_DBF_SETUP] = {"qeth_setup",
  30. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_MSG] = {"qeth_msg",
  32. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  33. [QETH_DBF_CTRL] = {"qeth_control",
  34. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  35. };
  36. EXPORT_SYMBOL_GPL(qeth_dbf);
  37. struct qeth_card_list_struct qeth_core_card_list;
  38. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  39. struct kmem_cache *qeth_core_header_cache;
  40. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  41. static struct device *qeth_core_root_dev;
  42. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  43. static struct lock_class_key qdio_out_skb_queue_key;
  44. static void qeth_send_control_data_cb(struct qeth_channel *,
  45. struct qeth_cmd_buffer *);
  46. static int qeth_issue_next_read(struct qeth_card *);
  47. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  48. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  49. static void qeth_free_buffer_pool(struct qeth_card *);
  50. static int qeth_qdio_establish(struct qeth_card *);
  51. static inline const char *qeth_get_cardname(struct qeth_card *card)
  52. {
  53. if (card->info.guestlan) {
  54. switch (card->info.type) {
  55. case QETH_CARD_TYPE_OSD:
  56. return " Guest LAN QDIO";
  57. case QETH_CARD_TYPE_IQD:
  58. return " Guest LAN Hiper";
  59. case QETH_CARD_TYPE_OSM:
  60. return " Guest LAN QDIO - OSM";
  61. case QETH_CARD_TYPE_OSX:
  62. return " Guest LAN QDIO - OSX";
  63. default:
  64. return " unknown";
  65. }
  66. } else {
  67. switch (card->info.type) {
  68. case QETH_CARD_TYPE_OSD:
  69. return " OSD Express";
  70. case QETH_CARD_TYPE_IQD:
  71. return " HiperSockets";
  72. case QETH_CARD_TYPE_OSN:
  73. return " OSN QDIO";
  74. case QETH_CARD_TYPE_OSM:
  75. return " OSM QDIO";
  76. case QETH_CARD_TYPE_OSX:
  77. return " OSX QDIO";
  78. default:
  79. return " unknown";
  80. }
  81. }
  82. return " n/a";
  83. }
  84. /* max length to be returned: 14 */
  85. const char *qeth_get_cardname_short(struct qeth_card *card)
  86. {
  87. if (card->info.guestlan) {
  88. switch (card->info.type) {
  89. case QETH_CARD_TYPE_OSD:
  90. return "GuestLAN QDIO";
  91. case QETH_CARD_TYPE_IQD:
  92. return "GuestLAN Hiper";
  93. case QETH_CARD_TYPE_OSM:
  94. return "GuestLAN OSM";
  95. case QETH_CARD_TYPE_OSX:
  96. return "GuestLAN OSX";
  97. default:
  98. return "unknown";
  99. }
  100. } else {
  101. switch (card->info.type) {
  102. case QETH_CARD_TYPE_OSD:
  103. switch (card->info.link_type) {
  104. case QETH_LINK_TYPE_FAST_ETH:
  105. return "OSD_100";
  106. case QETH_LINK_TYPE_HSTR:
  107. return "HSTR";
  108. case QETH_LINK_TYPE_GBIT_ETH:
  109. return "OSD_1000";
  110. case QETH_LINK_TYPE_10GBIT_ETH:
  111. return "OSD_10GIG";
  112. case QETH_LINK_TYPE_LANE_ETH100:
  113. return "OSD_FE_LANE";
  114. case QETH_LINK_TYPE_LANE_TR:
  115. return "OSD_TR_LANE";
  116. case QETH_LINK_TYPE_LANE_ETH1000:
  117. return "OSD_GbE_LANE";
  118. case QETH_LINK_TYPE_LANE:
  119. return "OSD_ATM_LANE";
  120. default:
  121. return "OSD_Express";
  122. }
  123. case QETH_CARD_TYPE_IQD:
  124. return "HiperSockets";
  125. case QETH_CARD_TYPE_OSN:
  126. return "OSN";
  127. case QETH_CARD_TYPE_OSM:
  128. return "OSM_1000";
  129. case QETH_CARD_TYPE_OSX:
  130. return "OSX_10GIG";
  131. default:
  132. return "unknown";
  133. }
  134. }
  135. return "n/a";
  136. }
  137. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  138. int clear_start_mask)
  139. {
  140. unsigned long flags;
  141. spin_lock_irqsave(&card->thread_mask_lock, flags);
  142. card->thread_allowed_mask = threads;
  143. if (clear_start_mask)
  144. card->thread_start_mask &= threads;
  145. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  146. wake_up(&card->wait_q);
  147. }
  148. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  149. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  150. {
  151. unsigned long flags;
  152. int rc = 0;
  153. spin_lock_irqsave(&card->thread_mask_lock, flags);
  154. rc = (card->thread_running_mask & threads);
  155. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  156. return rc;
  157. }
  158. EXPORT_SYMBOL_GPL(qeth_threads_running);
  159. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  160. {
  161. return wait_event_interruptible(card->wait_q,
  162. qeth_threads_running(card, threads) == 0);
  163. }
  164. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  165. void qeth_clear_working_pool_list(struct qeth_card *card)
  166. {
  167. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  168. QETH_CARD_TEXT(card, 5, "clwrklst");
  169. list_for_each_entry_safe(pool_entry, tmp,
  170. &card->qdio.in_buf_pool.entry_list, list){
  171. list_del(&pool_entry->list);
  172. }
  173. }
  174. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  175. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  176. {
  177. struct qeth_buffer_pool_entry *pool_entry;
  178. void *ptr;
  179. int i, j;
  180. QETH_CARD_TEXT(card, 5, "alocpool");
  181. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  182. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  183. if (!pool_entry) {
  184. qeth_free_buffer_pool(card);
  185. return -ENOMEM;
  186. }
  187. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  188. ptr = (void *) __get_free_page(GFP_KERNEL);
  189. if (!ptr) {
  190. while (j > 0)
  191. free_page((unsigned long)
  192. pool_entry->elements[--j]);
  193. kfree(pool_entry);
  194. qeth_free_buffer_pool(card);
  195. return -ENOMEM;
  196. }
  197. pool_entry->elements[j] = ptr;
  198. }
  199. list_add(&pool_entry->init_list,
  200. &card->qdio.init_pool.entry_list);
  201. }
  202. return 0;
  203. }
  204. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  205. {
  206. QETH_CARD_TEXT(card, 2, "realcbp");
  207. if ((card->state != CARD_STATE_DOWN) &&
  208. (card->state != CARD_STATE_RECOVER))
  209. return -EPERM;
  210. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  211. qeth_clear_working_pool_list(card);
  212. qeth_free_buffer_pool(card);
  213. card->qdio.in_buf_pool.buf_count = bufcnt;
  214. card->qdio.init_pool.buf_count = bufcnt;
  215. return qeth_alloc_buffer_pool(card);
  216. }
  217. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  218. static int qeth_issue_next_read(struct qeth_card *card)
  219. {
  220. int rc;
  221. struct qeth_cmd_buffer *iob;
  222. QETH_CARD_TEXT(card, 5, "issnxrd");
  223. if (card->read.state != CH_STATE_UP)
  224. return -EIO;
  225. iob = qeth_get_buffer(&card->read);
  226. if (!iob) {
  227. dev_warn(&card->gdev->dev, "The qeth device driver "
  228. "failed to recover an error on the device\n");
  229. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  230. "available\n", dev_name(&card->gdev->dev));
  231. return -ENOMEM;
  232. }
  233. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  234. QETH_CARD_TEXT(card, 6, "noirqpnd");
  235. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  236. (addr_t) iob, 0, 0);
  237. if (rc) {
  238. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  239. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  240. atomic_set(&card->read.irq_pending, 0);
  241. card->read_or_write_problem = 1;
  242. qeth_schedule_recovery(card);
  243. wake_up(&card->wait_q);
  244. }
  245. return rc;
  246. }
  247. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  248. {
  249. struct qeth_reply *reply;
  250. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  251. if (reply) {
  252. atomic_set(&reply->refcnt, 1);
  253. atomic_set(&reply->received, 0);
  254. reply->card = card;
  255. };
  256. return reply;
  257. }
  258. static void qeth_get_reply(struct qeth_reply *reply)
  259. {
  260. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  261. atomic_inc(&reply->refcnt);
  262. }
  263. static void qeth_put_reply(struct qeth_reply *reply)
  264. {
  265. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  266. if (atomic_dec_and_test(&reply->refcnt))
  267. kfree(reply);
  268. }
  269. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  270. struct qeth_card *card)
  271. {
  272. char *ipa_name;
  273. int com = cmd->hdr.command;
  274. ipa_name = qeth_get_ipa_cmd_name(com);
  275. if (rc)
  276. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  277. "x%X \"%s\"\n",
  278. ipa_name, com, dev_name(&card->gdev->dev),
  279. QETH_CARD_IFNAME(card), rc,
  280. qeth_get_ipa_msg(rc));
  281. else
  282. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  283. ipa_name, com, dev_name(&card->gdev->dev),
  284. QETH_CARD_IFNAME(card));
  285. }
  286. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  287. struct qeth_cmd_buffer *iob)
  288. {
  289. struct qeth_ipa_cmd *cmd = NULL;
  290. QETH_CARD_TEXT(card, 5, "chkipad");
  291. if (IS_IPA(iob->data)) {
  292. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  293. if (IS_IPA_REPLY(cmd)) {
  294. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  295. cmd->hdr.command != IPA_CMD_DELCCID &&
  296. cmd->hdr.command != IPA_CMD_MODCCID &&
  297. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  298. qeth_issue_ipa_msg(cmd,
  299. cmd->hdr.return_code, card);
  300. return cmd;
  301. } else {
  302. switch (cmd->hdr.command) {
  303. case IPA_CMD_STOPLAN:
  304. dev_warn(&card->gdev->dev,
  305. "The link for interface %s on CHPID"
  306. " 0x%X failed\n",
  307. QETH_CARD_IFNAME(card),
  308. card->info.chpid);
  309. card->lan_online = 0;
  310. if (card->dev && netif_carrier_ok(card->dev))
  311. netif_carrier_off(card->dev);
  312. return NULL;
  313. case IPA_CMD_STARTLAN:
  314. dev_info(&card->gdev->dev,
  315. "The link for %s on CHPID 0x%X has"
  316. " been restored\n",
  317. QETH_CARD_IFNAME(card),
  318. card->info.chpid);
  319. netif_carrier_on(card->dev);
  320. card->lan_online = 1;
  321. if (card->info.hwtrap)
  322. card->info.hwtrap = 2;
  323. qeth_schedule_recovery(card);
  324. return NULL;
  325. case IPA_CMD_MODCCID:
  326. return cmd;
  327. case IPA_CMD_REGISTER_LOCAL_ADDR:
  328. QETH_CARD_TEXT(card, 3, "irla");
  329. break;
  330. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  331. QETH_CARD_TEXT(card, 3, "urla");
  332. break;
  333. default:
  334. QETH_DBF_MESSAGE(2, "Received data is IPA "
  335. "but not a reply!\n");
  336. break;
  337. }
  338. }
  339. }
  340. return cmd;
  341. }
  342. void qeth_clear_ipacmd_list(struct qeth_card *card)
  343. {
  344. struct qeth_reply *reply, *r;
  345. unsigned long flags;
  346. QETH_CARD_TEXT(card, 4, "clipalst");
  347. spin_lock_irqsave(&card->lock, flags);
  348. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  349. qeth_get_reply(reply);
  350. reply->rc = -EIO;
  351. atomic_inc(&reply->received);
  352. list_del_init(&reply->list);
  353. wake_up(&reply->wait_q);
  354. qeth_put_reply(reply);
  355. }
  356. spin_unlock_irqrestore(&card->lock, flags);
  357. atomic_set(&card->write.irq_pending, 0);
  358. }
  359. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  360. static int qeth_check_idx_response(struct qeth_card *card,
  361. unsigned char *buffer)
  362. {
  363. if (!buffer)
  364. return 0;
  365. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  366. if ((buffer[2] & 0xc0) == 0xc0) {
  367. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  368. "with cause code 0x%02x%s\n",
  369. buffer[4],
  370. ((buffer[4] == 0x22) ?
  371. " -- try another portname" : ""));
  372. QETH_CARD_TEXT(card, 2, "ckidxres");
  373. QETH_CARD_TEXT(card, 2, " idxterm");
  374. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  375. if (buffer[4] == 0xf6) {
  376. dev_err(&card->gdev->dev,
  377. "The qeth device is not configured "
  378. "for the OSI layer required by z/VM\n");
  379. return -EPERM;
  380. }
  381. return -EIO;
  382. }
  383. return 0;
  384. }
  385. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  386. __u32 len)
  387. {
  388. struct qeth_card *card;
  389. card = CARD_FROM_CDEV(channel->ccwdev);
  390. QETH_CARD_TEXT(card, 4, "setupccw");
  391. if (channel == &card->read)
  392. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  393. else
  394. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  395. channel->ccw.count = len;
  396. channel->ccw.cda = (__u32) __pa(iob);
  397. }
  398. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  399. {
  400. __u8 index;
  401. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  402. index = channel->io_buf_no;
  403. do {
  404. if (channel->iob[index].state == BUF_STATE_FREE) {
  405. channel->iob[index].state = BUF_STATE_LOCKED;
  406. channel->io_buf_no = (channel->io_buf_no + 1) %
  407. QETH_CMD_BUFFER_NO;
  408. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  409. return channel->iob + index;
  410. }
  411. index = (index + 1) % QETH_CMD_BUFFER_NO;
  412. } while (index != channel->io_buf_no);
  413. return NULL;
  414. }
  415. void qeth_release_buffer(struct qeth_channel *channel,
  416. struct qeth_cmd_buffer *iob)
  417. {
  418. unsigned long flags;
  419. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  420. spin_lock_irqsave(&channel->iob_lock, flags);
  421. memset(iob->data, 0, QETH_BUFSIZE);
  422. iob->state = BUF_STATE_FREE;
  423. iob->callback = qeth_send_control_data_cb;
  424. iob->rc = 0;
  425. spin_unlock_irqrestore(&channel->iob_lock, flags);
  426. }
  427. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  428. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  429. {
  430. struct qeth_cmd_buffer *buffer = NULL;
  431. unsigned long flags;
  432. spin_lock_irqsave(&channel->iob_lock, flags);
  433. buffer = __qeth_get_buffer(channel);
  434. spin_unlock_irqrestore(&channel->iob_lock, flags);
  435. return buffer;
  436. }
  437. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  438. {
  439. struct qeth_cmd_buffer *buffer;
  440. wait_event(channel->wait_q,
  441. ((buffer = qeth_get_buffer(channel)) != NULL));
  442. return buffer;
  443. }
  444. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  445. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  446. {
  447. int cnt;
  448. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  449. qeth_release_buffer(channel, &channel->iob[cnt]);
  450. channel->buf_no = 0;
  451. channel->io_buf_no = 0;
  452. }
  453. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  454. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  455. struct qeth_cmd_buffer *iob)
  456. {
  457. struct qeth_card *card;
  458. struct qeth_reply *reply, *r;
  459. struct qeth_ipa_cmd *cmd;
  460. unsigned long flags;
  461. int keep_reply;
  462. int rc = 0;
  463. card = CARD_FROM_CDEV(channel->ccwdev);
  464. QETH_CARD_TEXT(card, 4, "sndctlcb");
  465. rc = qeth_check_idx_response(card, iob->data);
  466. switch (rc) {
  467. case 0:
  468. break;
  469. case -EIO:
  470. qeth_clear_ipacmd_list(card);
  471. qeth_schedule_recovery(card);
  472. /* fall through */
  473. default:
  474. goto out;
  475. }
  476. cmd = qeth_check_ipa_data(card, iob);
  477. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  478. goto out;
  479. /*in case of OSN : check if cmd is set */
  480. if (card->info.type == QETH_CARD_TYPE_OSN &&
  481. cmd &&
  482. cmd->hdr.command != IPA_CMD_STARTLAN &&
  483. card->osn_info.assist_cb != NULL) {
  484. card->osn_info.assist_cb(card->dev, cmd);
  485. goto out;
  486. }
  487. spin_lock_irqsave(&card->lock, flags);
  488. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  489. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  490. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  491. qeth_get_reply(reply);
  492. list_del_init(&reply->list);
  493. spin_unlock_irqrestore(&card->lock, flags);
  494. keep_reply = 0;
  495. if (reply->callback != NULL) {
  496. if (cmd) {
  497. reply->offset = (__u16)((char *)cmd -
  498. (char *)iob->data);
  499. keep_reply = reply->callback(card,
  500. reply,
  501. (unsigned long)cmd);
  502. } else
  503. keep_reply = reply->callback(card,
  504. reply,
  505. (unsigned long)iob);
  506. }
  507. if (cmd)
  508. reply->rc = (u16) cmd->hdr.return_code;
  509. else if (iob->rc)
  510. reply->rc = iob->rc;
  511. if (keep_reply) {
  512. spin_lock_irqsave(&card->lock, flags);
  513. list_add_tail(&reply->list,
  514. &card->cmd_waiter_list);
  515. spin_unlock_irqrestore(&card->lock, flags);
  516. } else {
  517. atomic_inc(&reply->received);
  518. wake_up(&reply->wait_q);
  519. }
  520. qeth_put_reply(reply);
  521. goto out;
  522. }
  523. }
  524. spin_unlock_irqrestore(&card->lock, flags);
  525. out:
  526. memcpy(&card->seqno.pdu_hdr_ack,
  527. QETH_PDU_HEADER_SEQ_NO(iob->data),
  528. QETH_SEQ_NO_LENGTH);
  529. qeth_release_buffer(channel, iob);
  530. }
  531. static int qeth_setup_channel(struct qeth_channel *channel)
  532. {
  533. int cnt;
  534. QETH_DBF_TEXT(SETUP, 2, "setupch");
  535. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  536. channel->iob[cnt].data =
  537. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  538. if (channel->iob[cnt].data == NULL)
  539. break;
  540. channel->iob[cnt].state = BUF_STATE_FREE;
  541. channel->iob[cnt].channel = channel;
  542. channel->iob[cnt].callback = qeth_send_control_data_cb;
  543. channel->iob[cnt].rc = 0;
  544. }
  545. if (cnt < QETH_CMD_BUFFER_NO) {
  546. while (cnt-- > 0)
  547. kfree(channel->iob[cnt].data);
  548. return -ENOMEM;
  549. }
  550. channel->buf_no = 0;
  551. channel->io_buf_no = 0;
  552. atomic_set(&channel->irq_pending, 0);
  553. spin_lock_init(&channel->iob_lock);
  554. init_waitqueue_head(&channel->wait_q);
  555. return 0;
  556. }
  557. static int qeth_set_thread_start_bit(struct qeth_card *card,
  558. unsigned long thread)
  559. {
  560. unsigned long flags;
  561. spin_lock_irqsave(&card->thread_mask_lock, flags);
  562. if (!(card->thread_allowed_mask & thread) ||
  563. (card->thread_start_mask & thread)) {
  564. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  565. return -EPERM;
  566. }
  567. card->thread_start_mask |= thread;
  568. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  569. return 0;
  570. }
  571. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  572. {
  573. unsigned long flags;
  574. spin_lock_irqsave(&card->thread_mask_lock, flags);
  575. card->thread_start_mask &= ~thread;
  576. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  577. wake_up(&card->wait_q);
  578. }
  579. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  580. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  581. {
  582. unsigned long flags;
  583. spin_lock_irqsave(&card->thread_mask_lock, flags);
  584. card->thread_running_mask &= ~thread;
  585. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  586. wake_up(&card->wait_q);
  587. }
  588. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  589. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  590. {
  591. unsigned long flags;
  592. int rc = 0;
  593. spin_lock_irqsave(&card->thread_mask_lock, flags);
  594. if (card->thread_start_mask & thread) {
  595. if ((card->thread_allowed_mask & thread) &&
  596. !(card->thread_running_mask & thread)) {
  597. rc = 1;
  598. card->thread_start_mask &= ~thread;
  599. card->thread_running_mask |= thread;
  600. } else
  601. rc = -EPERM;
  602. }
  603. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  604. return rc;
  605. }
  606. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  607. {
  608. int rc = 0;
  609. wait_event(card->wait_q,
  610. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  611. return rc;
  612. }
  613. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  614. void qeth_schedule_recovery(struct qeth_card *card)
  615. {
  616. QETH_CARD_TEXT(card, 2, "startrec");
  617. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  618. schedule_work(&card->kernel_thread_starter);
  619. }
  620. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  621. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  622. {
  623. int dstat, cstat;
  624. char *sense;
  625. struct qeth_card *card;
  626. sense = (char *) irb->ecw;
  627. cstat = irb->scsw.cmd.cstat;
  628. dstat = irb->scsw.cmd.dstat;
  629. card = CARD_FROM_CDEV(cdev);
  630. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  631. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  632. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  633. QETH_CARD_TEXT(card, 2, "CGENCHK");
  634. dev_warn(&cdev->dev, "The qeth device driver "
  635. "failed to recover an error on the device\n");
  636. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  637. dev_name(&cdev->dev), dstat, cstat);
  638. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  639. 16, 1, irb, 64, 1);
  640. return 1;
  641. }
  642. if (dstat & DEV_STAT_UNIT_CHECK) {
  643. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  644. SENSE_RESETTING_EVENT_FLAG) {
  645. QETH_CARD_TEXT(card, 2, "REVIND");
  646. return 1;
  647. }
  648. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  649. SENSE_COMMAND_REJECT_FLAG) {
  650. QETH_CARD_TEXT(card, 2, "CMDREJi");
  651. return 1;
  652. }
  653. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  654. QETH_CARD_TEXT(card, 2, "AFFE");
  655. return 1;
  656. }
  657. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  658. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  659. return 0;
  660. }
  661. QETH_CARD_TEXT(card, 2, "DGENCHK");
  662. return 1;
  663. }
  664. return 0;
  665. }
  666. static long __qeth_check_irb_error(struct ccw_device *cdev,
  667. unsigned long intparm, struct irb *irb)
  668. {
  669. struct qeth_card *card;
  670. card = CARD_FROM_CDEV(cdev);
  671. if (!IS_ERR(irb))
  672. return 0;
  673. switch (PTR_ERR(irb)) {
  674. case -EIO:
  675. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  676. dev_name(&cdev->dev));
  677. QETH_CARD_TEXT(card, 2, "ckirberr");
  678. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  679. break;
  680. case -ETIMEDOUT:
  681. dev_warn(&cdev->dev, "A hardware operation timed out"
  682. " on the device\n");
  683. QETH_CARD_TEXT(card, 2, "ckirberr");
  684. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  685. if (intparm == QETH_RCD_PARM) {
  686. if (card && (card->data.ccwdev == cdev)) {
  687. card->data.state = CH_STATE_DOWN;
  688. wake_up(&card->wait_q);
  689. }
  690. }
  691. break;
  692. default:
  693. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  694. dev_name(&cdev->dev), PTR_ERR(irb));
  695. QETH_CARD_TEXT(card, 2, "ckirberr");
  696. QETH_CARD_TEXT(card, 2, " rc???");
  697. }
  698. return PTR_ERR(irb);
  699. }
  700. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  701. struct irb *irb)
  702. {
  703. int rc;
  704. int cstat, dstat;
  705. struct qeth_cmd_buffer *buffer;
  706. struct qeth_channel *channel;
  707. struct qeth_card *card;
  708. struct qeth_cmd_buffer *iob;
  709. __u8 index;
  710. if (__qeth_check_irb_error(cdev, intparm, irb))
  711. return;
  712. cstat = irb->scsw.cmd.cstat;
  713. dstat = irb->scsw.cmd.dstat;
  714. card = CARD_FROM_CDEV(cdev);
  715. if (!card)
  716. return;
  717. QETH_CARD_TEXT(card, 5, "irq");
  718. if (card->read.ccwdev == cdev) {
  719. channel = &card->read;
  720. QETH_CARD_TEXT(card, 5, "read");
  721. } else if (card->write.ccwdev == cdev) {
  722. channel = &card->write;
  723. QETH_CARD_TEXT(card, 5, "write");
  724. } else {
  725. channel = &card->data;
  726. QETH_CARD_TEXT(card, 5, "data");
  727. }
  728. atomic_set(&channel->irq_pending, 0);
  729. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  730. channel->state = CH_STATE_STOPPED;
  731. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  732. channel->state = CH_STATE_HALTED;
  733. /*let's wake up immediately on data channel*/
  734. if ((channel == &card->data) && (intparm != 0) &&
  735. (intparm != QETH_RCD_PARM))
  736. goto out;
  737. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  738. QETH_CARD_TEXT(card, 6, "clrchpar");
  739. /* we don't have to handle this further */
  740. intparm = 0;
  741. }
  742. if (intparm == QETH_HALT_CHANNEL_PARM) {
  743. QETH_CARD_TEXT(card, 6, "hltchpar");
  744. /* we don't have to handle this further */
  745. intparm = 0;
  746. }
  747. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  748. (dstat & DEV_STAT_UNIT_CHECK) ||
  749. (cstat)) {
  750. if (irb->esw.esw0.erw.cons) {
  751. dev_warn(&channel->ccwdev->dev,
  752. "The qeth device driver failed to recover "
  753. "an error on the device\n");
  754. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  755. "0x%X dstat 0x%X\n",
  756. dev_name(&channel->ccwdev->dev), cstat, dstat);
  757. print_hex_dump(KERN_WARNING, "qeth: irb ",
  758. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  759. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  760. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  761. }
  762. if (intparm == QETH_RCD_PARM) {
  763. channel->state = CH_STATE_DOWN;
  764. goto out;
  765. }
  766. rc = qeth_get_problem(cdev, irb);
  767. if (rc) {
  768. qeth_clear_ipacmd_list(card);
  769. qeth_schedule_recovery(card);
  770. goto out;
  771. }
  772. }
  773. if (intparm == QETH_RCD_PARM) {
  774. channel->state = CH_STATE_RCD_DONE;
  775. goto out;
  776. }
  777. if (intparm) {
  778. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  779. buffer->state = BUF_STATE_PROCESSED;
  780. }
  781. if (channel == &card->data)
  782. return;
  783. if (channel == &card->read &&
  784. channel->state == CH_STATE_UP)
  785. qeth_issue_next_read(card);
  786. iob = channel->iob;
  787. index = channel->buf_no;
  788. while (iob[index].state == BUF_STATE_PROCESSED) {
  789. if (iob[index].callback != NULL)
  790. iob[index].callback(channel, iob + index);
  791. index = (index + 1) % QETH_CMD_BUFFER_NO;
  792. }
  793. channel->buf_no = index;
  794. out:
  795. wake_up(&card->wait_q);
  796. return;
  797. }
  798. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  799. struct qeth_qdio_out_buffer *buf)
  800. {
  801. int i;
  802. struct sk_buff *skb;
  803. /* is PCI flag set on buffer? */
  804. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  805. atomic_dec(&queue->set_pci_flags_count);
  806. skb = skb_dequeue(&buf->skb_list);
  807. while (skb) {
  808. atomic_dec(&skb->users);
  809. dev_kfree_skb_any(skb);
  810. skb = skb_dequeue(&buf->skb_list);
  811. }
  812. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  813. if (buf->buffer->element[i].addr && buf->is_header[i])
  814. kmem_cache_free(qeth_core_header_cache,
  815. buf->buffer->element[i].addr);
  816. buf->is_header[i] = 0;
  817. buf->buffer->element[i].length = 0;
  818. buf->buffer->element[i].addr = NULL;
  819. buf->buffer->element[i].eflags = 0;
  820. buf->buffer->element[i].sflags = 0;
  821. }
  822. buf->buffer->element[15].eflags = 0;
  823. buf->buffer->element[15].sflags = 0;
  824. buf->next_element_to_fill = 0;
  825. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  826. }
  827. void qeth_clear_qdio_buffers(struct qeth_card *card)
  828. {
  829. int i, j;
  830. QETH_CARD_TEXT(card, 2, "clearqdbf");
  831. /* clear outbound buffers to free skbs */
  832. for (i = 0; i < card->qdio.no_out_queues; ++i)
  833. if (card->qdio.out_qs[i]) {
  834. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  835. qeth_clear_output_buffer(card->qdio.out_qs[i],
  836. &card->qdio.out_qs[i]->bufs[j]);
  837. }
  838. }
  839. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  840. static void qeth_free_buffer_pool(struct qeth_card *card)
  841. {
  842. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  843. int i = 0;
  844. list_for_each_entry_safe(pool_entry, tmp,
  845. &card->qdio.init_pool.entry_list, init_list){
  846. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  847. free_page((unsigned long)pool_entry->elements[i]);
  848. list_del(&pool_entry->init_list);
  849. kfree(pool_entry);
  850. }
  851. }
  852. static void qeth_free_qdio_buffers(struct qeth_card *card)
  853. {
  854. int i, j;
  855. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  856. QETH_QDIO_UNINITIALIZED)
  857. return;
  858. kfree(card->qdio.in_q);
  859. card->qdio.in_q = NULL;
  860. /* inbound buffer pool */
  861. qeth_free_buffer_pool(card);
  862. /* free outbound qdio_qs */
  863. if (card->qdio.out_qs) {
  864. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  865. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  866. qeth_clear_output_buffer(card->qdio.out_qs[i],
  867. &card->qdio.out_qs[i]->bufs[j]);
  868. kfree(card->qdio.out_qs[i]);
  869. }
  870. kfree(card->qdio.out_qs);
  871. card->qdio.out_qs = NULL;
  872. }
  873. }
  874. static void qeth_clean_channel(struct qeth_channel *channel)
  875. {
  876. int cnt;
  877. QETH_DBF_TEXT(SETUP, 2, "freech");
  878. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  879. kfree(channel->iob[cnt].data);
  880. }
  881. static void qeth_get_channel_path_desc(struct qeth_card *card)
  882. {
  883. struct ccw_device *ccwdev;
  884. struct channelPath_dsc {
  885. u8 flags;
  886. u8 lsn;
  887. u8 desc;
  888. u8 chpid;
  889. u8 swla;
  890. u8 zeroes;
  891. u8 chla;
  892. u8 chpp;
  893. } *chp_dsc;
  894. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  895. ccwdev = card->data.ccwdev;
  896. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  897. if (chp_dsc != NULL) {
  898. /* CHPP field bit 6 == 1 -> single queue */
  899. if ((chp_dsc->chpp & 0x02) == 0x02) {
  900. if ((atomic_read(&card->qdio.state) !=
  901. QETH_QDIO_UNINITIALIZED) &&
  902. (card->qdio.no_out_queues == 4))
  903. /* change from 4 to 1 outbound queues */
  904. qeth_free_qdio_buffers(card);
  905. card->qdio.no_out_queues = 1;
  906. if (card->qdio.default_out_queue != 0)
  907. dev_info(&card->gdev->dev,
  908. "Priority Queueing not supported\n");
  909. card->qdio.default_out_queue = 0;
  910. } else {
  911. if ((atomic_read(&card->qdio.state) !=
  912. QETH_QDIO_UNINITIALIZED) &&
  913. (card->qdio.no_out_queues == 1)) {
  914. /* change from 1 to 4 outbound queues */
  915. qeth_free_qdio_buffers(card);
  916. card->qdio.default_out_queue = 2;
  917. }
  918. card->qdio.no_out_queues = 4;
  919. }
  920. card->info.func_level = 0x4100 + chp_dsc->desc;
  921. kfree(chp_dsc);
  922. }
  923. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  924. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  925. return;
  926. }
  927. static void qeth_init_qdio_info(struct qeth_card *card)
  928. {
  929. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  930. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  931. /* inbound */
  932. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  933. if (card->info.type == QETH_CARD_TYPE_IQD)
  934. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  935. else
  936. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  937. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  938. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  939. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  940. }
  941. static void qeth_set_intial_options(struct qeth_card *card)
  942. {
  943. card->options.route4.type = NO_ROUTER;
  944. card->options.route6.type = NO_ROUTER;
  945. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  946. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  947. card->options.fake_broadcast = 0;
  948. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  949. card->options.performance_stats = 0;
  950. card->options.rx_sg_cb = QETH_RX_SG_CB;
  951. card->options.isolation = ISOLATION_MODE_NONE;
  952. }
  953. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  954. {
  955. unsigned long flags;
  956. int rc = 0;
  957. spin_lock_irqsave(&card->thread_mask_lock, flags);
  958. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  959. (u8) card->thread_start_mask,
  960. (u8) card->thread_allowed_mask,
  961. (u8) card->thread_running_mask);
  962. rc = (card->thread_start_mask & thread);
  963. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  964. return rc;
  965. }
  966. static void qeth_start_kernel_thread(struct work_struct *work)
  967. {
  968. struct qeth_card *card = container_of(work, struct qeth_card,
  969. kernel_thread_starter);
  970. QETH_CARD_TEXT(card , 2, "strthrd");
  971. if (card->read.state != CH_STATE_UP &&
  972. card->write.state != CH_STATE_UP)
  973. return;
  974. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  975. kthread_run(card->discipline.recover, (void *) card,
  976. "qeth_recover");
  977. }
  978. static int qeth_setup_card(struct qeth_card *card)
  979. {
  980. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  981. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  982. card->read.state = CH_STATE_DOWN;
  983. card->write.state = CH_STATE_DOWN;
  984. card->data.state = CH_STATE_DOWN;
  985. card->state = CARD_STATE_DOWN;
  986. card->lan_online = 0;
  987. card->read_or_write_problem = 0;
  988. card->dev = NULL;
  989. spin_lock_init(&card->vlanlock);
  990. spin_lock_init(&card->mclock);
  991. spin_lock_init(&card->lock);
  992. spin_lock_init(&card->ip_lock);
  993. spin_lock_init(&card->thread_mask_lock);
  994. mutex_init(&card->conf_mutex);
  995. mutex_init(&card->discipline_mutex);
  996. card->thread_start_mask = 0;
  997. card->thread_allowed_mask = 0;
  998. card->thread_running_mask = 0;
  999. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1000. INIT_LIST_HEAD(&card->ip_list);
  1001. INIT_LIST_HEAD(card->ip_tbd_list);
  1002. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1003. init_waitqueue_head(&card->wait_q);
  1004. /* initial options */
  1005. qeth_set_intial_options(card);
  1006. /* IP address takeover */
  1007. INIT_LIST_HEAD(&card->ipato.entries);
  1008. card->ipato.enabled = 0;
  1009. card->ipato.invert4 = 0;
  1010. card->ipato.invert6 = 0;
  1011. /* init QDIO stuff */
  1012. qeth_init_qdio_info(card);
  1013. return 0;
  1014. }
  1015. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1016. {
  1017. struct qeth_card *card = container_of(slr, struct qeth_card,
  1018. qeth_service_level);
  1019. if (card->info.mcl_level[0])
  1020. seq_printf(m, "qeth: %s firmware level %s\n",
  1021. CARD_BUS_ID(card), card->info.mcl_level);
  1022. }
  1023. static struct qeth_card *qeth_alloc_card(void)
  1024. {
  1025. struct qeth_card *card;
  1026. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1027. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1028. if (!card)
  1029. goto out;
  1030. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1031. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1032. if (!card->ip_tbd_list) {
  1033. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1034. goto out_card;
  1035. }
  1036. if (qeth_setup_channel(&card->read))
  1037. goto out_ip;
  1038. if (qeth_setup_channel(&card->write))
  1039. goto out_channel;
  1040. card->options.layer2 = -1;
  1041. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1042. register_service_level(&card->qeth_service_level);
  1043. return card;
  1044. out_channel:
  1045. qeth_clean_channel(&card->read);
  1046. out_ip:
  1047. kfree(card->ip_tbd_list);
  1048. out_card:
  1049. kfree(card);
  1050. out:
  1051. return NULL;
  1052. }
  1053. static int qeth_determine_card_type(struct qeth_card *card)
  1054. {
  1055. int i = 0;
  1056. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1057. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1058. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1059. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1060. if ((CARD_RDEV(card)->id.dev_type ==
  1061. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1062. (CARD_RDEV(card)->id.dev_model ==
  1063. known_devices[i][QETH_DEV_MODEL_IND])) {
  1064. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1065. card->qdio.no_out_queues =
  1066. known_devices[i][QETH_QUEUE_NO_IND];
  1067. card->info.is_multicast_different =
  1068. known_devices[i][QETH_MULTICAST_IND];
  1069. qeth_get_channel_path_desc(card);
  1070. return 0;
  1071. }
  1072. i++;
  1073. }
  1074. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1075. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1076. "unknown type\n");
  1077. return -ENOENT;
  1078. }
  1079. static int qeth_clear_channel(struct qeth_channel *channel)
  1080. {
  1081. unsigned long flags;
  1082. struct qeth_card *card;
  1083. int rc;
  1084. card = CARD_FROM_CDEV(channel->ccwdev);
  1085. QETH_CARD_TEXT(card, 3, "clearch");
  1086. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1087. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1088. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1089. if (rc)
  1090. return rc;
  1091. rc = wait_event_interruptible_timeout(card->wait_q,
  1092. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1093. if (rc == -ERESTARTSYS)
  1094. return rc;
  1095. if (channel->state != CH_STATE_STOPPED)
  1096. return -ETIME;
  1097. channel->state = CH_STATE_DOWN;
  1098. return 0;
  1099. }
  1100. static int qeth_halt_channel(struct qeth_channel *channel)
  1101. {
  1102. unsigned long flags;
  1103. struct qeth_card *card;
  1104. int rc;
  1105. card = CARD_FROM_CDEV(channel->ccwdev);
  1106. QETH_CARD_TEXT(card, 3, "haltch");
  1107. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1108. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1109. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1110. if (rc)
  1111. return rc;
  1112. rc = wait_event_interruptible_timeout(card->wait_q,
  1113. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1114. if (rc == -ERESTARTSYS)
  1115. return rc;
  1116. if (channel->state != CH_STATE_HALTED)
  1117. return -ETIME;
  1118. return 0;
  1119. }
  1120. static int qeth_halt_channels(struct qeth_card *card)
  1121. {
  1122. int rc1 = 0, rc2 = 0, rc3 = 0;
  1123. QETH_CARD_TEXT(card, 3, "haltchs");
  1124. rc1 = qeth_halt_channel(&card->read);
  1125. rc2 = qeth_halt_channel(&card->write);
  1126. rc3 = qeth_halt_channel(&card->data);
  1127. if (rc1)
  1128. return rc1;
  1129. if (rc2)
  1130. return rc2;
  1131. return rc3;
  1132. }
  1133. static int qeth_clear_channels(struct qeth_card *card)
  1134. {
  1135. int rc1 = 0, rc2 = 0, rc3 = 0;
  1136. QETH_CARD_TEXT(card, 3, "clearchs");
  1137. rc1 = qeth_clear_channel(&card->read);
  1138. rc2 = qeth_clear_channel(&card->write);
  1139. rc3 = qeth_clear_channel(&card->data);
  1140. if (rc1)
  1141. return rc1;
  1142. if (rc2)
  1143. return rc2;
  1144. return rc3;
  1145. }
  1146. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1147. {
  1148. int rc = 0;
  1149. QETH_CARD_TEXT(card, 3, "clhacrd");
  1150. if (halt)
  1151. rc = qeth_halt_channels(card);
  1152. if (rc)
  1153. return rc;
  1154. return qeth_clear_channels(card);
  1155. }
  1156. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1157. {
  1158. int rc = 0;
  1159. QETH_CARD_TEXT(card, 3, "qdioclr");
  1160. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1161. QETH_QDIO_CLEANING)) {
  1162. case QETH_QDIO_ESTABLISHED:
  1163. if (card->info.type == QETH_CARD_TYPE_IQD)
  1164. rc = qdio_shutdown(CARD_DDEV(card),
  1165. QDIO_FLAG_CLEANUP_USING_HALT);
  1166. else
  1167. rc = qdio_shutdown(CARD_DDEV(card),
  1168. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1169. if (rc)
  1170. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1171. qdio_free(CARD_DDEV(card));
  1172. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1173. break;
  1174. case QETH_QDIO_CLEANING:
  1175. return rc;
  1176. default:
  1177. break;
  1178. }
  1179. rc = qeth_clear_halt_card(card, use_halt);
  1180. if (rc)
  1181. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1182. card->state = CARD_STATE_DOWN;
  1183. return rc;
  1184. }
  1185. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1186. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1187. int *length)
  1188. {
  1189. struct ciw *ciw;
  1190. char *rcd_buf;
  1191. int ret;
  1192. struct qeth_channel *channel = &card->data;
  1193. unsigned long flags;
  1194. /*
  1195. * scan for RCD command in extended SenseID data
  1196. */
  1197. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1198. if (!ciw || ciw->cmd == 0)
  1199. return -EOPNOTSUPP;
  1200. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1201. if (!rcd_buf)
  1202. return -ENOMEM;
  1203. channel->ccw.cmd_code = ciw->cmd;
  1204. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1205. channel->ccw.count = ciw->count;
  1206. channel->ccw.flags = CCW_FLAG_SLI;
  1207. channel->state = CH_STATE_RCD;
  1208. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1209. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1210. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1211. QETH_RCD_TIMEOUT);
  1212. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1213. if (!ret)
  1214. wait_event(card->wait_q,
  1215. (channel->state == CH_STATE_RCD_DONE ||
  1216. channel->state == CH_STATE_DOWN));
  1217. if (channel->state == CH_STATE_DOWN)
  1218. ret = -EIO;
  1219. else
  1220. channel->state = CH_STATE_DOWN;
  1221. if (ret) {
  1222. kfree(rcd_buf);
  1223. *buffer = NULL;
  1224. *length = 0;
  1225. } else {
  1226. *length = ciw->count;
  1227. *buffer = rcd_buf;
  1228. }
  1229. return ret;
  1230. }
  1231. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1232. {
  1233. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1234. card->info.chpid = prcd[30];
  1235. card->info.unit_addr2 = prcd[31];
  1236. card->info.cula = prcd[63];
  1237. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1238. (prcd[0x11] == _ascebc['M']));
  1239. }
  1240. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1241. {
  1242. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1243. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1244. card->info.blkt.time_total = 250;
  1245. card->info.blkt.inter_packet = 5;
  1246. card->info.blkt.inter_packet_jumbo = 15;
  1247. } else {
  1248. card->info.blkt.time_total = 0;
  1249. card->info.blkt.inter_packet = 0;
  1250. card->info.blkt.inter_packet_jumbo = 0;
  1251. }
  1252. }
  1253. static void qeth_init_tokens(struct qeth_card *card)
  1254. {
  1255. card->token.issuer_rm_w = 0x00010103UL;
  1256. card->token.cm_filter_w = 0x00010108UL;
  1257. card->token.cm_connection_w = 0x0001010aUL;
  1258. card->token.ulp_filter_w = 0x0001010bUL;
  1259. card->token.ulp_connection_w = 0x0001010dUL;
  1260. }
  1261. static void qeth_init_func_level(struct qeth_card *card)
  1262. {
  1263. switch (card->info.type) {
  1264. case QETH_CARD_TYPE_IQD:
  1265. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1266. break;
  1267. case QETH_CARD_TYPE_OSD:
  1268. case QETH_CARD_TYPE_OSN:
  1269. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1270. break;
  1271. default:
  1272. break;
  1273. }
  1274. }
  1275. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1276. void (*idx_reply_cb)(struct qeth_channel *,
  1277. struct qeth_cmd_buffer *))
  1278. {
  1279. struct qeth_cmd_buffer *iob;
  1280. unsigned long flags;
  1281. int rc;
  1282. struct qeth_card *card;
  1283. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1284. card = CARD_FROM_CDEV(channel->ccwdev);
  1285. iob = qeth_get_buffer(channel);
  1286. iob->callback = idx_reply_cb;
  1287. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1288. channel->ccw.count = QETH_BUFSIZE;
  1289. channel->ccw.cda = (__u32) __pa(iob->data);
  1290. wait_event(card->wait_q,
  1291. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1292. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1293. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1294. rc = ccw_device_start(channel->ccwdev,
  1295. &channel->ccw, (addr_t) iob, 0, 0);
  1296. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1297. if (rc) {
  1298. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1299. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1300. atomic_set(&channel->irq_pending, 0);
  1301. wake_up(&card->wait_q);
  1302. return rc;
  1303. }
  1304. rc = wait_event_interruptible_timeout(card->wait_q,
  1305. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1306. if (rc == -ERESTARTSYS)
  1307. return rc;
  1308. if (channel->state != CH_STATE_UP) {
  1309. rc = -ETIME;
  1310. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1311. qeth_clear_cmd_buffers(channel);
  1312. } else
  1313. rc = 0;
  1314. return rc;
  1315. }
  1316. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1317. void (*idx_reply_cb)(struct qeth_channel *,
  1318. struct qeth_cmd_buffer *))
  1319. {
  1320. struct qeth_card *card;
  1321. struct qeth_cmd_buffer *iob;
  1322. unsigned long flags;
  1323. __u16 temp;
  1324. __u8 tmp;
  1325. int rc;
  1326. struct ccw_dev_id temp_devid;
  1327. card = CARD_FROM_CDEV(channel->ccwdev);
  1328. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1329. iob = qeth_get_buffer(channel);
  1330. iob->callback = idx_reply_cb;
  1331. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1332. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1333. channel->ccw.cda = (__u32) __pa(iob->data);
  1334. if (channel == &card->write) {
  1335. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1336. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1337. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1338. card->seqno.trans_hdr++;
  1339. } else {
  1340. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1341. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1342. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1343. }
  1344. tmp = ((__u8)card->info.portno) | 0x80;
  1345. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1346. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1347. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1348. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1349. &card->info.func_level, sizeof(__u16));
  1350. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1351. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1352. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1353. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1354. wait_event(card->wait_q,
  1355. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1356. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1357. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1358. rc = ccw_device_start(channel->ccwdev,
  1359. &channel->ccw, (addr_t) iob, 0, 0);
  1360. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1361. if (rc) {
  1362. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1363. rc);
  1364. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1365. atomic_set(&channel->irq_pending, 0);
  1366. wake_up(&card->wait_q);
  1367. return rc;
  1368. }
  1369. rc = wait_event_interruptible_timeout(card->wait_q,
  1370. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1371. if (rc == -ERESTARTSYS)
  1372. return rc;
  1373. if (channel->state != CH_STATE_ACTIVATING) {
  1374. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1375. " failed to recover an error on the device\n");
  1376. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1377. dev_name(&channel->ccwdev->dev));
  1378. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1379. qeth_clear_cmd_buffers(channel);
  1380. return -ETIME;
  1381. }
  1382. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1383. }
  1384. static int qeth_peer_func_level(int level)
  1385. {
  1386. if ((level & 0xff) == 8)
  1387. return (level & 0xff) + 0x400;
  1388. if (((level >> 8) & 3) == 1)
  1389. return (level & 0xff) + 0x200;
  1390. return level;
  1391. }
  1392. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1393. struct qeth_cmd_buffer *iob)
  1394. {
  1395. struct qeth_card *card;
  1396. __u16 temp;
  1397. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1398. if (channel->state == CH_STATE_DOWN) {
  1399. channel->state = CH_STATE_ACTIVATING;
  1400. goto out;
  1401. }
  1402. card = CARD_FROM_CDEV(channel->ccwdev);
  1403. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1404. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1405. dev_err(&card->write.ccwdev->dev,
  1406. "The adapter is used exclusively by another "
  1407. "host\n");
  1408. else
  1409. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1410. " negative reply\n",
  1411. dev_name(&card->write.ccwdev->dev));
  1412. goto out;
  1413. }
  1414. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1415. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1416. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1417. "function level mismatch (sent: 0x%x, received: "
  1418. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1419. card->info.func_level, temp);
  1420. goto out;
  1421. }
  1422. channel->state = CH_STATE_UP;
  1423. out:
  1424. qeth_release_buffer(channel, iob);
  1425. }
  1426. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1427. struct qeth_cmd_buffer *iob)
  1428. {
  1429. struct qeth_card *card;
  1430. __u16 temp;
  1431. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1432. if (channel->state == CH_STATE_DOWN) {
  1433. channel->state = CH_STATE_ACTIVATING;
  1434. goto out;
  1435. }
  1436. card = CARD_FROM_CDEV(channel->ccwdev);
  1437. if (qeth_check_idx_response(card, iob->data))
  1438. goto out;
  1439. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1440. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1441. case QETH_IDX_ACT_ERR_EXCL:
  1442. dev_err(&card->write.ccwdev->dev,
  1443. "The adapter is used exclusively by another "
  1444. "host\n");
  1445. break;
  1446. case QETH_IDX_ACT_ERR_AUTH:
  1447. case QETH_IDX_ACT_ERR_AUTH_USER:
  1448. dev_err(&card->read.ccwdev->dev,
  1449. "Setting the device online failed because of "
  1450. "insufficient authorization\n");
  1451. break;
  1452. default:
  1453. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1454. " negative reply\n",
  1455. dev_name(&card->read.ccwdev->dev));
  1456. }
  1457. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1458. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1459. goto out;
  1460. }
  1461. /**
  1462. * * temporary fix for microcode bug
  1463. * * to revert it,replace OR by AND
  1464. * */
  1465. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1466. (card->info.type == QETH_CARD_TYPE_OSD))
  1467. card->info.portname_required = 1;
  1468. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1469. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1470. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1471. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1472. dev_name(&card->read.ccwdev->dev),
  1473. card->info.func_level, temp);
  1474. goto out;
  1475. }
  1476. memcpy(&card->token.issuer_rm_r,
  1477. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1478. QETH_MPC_TOKEN_LENGTH);
  1479. memcpy(&card->info.mcl_level[0],
  1480. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1481. channel->state = CH_STATE_UP;
  1482. out:
  1483. qeth_release_buffer(channel, iob);
  1484. }
  1485. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1486. struct qeth_cmd_buffer *iob)
  1487. {
  1488. qeth_setup_ccw(&card->write, iob->data, len);
  1489. iob->callback = qeth_release_buffer;
  1490. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1491. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1492. card->seqno.trans_hdr++;
  1493. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1494. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1495. card->seqno.pdu_hdr++;
  1496. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1497. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1498. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1499. }
  1500. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1501. int qeth_send_control_data(struct qeth_card *card, int len,
  1502. struct qeth_cmd_buffer *iob,
  1503. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1504. unsigned long),
  1505. void *reply_param)
  1506. {
  1507. int rc;
  1508. unsigned long flags;
  1509. struct qeth_reply *reply = NULL;
  1510. unsigned long timeout, event_timeout;
  1511. struct qeth_ipa_cmd *cmd;
  1512. QETH_CARD_TEXT(card, 2, "sendctl");
  1513. if (card->read_or_write_problem) {
  1514. qeth_release_buffer(iob->channel, iob);
  1515. return -EIO;
  1516. }
  1517. reply = qeth_alloc_reply(card);
  1518. if (!reply) {
  1519. return -ENOMEM;
  1520. }
  1521. reply->callback = reply_cb;
  1522. reply->param = reply_param;
  1523. if (card->state == CARD_STATE_DOWN)
  1524. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1525. else
  1526. reply->seqno = card->seqno.ipa++;
  1527. init_waitqueue_head(&reply->wait_q);
  1528. spin_lock_irqsave(&card->lock, flags);
  1529. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1530. spin_unlock_irqrestore(&card->lock, flags);
  1531. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1532. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1533. qeth_prepare_control_data(card, len, iob);
  1534. if (IS_IPA(iob->data))
  1535. event_timeout = QETH_IPA_TIMEOUT;
  1536. else
  1537. event_timeout = QETH_TIMEOUT;
  1538. timeout = jiffies + event_timeout;
  1539. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1540. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1541. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1542. (addr_t) iob, 0, 0);
  1543. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1544. if (rc) {
  1545. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1546. "ccw_device_start rc = %i\n",
  1547. dev_name(&card->write.ccwdev->dev), rc);
  1548. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1549. spin_lock_irqsave(&card->lock, flags);
  1550. list_del_init(&reply->list);
  1551. qeth_put_reply(reply);
  1552. spin_unlock_irqrestore(&card->lock, flags);
  1553. qeth_release_buffer(iob->channel, iob);
  1554. atomic_set(&card->write.irq_pending, 0);
  1555. wake_up(&card->wait_q);
  1556. return rc;
  1557. }
  1558. /* we have only one long running ipassist, since we can ensure
  1559. process context of this command we can sleep */
  1560. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1561. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1562. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1563. if (!wait_event_timeout(reply->wait_q,
  1564. atomic_read(&reply->received), event_timeout))
  1565. goto time_err;
  1566. } else {
  1567. while (!atomic_read(&reply->received)) {
  1568. if (time_after(jiffies, timeout))
  1569. goto time_err;
  1570. cpu_relax();
  1571. };
  1572. }
  1573. if (reply->rc == -EIO)
  1574. goto error;
  1575. rc = reply->rc;
  1576. qeth_put_reply(reply);
  1577. return rc;
  1578. time_err:
  1579. reply->rc = -ETIME;
  1580. spin_lock_irqsave(&reply->card->lock, flags);
  1581. list_del_init(&reply->list);
  1582. spin_unlock_irqrestore(&reply->card->lock, flags);
  1583. atomic_inc(&reply->received);
  1584. error:
  1585. atomic_set(&card->write.irq_pending, 0);
  1586. qeth_release_buffer(iob->channel, iob);
  1587. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1588. rc = reply->rc;
  1589. qeth_put_reply(reply);
  1590. return rc;
  1591. }
  1592. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1593. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1594. unsigned long data)
  1595. {
  1596. struct qeth_cmd_buffer *iob;
  1597. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1598. iob = (struct qeth_cmd_buffer *) data;
  1599. memcpy(&card->token.cm_filter_r,
  1600. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1601. QETH_MPC_TOKEN_LENGTH);
  1602. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1603. return 0;
  1604. }
  1605. static int qeth_cm_enable(struct qeth_card *card)
  1606. {
  1607. int rc;
  1608. struct qeth_cmd_buffer *iob;
  1609. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1610. iob = qeth_wait_for_buffer(&card->write);
  1611. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1612. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1613. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1614. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1615. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1616. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1617. qeth_cm_enable_cb, NULL);
  1618. return rc;
  1619. }
  1620. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1621. unsigned long data)
  1622. {
  1623. struct qeth_cmd_buffer *iob;
  1624. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1625. iob = (struct qeth_cmd_buffer *) data;
  1626. memcpy(&card->token.cm_connection_r,
  1627. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1628. QETH_MPC_TOKEN_LENGTH);
  1629. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1630. return 0;
  1631. }
  1632. static int qeth_cm_setup(struct qeth_card *card)
  1633. {
  1634. int rc;
  1635. struct qeth_cmd_buffer *iob;
  1636. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1637. iob = qeth_wait_for_buffer(&card->write);
  1638. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1639. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1640. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1641. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1642. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1643. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1644. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1645. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1646. qeth_cm_setup_cb, NULL);
  1647. return rc;
  1648. }
  1649. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1650. {
  1651. switch (card->info.type) {
  1652. case QETH_CARD_TYPE_UNKNOWN:
  1653. return 1500;
  1654. case QETH_CARD_TYPE_IQD:
  1655. return card->info.max_mtu;
  1656. case QETH_CARD_TYPE_OSD:
  1657. switch (card->info.link_type) {
  1658. case QETH_LINK_TYPE_HSTR:
  1659. case QETH_LINK_TYPE_LANE_TR:
  1660. return 2000;
  1661. default:
  1662. return 1492;
  1663. }
  1664. case QETH_CARD_TYPE_OSM:
  1665. case QETH_CARD_TYPE_OSX:
  1666. return 1492;
  1667. default:
  1668. return 1500;
  1669. }
  1670. }
  1671. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1672. {
  1673. switch (framesize) {
  1674. case 0x4000:
  1675. return 8192;
  1676. case 0x6000:
  1677. return 16384;
  1678. case 0xa000:
  1679. return 32768;
  1680. case 0xffff:
  1681. return 57344;
  1682. default:
  1683. return 0;
  1684. }
  1685. }
  1686. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1687. {
  1688. switch (card->info.type) {
  1689. case QETH_CARD_TYPE_OSD:
  1690. case QETH_CARD_TYPE_OSM:
  1691. case QETH_CARD_TYPE_OSX:
  1692. case QETH_CARD_TYPE_IQD:
  1693. return ((mtu >= 576) &&
  1694. (mtu <= card->info.max_mtu));
  1695. case QETH_CARD_TYPE_OSN:
  1696. case QETH_CARD_TYPE_UNKNOWN:
  1697. default:
  1698. return 1;
  1699. }
  1700. }
  1701. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1702. unsigned long data)
  1703. {
  1704. __u16 mtu, framesize;
  1705. __u16 len;
  1706. __u8 link_type;
  1707. struct qeth_cmd_buffer *iob;
  1708. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1709. iob = (struct qeth_cmd_buffer *) data;
  1710. memcpy(&card->token.ulp_filter_r,
  1711. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1712. QETH_MPC_TOKEN_LENGTH);
  1713. if (card->info.type == QETH_CARD_TYPE_IQD) {
  1714. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1715. mtu = qeth_get_mtu_outof_framesize(framesize);
  1716. if (!mtu) {
  1717. iob->rc = -EINVAL;
  1718. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1719. return 0;
  1720. }
  1721. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  1722. /* frame size has changed */
  1723. if (card->dev &&
  1724. ((card->dev->mtu == card->info.initial_mtu) ||
  1725. (card->dev->mtu > mtu)))
  1726. card->dev->mtu = mtu;
  1727. qeth_free_qdio_buffers(card);
  1728. }
  1729. card->info.initial_mtu = mtu;
  1730. card->info.max_mtu = mtu;
  1731. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1732. } else {
  1733. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1734. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  1735. iob->data);
  1736. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1737. }
  1738. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1739. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1740. memcpy(&link_type,
  1741. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1742. card->info.link_type = link_type;
  1743. } else
  1744. card->info.link_type = 0;
  1745. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  1746. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1747. return 0;
  1748. }
  1749. static int qeth_ulp_enable(struct qeth_card *card)
  1750. {
  1751. int rc;
  1752. char prot_type;
  1753. struct qeth_cmd_buffer *iob;
  1754. /*FIXME: trace view callbacks*/
  1755. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1756. iob = qeth_wait_for_buffer(&card->write);
  1757. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1758. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1759. (__u8) card->info.portno;
  1760. if (card->options.layer2)
  1761. if (card->info.type == QETH_CARD_TYPE_OSN)
  1762. prot_type = QETH_PROT_OSN2;
  1763. else
  1764. prot_type = QETH_PROT_LAYER2;
  1765. else
  1766. prot_type = QETH_PROT_TCPIP;
  1767. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1768. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1769. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1770. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1771. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1772. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1773. card->info.portname, 9);
  1774. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1775. qeth_ulp_enable_cb, NULL);
  1776. return rc;
  1777. }
  1778. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1779. unsigned long data)
  1780. {
  1781. struct qeth_cmd_buffer *iob;
  1782. int rc = 0;
  1783. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1784. iob = (struct qeth_cmd_buffer *) data;
  1785. memcpy(&card->token.ulp_connection_r,
  1786. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1787. QETH_MPC_TOKEN_LENGTH);
  1788. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1789. 3)) {
  1790. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1791. dev_err(&card->gdev->dev, "A connection could not be "
  1792. "established because of an OLM limit\n");
  1793. iob->rc = -EMLINK;
  1794. }
  1795. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1796. return rc;
  1797. }
  1798. static int qeth_ulp_setup(struct qeth_card *card)
  1799. {
  1800. int rc;
  1801. __u16 temp;
  1802. struct qeth_cmd_buffer *iob;
  1803. struct ccw_dev_id dev_id;
  1804. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1805. iob = qeth_wait_for_buffer(&card->write);
  1806. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1807. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1808. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1809. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1810. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1811. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1812. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1813. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1814. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1815. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1816. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1817. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1818. qeth_ulp_setup_cb, NULL);
  1819. return rc;
  1820. }
  1821. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1822. {
  1823. int i, j;
  1824. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1825. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1826. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1827. return 0;
  1828. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1829. GFP_KERNEL);
  1830. if (!card->qdio.in_q)
  1831. goto out_nomem;
  1832. QETH_DBF_TEXT(SETUP, 2, "inq");
  1833. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1834. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1835. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1836. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1837. card->qdio.in_q->bufs[i].buffer =
  1838. &card->qdio.in_q->qdio_bufs[i];
  1839. /* inbound buffer pool */
  1840. if (qeth_alloc_buffer_pool(card))
  1841. goto out_freeinq;
  1842. /* outbound */
  1843. card->qdio.out_qs =
  1844. kmalloc(card->qdio.no_out_queues *
  1845. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1846. if (!card->qdio.out_qs)
  1847. goto out_freepool;
  1848. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1849. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1850. GFP_KERNEL);
  1851. if (!card->qdio.out_qs[i])
  1852. goto out_freeoutq;
  1853. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1854. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1855. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1856. card->qdio.out_qs[i]->queue_no = i;
  1857. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1858. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1859. card->qdio.out_qs[i]->bufs[j].buffer =
  1860. &card->qdio.out_qs[i]->qdio_bufs[j];
  1861. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1862. skb_list);
  1863. lockdep_set_class(
  1864. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1865. &qdio_out_skb_queue_key);
  1866. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1867. }
  1868. }
  1869. return 0;
  1870. out_freeoutq:
  1871. while (i > 0)
  1872. kfree(card->qdio.out_qs[--i]);
  1873. kfree(card->qdio.out_qs);
  1874. card->qdio.out_qs = NULL;
  1875. out_freepool:
  1876. qeth_free_buffer_pool(card);
  1877. out_freeinq:
  1878. kfree(card->qdio.in_q);
  1879. card->qdio.in_q = NULL;
  1880. out_nomem:
  1881. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1882. return -ENOMEM;
  1883. }
  1884. static void qeth_create_qib_param_field(struct qeth_card *card,
  1885. char *param_field)
  1886. {
  1887. param_field[0] = _ascebc['P'];
  1888. param_field[1] = _ascebc['C'];
  1889. param_field[2] = _ascebc['I'];
  1890. param_field[3] = _ascebc['T'];
  1891. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1892. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1893. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1894. }
  1895. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1896. char *param_field)
  1897. {
  1898. param_field[16] = _ascebc['B'];
  1899. param_field[17] = _ascebc['L'];
  1900. param_field[18] = _ascebc['K'];
  1901. param_field[19] = _ascebc['T'];
  1902. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1903. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1904. *((unsigned int *) (&param_field[28])) =
  1905. card->info.blkt.inter_packet_jumbo;
  1906. }
  1907. static int qeth_qdio_activate(struct qeth_card *card)
  1908. {
  1909. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1910. return qdio_activate(CARD_DDEV(card));
  1911. }
  1912. static int qeth_dm_act(struct qeth_card *card)
  1913. {
  1914. int rc;
  1915. struct qeth_cmd_buffer *iob;
  1916. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1917. iob = qeth_wait_for_buffer(&card->write);
  1918. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1919. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1920. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1921. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1922. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1923. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1924. return rc;
  1925. }
  1926. static int qeth_mpc_initialize(struct qeth_card *card)
  1927. {
  1928. int rc;
  1929. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1930. rc = qeth_issue_next_read(card);
  1931. if (rc) {
  1932. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1933. return rc;
  1934. }
  1935. rc = qeth_cm_enable(card);
  1936. if (rc) {
  1937. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1938. goto out_qdio;
  1939. }
  1940. rc = qeth_cm_setup(card);
  1941. if (rc) {
  1942. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1943. goto out_qdio;
  1944. }
  1945. rc = qeth_ulp_enable(card);
  1946. if (rc) {
  1947. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1948. goto out_qdio;
  1949. }
  1950. rc = qeth_ulp_setup(card);
  1951. if (rc) {
  1952. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1953. goto out_qdio;
  1954. }
  1955. rc = qeth_alloc_qdio_buffers(card);
  1956. if (rc) {
  1957. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1958. goto out_qdio;
  1959. }
  1960. rc = qeth_qdio_establish(card);
  1961. if (rc) {
  1962. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1963. qeth_free_qdio_buffers(card);
  1964. goto out_qdio;
  1965. }
  1966. rc = qeth_qdio_activate(card);
  1967. if (rc) {
  1968. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1969. goto out_qdio;
  1970. }
  1971. rc = qeth_dm_act(card);
  1972. if (rc) {
  1973. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1974. goto out_qdio;
  1975. }
  1976. return 0;
  1977. out_qdio:
  1978. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1979. return rc;
  1980. }
  1981. static void qeth_print_status_with_portname(struct qeth_card *card)
  1982. {
  1983. char dbf_text[15];
  1984. int i;
  1985. sprintf(dbf_text, "%s", card->info.portname + 1);
  1986. for (i = 0; i < 8; i++)
  1987. dbf_text[i] =
  1988. (char) _ebcasc[(__u8) dbf_text[i]];
  1989. dbf_text[8] = 0;
  1990. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1991. "with link type %s (portname: %s)\n",
  1992. qeth_get_cardname(card),
  1993. (card->info.mcl_level[0]) ? " (level: " : "",
  1994. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1995. (card->info.mcl_level[0]) ? ")" : "",
  1996. qeth_get_cardname_short(card),
  1997. dbf_text);
  1998. }
  1999. static void qeth_print_status_no_portname(struct qeth_card *card)
  2000. {
  2001. if (card->info.portname[0])
  2002. dev_info(&card->gdev->dev, "Device is a%s "
  2003. "card%s%s%s\nwith link type %s "
  2004. "(no portname needed by interface).\n",
  2005. qeth_get_cardname(card),
  2006. (card->info.mcl_level[0]) ? " (level: " : "",
  2007. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2008. (card->info.mcl_level[0]) ? ")" : "",
  2009. qeth_get_cardname_short(card));
  2010. else
  2011. dev_info(&card->gdev->dev, "Device is a%s "
  2012. "card%s%s%s\nwith link type %s.\n",
  2013. qeth_get_cardname(card),
  2014. (card->info.mcl_level[0]) ? " (level: " : "",
  2015. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2016. (card->info.mcl_level[0]) ? ")" : "",
  2017. qeth_get_cardname_short(card));
  2018. }
  2019. void qeth_print_status_message(struct qeth_card *card)
  2020. {
  2021. switch (card->info.type) {
  2022. case QETH_CARD_TYPE_OSD:
  2023. case QETH_CARD_TYPE_OSM:
  2024. case QETH_CARD_TYPE_OSX:
  2025. /* VM will use a non-zero first character
  2026. * to indicate a HiperSockets like reporting
  2027. * of the level OSA sets the first character to zero
  2028. * */
  2029. if (!card->info.mcl_level[0]) {
  2030. sprintf(card->info.mcl_level, "%02x%02x",
  2031. card->info.mcl_level[2],
  2032. card->info.mcl_level[3]);
  2033. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2034. break;
  2035. }
  2036. /* fallthrough */
  2037. case QETH_CARD_TYPE_IQD:
  2038. if ((card->info.guestlan) ||
  2039. (card->info.mcl_level[0] & 0x80)) {
  2040. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2041. card->info.mcl_level[0]];
  2042. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2043. card->info.mcl_level[1]];
  2044. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2045. card->info.mcl_level[2]];
  2046. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2047. card->info.mcl_level[3]];
  2048. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2049. }
  2050. break;
  2051. default:
  2052. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2053. }
  2054. if (card->info.portname_required)
  2055. qeth_print_status_with_portname(card);
  2056. else
  2057. qeth_print_status_no_portname(card);
  2058. }
  2059. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2060. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2061. {
  2062. struct qeth_buffer_pool_entry *entry;
  2063. QETH_CARD_TEXT(card, 5, "inwrklst");
  2064. list_for_each_entry(entry,
  2065. &card->qdio.init_pool.entry_list, init_list) {
  2066. qeth_put_buffer_pool_entry(card, entry);
  2067. }
  2068. }
  2069. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2070. struct qeth_card *card)
  2071. {
  2072. struct list_head *plh;
  2073. struct qeth_buffer_pool_entry *entry;
  2074. int i, free;
  2075. struct page *page;
  2076. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2077. return NULL;
  2078. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2079. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2080. free = 1;
  2081. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2082. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2083. free = 0;
  2084. break;
  2085. }
  2086. }
  2087. if (free) {
  2088. list_del_init(&entry->list);
  2089. return entry;
  2090. }
  2091. }
  2092. /* no free buffer in pool so take first one and swap pages */
  2093. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2094. struct qeth_buffer_pool_entry, list);
  2095. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2096. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2097. page = alloc_page(GFP_ATOMIC);
  2098. if (!page) {
  2099. return NULL;
  2100. } else {
  2101. free_page((unsigned long)entry->elements[i]);
  2102. entry->elements[i] = page_address(page);
  2103. if (card->options.performance_stats)
  2104. card->perf_stats.sg_alloc_page_rx++;
  2105. }
  2106. }
  2107. }
  2108. list_del_init(&entry->list);
  2109. return entry;
  2110. }
  2111. static int qeth_init_input_buffer(struct qeth_card *card,
  2112. struct qeth_qdio_buffer *buf)
  2113. {
  2114. struct qeth_buffer_pool_entry *pool_entry;
  2115. int i;
  2116. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2117. if (!pool_entry)
  2118. return 1;
  2119. /*
  2120. * since the buffer is accessed only from the input_tasklet
  2121. * there shouldn't be a need to synchronize; also, since we use
  2122. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2123. * buffers
  2124. */
  2125. buf->pool_entry = pool_entry;
  2126. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2127. buf->buffer->element[i].length = PAGE_SIZE;
  2128. buf->buffer->element[i].addr = pool_entry->elements[i];
  2129. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2130. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2131. else
  2132. buf->buffer->element[i].eflags = 0;
  2133. buf->buffer->element[i].sflags = 0;
  2134. }
  2135. return 0;
  2136. }
  2137. int qeth_init_qdio_queues(struct qeth_card *card)
  2138. {
  2139. int i, j;
  2140. int rc;
  2141. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2142. /* inbound queue */
  2143. memset(card->qdio.in_q->qdio_bufs, 0,
  2144. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2145. qeth_initialize_working_pool_list(card);
  2146. /*give only as many buffers to hardware as we have buffer pool entries*/
  2147. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2148. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2149. card->qdio.in_q->next_buf_to_init =
  2150. card->qdio.in_buf_pool.buf_count - 1;
  2151. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2152. card->qdio.in_buf_pool.buf_count - 1);
  2153. if (rc) {
  2154. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2155. return rc;
  2156. }
  2157. /* outbound queue */
  2158. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2159. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2160. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2161. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2162. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2163. &card->qdio.out_qs[i]->bufs[j]);
  2164. }
  2165. card->qdio.out_qs[i]->card = card;
  2166. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2167. card->qdio.out_qs[i]->do_pack = 0;
  2168. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2169. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2170. atomic_set(&card->qdio.out_qs[i]->state,
  2171. QETH_OUT_Q_UNLOCKED);
  2172. }
  2173. return 0;
  2174. }
  2175. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2176. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2177. {
  2178. switch (link_type) {
  2179. case QETH_LINK_TYPE_HSTR:
  2180. return 2;
  2181. default:
  2182. return 1;
  2183. }
  2184. }
  2185. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2186. struct qeth_ipa_cmd *cmd, __u8 command,
  2187. enum qeth_prot_versions prot)
  2188. {
  2189. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2190. cmd->hdr.command = command;
  2191. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2192. cmd->hdr.seqno = card->seqno.ipa;
  2193. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2194. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2195. if (card->options.layer2)
  2196. cmd->hdr.prim_version_no = 2;
  2197. else
  2198. cmd->hdr.prim_version_no = 1;
  2199. cmd->hdr.param_count = 1;
  2200. cmd->hdr.prot_version = prot;
  2201. cmd->hdr.ipa_supported = 0;
  2202. cmd->hdr.ipa_enabled = 0;
  2203. }
  2204. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2205. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2206. {
  2207. struct qeth_cmd_buffer *iob;
  2208. struct qeth_ipa_cmd *cmd;
  2209. iob = qeth_wait_for_buffer(&card->write);
  2210. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2211. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2212. return iob;
  2213. }
  2214. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2215. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2216. char prot_type)
  2217. {
  2218. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2219. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2220. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2221. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2222. }
  2223. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2224. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2225. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2226. unsigned long),
  2227. void *reply_param)
  2228. {
  2229. int rc;
  2230. char prot_type;
  2231. QETH_CARD_TEXT(card, 4, "sendipa");
  2232. if (card->options.layer2)
  2233. if (card->info.type == QETH_CARD_TYPE_OSN)
  2234. prot_type = QETH_PROT_OSN2;
  2235. else
  2236. prot_type = QETH_PROT_LAYER2;
  2237. else
  2238. prot_type = QETH_PROT_TCPIP;
  2239. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2240. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2241. iob, reply_cb, reply_param);
  2242. if (rc == -ETIME) {
  2243. qeth_clear_ipacmd_list(card);
  2244. qeth_schedule_recovery(card);
  2245. }
  2246. return rc;
  2247. }
  2248. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2249. int qeth_send_startlan(struct qeth_card *card)
  2250. {
  2251. int rc;
  2252. struct qeth_cmd_buffer *iob;
  2253. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2254. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2255. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2256. return rc;
  2257. }
  2258. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2259. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2260. struct qeth_reply *reply, unsigned long data)
  2261. {
  2262. struct qeth_ipa_cmd *cmd;
  2263. QETH_CARD_TEXT(card, 4, "defadpcb");
  2264. cmd = (struct qeth_ipa_cmd *) data;
  2265. if (cmd->hdr.return_code == 0)
  2266. cmd->hdr.return_code =
  2267. cmd->data.setadapterparms.hdr.return_code;
  2268. return 0;
  2269. }
  2270. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2271. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2272. struct qeth_reply *reply, unsigned long data)
  2273. {
  2274. struct qeth_ipa_cmd *cmd;
  2275. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2276. cmd = (struct qeth_ipa_cmd *) data;
  2277. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2278. card->info.link_type =
  2279. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2280. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2281. }
  2282. card->options.adp.supported_funcs =
  2283. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2284. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2285. }
  2286. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2287. __u32 command, __u32 cmdlen)
  2288. {
  2289. struct qeth_cmd_buffer *iob;
  2290. struct qeth_ipa_cmd *cmd;
  2291. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2292. QETH_PROT_IPV4);
  2293. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2294. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2295. cmd->data.setadapterparms.hdr.command_code = command;
  2296. cmd->data.setadapterparms.hdr.used_total = 1;
  2297. cmd->data.setadapterparms.hdr.seq_no = 1;
  2298. return iob;
  2299. }
  2300. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2301. int qeth_query_setadapterparms(struct qeth_card *card)
  2302. {
  2303. int rc;
  2304. struct qeth_cmd_buffer *iob;
  2305. QETH_CARD_TEXT(card, 3, "queryadp");
  2306. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2307. sizeof(struct qeth_ipacmd_setadpparms));
  2308. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2309. return rc;
  2310. }
  2311. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2312. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2313. struct qeth_reply *reply, unsigned long data)
  2314. {
  2315. struct qeth_ipa_cmd *cmd;
  2316. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2317. cmd = (struct qeth_ipa_cmd *) data;
  2318. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2319. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2320. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2321. } else {
  2322. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2323. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2324. }
  2325. QETH_DBF_TEXT(SETUP, 2, "suppenbl");
  2326. QETH_DBF_TEXT_(SETUP, 2, "%x", cmd->hdr.ipa_supported);
  2327. QETH_DBF_TEXT_(SETUP, 2, "%x", cmd->hdr.ipa_enabled);
  2328. return 0;
  2329. }
  2330. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2331. {
  2332. int rc;
  2333. struct qeth_cmd_buffer *iob;
  2334. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2335. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2336. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2337. return rc;
  2338. }
  2339. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2340. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2341. struct qeth_reply *reply, unsigned long data)
  2342. {
  2343. struct qeth_ipa_cmd *cmd;
  2344. __u16 rc;
  2345. cmd = (struct qeth_ipa_cmd *)data;
  2346. rc = cmd->hdr.return_code;
  2347. if (rc)
  2348. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2349. else
  2350. card->info.diagass_support = cmd->data.diagass.ext;
  2351. return 0;
  2352. }
  2353. static int qeth_query_setdiagass(struct qeth_card *card)
  2354. {
  2355. struct qeth_cmd_buffer *iob;
  2356. struct qeth_ipa_cmd *cmd;
  2357. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2358. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2359. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2360. cmd->data.diagass.subcmd_len = 16;
  2361. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2362. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2363. }
  2364. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2365. {
  2366. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2367. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2368. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2369. struct ccw_dev_id ccwid;
  2370. int level, rc;
  2371. tid->chpid = card->info.chpid;
  2372. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2373. tid->ssid = ccwid.ssid;
  2374. tid->devno = ccwid.devno;
  2375. if (!info)
  2376. return;
  2377. rc = stsi(NULL, 0, 0, 0);
  2378. if (rc == -ENOSYS)
  2379. level = rc;
  2380. else
  2381. level = (((unsigned int) rc) >> 28);
  2382. if ((level >= 2) && (stsi(info222, 2, 2, 2) != -ENOSYS))
  2383. tid->lparnr = info222->lpar_number;
  2384. if ((level >= 3) && (stsi(info322, 3, 2, 2) != -ENOSYS)) {
  2385. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2386. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2387. }
  2388. free_page(info);
  2389. return;
  2390. }
  2391. static int qeth_hw_trap_cb(struct qeth_card *card,
  2392. struct qeth_reply *reply, unsigned long data)
  2393. {
  2394. struct qeth_ipa_cmd *cmd;
  2395. __u16 rc;
  2396. cmd = (struct qeth_ipa_cmd *)data;
  2397. rc = cmd->hdr.return_code;
  2398. if (rc)
  2399. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2400. return 0;
  2401. }
  2402. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2403. {
  2404. struct qeth_cmd_buffer *iob;
  2405. struct qeth_ipa_cmd *cmd;
  2406. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2407. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2408. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2409. cmd->data.diagass.subcmd_len = 80;
  2410. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2411. cmd->data.diagass.type = 1;
  2412. cmd->data.diagass.action = action;
  2413. switch (action) {
  2414. case QETH_DIAGS_TRAP_ARM:
  2415. cmd->data.diagass.options = 0x0003;
  2416. cmd->data.diagass.ext = 0x00010000 +
  2417. sizeof(struct qeth_trap_id);
  2418. qeth_get_trap_id(card,
  2419. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2420. break;
  2421. case QETH_DIAGS_TRAP_DISARM:
  2422. cmd->data.diagass.options = 0x0001;
  2423. break;
  2424. case QETH_DIAGS_TRAP_CAPTURE:
  2425. break;
  2426. }
  2427. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2428. }
  2429. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2430. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2431. unsigned int qdio_error, const char *dbftext)
  2432. {
  2433. if (qdio_error) {
  2434. QETH_CARD_TEXT(card, 2, dbftext);
  2435. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2436. buf->element[15].sflags);
  2437. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2438. buf->element[14].sflags);
  2439. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2440. if ((buf->element[15].sflags) == 0x12) {
  2441. card->stats.rx_dropped++;
  2442. return 0;
  2443. } else
  2444. return 1;
  2445. }
  2446. return 0;
  2447. }
  2448. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2449. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2450. {
  2451. struct qeth_qdio_q *queue = card->qdio.in_q;
  2452. int count;
  2453. int i;
  2454. int rc;
  2455. int newcount = 0;
  2456. count = (index < queue->next_buf_to_init)?
  2457. card->qdio.in_buf_pool.buf_count -
  2458. (queue->next_buf_to_init - index) :
  2459. card->qdio.in_buf_pool.buf_count -
  2460. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2461. /* only requeue at a certain threshold to avoid SIGAs */
  2462. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2463. for (i = queue->next_buf_to_init;
  2464. i < queue->next_buf_to_init + count; ++i) {
  2465. if (qeth_init_input_buffer(card,
  2466. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2467. break;
  2468. } else {
  2469. newcount++;
  2470. }
  2471. }
  2472. if (newcount < count) {
  2473. /* we are in memory shortage so we switch back to
  2474. traditional skb allocation and drop packages */
  2475. atomic_set(&card->force_alloc_skb, 3);
  2476. count = newcount;
  2477. } else {
  2478. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2479. }
  2480. /*
  2481. * according to old code it should be avoided to requeue all
  2482. * 128 buffers in order to benefit from PCI avoidance.
  2483. * this function keeps at least one buffer (the buffer at
  2484. * 'index') un-requeued -> this buffer is the first buffer that
  2485. * will be requeued the next time
  2486. */
  2487. if (card->options.performance_stats) {
  2488. card->perf_stats.inbound_do_qdio_cnt++;
  2489. card->perf_stats.inbound_do_qdio_start_time =
  2490. qeth_get_micros();
  2491. }
  2492. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2493. queue->next_buf_to_init, count);
  2494. if (card->options.performance_stats)
  2495. card->perf_stats.inbound_do_qdio_time +=
  2496. qeth_get_micros() -
  2497. card->perf_stats.inbound_do_qdio_start_time;
  2498. if (rc) {
  2499. dev_warn(&card->gdev->dev,
  2500. "QDIO reported an error, rc=%i\n", rc);
  2501. QETH_CARD_TEXT(card, 2, "qinberr");
  2502. }
  2503. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2504. QDIO_MAX_BUFFERS_PER_Q;
  2505. }
  2506. }
  2507. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2508. static int qeth_handle_send_error(struct qeth_card *card,
  2509. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2510. {
  2511. int sbalf15 = buffer->buffer->element[15].sflags;
  2512. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2513. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2514. if (sbalf15 == 0) {
  2515. qdio_err = 0;
  2516. } else {
  2517. qdio_err = 1;
  2518. }
  2519. }
  2520. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2521. if (!qdio_err)
  2522. return QETH_SEND_ERROR_NONE;
  2523. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2524. return QETH_SEND_ERROR_RETRY;
  2525. QETH_CARD_TEXT(card, 1, "lnkfail");
  2526. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2527. (u16)qdio_err, (u8)sbalf15);
  2528. return QETH_SEND_ERROR_LINK_FAILURE;
  2529. }
  2530. /*
  2531. * Switched to packing state if the number of used buffers on a queue
  2532. * reaches a certain limit.
  2533. */
  2534. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2535. {
  2536. if (!queue->do_pack) {
  2537. if (atomic_read(&queue->used_buffers)
  2538. >= QETH_HIGH_WATERMARK_PACK){
  2539. /* switch non-PACKING -> PACKING */
  2540. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2541. if (queue->card->options.performance_stats)
  2542. queue->card->perf_stats.sc_dp_p++;
  2543. queue->do_pack = 1;
  2544. }
  2545. }
  2546. }
  2547. /*
  2548. * Switches from packing to non-packing mode. If there is a packing
  2549. * buffer on the queue this buffer will be prepared to be flushed.
  2550. * In that case 1 is returned to inform the caller. If no buffer
  2551. * has to be flushed, zero is returned.
  2552. */
  2553. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2554. {
  2555. struct qeth_qdio_out_buffer *buffer;
  2556. int flush_count = 0;
  2557. if (queue->do_pack) {
  2558. if (atomic_read(&queue->used_buffers)
  2559. <= QETH_LOW_WATERMARK_PACK) {
  2560. /* switch PACKING -> non-PACKING */
  2561. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2562. if (queue->card->options.performance_stats)
  2563. queue->card->perf_stats.sc_p_dp++;
  2564. queue->do_pack = 0;
  2565. /* flush packing buffers */
  2566. buffer = &queue->bufs[queue->next_buf_to_fill];
  2567. if ((atomic_read(&buffer->state) ==
  2568. QETH_QDIO_BUF_EMPTY) &&
  2569. (buffer->next_element_to_fill > 0)) {
  2570. atomic_set(&buffer->state,
  2571. QETH_QDIO_BUF_PRIMED);
  2572. flush_count++;
  2573. queue->next_buf_to_fill =
  2574. (queue->next_buf_to_fill + 1) %
  2575. QDIO_MAX_BUFFERS_PER_Q;
  2576. }
  2577. }
  2578. }
  2579. return flush_count;
  2580. }
  2581. /*
  2582. * Called to flush a packing buffer if no more pci flags are on the queue.
  2583. * Checks if there is a packing buffer and prepares it to be flushed.
  2584. * In that case returns 1, otherwise zero.
  2585. */
  2586. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2587. {
  2588. struct qeth_qdio_out_buffer *buffer;
  2589. buffer = &queue->bufs[queue->next_buf_to_fill];
  2590. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2591. (buffer->next_element_to_fill > 0)) {
  2592. /* it's a packing buffer */
  2593. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2594. queue->next_buf_to_fill =
  2595. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2596. return 1;
  2597. }
  2598. return 0;
  2599. }
  2600. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2601. int count)
  2602. {
  2603. struct qeth_qdio_out_buffer *buf;
  2604. int rc;
  2605. int i;
  2606. unsigned int qdio_flags;
  2607. for (i = index; i < index + count; ++i) {
  2608. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2609. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  2610. SBAL_EFLAGS_LAST_ENTRY;
  2611. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2612. continue;
  2613. if (!queue->do_pack) {
  2614. if ((atomic_read(&queue->used_buffers) >=
  2615. (QETH_HIGH_WATERMARK_PACK -
  2616. QETH_WATERMARK_PACK_FUZZ)) &&
  2617. !atomic_read(&queue->set_pci_flags_count)) {
  2618. /* it's likely that we'll go to packing
  2619. * mode soon */
  2620. atomic_inc(&queue->set_pci_flags_count);
  2621. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2622. }
  2623. } else {
  2624. if (!atomic_read(&queue->set_pci_flags_count)) {
  2625. /*
  2626. * there's no outstanding PCI any more, so we
  2627. * have to request a PCI to be sure the the PCI
  2628. * will wake at some time in the future then we
  2629. * can flush packed buffers that might still be
  2630. * hanging around, which can happen if no
  2631. * further send was requested by the stack
  2632. */
  2633. atomic_inc(&queue->set_pci_flags_count);
  2634. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2635. }
  2636. }
  2637. }
  2638. queue->card->dev->trans_start = jiffies;
  2639. if (queue->card->options.performance_stats) {
  2640. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2641. queue->card->perf_stats.outbound_do_qdio_start_time =
  2642. qeth_get_micros();
  2643. }
  2644. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2645. if (atomic_read(&queue->set_pci_flags_count))
  2646. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2647. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2648. queue->queue_no, index, count);
  2649. if (queue->card->options.performance_stats)
  2650. queue->card->perf_stats.outbound_do_qdio_time +=
  2651. qeth_get_micros() -
  2652. queue->card->perf_stats.outbound_do_qdio_start_time;
  2653. atomic_add(count, &queue->used_buffers);
  2654. if (rc) {
  2655. queue->card->stats.tx_errors += count;
  2656. /* ignore temporary SIGA errors without busy condition */
  2657. if (rc == QDIO_ERROR_SIGA_TARGET)
  2658. return;
  2659. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2660. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2661. /* this must not happen under normal circumstances. if it
  2662. * happens something is really wrong -> recover */
  2663. qeth_schedule_recovery(queue->card);
  2664. return;
  2665. }
  2666. if (queue->card->options.performance_stats)
  2667. queue->card->perf_stats.bufs_sent += count;
  2668. }
  2669. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2670. {
  2671. int index;
  2672. int flush_cnt = 0;
  2673. int q_was_packing = 0;
  2674. /*
  2675. * check if weed have to switch to non-packing mode or if
  2676. * we have to get a pci flag out on the queue
  2677. */
  2678. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2679. !atomic_read(&queue->set_pci_flags_count)) {
  2680. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2681. QETH_OUT_Q_UNLOCKED) {
  2682. /*
  2683. * If we get in here, there was no action in
  2684. * do_send_packet. So, we check if there is a
  2685. * packing buffer to be flushed here.
  2686. */
  2687. netif_stop_queue(queue->card->dev);
  2688. index = queue->next_buf_to_fill;
  2689. q_was_packing = queue->do_pack;
  2690. /* queue->do_pack may change */
  2691. barrier();
  2692. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2693. if (!flush_cnt &&
  2694. !atomic_read(&queue->set_pci_flags_count))
  2695. flush_cnt +=
  2696. qeth_flush_buffers_on_no_pci(queue);
  2697. if (queue->card->options.performance_stats &&
  2698. q_was_packing)
  2699. queue->card->perf_stats.bufs_sent_pack +=
  2700. flush_cnt;
  2701. if (flush_cnt)
  2702. qeth_flush_buffers(queue, index, flush_cnt);
  2703. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2704. }
  2705. }
  2706. }
  2707. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  2708. unsigned long card_ptr)
  2709. {
  2710. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2711. if (card->dev && (card->dev->flags & IFF_UP))
  2712. napi_schedule(&card->napi);
  2713. }
  2714. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  2715. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  2716. unsigned int queue, int first_element, int count,
  2717. unsigned long card_ptr)
  2718. {
  2719. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2720. if (qdio_err)
  2721. qeth_schedule_recovery(card);
  2722. }
  2723. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  2724. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2725. unsigned int qdio_error, int __queue, int first_element,
  2726. int count, unsigned long card_ptr)
  2727. {
  2728. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2729. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2730. struct qeth_qdio_out_buffer *buffer;
  2731. int i;
  2732. QETH_CARD_TEXT(card, 6, "qdouhdl");
  2733. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2734. QETH_CARD_TEXT(card, 2, "achkcond");
  2735. netif_stop_queue(card->dev);
  2736. qeth_schedule_recovery(card);
  2737. return;
  2738. }
  2739. if (card->options.performance_stats) {
  2740. card->perf_stats.outbound_handler_cnt++;
  2741. card->perf_stats.outbound_handler_start_time =
  2742. qeth_get_micros();
  2743. }
  2744. for (i = first_element; i < (first_element + count); ++i) {
  2745. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2746. qeth_handle_send_error(card, buffer, qdio_error);
  2747. qeth_clear_output_buffer(queue, buffer);
  2748. }
  2749. atomic_sub(count, &queue->used_buffers);
  2750. /* check if we need to do something on this outbound queue */
  2751. if (card->info.type != QETH_CARD_TYPE_IQD)
  2752. qeth_check_outbound_queue(queue);
  2753. netif_wake_queue(queue->card->dev);
  2754. if (card->options.performance_stats)
  2755. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2756. card->perf_stats.outbound_handler_start_time;
  2757. }
  2758. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2759. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2760. int ipv, int cast_type)
  2761. {
  2762. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2763. card->info.type == QETH_CARD_TYPE_OSX))
  2764. return card->qdio.default_out_queue;
  2765. switch (card->qdio.no_out_queues) {
  2766. case 4:
  2767. if (cast_type && card->info.is_multicast_different)
  2768. return card->info.is_multicast_different &
  2769. (card->qdio.no_out_queues - 1);
  2770. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2771. const u8 tos = ip_hdr(skb)->tos;
  2772. if (card->qdio.do_prio_queueing ==
  2773. QETH_PRIO_Q_ING_TOS) {
  2774. if (tos & IP_TOS_NOTIMPORTANT)
  2775. return 3;
  2776. if (tos & IP_TOS_HIGHRELIABILITY)
  2777. return 2;
  2778. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2779. return 1;
  2780. if (tos & IP_TOS_LOWDELAY)
  2781. return 0;
  2782. }
  2783. if (card->qdio.do_prio_queueing ==
  2784. QETH_PRIO_Q_ING_PREC)
  2785. return 3 - (tos >> 6);
  2786. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2787. /* TODO: IPv6!!! */
  2788. }
  2789. return card->qdio.default_out_queue;
  2790. case 1: /* fallthrough for single-out-queue 1920-device */
  2791. default:
  2792. return card->qdio.default_out_queue;
  2793. }
  2794. }
  2795. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2796. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2797. struct sk_buff *skb, int elems)
  2798. {
  2799. int dlen = skb->len - skb->data_len;
  2800. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  2801. PFN_DOWN((unsigned long)skb->data);
  2802. elements_needed += skb_shinfo(skb)->nr_frags;
  2803. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2804. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2805. "(Number=%d / Length=%d). Discarded.\n",
  2806. (elements_needed+elems), skb->len);
  2807. return 0;
  2808. }
  2809. return elements_needed;
  2810. }
  2811. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2812. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  2813. {
  2814. int hroom, inpage, rest;
  2815. if (((unsigned long)skb->data & PAGE_MASK) !=
  2816. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  2817. hroom = skb_headroom(skb);
  2818. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  2819. rest = len - inpage;
  2820. if (rest > hroom)
  2821. return 1;
  2822. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  2823. skb->data -= rest;
  2824. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  2825. }
  2826. return 0;
  2827. }
  2828. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  2829. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2830. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2831. int offset)
  2832. {
  2833. int length = skb->len - skb->data_len;
  2834. int length_here;
  2835. int element;
  2836. char *data;
  2837. int first_lap, cnt;
  2838. struct skb_frag_struct *frag;
  2839. element = *next_element_to_fill;
  2840. data = skb->data;
  2841. first_lap = (is_tso == 0 ? 1 : 0);
  2842. if (offset >= 0) {
  2843. data = skb->data + offset;
  2844. length -= offset;
  2845. first_lap = 0;
  2846. }
  2847. while (length > 0) {
  2848. /* length_here is the remaining amount of data in this page */
  2849. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2850. if (length < length_here)
  2851. length_here = length;
  2852. buffer->element[element].addr = data;
  2853. buffer->element[element].length = length_here;
  2854. length -= length_here;
  2855. if (!length) {
  2856. if (first_lap)
  2857. if (skb_shinfo(skb)->nr_frags)
  2858. buffer->element[element].eflags =
  2859. SBAL_EFLAGS_FIRST_FRAG;
  2860. else
  2861. buffer->element[element].eflags = 0;
  2862. else
  2863. buffer->element[element].eflags =
  2864. SBAL_EFLAGS_MIDDLE_FRAG;
  2865. } else {
  2866. if (first_lap)
  2867. buffer->element[element].eflags =
  2868. SBAL_EFLAGS_FIRST_FRAG;
  2869. else
  2870. buffer->element[element].eflags =
  2871. SBAL_EFLAGS_MIDDLE_FRAG;
  2872. }
  2873. data += length_here;
  2874. element++;
  2875. first_lap = 0;
  2876. }
  2877. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  2878. frag = &skb_shinfo(skb)->frags[cnt];
  2879. buffer->element[element].addr = (char *)page_to_phys(frag->page)
  2880. + frag->page_offset;
  2881. buffer->element[element].length = frag->size;
  2882. buffer->element[element].eflags = SBAL_EFLAGS_MIDDLE_FRAG;
  2883. element++;
  2884. }
  2885. if (buffer->element[element - 1].eflags)
  2886. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  2887. *next_element_to_fill = element;
  2888. }
  2889. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2890. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2891. struct qeth_hdr *hdr, int offset, int hd_len)
  2892. {
  2893. struct qdio_buffer *buffer;
  2894. int flush_cnt = 0, hdr_len, large_send = 0;
  2895. buffer = buf->buffer;
  2896. atomic_inc(&skb->users);
  2897. skb_queue_tail(&buf->skb_list, skb);
  2898. /*check first on TSO ....*/
  2899. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2900. int element = buf->next_element_to_fill;
  2901. hdr_len = sizeof(struct qeth_hdr_tso) +
  2902. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2903. /*fill first buffer entry only with header information */
  2904. buffer->element[element].addr = skb->data;
  2905. buffer->element[element].length = hdr_len;
  2906. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  2907. buf->next_element_to_fill++;
  2908. skb->data += hdr_len;
  2909. skb->len -= hdr_len;
  2910. large_send = 1;
  2911. }
  2912. if (offset >= 0) {
  2913. int element = buf->next_element_to_fill;
  2914. buffer->element[element].addr = hdr;
  2915. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2916. hd_len;
  2917. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  2918. buf->is_header[element] = 1;
  2919. buf->next_element_to_fill++;
  2920. }
  2921. __qeth_fill_buffer(skb, buffer, large_send,
  2922. (int *)&buf->next_element_to_fill, offset);
  2923. if (!queue->do_pack) {
  2924. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  2925. /* set state to PRIMED -> will be flushed */
  2926. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2927. flush_cnt = 1;
  2928. } else {
  2929. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  2930. if (queue->card->options.performance_stats)
  2931. queue->card->perf_stats.skbs_sent_pack++;
  2932. if (buf->next_element_to_fill >=
  2933. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2934. /*
  2935. * packed buffer if full -> set state PRIMED
  2936. * -> will be flushed
  2937. */
  2938. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2939. flush_cnt = 1;
  2940. }
  2941. }
  2942. return flush_cnt;
  2943. }
  2944. int qeth_do_send_packet_fast(struct qeth_card *card,
  2945. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2946. struct qeth_hdr *hdr, int elements_needed,
  2947. int offset, int hd_len)
  2948. {
  2949. struct qeth_qdio_out_buffer *buffer;
  2950. int index;
  2951. /* spin until we get the queue ... */
  2952. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2953. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2954. /* ... now we've got the queue */
  2955. index = queue->next_buf_to_fill;
  2956. buffer = &queue->bufs[queue->next_buf_to_fill];
  2957. /*
  2958. * check if buffer is empty to make sure that we do not 'overtake'
  2959. * ourselves and try to fill a buffer that is already primed
  2960. */
  2961. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2962. goto out;
  2963. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2964. QDIO_MAX_BUFFERS_PER_Q;
  2965. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2966. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2967. qeth_flush_buffers(queue, index, 1);
  2968. return 0;
  2969. out:
  2970. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2971. return -EBUSY;
  2972. }
  2973. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2974. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2975. struct sk_buff *skb, struct qeth_hdr *hdr,
  2976. int elements_needed)
  2977. {
  2978. struct qeth_qdio_out_buffer *buffer;
  2979. int start_index;
  2980. int flush_count = 0;
  2981. int do_pack = 0;
  2982. int tmp;
  2983. int rc = 0;
  2984. /* spin until we get the queue ... */
  2985. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2986. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2987. start_index = queue->next_buf_to_fill;
  2988. buffer = &queue->bufs[queue->next_buf_to_fill];
  2989. /*
  2990. * check if buffer is empty to make sure that we do not 'overtake'
  2991. * ourselves and try to fill a buffer that is already primed
  2992. */
  2993. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2994. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2995. return -EBUSY;
  2996. }
  2997. /* check if we need to switch packing state of this queue */
  2998. qeth_switch_to_packing_if_needed(queue);
  2999. if (queue->do_pack) {
  3000. do_pack = 1;
  3001. /* does packet fit in current buffer? */
  3002. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3003. buffer->next_element_to_fill) < elements_needed) {
  3004. /* ... no -> set state PRIMED */
  3005. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3006. flush_count++;
  3007. queue->next_buf_to_fill =
  3008. (queue->next_buf_to_fill + 1) %
  3009. QDIO_MAX_BUFFERS_PER_Q;
  3010. buffer = &queue->bufs[queue->next_buf_to_fill];
  3011. /* we did a step forward, so check buffer state
  3012. * again */
  3013. if (atomic_read(&buffer->state) !=
  3014. QETH_QDIO_BUF_EMPTY) {
  3015. qeth_flush_buffers(queue, start_index,
  3016. flush_count);
  3017. atomic_set(&queue->state,
  3018. QETH_OUT_Q_UNLOCKED);
  3019. return -EBUSY;
  3020. }
  3021. }
  3022. }
  3023. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3024. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3025. QDIO_MAX_BUFFERS_PER_Q;
  3026. flush_count += tmp;
  3027. if (flush_count)
  3028. qeth_flush_buffers(queue, start_index, flush_count);
  3029. else if (!atomic_read(&queue->set_pci_flags_count))
  3030. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3031. /*
  3032. * queue->state will go from LOCKED -> UNLOCKED or from
  3033. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3034. * (switch packing state or flush buffer to get another pci flag out).
  3035. * In that case we will enter this loop
  3036. */
  3037. while (atomic_dec_return(&queue->state)) {
  3038. flush_count = 0;
  3039. start_index = queue->next_buf_to_fill;
  3040. /* check if we can go back to non-packing state */
  3041. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3042. /*
  3043. * check if we need to flush a packing buffer to get a pci
  3044. * flag out on the queue
  3045. */
  3046. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3047. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3048. if (flush_count)
  3049. qeth_flush_buffers(queue, start_index, flush_count);
  3050. }
  3051. /* at this point the queue is UNLOCKED again */
  3052. if (queue->card->options.performance_stats && do_pack)
  3053. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3054. return rc;
  3055. }
  3056. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3057. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3058. struct qeth_reply *reply, unsigned long data)
  3059. {
  3060. struct qeth_ipa_cmd *cmd;
  3061. struct qeth_ipacmd_setadpparms *setparms;
  3062. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3063. cmd = (struct qeth_ipa_cmd *) data;
  3064. setparms = &(cmd->data.setadapterparms);
  3065. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3066. if (cmd->hdr.return_code) {
  3067. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3068. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3069. }
  3070. card->info.promisc_mode = setparms->data.mode;
  3071. return 0;
  3072. }
  3073. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3074. {
  3075. enum qeth_ipa_promisc_modes mode;
  3076. struct net_device *dev = card->dev;
  3077. struct qeth_cmd_buffer *iob;
  3078. struct qeth_ipa_cmd *cmd;
  3079. QETH_CARD_TEXT(card, 4, "setprom");
  3080. if (((dev->flags & IFF_PROMISC) &&
  3081. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3082. (!(dev->flags & IFF_PROMISC) &&
  3083. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3084. return;
  3085. mode = SET_PROMISC_MODE_OFF;
  3086. if (dev->flags & IFF_PROMISC)
  3087. mode = SET_PROMISC_MODE_ON;
  3088. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3089. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3090. sizeof(struct qeth_ipacmd_setadpparms));
  3091. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3092. cmd->data.setadapterparms.data.mode = mode;
  3093. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3094. }
  3095. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3096. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3097. {
  3098. struct qeth_card *card;
  3099. char dbf_text[15];
  3100. card = dev->ml_priv;
  3101. QETH_CARD_TEXT(card, 4, "chgmtu");
  3102. sprintf(dbf_text, "%8x", new_mtu);
  3103. QETH_CARD_TEXT(card, 4, dbf_text);
  3104. if (new_mtu < 64)
  3105. return -EINVAL;
  3106. if (new_mtu > 65535)
  3107. return -EINVAL;
  3108. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3109. (!qeth_mtu_is_valid(card, new_mtu)))
  3110. return -EINVAL;
  3111. dev->mtu = new_mtu;
  3112. return 0;
  3113. }
  3114. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3115. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3116. {
  3117. struct qeth_card *card;
  3118. card = dev->ml_priv;
  3119. QETH_CARD_TEXT(card, 5, "getstat");
  3120. return &card->stats;
  3121. }
  3122. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3123. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3124. struct qeth_reply *reply, unsigned long data)
  3125. {
  3126. struct qeth_ipa_cmd *cmd;
  3127. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3128. cmd = (struct qeth_ipa_cmd *) data;
  3129. if (!card->options.layer2 ||
  3130. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3131. memcpy(card->dev->dev_addr,
  3132. &cmd->data.setadapterparms.data.change_addr.addr,
  3133. OSA_ADDR_LEN);
  3134. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3135. }
  3136. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3137. return 0;
  3138. }
  3139. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3140. {
  3141. int rc;
  3142. struct qeth_cmd_buffer *iob;
  3143. struct qeth_ipa_cmd *cmd;
  3144. QETH_CARD_TEXT(card, 4, "chgmac");
  3145. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3146. sizeof(struct qeth_ipacmd_setadpparms));
  3147. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3148. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3149. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3150. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3151. card->dev->dev_addr, OSA_ADDR_LEN);
  3152. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3153. NULL);
  3154. return rc;
  3155. }
  3156. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3157. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3158. struct qeth_reply *reply, unsigned long data)
  3159. {
  3160. struct qeth_ipa_cmd *cmd;
  3161. struct qeth_set_access_ctrl *access_ctrl_req;
  3162. QETH_CARD_TEXT(card, 4, "setaccb");
  3163. cmd = (struct qeth_ipa_cmd *) data;
  3164. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3165. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3166. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3167. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3168. cmd->data.setadapterparms.hdr.return_code);
  3169. switch (cmd->data.setadapterparms.hdr.return_code) {
  3170. case SET_ACCESS_CTRL_RC_SUCCESS:
  3171. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3172. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3173. {
  3174. card->options.isolation = access_ctrl_req->subcmd_code;
  3175. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3176. dev_info(&card->gdev->dev,
  3177. "QDIO data connection isolation is deactivated\n");
  3178. } else {
  3179. dev_info(&card->gdev->dev,
  3180. "QDIO data connection isolation is activated\n");
  3181. }
  3182. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3183. card->gdev->dev.kobj.name,
  3184. access_ctrl_req->subcmd_code,
  3185. cmd->data.setadapterparms.hdr.return_code);
  3186. break;
  3187. }
  3188. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3189. {
  3190. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3191. card->gdev->dev.kobj.name,
  3192. access_ctrl_req->subcmd_code,
  3193. cmd->data.setadapterparms.hdr.return_code);
  3194. dev_err(&card->gdev->dev, "Adapter does not "
  3195. "support QDIO data connection isolation\n");
  3196. /* ensure isolation mode is "none" */
  3197. card->options.isolation = ISOLATION_MODE_NONE;
  3198. break;
  3199. }
  3200. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3201. {
  3202. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3203. card->gdev->dev.kobj.name,
  3204. access_ctrl_req->subcmd_code,
  3205. cmd->data.setadapterparms.hdr.return_code);
  3206. dev_err(&card->gdev->dev,
  3207. "Adapter is dedicated. "
  3208. "QDIO data connection isolation not supported\n");
  3209. /* ensure isolation mode is "none" */
  3210. card->options.isolation = ISOLATION_MODE_NONE;
  3211. break;
  3212. }
  3213. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3214. {
  3215. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3216. card->gdev->dev.kobj.name,
  3217. access_ctrl_req->subcmd_code,
  3218. cmd->data.setadapterparms.hdr.return_code);
  3219. dev_err(&card->gdev->dev,
  3220. "TSO does not permit QDIO data connection isolation\n");
  3221. /* ensure isolation mode is "none" */
  3222. card->options.isolation = ISOLATION_MODE_NONE;
  3223. break;
  3224. }
  3225. default:
  3226. {
  3227. /* this should never happen */
  3228. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3229. "==UNKNOWN\n",
  3230. card->gdev->dev.kobj.name,
  3231. access_ctrl_req->subcmd_code,
  3232. cmd->data.setadapterparms.hdr.return_code);
  3233. /* ensure isolation mode is "none" */
  3234. card->options.isolation = ISOLATION_MODE_NONE;
  3235. break;
  3236. }
  3237. }
  3238. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3239. return 0;
  3240. }
  3241. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3242. enum qeth_ipa_isolation_modes isolation)
  3243. {
  3244. int rc;
  3245. struct qeth_cmd_buffer *iob;
  3246. struct qeth_ipa_cmd *cmd;
  3247. struct qeth_set_access_ctrl *access_ctrl_req;
  3248. QETH_CARD_TEXT(card, 4, "setacctl");
  3249. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3250. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3251. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3252. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3253. sizeof(struct qeth_set_access_ctrl));
  3254. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3255. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3256. access_ctrl_req->subcmd_code = isolation;
  3257. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3258. NULL);
  3259. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3260. return rc;
  3261. }
  3262. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3263. {
  3264. int rc = 0;
  3265. QETH_CARD_TEXT(card, 4, "setactlo");
  3266. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3267. card->info.type == QETH_CARD_TYPE_OSX) &&
  3268. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3269. rc = qeth_setadpparms_set_access_ctrl(card,
  3270. card->options.isolation);
  3271. if (rc) {
  3272. QETH_DBF_MESSAGE(3,
  3273. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3274. card->gdev->dev.kobj.name,
  3275. rc);
  3276. }
  3277. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3278. card->options.isolation = ISOLATION_MODE_NONE;
  3279. dev_err(&card->gdev->dev, "Adapter does not "
  3280. "support QDIO data connection isolation\n");
  3281. rc = -EOPNOTSUPP;
  3282. }
  3283. return rc;
  3284. }
  3285. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3286. void qeth_tx_timeout(struct net_device *dev)
  3287. {
  3288. struct qeth_card *card;
  3289. card = dev->ml_priv;
  3290. QETH_CARD_TEXT(card, 4, "txtimeo");
  3291. card->stats.tx_errors++;
  3292. qeth_schedule_recovery(card);
  3293. }
  3294. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3295. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3296. {
  3297. struct qeth_card *card = dev->ml_priv;
  3298. int rc = 0;
  3299. switch (regnum) {
  3300. case MII_BMCR: /* Basic mode control register */
  3301. rc = BMCR_FULLDPLX;
  3302. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3303. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3304. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3305. rc |= BMCR_SPEED100;
  3306. break;
  3307. case MII_BMSR: /* Basic mode status register */
  3308. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3309. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3310. BMSR_100BASE4;
  3311. break;
  3312. case MII_PHYSID1: /* PHYS ID 1 */
  3313. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3314. dev->dev_addr[2];
  3315. rc = (rc >> 5) & 0xFFFF;
  3316. break;
  3317. case MII_PHYSID2: /* PHYS ID 2 */
  3318. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3319. break;
  3320. case MII_ADVERTISE: /* Advertisement control reg */
  3321. rc = ADVERTISE_ALL;
  3322. break;
  3323. case MII_LPA: /* Link partner ability reg */
  3324. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3325. LPA_100BASE4 | LPA_LPACK;
  3326. break;
  3327. case MII_EXPANSION: /* Expansion register */
  3328. break;
  3329. case MII_DCOUNTER: /* disconnect counter */
  3330. break;
  3331. case MII_FCSCOUNTER: /* false carrier counter */
  3332. break;
  3333. case MII_NWAYTEST: /* N-way auto-neg test register */
  3334. break;
  3335. case MII_RERRCOUNTER: /* rx error counter */
  3336. rc = card->stats.rx_errors;
  3337. break;
  3338. case MII_SREVISION: /* silicon revision */
  3339. break;
  3340. case MII_RESV1: /* reserved 1 */
  3341. break;
  3342. case MII_LBRERROR: /* loopback, rx, bypass error */
  3343. break;
  3344. case MII_PHYADDR: /* physical address */
  3345. break;
  3346. case MII_RESV2: /* reserved 2 */
  3347. break;
  3348. case MII_TPISTATUS: /* TPI status for 10mbps */
  3349. break;
  3350. case MII_NCONFIG: /* network interface config */
  3351. break;
  3352. default:
  3353. break;
  3354. }
  3355. return rc;
  3356. }
  3357. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3358. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3359. struct qeth_cmd_buffer *iob, int len,
  3360. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3361. unsigned long),
  3362. void *reply_param)
  3363. {
  3364. u16 s1, s2;
  3365. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3366. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3367. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3368. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3369. /* adjust PDU length fields in IPA_PDU_HEADER */
  3370. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3371. s2 = (u32) len;
  3372. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3373. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3374. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3375. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3376. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3377. reply_cb, reply_param);
  3378. }
  3379. static int qeth_snmp_command_cb(struct qeth_card *card,
  3380. struct qeth_reply *reply, unsigned long sdata)
  3381. {
  3382. struct qeth_ipa_cmd *cmd;
  3383. struct qeth_arp_query_info *qinfo;
  3384. struct qeth_snmp_cmd *snmp;
  3385. unsigned char *data;
  3386. __u16 data_len;
  3387. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3388. cmd = (struct qeth_ipa_cmd *) sdata;
  3389. data = (unsigned char *)((char *)cmd - reply->offset);
  3390. qinfo = (struct qeth_arp_query_info *) reply->param;
  3391. snmp = &cmd->data.setadapterparms.data.snmp;
  3392. if (cmd->hdr.return_code) {
  3393. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3394. return 0;
  3395. }
  3396. if (cmd->data.setadapterparms.hdr.return_code) {
  3397. cmd->hdr.return_code =
  3398. cmd->data.setadapterparms.hdr.return_code;
  3399. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3400. return 0;
  3401. }
  3402. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3403. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3404. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3405. else
  3406. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3407. /* check if there is enough room in userspace */
  3408. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3409. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3410. cmd->hdr.return_code = -ENOMEM;
  3411. return 0;
  3412. }
  3413. QETH_CARD_TEXT_(card, 4, "snore%i",
  3414. cmd->data.setadapterparms.hdr.used_total);
  3415. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3416. cmd->data.setadapterparms.hdr.seq_no);
  3417. /*copy entries to user buffer*/
  3418. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3419. memcpy(qinfo->udata + qinfo->udata_offset,
  3420. (char *)snmp,
  3421. data_len + offsetof(struct qeth_snmp_cmd, data));
  3422. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3423. } else {
  3424. memcpy(qinfo->udata + qinfo->udata_offset,
  3425. (char *)&snmp->request, data_len);
  3426. }
  3427. qinfo->udata_offset += data_len;
  3428. /* check if all replies received ... */
  3429. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3430. cmd->data.setadapterparms.hdr.used_total);
  3431. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3432. cmd->data.setadapterparms.hdr.seq_no);
  3433. if (cmd->data.setadapterparms.hdr.seq_no <
  3434. cmd->data.setadapterparms.hdr.used_total)
  3435. return 1;
  3436. return 0;
  3437. }
  3438. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3439. {
  3440. struct qeth_cmd_buffer *iob;
  3441. struct qeth_ipa_cmd *cmd;
  3442. struct qeth_snmp_ureq *ureq;
  3443. int req_len;
  3444. struct qeth_arp_query_info qinfo = {0, };
  3445. int rc = 0;
  3446. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3447. if (card->info.guestlan)
  3448. return -EOPNOTSUPP;
  3449. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3450. (!card->options.layer2)) {
  3451. return -EOPNOTSUPP;
  3452. }
  3453. /* skip 4 bytes (data_len struct member) to get req_len */
  3454. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3455. return -EFAULT;
  3456. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3457. if (IS_ERR(ureq)) {
  3458. QETH_CARD_TEXT(card, 2, "snmpnome");
  3459. return PTR_ERR(ureq);
  3460. }
  3461. qinfo.udata_len = ureq->hdr.data_len;
  3462. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3463. if (!qinfo.udata) {
  3464. kfree(ureq);
  3465. return -ENOMEM;
  3466. }
  3467. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3468. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3469. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3470. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3471. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3472. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3473. qeth_snmp_command_cb, (void *)&qinfo);
  3474. if (rc)
  3475. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3476. QETH_CARD_IFNAME(card), rc);
  3477. else {
  3478. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3479. rc = -EFAULT;
  3480. }
  3481. kfree(ureq);
  3482. kfree(qinfo.udata);
  3483. return rc;
  3484. }
  3485. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3486. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3487. {
  3488. switch (card->info.type) {
  3489. case QETH_CARD_TYPE_IQD:
  3490. return 2;
  3491. default:
  3492. return 0;
  3493. }
  3494. }
  3495. static void qeth_determine_capabilities(struct qeth_card *card)
  3496. {
  3497. int rc;
  3498. int length;
  3499. char *prcd;
  3500. struct ccw_device *ddev;
  3501. int ddev_offline = 0;
  3502. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3503. ddev = CARD_DDEV(card);
  3504. if (!ddev->online) {
  3505. ddev_offline = 1;
  3506. rc = ccw_device_set_online(ddev);
  3507. if (rc) {
  3508. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3509. goto out;
  3510. }
  3511. }
  3512. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3513. if (rc) {
  3514. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3515. dev_name(&card->gdev->dev), rc);
  3516. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3517. goto out_offline;
  3518. }
  3519. qeth_configure_unitaddr(card, prcd);
  3520. qeth_configure_blkt_default(card, prcd);
  3521. kfree(prcd);
  3522. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  3523. if (rc)
  3524. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3525. out_offline:
  3526. if (ddev_offline == 1)
  3527. ccw_device_set_offline(ddev);
  3528. out:
  3529. return;
  3530. }
  3531. static int qeth_qdio_establish(struct qeth_card *card)
  3532. {
  3533. struct qdio_initialize init_data;
  3534. char *qib_param_field;
  3535. struct qdio_buffer **in_sbal_ptrs;
  3536. struct qdio_buffer **out_sbal_ptrs;
  3537. int i, j, k;
  3538. int rc = 0;
  3539. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3540. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3541. GFP_KERNEL);
  3542. if (!qib_param_field)
  3543. return -ENOMEM;
  3544. qeth_create_qib_param_field(card, qib_param_field);
  3545. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3546. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3547. GFP_KERNEL);
  3548. if (!in_sbal_ptrs) {
  3549. kfree(qib_param_field);
  3550. return -ENOMEM;
  3551. }
  3552. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3553. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3554. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3555. out_sbal_ptrs =
  3556. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3557. sizeof(void *), GFP_KERNEL);
  3558. if (!out_sbal_ptrs) {
  3559. kfree(in_sbal_ptrs);
  3560. kfree(qib_param_field);
  3561. return -ENOMEM;
  3562. }
  3563. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3564. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3565. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3566. card->qdio.out_qs[i]->bufs[j].buffer);
  3567. }
  3568. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3569. init_data.cdev = CARD_DDEV(card);
  3570. init_data.q_format = qeth_get_qdio_q_format(card);
  3571. init_data.qib_param_field_format = 0;
  3572. init_data.qib_param_field = qib_param_field;
  3573. init_data.no_input_qs = 1;
  3574. init_data.no_output_qs = card->qdio.no_out_queues;
  3575. init_data.input_handler = card->discipline.input_handler;
  3576. init_data.output_handler = card->discipline.output_handler;
  3577. init_data.queue_start_poll = card->discipline.start_poll;
  3578. init_data.int_parm = (unsigned long) card;
  3579. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3580. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3581. init_data.scan_threshold =
  3582. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  3583. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3584. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3585. rc = qdio_allocate(&init_data);
  3586. if (rc) {
  3587. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3588. goto out;
  3589. }
  3590. rc = qdio_establish(&init_data);
  3591. if (rc) {
  3592. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3593. qdio_free(CARD_DDEV(card));
  3594. }
  3595. }
  3596. out:
  3597. kfree(out_sbal_ptrs);
  3598. kfree(in_sbal_ptrs);
  3599. kfree(qib_param_field);
  3600. return rc;
  3601. }
  3602. static void qeth_core_free_card(struct qeth_card *card)
  3603. {
  3604. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3605. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3606. qeth_clean_channel(&card->read);
  3607. qeth_clean_channel(&card->write);
  3608. if (card->dev)
  3609. free_netdev(card->dev);
  3610. kfree(card->ip_tbd_list);
  3611. qeth_free_qdio_buffers(card);
  3612. unregister_service_level(&card->qeth_service_level);
  3613. kfree(card);
  3614. }
  3615. static struct ccw_device_id qeth_ids[] = {
  3616. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3617. .driver_info = QETH_CARD_TYPE_OSD},
  3618. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3619. .driver_info = QETH_CARD_TYPE_IQD},
  3620. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3621. .driver_info = QETH_CARD_TYPE_OSN},
  3622. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3623. .driver_info = QETH_CARD_TYPE_OSM},
  3624. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3625. .driver_info = QETH_CARD_TYPE_OSX},
  3626. {},
  3627. };
  3628. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3629. static struct ccw_driver qeth_ccw_driver = {
  3630. .driver = {
  3631. .owner = THIS_MODULE,
  3632. .name = "qeth",
  3633. },
  3634. .ids = qeth_ids,
  3635. .probe = ccwgroup_probe_ccwdev,
  3636. .remove = ccwgroup_remove_ccwdev,
  3637. };
  3638. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3639. unsigned long driver_id)
  3640. {
  3641. return ccwgroup_create_from_string(root_dev, driver_id,
  3642. &qeth_ccw_driver, 3, buf);
  3643. }
  3644. int qeth_core_hardsetup_card(struct qeth_card *card)
  3645. {
  3646. int retries = 0;
  3647. int rc;
  3648. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3649. atomic_set(&card->force_alloc_skb, 0);
  3650. qeth_get_channel_path_desc(card);
  3651. retry:
  3652. if (retries)
  3653. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3654. dev_name(&card->gdev->dev));
  3655. ccw_device_set_offline(CARD_DDEV(card));
  3656. ccw_device_set_offline(CARD_WDEV(card));
  3657. ccw_device_set_offline(CARD_RDEV(card));
  3658. rc = ccw_device_set_online(CARD_RDEV(card));
  3659. if (rc)
  3660. goto retriable;
  3661. rc = ccw_device_set_online(CARD_WDEV(card));
  3662. if (rc)
  3663. goto retriable;
  3664. rc = ccw_device_set_online(CARD_DDEV(card));
  3665. if (rc)
  3666. goto retriable;
  3667. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3668. retriable:
  3669. if (rc == -ERESTARTSYS) {
  3670. QETH_DBF_TEXT(SETUP, 2, "break1");
  3671. return rc;
  3672. } else if (rc) {
  3673. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3674. if (++retries > 3)
  3675. goto out;
  3676. else
  3677. goto retry;
  3678. }
  3679. qeth_determine_capabilities(card);
  3680. qeth_init_tokens(card);
  3681. qeth_init_func_level(card);
  3682. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3683. if (rc == -ERESTARTSYS) {
  3684. QETH_DBF_TEXT(SETUP, 2, "break2");
  3685. return rc;
  3686. } else if (rc) {
  3687. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3688. if (--retries < 0)
  3689. goto out;
  3690. else
  3691. goto retry;
  3692. }
  3693. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3694. if (rc == -ERESTARTSYS) {
  3695. QETH_DBF_TEXT(SETUP, 2, "break3");
  3696. return rc;
  3697. } else if (rc) {
  3698. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3699. if (--retries < 0)
  3700. goto out;
  3701. else
  3702. goto retry;
  3703. }
  3704. card->read_or_write_problem = 0;
  3705. rc = qeth_mpc_initialize(card);
  3706. if (rc) {
  3707. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3708. goto out;
  3709. }
  3710. card->options.ipa4.supported_funcs = 0;
  3711. card->options.adp.supported_funcs = 0;
  3712. card->info.diagass_support = 0;
  3713. qeth_query_ipassists(card, QETH_PROT_IPV4);
  3714. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  3715. qeth_query_setadapterparms(card);
  3716. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  3717. qeth_query_setdiagass(card);
  3718. return 0;
  3719. out:
  3720. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3721. "an error on the device\n");
  3722. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3723. dev_name(&card->gdev->dev), rc);
  3724. return rc;
  3725. }
  3726. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3727. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3728. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3729. {
  3730. struct page *page = virt_to_page(element->addr);
  3731. if (*pskb == NULL) {
  3732. /* the upper protocol layers assume that there is data in the
  3733. * skb itself. Copy a small amount (64 bytes) to make them
  3734. * happy. */
  3735. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3736. if (!(*pskb))
  3737. return -ENOMEM;
  3738. skb_reserve(*pskb, ETH_HLEN);
  3739. if (data_len <= 64) {
  3740. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3741. data_len);
  3742. } else {
  3743. get_page(page);
  3744. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3745. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3746. data_len - 64);
  3747. (*pskb)->data_len += data_len - 64;
  3748. (*pskb)->len += data_len - 64;
  3749. (*pskb)->truesize += data_len - 64;
  3750. (*pfrag)++;
  3751. }
  3752. } else {
  3753. get_page(page);
  3754. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3755. (*pskb)->data_len += data_len;
  3756. (*pskb)->len += data_len;
  3757. (*pskb)->truesize += data_len;
  3758. (*pfrag)++;
  3759. }
  3760. return 0;
  3761. }
  3762. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3763. struct qdio_buffer *buffer,
  3764. struct qdio_buffer_element **__element, int *__offset,
  3765. struct qeth_hdr **hdr)
  3766. {
  3767. struct qdio_buffer_element *element = *__element;
  3768. int offset = *__offset;
  3769. struct sk_buff *skb = NULL;
  3770. int skb_len = 0;
  3771. void *data_ptr;
  3772. int data_len;
  3773. int headroom = 0;
  3774. int use_rx_sg = 0;
  3775. int frag = 0;
  3776. /* qeth_hdr must not cross element boundaries */
  3777. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3778. if (qeth_is_last_sbale(element))
  3779. return NULL;
  3780. element++;
  3781. offset = 0;
  3782. if (element->length < sizeof(struct qeth_hdr))
  3783. return NULL;
  3784. }
  3785. *hdr = element->addr + offset;
  3786. offset += sizeof(struct qeth_hdr);
  3787. switch ((*hdr)->hdr.l2.id) {
  3788. case QETH_HEADER_TYPE_LAYER2:
  3789. skb_len = (*hdr)->hdr.l2.pkt_length;
  3790. break;
  3791. case QETH_HEADER_TYPE_LAYER3:
  3792. skb_len = (*hdr)->hdr.l3.length;
  3793. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3794. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3795. headroom = TR_HLEN;
  3796. else
  3797. headroom = ETH_HLEN;
  3798. break;
  3799. case QETH_HEADER_TYPE_OSN:
  3800. skb_len = (*hdr)->hdr.osn.pdu_length;
  3801. headroom = sizeof(struct qeth_hdr);
  3802. break;
  3803. default:
  3804. break;
  3805. }
  3806. if (!skb_len)
  3807. return NULL;
  3808. if ((skb_len >= card->options.rx_sg_cb) &&
  3809. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3810. (!atomic_read(&card->force_alloc_skb))) {
  3811. use_rx_sg = 1;
  3812. } else {
  3813. skb = dev_alloc_skb(skb_len + headroom);
  3814. if (!skb)
  3815. goto no_mem;
  3816. if (headroom)
  3817. skb_reserve(skb, headroom);
  3818. }
  3819. data_ptr = element->addr + offset;
  3820. while (skb_len) {
  3821. data_len = min(skb_len, (int)(element->length - offset));
  3822. if (data_len) {
  3823. if (use_rx_sg) {
  3824. if (qeth_create_skb_frag(element, &skb, offset,
  3825. &frag, data_len))
  3826. goto no_mem;
  3827. } else {
  3828. memcpy(skb_put(skb, data_len), data_ptr,
  3829. data_len);
  3830. }
  3831. }
  3832. skb_len -= data_len;
  3833. if (skb_len) {
  3834. if (qeth_is_last_sbale(element)) {
  3835. QETH_CARD_TEXT(card, 4, "unexeob");
  3836. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  3837. dev_kfree_skb_any(skb);
  3838. card->stats.rx_errors++;
  3839. return NULL;
  3840. }
  3841. element++;
  3842. offset = 0;
  3843. data_ptr = element->addr;
  3844. } else {
  3845. offset += data_len;
  3846. }
  3847. }
  3848. *__element = element;
  3849. *__offset = offset;
  3850. if (use_rx_sg && card->options.performance_stats) {
  3851. card->perf_stats.sg_skbs_rx++;
  3852. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3853. }
  3854. return skb;
  3855. no_mem:
  3856. if (net_ratelimit()) {
  3857. QETH_CARD_TEXT(card, 2, "noskbmem");
  3858. }
  3859. card->stats.rx_dropped++;
  3860. return NULL;
  3861. }
  3862. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3863. static void qeth_unregister_dbf_views(void)
  3864. {
  3865. int x;
  3866. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3867. debug_unregister(qeth_dbf[x].id);
  3868. qeth_dbf[x].id = NULL;
  3869. }
  3870. }
  3871. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  3872. {
  3873. char dbf_txt_buf[32];
  3874. va_list args;
  3875. if (level > id->level)
  3876. return;
  3877. va_start(args, fmt);
  3878. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3879. va_end(args);
  3880. debug_text_event(id, level, dbf_txt_buf);
  3881. }
  3882. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3883. static int qeth_register_dbf_views(void)
  3884. {
  3885. int ret;
  3886. int x;
  3887. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3888. /* register the areas */
  3889. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3890. qeth_dbf[x].pages,
  3891. qeth_dbf[x].areas,
  3892. qeth_dbf[x].len);
  3893. if (qeth_dbf[x].id == NULL) {
  3894. qeth_unregister_dbf_views();
  3895. return -ENOMEM;
  3896. }
  3897. /* register a view */
  3898. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3899. if (ret) {
  3900. qeth_unregister_dbf_views();
  3901. return ret;
  3902. }
  3903. /* set a passing level */
  3904. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3905. }
  3906. return 0;
  3907. }
  3908. int qeth_core_load_discipline(struct qeth_card *card,
  3909. enum qeth_discipline_id discipline)
  3910. {
  3911. int rc = 0;
  3912. switch (discipline) {
  3913. case QETH_DISCIPLINE_LAYER3:
  3914. card->discipline.ccwgdriver = try_then_request_module(
  3915. symbol_get(qeth_l3_ccwgroup_driver),
  3916. "qeth_l3");
  3917. break;
  3918. case QETH_DISCIPLINE_LAYER2:
  3919. card->discipline.ccwgdriver = try_then_request_module(
  3920. symbol_get(qeth_l2_ccwgroup_driver),
  3921. "qeth_l2");
  3922. break;
  3923. }
  3924. if (!card->discipline.ccwgdriver) {
  3925. dev_err(&card->gdev->dev, "There is no kernel module to "
  3926. "support discipline %d\n", discipline);
  3927. rc = -EINVAL;
  3928. }
  3929. return rc;
  3930. }
  3931. void qeth_core_free_discipline(struct qeth_card *card)
  3932. {
  3933. if (card->options.layer2)
  3934. symbol_put(qeth_l2_ccwgroup_driver);
  3935. else
  3936. symbol_put(qeth_l3_ccwgroup_driver);
  3937. card->discipline.ccwgdriver = NULL;
  3938. }
  3939. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3940. {
  3941. struct qeth_card *card;
  3942. struct device *dev;
  3943. int rc;
  3944. unsigned long flags;
  3945. char dbf_name[20];
  3946. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3947. dev = &gdev->dev;
  3948. if (!get_device(dev))
  3949. return -ENODEV;
  3950. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3951. card = qeth_alloc_card();
  3952. if (!card) {
  3953. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3954. rc = -ENOMEM;
  3955. goto err_dev;
  3956. }
  3957. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  3958. dev_name(&gdev->dev));
  3959. card->debug = debug_register(dbf_name, 2, 1, 8);
  3960. if (!card->debug) {
  3961. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  3962. rc = -ENOMEM;
  3963. goto err_card;
  3964. }
  3965. debug_register_view(card->debug, &debug_hex_ascii_view);
  3966. card->read.ccwdev = gdev->cdev[0];
  3967. card->write.ccwdev = gdev->cdev[1];
  3968. card->data.ccwdev = gdev->cdev[2];
  3969. dev_set_drvdata(&gdev->dev, card);
  3970. card->gdev = gdev;
  3971. gdev->cdev[0]->handler = qeth_irq;
  3972. gdev->cdev[1]->handler = qeth_irq;
  3973. gdev->cdev[2]->handler = qeth_irq;
  3974. rc = qeth_determine_card_type(card);
  3975. if (rc) {
  3976. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3977. goto err_dbf;
  3978. }
  3979. rc = qeth_setup_card(card);
  3980. if (rc) {
  3981. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3982. goto err_dbf;
  3983. }
  3984. if (card->info.type == QETH_CARD_TYPE_OSN)
  3985. rc = qeth_core_create_osn_attributes(dev);
  3986. else
  3987. rc = qeth_core_create_device_attributes(dev);
  3988. if (rc)
  3989. goto err_dbf;
  3990. switch (card->info.type) {
  3991. case QETH_CARD_TYPE_OSN:
  3992. case QETH_CARD_TYPE_OSM:
  3993. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3994. if (rc)
  3995. goto err_attr;
  3996. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3997. if (rc)
  3998. goto err_disc;
  3999. case QETH_CARD_TYPE_OSD:
  4000. case QETH_CARD_TYPE_OSX:
  4001. default:
  4002. break;
  4003. }
  4004. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4005. list_add_tail(&card->list, &qeth_core_card_list.list);
  4006. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4007. qeth_determine_capabilities(card);
  4008. return 0;
  4009. err_disc:
  4010. qeth_core_free_discipline(card);
  4011. err_attr:
  4012. if (card->info.type == QETH_CARD_TYPE_OSN)
  4013. qeth_core_remove_osn_attributes(dev);
  4014. else
  4015. qeth_core_remove_device_attributes(dev);
  4016. err_dbf:
  4017. debug_unregister(card->debug);
  4018. err_card:
  4019. qeth_core_free_card(card);
  4020. err_dev:
  4021. put_device(dev);
  4022. return rc;
  4023. }
  4024. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4025. {
  4026. unsigned long flags;
  4027. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4028. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4029. if (card->info.type == QETH_CARD_TYPE_OSN) {
  4030. qeth_core_remove_osn_attributes(&gdev->dev);
  4031. } else {
  4032. qeth_core_remove_device_attributes(&gdev->dev);
  4033. }
  4034. if (card->discipline.ccwgdriver) {
  4035. card->discipline.ccwgdriver->remove(gdev);
  4036. qeth_core_free_discipline(card);
  4037. }
  4038. debug_unregister(card->debug);
  4039. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4040. list_del(&card->list);
  4041. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4042. qeth_core_free_card(card);
  4043. dev_set_drvdata(&gdev->dev, NULL);
  4044. put_device(&gdev->dev);
  4045. return;
  4046. }
  4047. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4048. {
  4049. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4050. int rc = 0;
  4051. int def_discipline;
  4052. if (!card->discipline.ccwgdriver) {
  4053. if (card->info.type == QETH_CARD_TYPE_IQD)
  4054. def_discipline = QETH_DISCIPLINE_LAYER3;
  4055. else
  4056. def_discipline = QETH_DISCIPLINE_LAYER2;
  4057. rc = qeth_core_load_discipline(card, def_discipline);
  4058. if (rc)
  4059. goto err;
  4060. rc = card->discipline.ccwgdriver->probe(card->gdev);
  4061. if (rc)
  4062. goto err;
  4063. }
  4064. rc = card->discipline.ccwgdriver->set_online(gdev);
  4065. err:
  4066. return rc;
  4067. }
  4068. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4069. {
  4070. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4071. return card->discipline.ccwgdriver->set_offline(gdev);
  4072. }
  4073. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4074. {
  4075. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4076. if (card->discipline.ccwgdriver &&
  4077. card->discipline.ccwgdriver->shutdown)
  4078. card->discipline.ccwgdriver->shutdown(gdev);
  4079. }
  4080. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4081. {
  4082. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4083. if (card->discipline.ccwgdriver &&
  4084. card->discipline.ccwgdriver->prepare)
  4085. return card->discipline.ccwgdriver->prepare(gdev);
  4086. return 0;
  4087. }
  4088. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4089. {
  4090. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4091. if (card->discipline.ccwgdriver &&
  4092. card->discipline.ccwgdriver->complete)
  4093. card->discipline.ccwgdriver->complete(gdev);
  4094. }
  4095. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4096. {
  4097. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4098. if (card->discipline.ccwgdriver &&
  4099. card->discipline.ccwgdriver->freeze)
  4100. return card->discipline.ccwgdriver->freeze(gdev);
  4101. return 0;
  4102. }
  4103. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4104. {
  4105. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4106. if (card->discipline.ccwgdriver &&
  4107. card->discipline.ccwgdriver->thaw)
  4108. return card->discipline.ccwgdriver->thaw(gdev);
  4109. return 0;
  4110. }
  4111. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4112. {
  4113. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4114. if (card->discipline.ccwgdriver &&
  4115. card->discipline.ccwgdriver->restore)
  4116. return card->discipline.ccwgdriver->restore(gdev);
  4117. return 0;
  4118. }
  4119. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4120. .driver = {
  4121. .owner = THIS_MODULE,
  4122. .name = "qeth",
  4123. },
  4124. .driver_id = 0xD8C5E3C8,
  4125. .probe = qeth_core_probe_device,
  4126. .remove = qeth_core_remove_device,
  4127. .set_online = qeth_core_set_online,
  4128. .set_offline = qeth_core_set_offline,
  4129. .shutdown = qeth_core_shutdown,
  4130. .prepare = qeth_core_prepare,
  4131. .complete = qeth_core_complete,
  4132. .freeze = qeth_core_freeze,
  4133. .thaw = qeth_core_thaw,
  4134. .restore = qeth_core_restore,
  4135. };
  4136. static ssize_t
  4137. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4138. size_t count)
  4139. {
  4140. int err;
  4141. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4142. qeth_core_ccwgroup_driver.driver_id);
  4143. if (err)
  4144. return err;
  4145. else
  4146. return count;
  4147. }
  4148. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4149. static struct {
  4150. const char str[ETH_GSTRING_LEN];
  4151. } qeth_ethtool_stats_keys[] = {
  4152. /* 0 */{"rx skbs"},
  4153. {"rx buffers"},
  4154. {"tx skbs"},
  4155. {"tx buffers"},
  4156. {"tx skbs no packing"},
  4157. {"tx buffers no packing"},
  4158. {"tx skbs packing"},
  4159. {"tx buffers packing"},
  4160. {"tx sg skbs"},
  4161. {"tx sg frags"},
  4162. /* 10 */{"rx sg skbs"},
  4163. {"rx sg frags"},
  4164. {"rx sg page allocs"},
  4165. {"tx large kbytes"},
  4166. {"tx large count"},
  4167. {"tx pk state ch n->p"},
  4168. {"tx pk state ch p->n"},
  4169. {"tx pk watermark low"},
  4170. {"tx pk watermark high"},
  4171. {"queue 0 buffer usage"},
  4172. /* 20 */{"queue 1 buffer usage"},
  4173. {"queue 2 buffer usage"},
  4174. {"queue 3 buffer usage"},
  4175. {"rx poll time"},
  4176. {"rx poll count"},
  4177. {"rx do_QDIO time"},
  4178. {"rx do_QDIO count"},
  4179. {"tx handler time"},
  4180. {"tx handler count"},
  4181. {"tx time"},
  4182. /* 30 */{"tx count"},
  4183. {"tx do_QDIO time"},
  4184. {"tx do_QDIO count"},
  4185. {"tx csum"},
  4186. {"tx lin"},
  4187. };
  4188. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4189. {
  4190. switch (stringset) {
  4191. case ETH_SS_STATS:
  4192. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4193. default:
  4194. return -EINVAL;
  4195. }
  4196. }
  4197. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4198. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4199. struct ethtool_stats *stats, u64 *data)
  4200. {
  4201. struct qeth_card *card = dev->ml_priv;
  4202. data[0] = card->stats.rx_packets -
  4203. card->perf_stats.initial_rx_packets;
  4204. data[1] = card->perf_stats.bufs_rec;
  4205. data[2] = card->stats.tx_packets -
  4206. card->perf_stats.initial_tx_packets;
  4207. data[3] = card->perf_stats.bufs_sent;
  4208. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4209. - card->perf_stats.skbs_sent_pack;
  4210. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4211. data[6] = card->perf_stats.skbs_sent_pack;
  4212. data[7] = card->perf_stats.bufs_sent_pack;
  4213. data[8] = card->perf_stats.sg_skbs_sent;
  4214. data[9] = card->perf_stats.sg_frags_sent;
  4215. data[10] = card->perf_stats.sg_skbs_rx;
  4216. data[11] = card->perf_stats.sg_frags_rx;
  4217. data[12] = card->perf_stats.sg_alloc_page_rx;
  4218. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4219. data[14] = card->perf_stats.large_send_cnt;
  4220. data[15] = card->perf_stats.sc_dp_p;
  4221. data[16] = card->perf_stats.sc_p_dp;
  4222. data[17] = QETH_LOW_WATERMARK_PACK;
  4223. data[18] = QETH_HIGH_WATERMARK_PACK;
  4224. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4225. data[20] = (card->qdio.no_out_queues > 1) ?
  4226. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4227. data[21] = (card->qdio.no_out_queues > 2) ?
  4228. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4229. data[22] = (card->qdio.no_out_queues > 3) ?
  4230. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4231. data[23] = card->perf_stats.inbound_time;
  4232. data[24] = card->perf_stats.inbound_cnt;
  4233. data[25] = card->perf_stats.inbound_do_qdio_time;
  4234. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4235. data[27] = card->perf_stats.outbound_handler_time;
  4236. data[28] = card->perf_stats.outbound_handler_cnt;
  4237. data[29] = card->perf_stats.outbound_time;
  4238. data[30] = card->perf_stats.outbound_cnt;
  4239. data[31] = card->perf_stats.outbound_do_qdio_time;
  4240. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4241. data[33] = card->perf_stats.tx_csum;
  4242. data[34] = card->perf_stats.tx_lin;
  4243. }
  4244. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4245. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4246. {
  4247. switch (stringset) {
  4248. case ETH_SS_STATS:
  4249. memcpy(data, &qeth_ethtool_stats_keys,
  4250. sizeof(qeth_ethtool_stats_keys));
  4251. break;
  4252. default:
  4253. WARN_ON(1);
  4254. break;
  4255. }
  4256. }
  4257. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4258. void qeth_core_get_drvinfo(struct net_device *dev,
  4259. struct ethtool_drvinfo *info)
  4260. {
  4261. struct qeth_card *card = dev->ml_priv;
  4262. if (card->options.layer2)
  4263. strcpy(info->driver, "qeth_l2");
  4264. else
  4265. strcpy(info->driver, "qeth_l3");
  4266. strcpy(info->version, "1.0");
  4267. strcpy(info->fw_version, card->info.mcl_level);
  4268. sprintf(info->bus_info, "%s/%s/%s",
  4269. CARD_RDEV_ID(card),
  4270. CARD_WDEV_ID(card),
  4271. CARD_DDEV_ID(card));
  4272. }
  4273. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4274. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4275. struct ethtool_cmd *ecmd)
  4276. {
  4277. struct qeth_card *card = netdev->ml_priv;
  4278. enum qeth_link_types link_type;
  4279. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4280. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4281. else
  4282. link_type = card->info.link_type;
  4283. ecmd->transceiver = XCVR_INTERNAL;
  4284. ecmd->supported = SUPPORTED_Autoneg;
  4285. ecmd->advertising = ADVERTISED_Autoneg;
  4286. ecmd->duplex = DUPLEX_FULL;
  4287. ecmd->autoneg = AUTONEG_ENABLE;
  4288. switch (link_type) {
  4289. case QETH_LINK_TYPE_FAST_ETH:
  4290. case QETH_LINK_TYPE_LANE_ETH100:
  4291. ecmd->supported |= SUPPORTED_10baseT_Half |
  4292. SUPPORTED_10baseT_Full |
  4293. SUPPORTED_100baseT_Half |
  4294. SUPPORTED_100baseT_Full |
  4295. SUPPORTED_TP;
  4296. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4297. ADVERTISED_10baseT_Full |
  4298. ADVERTISED_100baseT_Half |
  4299. ADVERTISED_100baseT_Full |
  4300. ADVERTISED_TP;
  4301. ecmd->speed = SPEED_100;
  4302. ecmd->port = PORT_TP;
  4303. break;
  4304. case QETH_LINK_TYPE_GBIT_ETH:
  4305. case QETH_LINK_TYPE_LANE_ETH1000:
  4306. ecmd->supported |= SUPPORTED_10baseT_Half |
  4307. SUPPORTED_10baseT_Full |
  4308. SUPPORTED_100baseT_Half |
  4309. SUPPORTED_100baseT_Full |
  4310. SUPPORTED_1000baseT_Half |
  4311. SUPPORTED_1000baseT_Full |
  4312. SUPPORTED_FIBRE;
  4313. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4314. ADVERTISED_10baseT_Full |
  4315. ADVERTISED_100baseT_Half |
  4316. ADVERTISED_100baseT_Full |
  4317. ADVERTISED_1000baseT_Half |
  4318. ADVERTISED_1000baseT_Full |
  4319. ADVERTISED_FIBRE;
  4320. ecmd->speed = SPEED_1000;
  4321. ecmd->port = PORT_FIBRE;
  4322. break;
  4323. case QETH_LINK_TYPE_10GBIT_ETH:
  4324. ecmd->supported |= SUPPORTED_10baseT_Half |
  4325. SUPPORTED_10baseT_Full |
  4326. SUPPORTED_100baseT_Half |
  4327. SUPPORTED_100baseT_Full |
  4328. SUPPORTED_1000baseT_Half |
  4329. SUPPORTED_1000baseT_Full |
  4330. SUPPORTED_10000baseT_Full |
  4331. SUPPORTED_FIBRE;
  4332. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4333. ADVERTISED_10baseT_Full |
  4334. ADVERTISED_100baseT_Half |
  4335. ADVERTISED_100baseT_Full |
  4336. ADVERTISED_1000baseT_Half |
  4337. ADVERTISED_1000baseT_Full |
  4338. ADVERTISED_10000baseT_Full |
  4339. ADVERTISED_FIBRE;
  4340. ecmd->speed = SPEED_10000;
  4341. ecmd->port = PORT_FIBRE;
  4342. break;
  4343. default:
  4344. ecmd->supported |= SUPPORTED_10baseT_Half |
  4345. SUPPORTED_10baseT_Full |
  4346. SUPPORTED_TP;
  4347. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4348. ADVERTISED_10baseT_Full |
  4349. ADVERTISED_TP;
  4350. ecmd->speed = SPEED_10;
  4351. ecmd->port = PORT_TP;
  4352. }
  4353. return 0;
  4354. }
  4355. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4356. static int __init qeth_core_init(void)
  4357. {
  4358. int rc;
  4359. pr_info("loading core functions\n");
  4360. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4361. rwlock_init(&qeth_core_card_list.rwlock);
  4362. rc = qeth_register_dbf_views();
  4363. if (rc)
  4364. goto out_err;
  4365. rc = ccw_driver_register(&qeth_ccw_driver);
  4366. if (rc)
  4367. goto ccw_err;
  4368. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4369. if (rc)
  4370. goto ccwgroup_err;
  4371. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4372. &driver_attr_group);
  4373. if (rc)
  4374. goto driver_err;
  4375. qeth_core_root_dev = root_device_register("qeth");
  4376. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4377. if (rc)
  4378. goto register_err;
  4379. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4380. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4381. if (!qeth_core_header_cache) {
  4382. rc = -ENOMEM;
  4383. goto slab_err;
  4384. }
  4385. return 0;
  4386. slab_err:
  4387. root_device_unregister(qeth_core_root_dev);
  4388. register_err:
  4389. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4390. &driver_attr_group);
  4391. driver_err:
  4392. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4393. ccwgroup_err:
  4394. ccw_driver_unregister(&qeth_ccw_driver);
  4395. ccw_err:
  4396. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4397. qeth_unregister_dbf_views();
  4398. out_err:
  4399. pr_err("Initializing the qeth device driver failed\n");
  4400. return rc;
  4401. }
  4402. static void __exit qeth_core_exit(void)
  4403. {
  4404. root_device_unregister(qeth_core_root_dev);
  4405. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4406. &driver_attr_group);
  4407. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4408. ccw_driver_unregister(&qeth_ccw_driver);
  4409. kmem_cache_destroy(qeth_core_header_cache);
  4410. qeth_unregister_dbf_views();
  4411. pr_info("core functions removed\n");
  4412. }
  4413. module_init(qeth_core_init);
  4414. module_exit(qeth_core_exit);
  4415. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4416. MODULE_DESCRIPTION("qeth core functions");
  4417. MODULE_LICENSE("GPL");