dm.c 21 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../base.h"
  31. #include "reg.h"
  32. #include "def.h"
  33. #include "phy.h"
  34. #include "dm.h"
  35. #include "fw.h"
  36. struct dig_t digtable;
  37. static const u32 edca_setting_dl[PEER_MAX] = {
  38. 0xa44f, /* 0 UNKNOWN */
  39. 0x5ea44f, /* 1 REALTEK_90 */
  40. 0x5ea44f, /* 2 REALTEK_92SE */
  41. 0xa630, /* 3 BROAD */
  42. 0xa44f, /* 4 RAL */
  43. 0xa630, /* 5 ATH */
  44. 0xa630, /* 6 CISCO */
  45. 0xa42b, /* 7 MARV */
  46. };
  47. static const u32 edca_setting_dl_gmode[PEER_MAX] = {
  48. 0x4322, /* 0 UNKNOWN */
  49. 0xa44f, /* 1 REALTEK_90 */
  50. 0x5ea44f, /* 2 REALTEK_92SE */
  51. 0xa42b, /* 3 BROAD */
  52. 0x5e4322, /* 4 RAL */
  53. 0x4322, /* 5 ATH */
  54. 0xa430, /* 6 CISCO */
  55. 0x5ea44f, /* 7 MARV */
  56. };
  57. static const u32 edca_setting_ul[PEER_MAX] = {
  58. 0x5e4322, /* 0 UNKNOWN */
  59. 0xa44f, /* 1 REALTEK_90 */
  60. 0x5ea44f, /* 2 REALTEK_92SE */
  61. 0x5ea322, /* 3 BROAD */
  62. 0x5ea422, /* 4 RAL */
  63. 0x5ea322, /* 5 ATH */
  64. 0x3ea44f, /* 6 CISCO */
  65. 0x5ea44f, /* 7 MARV */
  66. };
  67. static void _rtl92s_dm_check_edca_turbo(struct ieee80211_hw *hw)
  68. {
  69. struct rtl_priv *rtlpriv = rtl_priv(hw);
  70. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  71. static u64 last_txok_cnt;
  72. static u64 last_rxok_cnt;
  73. u64 cur_txok_cnt = 0;
  74. u64 cur_rxok_cnt = 0;
  75. u32 edca_be_ul = edca_setting_ul[mac->vendor];
  76. u32 edca_be_dl = edca_setting_dl[mac->vendor];
  77. u32 edca_gmode = edca_setting_dl_gmode[mac->vendor];
  78. if (mac->link_state != MAC80211_LINKED) {
  79. rtlpriv->dm.current_turbo_edca = false;
  80. goto dm_checkedcaturbo_exit;
  81. }
  82. if ((!rtlpriv->dm.is_any_nonbepkts) &&
  83. (!rtlpriv->dm.disable_framebursting)) {
  84. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  85. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  86. if (rtlpriv->phy.rf_type == RF_1T2R) {
  87. if (cur_txok_cnt > 4 * cur_rxok_cnt) {
  88. /* Uplink TP is present. */
  89. if (rtlpriv->dm.is_cur_rdlstate ||
  90. !rtlpriv->dm.current_turbo_edca) {
  91. rtl_write_dword(rtlpriv, EDCAPARA_BE,
  92. edca_be_ul);
  93. rtlpriv->dm.is_cur_rdlstate = false;
  94. }
  95. } else {/* Balance TP is present. */
  96. if (!rtlpriv->dm.is_cur_rdlstate ||
  97. !rtlpriv->dm.current_turbo_edca) {
  98. if (mac->mode == WIRELESS_MODE_G ||
  99. mac->mode == WIRELESS_MODE_B)
  100. rtl_write_dword(rtlpriv,
  101. EDCAPARA_BE,
  102. edca_gmode);
  103. else
  104. rtl_write_dword(rtlpriv,
  105. EDCAPARA_BE,
  106. edca_be_dl);
  107. rtlpriv->dm.is_cur_rdlstate = true;
  108. }
  109. }
  110. rtlpriv->dm.current_turbo_edca = true;
  111. } else {
  112. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  113. if (!rtlpriv->dm.is_cur_rdlstate ||
  114. !rtlpriv->dm.current_turbo_edca) {
  115. if (mac->mode == WIRELESS_MODE_G ||
  116. mac->mode == WIRELESS_MODE_B)
  117. rtl_write_dword(rtlpriv,
  118. EDCAPARA_BE,
  119. edca_gmode);
  120. else
  121. rtl_write_dword(rtlpriv,
  122. EDCAPARA_BE,
  123. edca_be_dl);
  124. rtlpriv->dm.is_cur_rdlstate = true;
  125. }
  126. } else {
  127. if (rtlpriv->dm.is_cur_rdlstate ||
  128. !rtlpriv->dm.current_turbo_edca) {
  129. rtl_write_dword(rtlpriv, EDCAPARA_BE,
  130. edca_be_ul);
  131. rtlpriv->dm.is_cur_rdlstate = false;
  132. }
  133. }
  134. rtlpriv->dm.current_turbo_edca = true;
  135. }
  136. } else {
  137. if (rtlpriv->dm.current_turbo_edca) {
  138. u8 tmp = AC0_BE;
  139. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  140. (u8 *)(&tmp));
  141. rtlpriv->dm.current_turbo_edca = false;
  142. }
  143. }
  144. dm_checkedcaturbo_exit:
  145. rtlpriv->dm.is_any_nonbepkts = false;
  146. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  147. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  148. }
  149. static void _rtl92s_dm_txpowertracking_callback_thermalmeter(
  150. struct ieee80211_hw *hw)
  151. {
  152. struct rtl_priv *rtlpriv = rtl_priv(hw);
  153. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  154. u8 thermalvalue = 0;
  155. rtlpriv->dm.txpower_trackinginit = true;
  156. thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  157. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  158. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  159. "eeprom_thermalmeter 0x%x\n", thermalvalue,
  160. rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter));
  161. if (thermalvalue) {
  162. rtlpriv->dm.thermalvalue = thermalvalue;
  163. rtl92s_phy_set_fw_cmd(hw, FW_CMD_TXPWR_TRACK_THERMAL);
  164. }
  165. rtlpriv->dm.txpowercount = 0;
  166. }
  167. static void _rtl92s_dm_check_txpowertracking_thermalmeter(
  168. struct ieee80211_hw *hw)
  169. {
  170. struct rtl_priv *rtlpriv = rtl_priv(hw);
  171. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  172. static u8 tm_trigger;
  173. u8 tx_power_checkcnt = 5;
  174. /* 2T2R TP issue */
  175. if (rtlphy->rf_type == RF_2T2R)
  176. return;
  177. if (!rtlpriv->dm.txpower_tracking)
  178. return;
  179. if (rtlpriv->dm.txpowercount <= tx_power_checkcnt) {
  180. rtlpriv->dm.txpowercount++;
  181. return;
  182. }
  183. if (!tm_trigger) {
  184. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER,
  185. RFREG_OFFSET_MASK, 0x60);
  186. tm_trigger = 1;
  187. } else {
  188. _rtl92s_dm_txpowertracking_callback_thermalmeter(hw);
  189. tm_trigger = 0;
  190. }
  191. }
  192. static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
  193. {
  194. struct rtl_priv *rtlpriv = rtl_priv(hw);
  195. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  196. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  197. struct rate_adaptive *ra = &(rtlpriv->ra);
  198. u32 low_rssi_thresh = 0;
  199. u32 middle_rssi_thresh = 0;
  200. u32 high_rssi_thresh = 0;
  201. struct ieee80211_sta *sta = NULL;
  202. if (is_hal_stop(rtlhal))
  203. return;
  204. if (!rtlpriv->dm.useramask)
  205. return;
  206. if (!rtlpriv->dm.inform_fw_driverctrldm) {
  207. rtl92s_phy_set_fw_cmd(hw, FW_CMD_CTRL_DM_BY_DRIVER);
  208. rtlpriv->dm.inform_fw_driverctrldm = true;
  209. }
  210. rcu_read_lock();
  211. if (mac->opmode == NL80211_IFTYPE_STATION)
  212. sta = get_sta(hw, mac->vif, mac->bssid);
  213. if ((mac->link_state == MAC80211_LINKED) &&
  214. (mac->opmode == NL80211_IFTYPE_STATION)) {
  215. switch (ra->pre_ratr_state) {
  216. case DM_RATR_STA_HIGH:
  217. high_rssi_thresh = 40;
  218. middle_rssi_thresh = 30;
  219. low_rssi_thresh = 20;
  220. break;
  221. case DM_RATR_STA_MIDDLE:
  222. high_rssi_thresh = 44;
  223. middle_rssi_thresh = 30;
  224. low_rssi_thresh = 20;
  225. break;
  226. case DM_RATR_STA_LOW:
  227. high_rssi_thresh = 44;
  228. middle_rssi_thresh = 34;
  229. low_rssi_thresh = 20;
  230. break;
  231. case DM_RATR_STA_ULTRALOW:
  232. high_rssi_thresh = 44;
  233. middle_rssi_thresh = 34;
  234. low_rssi_thresh = 24;
  235. break;
  236. default:
  237. high_rssi_thresh = 44;
  238. middle_rssi_thresh = 34;
  239. low_rssi_thresh = 24;
  240. break;
  241. }
  242. if (rtlpriv->dm.undecorated_smoothed_pwdb >
  243. (long)high_rssi_thresh) {
  244. ra->ratr_state = DM_RATR_STA_HIGH;
  245. } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  246. (long)middle_rssi_thresh) {
  247. ra->ratr_state = DM_RATR_STA_LOW;
  248. } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  249. (long)low_rssi_thresh) {
  250. ra->ratr_state = DM_RATR_STA_LOW;
  251. } else {
  252. ra->ratr_state = DM_RATR_STA_ULTRALOW;
  253. }
  254. if (ra->pre_ratr_state != ra->ratr_state) {
  255. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, ("RSSI = %ld "
  256. "RSSI_LEVEL = %d PreState = %d, CurState = %d\n",
  257. rtlpriv->dm.undecorated_smoothed_pwdb,
  258. ra->ratr_state,
  259. ra->pre_ratr_state, ra->ratr_state));
  260. rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
  261. ra->ratr_state);
  262. ra->pre_ratr_state = ra->ratr_state;
  263. }
  264. }
  265. rcu_read_unlock();
  266. }
  267. static void _rtl92s_dm_switch_baseband_mrc(struct ieee80211_hw *hw)
  268. {
  269. struct rtl_priv *rtlpriv = rtl_priv(hw);
  270. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  271. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  272. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  273. bool current_mrc;
  274. bool enable_mrc = true;
  275. long tmpentry_maxpwdb = 0;
  276. u8 rssi_a = 0;
  277. u8 rssi_b = 0;
  278. if (is_hal_stop(rtlhal))
  279. return;
  280. if ((rtlphy->rf_type == RF_1T1R) || (rtlphy->rf_type == RF_2T2R))
  281. return;
  282. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_MRC, (u8 *)(&current_mrc));
  283. if (mac->link_state >= MAC80211_LINKED) {
  284. if (rtlpriv->dm.undecorated_smoothed_pwdb > tmpentry_maxpwdb) {
  285. rssi_a = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_A];
  286. rssi_b = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_B];
  287. }
  288. }
  289. /* MRC settings would NOT affect TP on Wireless B mode. */
  290. if (mac->mode != WIRELESS_MODE_B) {
  291. if ((rssi_a == 0) && (rssi_b == 0)) {
  292. enable_mrc = true;
  293. } else if (rssi_b > 30) {
  294. /* Turn on B-Path */
  295. enable_mrc = true;
  296. } else if (rssi_b < 5) {
  297. /* Turn off B-path */
  298. enable_mrc = false;
  299. /* Take care of RSSI differentiation. */
  300. } else if (rssi_a > 15 && (rssi_a >= rssi_b)) {
  301. if ((rssi_a - rssi_b) > 15)
  302. /* Turn off B-path */
  303. enable_mrc = false;
  304. else if ((rssi_a - rssi_b) < 10)
  305. /* Turn on B-Path */
  306. enable_mrc = true;
  307. else
  308. enable_mrc = current_mrc;
  309. } else {
  310. /* Turn on B-Path */
  311. enable_mrc = true;
  312. }
  313. }
  314. /* Update MRC settings if needed. */
  315. if (enable_mrc != current_mrc)
  316. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC,
  317. (u8 *)&enable_mrc);
  318. }
  319. void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw)
  320. {
  321. struct rtl_priv *rtlpriv = rtl_priv(hw);
  322. rtlpriv->dm.current_turbo_edca = false;
  323. rtlpriv->dm.is_any_nonbepkts = false;
  324. rtlpriv->dm.is_cur_rdlstate = false;
  325. }
  326. static void _rtl92s_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  327. {
  328. struct rtl_priv *rtlpriv = rtl_priv(hw);
  329. struct rate_adaptive *ra = &(rtlpriv->ra);
  330. ra->ratr_state = DM_RATR_STA_MAX;
  331. ra->pre_ratr_state = DM_RATR_STA_MAX;
  332. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  333. rtlpriv->dm.useramask = true;
  334. else
  335. rtlpriv->dm.useramask = false;
  336. rtlpriv->dm.useramask = false;
  337. rtlpriv->dm.inform_fw_driverctrldm = false;
  338. }
  339. static void _rtl92s_dm_init_txpowertracking_thermalmeter(
  340. struct ieee80211_hw *hw)
  341. {
  342. struct rtl_priv *rtlpriv = rtl_priv(hw);
  343. rtlpriv->dm.txpower_tracking = true;
  344. rtlpriv->dm.txpowercount = 0;
  345. rtlpriv->dm.txpower_trackinginit = false;
  346. }
  347. static void _rtl92s_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  348. {
  349. struct rtl_priv *rtlpriv = rtl_priv(hw);
  350. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  351. u32 ret_value;
  352. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  353. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  354. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  355. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  356. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  357. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  358. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  359. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  360. falsealm_cnt->cnt_rate_illegal + falsealm_cnt->cnt_crc8_fail +
  361. falsealm_cnt->cnt_mcs_fail;
  362. /* read CCK false alarm */
  363. ret_value = rtl_get_bbreg(hw, 0xc64, MASKDWORD);
  364. falsealm_cnt->cnt_cck_fail = (ret_value & 0xffff);
  365. falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail +
  366. falsealm_cnt->cnt_cck_fail;
  367. }
  368. static void rtl92s_backoff_enable_flag(struct ieee80211_hw *hw)
  369. {
  370. struct rtl_priv *rtlpriv = rtl_priv(hw);
  371. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  372. if (falsealm_cnt->cnt_all > digtable.fa_highthresh) {
  373. if ((digtable.backoff_val - 6) <
  374. digtable.backoffval_range_min)
  375. digtable.backoff_val = digtable.backoffval_range_min;
  376. else
  377. digtable.backoff_val -= 6;
  378. } else if (falsealm_cnt->cnt_all < digtable.fa_lowthresh) {
  379. if ((digtable.backoff_val + 6) >
  380. digtable.backoffval_range_max)
  381. digtable.backoff_val =
  382. digtable.backoffval_range_max;
  383. else
  384. digtable.backoff_val += 6;
  385. }
  386. }
  387. static void _rtl92s_dm_initial_gain_sta_beforeconnect(struct ieee80211_hw *hw)
  388. {
  389. struct rtl_priv *rtlpriv = rtl_priv(hw);
  390. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  391. static u8 initialized, force_write;
  392. u8 initial_gain = 0;
  393. if ((digtable.pre_sta_connectstate == digtable.cur_sta_connectstate) ||
  394. (digtable.cur_sta_connectstate == DIG_STA_BEFORE_CONNECT)) {
  395. if (digtable.cur_sta_connectstate == DIG_STA_BEFORE_CONNECT) {
  396. if (rtlpriv->psc.rfpwr_state != ERFON)
  397. return;
  398. if (digtable.backoff_enable_flag)
  399. rtl92s_backoff_enable_flag(hw);
  400. else
  401. digtable.backoff_val = DM_DIG_BACKOFF;
  402. if ((digtable.rssi_val + 10 - digtable.backoff_val) >
  403. digtable.rx_gain_range_max)
  404. digtable.cur_igvalue =
  405. digtable.rx_gain_range_max;
  406. else if ((digtable.rssi_val + 10 - digtable.backoff_val)
  407. < digtable.rx_gain_range_min)
  408. digtable.cur_igvalue =
  409. digtable.rx_gain_range_min;
  410. else
  411. digtable.cur_igvalue = digtable.rssi_val + 10 -
  412. digtable.backoff_val;
  413. if (falsealm_cnt->cnt_all > 10000)
  414. digtable.cur_igvalue =
  415. (digtable.cur_igvalue > 0x33) ?
  416. digtable.cur_igvalue : 0x33;
  417. if (falsealm_cnt->cnt_all > 16000)
  418. digtable.cur_igvalue =
  419. digtable.rx_gain_range_max;
  420. /* connected -> connected or disconnected -> disconnected */
  421. } else {
  422. /* Firmware control DIG, do nothing in driver dm */
  423. return;
  424. }
  425. /* disconnected -> connected or connected ->
  426. * disconnected or beforeconnect->(dis)connected */
  427. } else {
  428. /* Enable FW DIG */
  429. digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  430. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_ENABLE);
  431. digtable.backoff_val = DM_DIG_BACKOFF;
  432. digtable.cur_igvalue = rtlpriv->phy.default_initialgain[0];
  433. digtable.pre_igvalue = 0;
  434. return;
  435. }
  436. /* Forced writing to prevent from fw-dig overwriting. */
  437. if (digtable.pre_igvalue != rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1,
  438. MASKBYTE0))
  439. force_write = 1;
  440. if ((digtable.pre_igvalue != digtable.cur_igvalue) ||
  441. !initialized || force_write) {
  442. /* Disable FW DIG */
  443. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_DISABLE);
  444. initial_gain = (u8)digtable.cur_igvalue;
  445. /* Set initial gain. */
  446. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, initial_gain);
  447. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, initial_gain);
  448. digtable.pre_igvalue = digtable.cur_igvalue;
  449. initialized = 1;
  450. force_write = 0;
  451. }
  452. }
  453. static void _rtl92s_dm_ctrl_initgain_bytwoport(struct ieee80211_hw *hw)
  454. {
  455. struct rtl_priv *rtlpriv = rtl_priv(hw);
  456. if (rtlpriv->mac80211.act_scanning)
  457. return;
  458. /* Decide the current status and if modify initial gain or not */
  459. if (rtlpriv->mac80211.link_state >= MAC80211_LINKED ||
  460. rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
  461. digtable.cur_sta_connectstate = DIG_STA_CONNECT;
  462. else
  463. digtable.cur_sta_connectstate = DIG_STA_DISCONNECT;
  464. digtable.rssi_val = rtlpriv->dm.undecorated_smoothed_pwdb;
  465. /* Change dig mode to rssi */
  466. if (digtable.cur_sta_connectstate != DIG_STA_DISCONNECT) {
  467. if (digtable.dig_twoport_algorithm ==
  468. DIG_TWO_PORT_ALGO_FALSE_ALARM) {
  469. digtable.dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
  470. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_MODE_SS);
  471. }
  472. }
  473. _rtl92s_dm_false_alarm_counter_statistics(hw);
  474. _rtl92s_dm_initial_gain_sta_beforeconnect(hw);
  475. digtable.pre_sta_connectstate = digtable.cur_sta_connectstate;
  476. }
  477. static void _rtl92s_dm_ctrl_initgain_byrssi(struct ieee80211_hw *hw)
  478. {
  479. struct rtl_priv *rtlpriv = rtl_priv(hw);
  480. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  481. /* 2T2R TP issue */
  482. if (rtlphy->rf_type == RF_2T2R)
  483. return;
  484. if (!rtlpriv->dm.dm_initialgain_enable)
  485. return;
  486. if (digtable.dig_enable_flag == false)
  487. return;
  488. _rtl92s_dm_ctrl_initgain_bytwoport(hw);
  489. }
  490. static void _rtl92s_dm_dynamic_txpower(struct ieee80211_hw *hw)
  491. {
  492. struct rtl_priv *rtlpriv = rtl_priv(hw);
  493. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  494. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  495. long undecorated_smoothed_pwdb;
  496. long txpwr_threshold_lv1, txpwr_threshold_lv2;
  497. /* 2T2R TP issue */
  498. if (rtlphy->rf_type == RF_2T2R)
  499. return;
  500. if (!rtlpriv->dm.dynamic_txpower_enable ||
  501. rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  502. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  503. return;
  504. }
  505. if ((mac->link_state < MAC80211_LINKED) &&
  506. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  507. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  508. ("Not connected to any\n"));
  509. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  510. rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  511. return;
  512. }
  513. if (mac->link_state >= MAC80211_LINKED) {
  514. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  515. undecorated_smoothed_pwdb =
  516. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  517. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  518. ("AP Client PWDB = 0x%lx\n",
  519. undecorated_smoothed_pwdb));
  520. } else {
  521. undecorated_smoothed_pwdb =
  522. rtlpriv->dm.undecorated_smoothed_pwdb;
  523. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  524. ("STA Default Port PWDB = 0x%lx\n",
  525. undecorated_smoothed_pwdb));
  526. }
  527. } else {
  528. undecorated_smoothed_pwdb =
  529. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  530. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  531. ("AP Ext Port PWDB = 0x%lx\n",
  532. undecorated_smoothed_pwdb));
  533. }
  534. txpwr_threshold_lv2 = TX_POWER_NEAR_FIELD_THRESH_LVL2;
  535. txpwr_threshold_lv1 = TX_POWER_NEAR_FIELD_THRESH_LVL1;
  536. if (rtl_get_bbreg(hw, 0xc90, MASKBYTE0) == 1)
  537. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  538. else if (undecorated_smoothed_pwdb >= txpwr_threshold_lv2)
  539. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL2;
  540. else if ((undecorated_smoothed_pwdb < (txpwr_threshold_lv2 - 3)) &&
  541. (undecorated_smoothed_pwdb >= txpwr_threshold_lv1))
  542. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL1;
  543. else if (undecorated_smoothed_pwdb < (txpwr_threshold_lv1 - 3))
  544. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  545. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl))
  546. rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
  547. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  548. }
  549. static void _rtl92s_dm_init_dig(struct ieee80211_hw *hw)
  550. {
  551. struct rtl_priv *rtlpriv = rtl_priv(hw);
  552. /* Disable DIG scheme now.*/
  553. digtable.dig_enable_flag = true;
  554. digtable.backoff_enable_flag = true;
  555. if ((rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) &&
  556. (hal_get_firmwareversion(rtlpriv) >= 0x3c))
  557. digtable.dig_algorithm = DIG_ALGO_BY_TOW_PORT;
  558. else
  559. digtable.dig_algorithm =
  560. DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM;
  561. digtable.dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
  562. digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  563. /* off=by real rssi value, on=by digtable.rssi_val for new dig */
  564. digtable.dig_dbgmode = DM_DBG_OFF;
  565. digtable.dig_slgorithm_switch = 0;
  566. /* 2007/10/04 MH Define init gain threshol. */
  567. digtable.dig_state = DM_STA_DIG_MAX;
  568. digtable.dig_highpwrstate = DM_STA_DIG_MAX;
  569. digtable.cur_sta_connectstate = DIG_STA_DISCONNECT;
  570. digtable.pre_sta_connectstate = DIG_STA_DISCONNECT;
  571. digtable.cur_ap_connectstate = DIG_AP_DISCONNECT;
  572. digtable.pre_ap_connectstate = DIG_AP_DISCONNECT;
  573. digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
  574. digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
  575. digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  576. digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  577. digtable.rssi_highpower_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
  578. digtable.rssi_highpower_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
  579. /* for dig debug rssi value */
  580. digtable.rssi_val = 50;
  581. digtable.backoff_val = DM_DIG_BACKOFF;
  582. digtable.rx_gain_range_max = DM_DIG_MAX;
  583. digtable.rx_gain_range_min = DM_DIG_MIN;
  584. digtable.backoffval_range_max = DM_DIG_BACKOFF_MAX;
  585. digtable.backoffval_range_min = DM_DIG_BACKOFF_MIN;
  586. }
  587. static void _rtl92s_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  588. {
  589. struct rtl_priv *rtlpriv = rtl_priv(hw);
  590. if ((hal_get_firmwareversion(rtlpriv) >= 60) &&
  591. (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER))
  592. rtlpriv->dm.dynamic_txpower_enable = true;
  593. else
  594. rtlpriv->dm.dynamic_txpower_enable = false;
  595. rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  596. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  597. }
  598. void rtl92s_dm_init(struct ieee80211_hw *hw)
  599. {
  600. struct rtl_priv *rtlpriv = rtl_priv(hw);
  601. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  602. rtlpriv->dm.undecorated_smoothed_pwdb = -1;
  603. _rtl92s_dm_init_dynamic_txpower(hw);
  604. rtl92s_dm_init_edca_turbo(hw);
  605. _rtl92s_dm_init_rate_adaptive_mask(hw);
  606. _rtl92s_dm_init_txpowertracking_thermalmeter(hw);
  607. _rtl92s_dm_init_dig(hw);
  608. rtl_write_dword(rtlpriv, WFM5, FW_CCA_CHK_ENABLE);
  609. }
  610. void rtl92s_dm_watchdog(struct ieee80211_hw *hw)
  611. {
  612. _rtl92s_dm_check_edca_turbo(hw);
  613. _rtl92s_dm_check_txpowertracking_thermalmeter(hw);
  614. _rtl92s_dm_ctrl_initgain_byrssi(hw);
  615. _rtl92s_dm_dynamic_txpower(hw);
  616. _rtl92s_dm_refresh_rateadaptive_mask(hw);
  617. _rtl92s_dm_switch_baseband_mrc(hw);
  618. }