fw.c 25 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../pci.h"
  31. #include "../base.h"
  32. #include "reg.h"
  33. #include "def.h"
  34. #include "fw.h"
  35. #include "sw.h"
  36. static bool _rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv)
  37. {
  38. return (rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) ?
  39. true : false;
  40. }
  41. static void _rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable)
  42. {
  43. struct rtl_priv *rtlpriv = rtl_priv(hw);
  44. u8 tmp;
  45. if (enable) {
  46. tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  47. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
  48. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  49. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
  50. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
  51. rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
  52. } else {
  53. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  54. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
  55. /* Reserved for fw extension.
  56. * 0x81[7] is used for mac0 status ,
  57. * so don't write this reg here
  58. * rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);*/
  59. }
  60. }
  61. static void _rtl92d_fw_block_write(struct ieee80211_hw *hw,
  62. const u8 *buffer, u32 size)
  63. {
  64. struct rtl_priv *rtlpriv = rtl_priv(hw);
  65. u32 blocksize = sizeof(u32);
  66. u8 *bufferptr = (u8 *) buffer;
  67. u32 *pu4BytePtr = (u32 *) buffer;
  68. u32 i, offset, blockCount, remainSize;
  69. blockCount = size / blocksize;
  70. remainSize = size % blocksize;
  71. for (i = 0; i < blockCount; i++) {
  72. offset = i * blocksize;
  73. rtl_write_dword(rtlpriv, (FW_8192D_START_ADDRESS + offset),
  74. *(pu4BytePtr + i));
  75. }
  76. if (remainSize) {
  77. offset = blockCount * blocksize;
  78. bufferptr += offset;
  79. for (i = 0; i < remainSize; i++) {
  80. rtl_write_byte(rtlpriv, (FW_8192D_START_ADDRESS +
  81. offset + i), *(bufferptr + i));
  82. }
  83. }
  84. }
  85. static void _rtl92d_fw_page_write(struct ieee80211_hw *hw,
  86. u32 page, const u8 *buffer, u32 size)
  87. {
  88. struct rtl_priv *rtlpriv = rtl_priv(hw);
  89. u8 value8;
  90. u8 u8page = (u8) (page & 0x07);
  91. value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
  92. rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
  93. _rtl92d_fw_block_write(hw, buffer, size);
  94. }
  95. static void _rtl92d_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
  96. {
  97. u32 fwlen = *pfwlen;
  98. u8 remain = (u8) (fwlen % 4);
  99. remain = (remain == 0) ? 0 : (4 - remain);
  100. while (remain > 0) {
  101. pfwbuf[fwlen] = 0;
  102. fwlen++;
  103. remain--;
  104. }
  105. *pfwlen = fwlen;
  106. }
  107. static void _rtl92d_write_fw(struct ieee80211_hw *hw,
  108. enum version_8192d version, u8 *buffer, u32 size)
  109. {
  110. struct rtl_priv *rtlpriv = rtl_priv(hw);
  111. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  112. u8 *bufferPtr = (u8 *) buffer;
  113. u32 pagenums, remainSize;
  114. u32 page, offset;
  115. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, ("FW size is %d bytes,\n", size));
  116. if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
  117. _rtl92d_fill_dummy(bufferPtr, &size);
  118. pagenums = size / FW_8192D_PAGE_SIZE;
  119. remainSize = size % FW_8192D_PAGE_SIZE;
  120. if (pagenums > 8) {
  121. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  122. ("Page numbers should not greater then 8\n"));
  123. }
  124. for (page = 0; page < pagenums; page++) {
  125. offset = page * FW_8192D_PAGE_SIZE;
  126. _rtl92d_fw_page_write(hw, page, (bufferPtr + offset),
  127. FW_8192D_PAGE_SIZE);
  128. }
  129. if (remainSize) {
  130. offset = pagenums * FW_8192D_PAGE_SIZE;
  131. page = pagenums;
  132. _rtl92d_fw_page_write(hw, page, (bufferPtr + offset),
  133. remainSize);
  134. }
  135. }
  136. static int _rtl92d_fw_free_to_go(struct ieee80211_hw *hw)
  137. {
  138. struct rtl_priv *rtlpriv = rtl_priv(hw);
  139. u32 counter = 0;
  140. u32 value32;
  141. do {
  142. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  143. } while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) &&
  144. (!(value32 & FWDL_ChkSum_rpt)));
  145. if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) {
  146. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  147. ("chksum report faill ! REG_MCUFWDL:0x%08x .\n",
  148. value32));
  149. return -EIO;
  150. }
  151. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  152. ("Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32));
  153. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  154. value32 |= MCUFWDL_RDY;
  155. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  156. return 0;
  157. }
  158. void rtl92d_firmware_selfreset(struct ieee80211_hw *hw)
  159. {
  160. struct rtl_priv *rtlpriv = rtl_priv(hw);
  161. u8 u1b_tmp;
  162. u8 delay = 100;
  163. /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */
  164. rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
  165. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  166. while (u1b_tmp & BIT(2)) {
  167. delay--;
  168. if (delay == 0)
  169. break;
  170. udelay(50);
  171. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  172. }
  173. RT_ASSERT((delay > 0), ("8051 reset failed!\n"));
  174. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  175. ("=====> 8051 reset success (%d) .\n", delay));
  176. }
  177. static int _rtl92d_fw_init(struct ieee80211_hw *hw)
  178. {
  179. struct rtl_priv *rtlpriv = rtl_priv(hw);
  180. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  181. u32 counter;
  182. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG, ("FW already have download\n"));
  183. /* polling for FW ready */
  184. counter = 0;
  185. do {
  186. if (rtlhal->interfaceindex == 0) {
  187. if (rtl_read_byte(rtlpriv, FW_MAC0_READY) &
  188. MAC0_READY) {
  189. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  190. ("Polling FW ready success!! "
  191. "REG_MCUFWDL: 0x%x .\n",
  192. rtl_read_byte(rtlpriv,
  193. FW_MAC0_READY)));
  194. return 0;
  195. }
  196. udelay(5);
  197. } else {
  198. if (rtl_read_byte(rtlpriv, FW_MAC1_READY) &
  199. MAC1_READY) {
  200. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  201. ("Polling FW ready success!! "
  202. "REG_MCUFWDL: 0x%x .\n",
  203. rtl_read_byte(rtlpriv,
  204. FW_MAC1_READY)));
  205. return 0;
  206. }
  207. udelay(5);
  208. }
  209. } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
  210. if (rtlhal->interfaceindex == 0) {
  211. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  212. ("Polling FW ready fail!! MAC0 FW init not ready: "
  213. "0x%x .\n",
  214. rtl_read_byte(rtlpriv, FW_MAC0_READY)));
  215. } else {
  216. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  217. ("Polling FW ready fail!! MAC1 FW init not ready: "
  218. "0x%x .\n",
  219. rtl_read_byte(rtlpriv, FW_MAC1_READY)));
  220. }
  221. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  222. ("Polling FW ready fail!! REG_MCUFWDL:0x%08ul .\n",
  223. rtl_read_dword(rtlpriv, REG_MCUFWDL)));
  224. return -1;
  225. }
  226. int rtl92d_download_fw(struct ieee80211_hw *hw)
  227. {
  228. struct rtl_priv *rtlpriv = rtl_priv(hw);
  229. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  230. u8 *pfwheader;
  231. u8 *pfwdata;
  232. u32 fwsize;
  233. int err;
  234. enum version_8192d version = rtlhal->version;
  235. u8 value;
  236. u32 count;
  237. bool fw_downloaded = false, fwdl_in_process = false;
  238. unsigned long flags;
  239. if (!rtlhal->pfirmware)
  240. return 1;
  241. fwsize = rtlhal->fwsize;
  242. pfwheader = (u8 *) rtlhal->pfirmware;
  243. pfwdata = (u8 *) rtlhal->pfirmware;
  244. rtlhal->fw_version = (u16) GET_FIRMWARE_HDR_VERSION(pfwheader);
  245. rtlhal->fw_subversion = (u16) GET_FIRMWARE_HDR_SUB_VER(pfwheader);
  246. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, (" FirmwareVersion(%d),"
  247. "FirmwareSubVersion(%d), Signature(%#x)\n",
  248. rtlhal->fw_version, rtlhal->fw_subversion,
  249. GET_FIRMWARE_HDR_SIGNATURE(pfwheader)));
  250. if (IS_FW_HEADER_EXIST(pfwheader)) {
  251. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  252. ("Shift 32 bytes for FW header!!\n"));
  253. pfwdata = pfwdata + 32;
  254. fwsize = fwsize - 32;
  255. }
  256. spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
  257. fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv);
  258. if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5))
  259. fwdl_in_process = true;
  260. else
  261. fwdl_in_process = false;
  262. if (fw_downloaded) {
  263. spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
  264. goto exit;
  265. } else if (fwdl_in_process) {
  266. spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
  267. for (count = 0; count < 5000; count++) {
  268. udelay(500);
  269. spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
  270. fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv);
  271. if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5))
  272. fwdl_in_process = true;
  273. else
  274. fwdl_in_process = false;
  275. spin_unlock_irqrestore(&globalmutex_for_fwdownload,
  276. flags);
  277. if (fw_downloaded)
  278. goto exit;
  279. else if (!fwdl_in_process)
  280. break;
  281. else
  282. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  283. ("Wait for another mac "
  284. "download fw\n"));
  285. }
  286. spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
  287. value = rtl_read_byte(rtlpriv, 0x1f);
  288. value |= BIT(5);
  289. rtl_write_byte(rtlpriv, 0x1f, value);
  290. spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
  291. } else {
  292. value = rtl_read_byte(rtlpriv, 0x1f);
  293. value |= BIT(5);
  294. rtl_write_byte(rtlpriv, 0x1f, value);
  295. spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
  296. }
  297. /* If 8051 is running in RAM code, driver should
  298. * inform Fw to reset by itself, or it will cause
  299. * download Fw fail.*/
  300. /* 8051 RAM code */
  301. if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
  302. rtl92d_firmware_selfreset(hw);
  303. rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
  304. }
  305. _rtl92d_enable_fw_download(hw, true);
  306. _rtl92d_write_fw(hw, version, pfwdata, fwsize);
  307. _rtl92d_enable_fw_download(hw, false);
  308. spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
  309. err = _rtl92d_fw_free_to_go(hw);
  310. /* download fw over,clear 0x1f[5] */
  311. value = rtl_read_byte(rtlpriv, 0x1f);
  312. value &= (~BIT(5));
  313. rtl_write_byte(rtlpriv, 0x1f, value);
  314. spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
  315. if (err) {
  316. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  317. ("fw is not ready to run!\n"));
  318. goto exit;
  319. } else {
  320. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  321. ("fw is ready to run!\n"));
  322. }
  323. exit:
  324. err = _rtl92d_fw_init(hw);
  325. return err;
  326. }
  327. static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
  328. {
  329. struct rtl_priv *rtlpriv = rtl_priv(hw);
  330. u8 val_hmetfr;
  331. bool result = false;
  332. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  333. if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
  334. result = true;
  335. return result;
  336. }
  337. static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw,
  338. u8 element_id, u32 cmd_len, u8 *cmdbuffer)
  339. {
  340. struct rtl_priv *rtlpriv = rtl_priv(hw);
  341. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  342. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  343. u8 boxnum;
  344. u16 box_reg = 0, box_extreg = 0;
  345. u8 u1b_tmp;
  346. bool isfw_read = false;
  347. u8 buf_index = 0;
  348. bool bwrite_sucess = false;
  349. u8 wait_h2c_limmit = 100;
  350. u8 wait_writeh2c_limmit = 100;
  351. u8 boxcontent[4], boxextcontent[2];
  352. u32 h2c_waitcounter = 0;
  353. unsigned long flag;
  354. u8 idx;
  355. if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) {
  356. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  357. ("Return as RF is off!!!\n"));
  358. return;
  359. }
  360. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("come in\n"));
  361. while (true) {
  362. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  363. if (rtlhal->h2c_setinprogress) {
  364. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  365. ("H2C set in progress! Wait to set.."
  366. "element_id(%d).\n", element_id));
  367. while (rtlhal->h2c_setinprogress) {
  368. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  369. flag);
  370. h2c_waitcounter++;
  371. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  372. ("Wait 100 us (%d times)...\n",
  373. h2c_waitcounter));
  374. udelay(100);
  375. if (h2c_waitcounter > 1000)
  376. return;
  377. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  378. flag);
  379. }
  380. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  381. } else {
  382. rtlhal->h2c_setinprogress = true;
  383. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  384. break;
  385. }
  386. }
  387. while (!bwrite_sucess) {
  388. wait_writeh2c_limmit--;
  389. if (wait_writeh2c_limmit == 0) {
  390. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  391. ("Write H2C fail because no trigger "
  392. "for FW INT!\n"));
  393. break;
  394. }
  395. boxnum = rtlhal->last_hmeboxnum;
  396. switch (boxnum) {
  397. case 0:
  398. box_reg = REG_HMEBOX_0;
  399. box_extreg = REG_HMEBOX_EXT_0;
  400. break;
  401. case 1:
  402. box_reg = REG_HMEBOX_1;
  403. box_extreg = REG_HMEBOX_EXT_1;
  404. break;
  405. case 2:
  406. box_reg = REG_HMEBOX_2;
  407. box_extreg = REG_HMEBOX_EXT_2;
  408. break;
  409. case 3:
  410. box_reg = REG_HMEBOX_3;
  411. box_extreg = REG_HMEBOX_EXT_3;
  412. break;
  413. default:
  414. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  415. ("switch case not process\n"));
  416. break;
  417. }
  418. isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
  419. while (!isfw_read) {
  420. wait_h2c_limmit--;
  421. if (wait_h2c_limmit == 0) {
  422. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  423. ("Wating too long for FW read "
  424. "clear HMEBox(%d)!\n", boxnum));
  425. break;
  426. }
  427. udelay(10);
  428. isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
  429. u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
  430. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  431. ("Wating for FW read clear HMEBox(%d)!!! "
  432. "0x1BF = %2x\n", boxnum, u1b_tmp));
  433. }
  434. if (!isfw_read) {
  435. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  436. ("Write H2C register BOX[%d] fail!!!!! "
  437. "Fw do not read.\n", boxnum));
  438. break;
  439. }
  440. memset(boxcontent, 0, sizeof(boxcontent));
  441. memset(boxextcontent, 0, sizeof(boxextcontent));
  442. boxcontent[0] = element_id;
  443. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  444. ("Write element_id box_reg(%4x) = %2x\n",
  445. box_reg, element_id));
  446. switch (cmd_len) {
  447. case 1:
  448. boxcontent[0] &= ~(BIT(7));
  449. memcpy(boxcontent + 1, cmdbuffer + buf_index, 1);
  450. for (idx = 0; idx < 4; idx++)
  451. rtl_write_byte(rtlpriv, box_reg + idx,
  452. boxcontent[idx]);
  453. break;
  454. case 2:
  455. boxcontent[0] &= ~(BIT(7));
  456. memcpy(boxcontent + 1, cmdbuffer + buf_index, 2);
  457. for (idx = 0; idx < 4; idx++)
  458. rtl_write_byte(rtlpriv, box_reg + idx,
  459. boxcontent[idx]);
  460. break;
  461. case 3:
  462. boxcontent[0] &= ~(BIT(7));
  463. memcpy(boxcontent + 1, cmdbuffer + buf_index, 3);
  464. for (idx = 0; idx < 4; idx++)
  465. rtl_write_byte(rtlpriv, box_reg + idx,
  466. boxcontent[idx]);
  467. break;
  468. case 4:
  469. boxcontent[0] |= (BIT(7));
  470. memcpy(boxextcontent, cmdbuffer + buf_index, 2);
  471. memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 2);
  472. for (idx = 0; idx < 2; idx++)
  473. rtl_write_byte(rtlpriv, box_extreg + idx,
  474. boxextcontent[idx]);
  475. for (idx = 0; idx < 4; idx++)
  476. rtl_write_byte(rtlpriv, box_reg + idx,
  477. boxcontent[idx]);
  478. break;
  479. case 5:
  480. boxcontent[0] |= (BIT(7));
  481. memcpy(boxextcontent, cmdbuffer + buf_index, 2);
  482. memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 3);
  483. for (idx = 0; idx < 2; idx++)
  484. rtl_write_byte(rtlpriv, box_extreg + idx,
  485. boxextcontent[idx]);
  486. for (idx = 0; idx < 4; idx++)
  487. rtl_write_byte(rtlpriv, box_reg + idx,
  488. boxcontent[idx]);
  489. break;
  490. default:
  491. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  492. ("switch case not process\n"));
  493. break;
  494. }
  495. bwrite_sucess = true;
  496. rtlhal->last_hmeboxnum = boxnum + 1;
  497. if (rtlhal->last_hmeboxnum == 4)
  498. rtlhal->last_hmeboxnum = 0;
  499. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  500. ("pHalData->last_hmeboxnum = %d\n",
  501. rtlhal->last_hmeboxnum));
  502. }
  503. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  504. rtlhal->h2c_setinprogress = false;
  505. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  506. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("go out\n"));
  507. }
  508. void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw,
  509. u8 element_id, u32 cmd_len, u8 *cmdbuffer)
  510. {
  511. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  512. u32 tmp_cmdbuf[2];
  513. if (rtlhal->fw_ready == false) {
  514. RT_ASSERT(false, ("return H2C cmd because of Fw "
  515. "download fail!!!\n"));
  516. return;
  517. }
  518. memset(tmp_cmdbuf, 0, 8);
  519. memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
  520. _rtl92d_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
  521. return;
  522. }
  523. void rtl92d_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  524. {
  525. struct rtl_priv *rtlpriv = rtl_priv(hw);
  526. u8 u1_h2c_set_pwrmode[3] = { 0 };
  527. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  528. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("FW LPS mode = %d\n", mode));
  529. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
  530. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, 1);
  531. SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
  532. ppsc->reg_max_lps_awakeintvl);
  533. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  534. "rtl92d_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
  535. u1_h2c_set_pwrmode, 3);
  536. rtl92d_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
  537. }
  538. static bool _rtl92d_cmd_send_packet(struct ieee80211_hw *hw,
  539. struct sk_buff *skb)
  540. {
  541. struct rtl_priv *rtlpriv = rtl_priv(hw);
  542. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  543. struct rtl8192_tx_ring *ring;
  544. struct rtl_tx_desc *pdesc;
  545. u8 idx = 0;
  546. unsigned long flags;
  547. struct sk_buff *pskb;
  548. ring = &rtlpci->tx_ring[BEACON_QUEUE];
  549. pskb = __skb_dequeue(&ring->queue);
  550. if (pskb)
  551. kfree_skb(pskb);
  552. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  553. pdesc = &ring->desc[idx];
  554. /* discard output from call below */
  555. rtlpriv->cfg->ops->get_desc((u8 *) pdesc, true, HW_DESC_OWN);
  556. rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
  557. __skb_queue_tail(&ring->queue, skb);
  558. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  559. rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
  560. return true;
  561. }
  562. #define BEACON_PG 0 /*->1 */
  563. #define PSPOLL_PG 2
  564. #define NULL_PG 3
  565. #define PROBERSP_PG 4 /*->5 */
  566. #define TOTAL_RESERVED_PKT_LEN 768
  567. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  568. /* page 0 beacon */
  569. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  570. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  571. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
  572. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  573. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  574. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  575. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  576. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  577. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  578. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  579. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  580. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  581. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  582. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  583. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  584. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  585. /* page 1 beacon */
  586. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  587. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  588. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  589. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  590. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  591. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  592. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  593. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  594. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  595. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  596. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  597. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  598. 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
  599. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  600. 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  601. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  602. /* page 2 ps-poll */
  603. 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
  604. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  605. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  606. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  607. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  608. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  609. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  610. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  611. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  612. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  613. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  614. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  615. 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  616. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  617. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  618. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  619. /* page 3 null */
  620. 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  621. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  622. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  623. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  624. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  625. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  626. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  627. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  628. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  629. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  630. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  631. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  632. 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  633. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  634. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  635. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  636. /* page 4 probe_resp */
  637. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  638. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  639. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  640. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  641. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  642. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  643. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  644. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  645. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  646. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  647. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  648. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  649. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  650. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  651. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  652. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  653. /* page 5 probe_resp */
  654. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  655. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  656. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  657. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  658. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  659. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  660. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  661. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  662. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  663. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  664. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  665. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  666. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  667. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  668. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  669. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  670. };
  671. void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished)
  672. {
  673. struct rtl_priv *rtlpriv = rtl_priv(hw);
  674. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  675. struct sk_buff *skb = NULL;
  676. u32 totalpacketlen;
  677. bool rtstatus;
  678. u8 u1RsvdPageLoc[3] = { 0 };
  679. bool dlok = false;
  680. u8 *beacon;
  681. u8 *p_pspoll;
  682. u8 *nullfunc;
  683. u8 *p_probersp;
  684. /*---------------------------------------------------------
  685. (1) beacon
  686. ---------------------------------------------------------*/
  687. beacon = &reserved_page_packet[BEACON_PG * 128];
  688. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  689. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  690. /*-------------------------------------------------------
  691. (2) ps-poll
  692. --------------------------------------------------------*/
  693. p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  694. SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
  695. SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
  696. SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
  697. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
  698. /*--------------------------------------------------------
  699. (3) null data
  700. ---------------------------------------------------------*/
  701. nullfunc = &reserved_page_packet[NULL_PG * 128];
  702. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  703. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  704. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  705. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
  706. /*---------------------------------------------------------
  707. (4) probe response
  708. ----------------------------------------------------------*/
  709. p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
  710. SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
  711. SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
  712. SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
  713. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
  714. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  715. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  716. "rtl92d_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  717. &reserved_page_packet[0], totalpacketlen);
  718. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  719. "rtl92d_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  720. u1RsvdPageLoc, 3);
  721. skb = dev_alloc_skb(totalpacketlen);
  722. memcpy((u8 *) skb_put(skb, totalpacketlen), &reserved_page_packet,
  723. totalpacketlen);
  724. rtstatus = _rtl92d_cmd_send_packet(hw, skb);
  725. if (rtstatus)
  726. dlok = true;
  727. if (dlok) {
  728. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  729. ("Set RSVD page location to Fw.\n"));
  730. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  731. "H2C_RSVDPAGE:\n", u1RsvdPageLoc, 3);
  732. rtl92d_fill_h2c_cmd(hw, H2C_RSVDPAGE,
  733. sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
  734. } else
  735. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  736. ("Set RSVD page location to Fw FAIL!!!!!!.\n"));
  737. }
  738. void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
  739. {
  740. u8 u1_joinbssrpt_parm[1] = {0};
  741. SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
  742. rtl92d_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
  743. }