phy.c 18 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../pci.h"
  31. #include "../ps.h"
  32. #include "reg.h"
  33. #include "def.h"
  34. #include "hw.h"
  35. #include "phy.h"
  36. #include "rf.h"
  37. #include "dm.h"
  38. #include "table.h"
  39. static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
  40. u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
  41. enum radio_path rfpath, u32 regaddr, u32 bitmask)
  42. {
  43. struct rtl_priv *rtlpriv = rtl_priv(hw);
  44. u32 original_value, readback_value, bitshift;
  45. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  46. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
  47. "rfpath(%#x), bitmask(%#x)\n",
  48. regaddr, rfpath, bitmask));
  49. spin_lock(&rtlpriv->locks.rf_lock);
  50. if (rtlphy->rf_mode != RF_OP_BY_FW) {
  51. original_value = _rtl92c_phy_rf_serial_read(hw,
  52. rfpath, regaddr);
  53. } else {
  54. original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  55. rfpath, regaddr);
  56. }
  57. bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  58. readback_value = (original_value & bitmask) >> bitshift;
  59. spin_unlock(&rtlpriv->locks.rf_lock);
  60. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  61. ("regaddr(%#x), rfpath(%#x), "
  62. "bitmask(%#x), original_value(%#x)\n",
  63. regaddr, rfpath, bitmask, original_value));
  64. return readback_value;
  65. }
  66. bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
  67. {
  68. struct rtl_priv *rtlpriv = rtl_priv(hw);
  69. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  70. bool is92c = IS_92C_SERIAL(rtlhal->version);
  71. bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
  72. if (is92c)
  73. rtl_write_byte(rtlpriv, 0x14, 0x71);
  74. return rtstatus;
  75. }
  76. bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
  77. {
  78. bool rtstatus = true;
  79. struct rtl_priv *rtlpriv = rtl_priv(hw);
  80. u16 regval;
  81. u32 regvaldw;
  82. u8 reg_hwparafile = 1;
  83. _rtl92c_phy_init_bb_rf_register_definition(hw);
  84. regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
  85. rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
  86. regval | BIT(13) | BIT(0) | BIT(1));
  87. rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
  88. rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
  89. rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
  90. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
  91. FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
  92. FEN_BB_GLB_RSTn | FEN_BBRSTB);
  93. rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
  94. regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
  95. rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
  96. if (reg_hwparafile == 1)
  97. rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
  98. return rtstatus;
  99. }
  100. void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
  101. enum radio_path rfpath,
  102. u32 regaddr, u32 bitmask, u32 data)
  103. {
  104. struct rtl_priv *rtlpriv = rtl_priv(hw);
  105. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  106. u32 original_value, bitshift;
  107. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  108. ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
  109. regaddr, bitmask, data, rfpath));
  110. spin_lock(&rtlpriv->locks.rf_lock);
  111. if (rtlphy->rf_mode != RF_OP_BY_FW) {
  112. if (bitmask != RFREG_OFFSET_MASK) {
  113. original_value = _rtl92c_phy_rf_serial_read(hw,
  114. rfpath,
  115. regaddr);
  116. bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  117. data =
  118. ((original_value & (~bitmask)) |
  119. (data << bitshift));
  120. }
  121. _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
  122. } else {
  123. if (bitmask != RFREG_OFFSET_MASK) {
  124. original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  125. rfpath,
  126. regaddr);
  127. bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  128. data =
  129. ((original_value & (~bitmask)) |
  130. (data << bitshift));
  131. }
  132. _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
  133. }
  134. spin_unlock(&rtlpriv->locks.rf_lock);
  135. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
  136. "bitmask(%#x), data(%#x), "
  137. "rfpath(%#x)\n", regaddr,
  138. bitmask, data, rfpath));
  139. }
  140. static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
  141. {
  142. struct rtl_priv *rtlpriv = rtl_priv(hw);
  143. u32 i;
  144. u32 arraylength;
  145. u32 *ptrarray;
  146. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
  147. arraylength = MAC_2T_ARRAYLENGTH;
  148. ptrarray = RTL8192CEMAC_2T_ARRAY;
  149. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  150. ("Img:RTL8192CEMAC_2T_ARRAY\n"));
  151. for (i = 0; i < arraylength; i = i + 2)
  152. rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
  153. return true;
  154. }
  155. bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
  156. u8 configtype)
  157. {
  158. int i;
  159. u32 *phy_regarray_table;
  160. u32 *agctab_array_table;
  161. u16 phy_reg_arraylen, agctab_arraylen;
  162. struct rtl_priv *rtlpriv = rtl_priv(hw);
  163. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  164. if (IS_92C_SERIAL(rtlhal->version)) {
  165. agctab_arraylen = AGCTAB_2TARRAYLENGTH;
  166. agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
  167. phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
  168. phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
  169. } else {
  170. agctab_arraylen = AGCTAB_1TARRAYLENGTH;
  171. agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
  172. phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
  173. phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
  174. }
  175. if (configtype == BASEBAND_CONFIG_PHY_REG) {
  176. for (i = 0; i < phy_reg_arraylen; i = i + 2) {
  177. if (phy_regarray_table[i] == 0xfe)
  178. mdelay(50);
  179. else if (phy_regarray_table[i] == 0xfd)
  180. mdelay(5);
  181. else if (phy_regarray_table[i] == 0xfc)
  182. mdelay(1);
  183. else if (phy_regarray_table[i] == 0xfb)
  184. udelay(50);
  185. else if (phy_regarray_table[i] == 0xfa)
  186. udelay(5);
  187. else if (phy_regarray_table[i] == 0xf9)
  188. udelay(1);
  189. rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
  190. phy_regarray_table[i + 1]);
  191. udelay(1);
  192. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  193. ("The phy_regarray_table[0] is %x"
  194. " Rtl819XPHY_REGArray[1] is %x\n",
  195. phy_regarray_table[i],
  196. phy_regarray_table[i + 1]));
  197. }
  198. } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
  199. for (i = 0; i < agctab_arraylen; i = i + 2) {
  200. rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
  201. agctab_array_table[i + 1]);
  202. udelay(1);
  203. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  204. ("The agctab_array_table[0] is "
  205. "%x Rtl819XPHY_REGArray[1] is %x\n",
  206. agctab_array_table[i],
  207. agctab_array_table[i + 1]));
  208. }
  209. }
  210. return true;
  211. }
  212. bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
  213. u8 configtype)
  214. {
  215. struct rtl_priv *rtlpriv = rtl_priv(hw);
  216. int i;
  217. u32 *phy_regarray_table_pg;
  218. u16 phy_regarray_pg_len;
  219. phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
  220. phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
  221. if (configtype == BASEBAND_CONFIG_PHY_REG) {
  222. for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
  223. if (phy_regarray_table_pg[i] == 0xfe)
  224. mdelay(50);
  225. else if (phy_regarray_table_pg[i] == 0xfd)
  226. mdelay(5);
  227. else if (phy_regarray_table_pg[i] == 0xfc)
  228. mdelay(1);
  229. else if (phy_regarray_table_pg[i] == 0xfb)
  230. udelay(50);
  231. else if (phy_regarray_table_pg[i] == 0xfa)
  232. udelay(5);
  233. else if (phy_regarray_table_pg[i] == 0xf9)
  234. udelay(1);
  235. _rtl92c_store_pwrIndex_diffrate_offset(hw,
  236. phy_regarray_table_pg[i],
  237. phy_regarray_table_pg[i + 1],
  238. phy_regarray_table_pg[i + 2]);
  239. }
  240. } else {
  241. RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
  242. ("configtype != BaseBand_Config_PHY_REG\n"));
  243. }
  244. return true;
  245. }
  246. bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
  247. enum radio_path rfpath)
  248. {
  249. int i;
  250. u32 *radioa_array_table;
  251. u32 *radiob_array_table;
  252. u16 radioa_arraylen, radiob_arraylen;
  253. struct rtl_priv *rtlpriv = rtl_priv(hw);
  254. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  255. if (IS_92C_SERIAL(rtlhal->version)) {
  256. radioa_arraylen = RADIOA_2TARRAYLENGTH;
  257. radioa_array_table = RTL8192CERADIOA_2TARRAY;
  258. radiob_arraylen = RADIOB_2TARRAYLENGTH;
  259. radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
  260. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  261. ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
  262. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  263. ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
  264. } else {
  265. radioa_arraylen = RADIOA_1TARRAYLENGTH;
  266. radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
  267. radiob_arraylen = RADIOB_1TARRAYLENGTH;
  268. radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
  269. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  270. ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
  271. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  272. ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
  273. }
  274. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
  275. switch (rfpath) {
  276. case RF90_PATH_A:
  277. for (i = 0; i < radioa_arraylen; i = i + 2) {
  278. if (radioa_array_table[i] == 0xfe)
  279. mdelay(50);
  280. else if (radioa_array_table[i] == 0xfd)
  281. mdelay(5);
  282. else if (radioa_array_table[i] == 0xfc)
  283. mdelay(1);
  284. else if (radioa_array_table[i] == 0xfb)
  285. udelay(50);
  286. else if (radioa_array_table[i] == 0xfa)
  287. udelay(5);
  288. else if (radioa_array_table[i] == 0xf9)
  289. udelay(1);
  290. else {
  291. rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
  292. RFREG_OFFSET_MASK,
  293. radioa_array_table[i + 1]);
  294. udelay(1);
  295. }
  296. }
  297. break;
  298. case RF90_PATH_B:
  299. for (i = 0; i < radiob_arraylen; i = i + 2) {
  300. if (radiob_array_table[i] == 0xfe) {
  301. mdelay(50);
  302. } else if (radiob_array_table[i] == 0xfd)
  303. mdelay(5);
  304. else if (radiob_array_table[i] == 0xfc)
  305. mdelay(1);
  306. else if (radiob_array_table[i] == 0xfb)
  307. udelay(50);
  308. else if (radiob_array_table[i] == 0xfa)
  309. udelay(5);
  310. else if (radiob_array_table[i] == 0xf9)
  311. udelay(1);
  312. else {
  313. rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
  314. RFREG_OFFSET_MASK,
  315. radiob_array_table[i + 1]);
  316. udelay(1);
  317. }
  318. }
  319. break;
  320. case RF90_PATH_C:
  321. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  322. ("switch case not process\n"));
  323. break;
  324. case RF90_PATH_D:
  325. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  326. ("switch case not process\n"));
  327. break;
  328. }
  329. return true;
  330. }
  331. void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
  332. {
  333. struct rtl_priv *rtlpriv = rtl_priv(hw);
  334. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  335. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  336. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  337. u8 reg_bw_opmode;
  338. u8 reg_prsr_rsc;
  339. RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
  340. ("Switch to %s bandwidth\n",
  341. rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
  342. "20MHz" : "40MHz"))
  343. if (is_hal_stop(rtlhal)) {
  344. rtlphy->set_bwmode_inprogress = false;
  345. return;
  346. }
  347. reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
  348. reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
  349. switch (rtlphy->current_chan_bw) {
  350. case HT_CHANNEL_WIDTH_20:
  351. reg_bw_opmode |= BW_OPMODE_20MHZ;
  352. rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
  353. break;
  354. case HT_CHANNEL_WIDTH_20_40:
  355. reg_bw_opmode &= ~BW_OPMODE_20MHZ;
  356. rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
  357. reg_prsr_rsc =
  358. (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
  359. rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
  360. break;
  361. default:
  362. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  363. ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
  364. break;
  365. }
  366. switch (rtlphy->current_chan_bw) {
  367. case HT_CHANNEL_WIDTH_20:
  368. rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
  369. rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
  370. rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
  371. break;
  372. case HT_CHANNEL_WIDTH_20_40:
  373. rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
  374. rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
  375. rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
  376. (mac->cur_40_prime_sc >> 1));
  377. rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
  378. rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
  379. rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
  380. (mac->cur_40_prime_sc ==
  381. HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
  382. break;
  383. default:
  384. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  385. ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
  386. break;
  387. }
  388. rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
  389. rtlphy->set_bwmode_inprogress = false;
  390. RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
  391. }
  392. void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
  393. {
  394. u8 tmpreg;
  395. u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
  396. struct rtl_priv *rtlpriv = rtl_priv(hw);
  397. tmpreg = rtl_read_byte(rtlpriv, 0xd03);
  398. if ((tmpreg & 0x70) != 0)
  399. rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
  400. else
  401. rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
  402. if ((tmpreg & 0x70) != 0) {
  403. rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
  404. if (is2t)
  405. rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
  406. MASK12BITS);
  407. rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
  408. (rf_a_mode & 0x8FFFF) | 0x10000);
  409. if (is2t)
  410. rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
  411. (rf_b_mode & 0x8FFFF) | 0x10000);
  412. }
  413. lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
  414. rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
  415. mdelay(100);
  416. if ((tmpreg & 0x70) != 0) {
  417. rtl_write_byte(rtlpriv, 0xd03, tmpreg);
  418. rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
  419. if (is2t)
  420. rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
  421. rf_b_mode);
  422. } else {
  423. rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
  424. }
  425. }
  426. static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
  427. {
  428. u32 u4b_tmp;
  429. u8 delay = 5;
  430. struct rtl_priv *rtlpriv = rtl_priv(hw);
  431. rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
  432. rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
  433. rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
  434. u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
  435. while (u4b_tmp != 0 && delay > 0) {
  436. rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
  437. rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
  438. rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
  439. u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
  440. delay--;
  441. }
  442. if (delay == 0) {
  443. rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
  444. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
  445. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
  446. rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
  447. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  448. ("Switch RF timeout !!!.\n"));
  449. return;
  450. }
  451. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
  452. rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
  453. }
  454. static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
  455. enum rf_pwrstate rfpwr_state)
  456. {
  457. struct rtl_priv *rtlpriv = rtl_priv(hw);
  458. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  459. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  460. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  461. bool bresult = true;
  462. u8 i, queue_id;
  463. struct rtl8192_tx_ring *ring = NULL;
  464. switch (rfpwr_state) {
  465. case ERFON:{
  466. if ((ppsc->rfpwr_state == ERFOFF) &&
  467. RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
  468. bool rtstatus;
  469. u32 InitializeCount = 0;
  470. do {
  471. InitializeCount++;
  472. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  473. ("IPS Set eRf nic enable\n"));
  474. rtstatus = rtl_ps_enable_nic(hw);
  475. } while ((rtstatus != true)
  476. && (InitializeCount < 10));
  477. RT_CLEAR_PS_LEVEL(ppsc,
  478. RT_RF_OFF_LEVL_HALT_NIC);
  479. } else {
  480. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  481. ("Set ERFON sleeped:%d ms\n",
  482. jiffies_to_msecs(jiffies -
  483. ppsc->
  484. last_sleep_jiffies)));
  485. ppsc->last_awake_jiffies = jiffies;
  486. rtl92ce_phy_set_rf_on(hw);
  487. }
  488. if (mac->link_state == MAC80211_LINKED) {
  489. rtlpriv->cfg->ops->led_control(hw,
  490. LED_CTL_LINK);
  491. } else {
  492. rtlpriv->cfg->ops->led_control(hw,
  493. LED_CTL_NO_LINK);
  494. }
  495. break;
  496. }
  497. case ERFOFF:{
  498. if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
  499. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  500. ("IPS Set eRf nic disable\n"));
  501. rtl_ps_disable_nic(hw);
  502. RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
  503. } else {
  504. if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
  505. rtlpriv->cfg->ops->led_control(hw,
  506. LED_CTL_NO_LINK);
  507. } else {
  508. rtlpriv->cfg->ops->led_control(hw,
  509. LED_CTL_POWER_OFF);
  510. }
  511. }
  512. break;
  513. }
  514. case ERFSLEEP:{
  515. if (ppsc->rfpwr_state == ERFOFF)
  516. break;
  517. for (queue_id = 0, i = 0;
  518. queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
  519. ring = &pcipriv->dev.tx_ring[queue_id];
  520. if (skb_queue_len(&ring->queue) == 0) {
  521. queue_id++;
  522. continue;
  523. } else {
  524. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  525. ("eRf Off/Sleep: %d times "
  526. "TcbBusyQueue[%d] =%d before "
  527. "doze!\n", (i + 1), queue_id,
  528. skb_queue_len(&ring->queue)));
  529. udelay(10);
  530. i++;
  531. }
  532. if (i >= MAX_DOZE_WAITING_TIMES_9x) {
  533. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  534. ("\n ERFSLEEP: %d times "
  535. "TcbBusyQueue[%d] = %d !\n",
  536. MAX_DOZE_WAITING_TIMES_9x,
  537. queue_id,
  538. skb_queue_len(&ring->queue)));
  539. break;
  540. }
  541. }
  542. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  543. ("Set ERFSLEEP awaked:%d ms\n",
  544. jiffies_to_msecs(jiffies -
  545. ppsc->last_awake_jiffies)));
  546. ppsc->last_sleep_jiffies = jiffies;
  547. _rtl92ce_phy_set_rf_sleep(hw);
  548. break;
  549. }
  550. default:
  551. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  552. ("switch case not process\n"));
  553. bresult = false;
  554. break;
  555. }
  556. if (bresult)
  557. ppsc->rfpwr_state = rfpwr_state;
  558. return bresult;
  559. }
  560. bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
  561. enum rf_pwrstate rfpwr_state)
  562. {
  563. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  564. bool bresult = false;
  565. if (rfpwr_state == ppsc->rfpwr_state)
  566. return bresult;
  567. bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
  568. return bresult;
  569. }