iwl-agn-ucode.c 16 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/sched.h>
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-io.h"
  36. #include "iwl-helpers.h"
  37. #include "iwl-agn-hw.h"
  38. #include "iwl-agn.h"
  39. #include "iwl-agn-calib.h"
  40. #include "iwl-trans.h"
  41. static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  42. {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  43. 0, COEX_UNASSOC_IDLE_FLAGS},
  44. {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  45. 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  46. {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  47. 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  48. {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  49. 0, COEX_CALIBRATION_FLAGS},
  50. {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  51. 0, COEX_PERIODIC_CALIBRATION_FLAGS},
  52. {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  53. 0, COEX_CONNECTION_ESTAB_FLAGS},
  54. {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  55. 0, COEX_ASSOCIATED_IDLE_FLAGS},
  56. {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  57. 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  58. {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  59. 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  60. {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  61. 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  62. {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  63. {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  64. {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  65. 0, COEX_STAND_ALONE_DEBUG_FLAGS},
  66. {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
  67. 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
  68. {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
  69. {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
  70. };
  71. /*
  72. * ucode
  73. */
  74. static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
  75. struct fw_desc *image, u32 dst_addr)
  76. {
  77. dma_addr_t phy_addr = image->p_addr;
  78. u32 byte_cnt = image->len;
  79. int ret;
  80. priv->ucode_write_complete = 0;
  81. iwl_write_direct32(priv,
  82. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  83. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
  84. iwl_write_direct32(priv,
  85. FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
  86. iwl_write_direct32(priv,
  87. FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
  88. phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
  89. iwl_write_direct32(priv,
  90. FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
  91. (iwl_get_dma_hi_addr(phy_addr)
  92. << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
  93. iwl_write_direct32(priv,
  94. FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
  95. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
  96. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
  97. FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
  98. iwl_write_direct32(priv,
  99. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  100. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  101. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
  102. FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
  103. IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
  104. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  105. priv->ucode_write_complete, 5 * HZ);
  106. if (ret == -ERESTARTSYS) {
  107. IWL_ERR(priv, "Could not load the %s uCode section due "
  108. "to interrupt\n", name);
  109. return ret;
  110. }
  111. if (!ret) {
  112. IWL_ERR(priv, "Could not load the %s uCode section\n",
  113. name);
  114. return -ETIMEDOUT;
  115. }
  116. return 0;
  117. }
  118. static int iwlagn_load_given_ucode(struct iwl_priv *priv,
  119. struct fw_img *image)
  120. {
  121. int ret = 0;
  122. ret = iwlagn_load_section(priv, "INST", &image->code,
  123. IWLAGN_RTC_INST_LOWER_BOUND);
  124. if (ret)
  125. return ret;
  126. return iwlagn_load_section(priv, "DATA", &image->data,
  127. IWLAGN_RTC_DATA_LOWER_BOUND);
  128. }
  129. /*
  130. * Calibration
  131. */
  132. static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
  133. {
  134. struct iwl_calib_xtal_freq_cmd cmd;
  135. __le16 *xtal_calib =
  136. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
  137. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
  138. cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
  139. cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
  140. return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
  141. (u8 *)&cmd, sizeof(cmd));
  142. }
  143. static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
  144. {
  145. struct iwl_calib_temperature_offset_cmd cmd;
  146. __le16 *offset_calib =
  147. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);
  148. memset(&cmd, 0, sizeof(cmd));
  149. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  150. memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(offset_calib));
  151. if (!(cmd.radio_sensor_offset))
  152. cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
  153. IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
  154. le16_to_cpu(cmd.radio_sensor_offset));
  155. return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
  156. (u8 *)&cmd, sizeof(cmd));
  157. }
  158. static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
  159. {
  160. struct iwl_calib_cfg_cmd calib_cfg_cmd;
  161. struct iwl_host_cmd cmd = {
  162. .id = CALIBRATION_CFG_CMD,
  163. .len = { sizeof(struct iwl_calib_cfg_cmd), },
  164. .data = { &calib_cfg_cmd, },
  165. };
  166. memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
  167. calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
  168. calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
  169. calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
  170. calib_cfg_cmd.ucd_calib_cfg.flags =
  171. IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
  172. return trans_send_cmd(&priv->trans, &cmd);
  173. }
  174. void iwlagn_rx_calib_result(struct iwl_priv *priv,
  175. struct iwl_rx_mem_buffer *rxb)
  176. {
  177. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  178. struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
  179. int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  180. int index;
  181. /* reduce the size of the length field itself */
  182. len -= 4;
  183. /* Define the order in which the results will be sent to the runtime
  184. * uCode. iwl_send_calib_results sends them in a row according to
  185. * their index. We sort them here
  186. */
  187. switch (hdr->op_code) {
  188. case IWL_PHY_CALIBRATE_DC_CMD:
  189. index = IWL_CALIB_DC;
  190. break;
  191. case IWL_PHY_CALIBRATE_LO_CMD:
  192. index = IWL_CALIB_LO;
  193. break;
  194. case IWL_PHY_CALIBRATE_TX_IQ_CMD:
  195. index = IWL_CALIB_TX_IQ;
  196. break;
  197. case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
  198. index = IWL_CALIB_TX_IQ_PERD;
  199. break;
  200. case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
  201. index = IWL_CALIB_BASE_BAND;
  202. break;
  203. default:
  204. IWL_ERR(priv, "Unknown calibration notification %d\n",
  205. hdr->op_code);
  206. return;
  207. }
  208. iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
  209. }
  210. int iwlagn_init_alive_start(struct iwl_priv *priv)
  211. {
  212. int ret;
  213. if (priv->cfg->bt_params &&
  214. priv->cfg->bt_params->advanced_bt_coexist) {
  215. /*
  216. * Tell uCode we are ready to perform calibration
  217. * need to perform this before any calibration
  218. * no need to close the envlope since we are going
  219. * to load the runtime uCode later.
  220. */
  221. ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
  222. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  223. if (ret)
  224. return ret;
  225. }
  226. ret = iwlagn_send_calib_cfg(priv);
  227. if (ret)
  228. return ret;
  229. /**
  230. * temperature offset calibration is only needed for runtime ucode,
  231. * so prepare the value now.
  232. */
  233. if (priv->cfg->need_temp_offset_calib)
  234. return iwlagn_set_temperature_offset_calib(priv);
  235. return 0;
  236. }
  237. static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
  238. {
  239. struct iwl_wimax_coex_cmd coex_cmd;
  240. if (priv->cfg->base_params->support_wimax_coexist) {
  241. /* UnMask wake up src at associated sleep */
  242. coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
  243. /* UnMask wake up src at unassociated sleep */
  244. coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
  245. memcpy(coex_cmd.sta_prio, cu_priorities,
  246. sizeof(struct iwl_wimax_coex_event_entry) *
  247. COEX_NUM_OF_EVENTS);
  248. /* enabling the coexistence feature */
  249. coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
  250. /* enabling the priorities tables */
  251. coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
  252. } else {
  253. /* coexistence is disabled */
  254. memset(&coex_cmd, 0, sizeof(coex_cmd));
  255. }
  256. return trans_send_cmd_pdu(&priv->trans,
  257. COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
  258. sizeof(coex_cmd), &coex_cmd);
  259. }
  260. static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
  261. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  262. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  263. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  264. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  265. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  266. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  267. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  268. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  269. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  270. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  271. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  272. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  273. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  274. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  275. ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  276. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  277. ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  278. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  279. 0, 0, 0, 0, 0, 0, 0
  280. };
  281. void iwlagn_send_prio_tbl(struct iwl_priv *priv)
  282. {
  283. struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
  284. memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
  285. sizeof(iwlagn_bt_prio_tbl));
  286. if (trans_send_cmd_pdu(&priv->trans,
  287. REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
  288. sizeof(prio_tbl_cmd), &prio_tbl_cmd))
  289. IWL_ERR(priv, "failed to send BT prio tbl command\n");
  290. }
  291. int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
  292. {
  293. struct iwl_bt_coex_prot_env_cmd env_cmd;
  294. int ret;
  295. env_cmd.action = action;
  296. env_cmd.type = type;
  297. ret = trans_send_cmd_pdu(&priv->trans,
  298. REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
  299. sizeof(env_cmd), &env_cmd);
  300. if (ret)
  301. IWL_ERR(priv, "failed to send BT env command\n");
  302. return ret;
  303. }
  304. static int iwlagn_alive_notify(struct iwl_priv *priv)
  305. {
  306. int ret;
  307. trans_tx_start(&priv->trans);
  308. ret = iwlagn_send_wimax_coex(priv);
  309. if (ret)
  310. return ret;
  311. ret = iwlagn_set_Xtal_calib(priv);
  312. if (ret)
  313. return ret;
  314. return iwl_send_calib_results(priv);
  315. }
  316. /**
  317. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  318. * using sample data 100 bytes apart. If these sample points are good,
  319. * it's a pretty good bet that everything between them is good, too.
  320. */
  321. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
  322. struct fw_desc *fw_desc)
  323. {
  324. __le32 *image = (__le32 *)fw_desc->v_addr;
  325. u32 len = fw_desc->len;
  326. u32 val;
  327. u32 i;
  328. IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
  329. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  330. /* read data comes through single port, auto-incr addr */
  331. /* NOTE: Use the debugless read so we don't flood kernel log
  332. * if IWL_DL_IO is set */
  333. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  334. i + IWLAGN_RTC_INST_LOWER_BOUND);
  335. val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  336. if (val != le32_to_cpu(*image))
  337. return -EIO;
  338. }
  339. return 0;
  340. }
  341. static void iwl_print_mismatch_inst(struct iwl_priv *priv,
  342. struct fw_desc *fw_desc)
  343. {
  344. __le32 *image = (__le32 *)fw_desc->v_addr;
  345. u32 len = fw_desc->len;
  346. u32 val;
  347. u32 offs;
  348. int errors = 0;
  349. IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
  350. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  351. IWLAGN_RTC_INST_LOWER_BOUND);
  352. for (offs = 0;
  353. offs < len && errors < 20;
  354. offs += sizeof(u32), image++) {
  355. /* read data comes through single port, auto-incr addr */
  356. val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  357. if (val != le32_to_cpu(*image)) {
  358. IWL_ERR(priv, "uCode INST section at "
  359. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  360. offs, val, le32_to_cpu(*image));
  361. errors++;
  362. }
  363. }
  364. }
  365. /**
  366. * iwl_verify_ucode - determine which instruction image is in SRAM,
  367. * and verify its contents
  368. */
  369. static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
  370. {
  371. if (!iwlcore_verify_inst_sparse(priv, &img->code)) {
  372. IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
  373. return 0;
  374. }
  375. IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
  376. iwl_print_mismatch_inst(priv, &img->code);
  377. return -EIO;
  378. }
  379. struct iwlagn_alive_data {
  380. bool valid;
  381. u8 subtype;
  382. };
  383. static void iwlagn_alive_fn(struct iwl_priv *priv,
  384. struct iwl_rx_packet *pkt,
  385. void *data)
  386. {
  387. struct iwlagn_alive_data *alive_data = data;
  388. struct iwl_alive_resp *palive;
  389. palive = &pkt->u.alive_frame;
  390. IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
  391. "0x%01X 0x%01X\n",
  392. palive->is_valid, palive->ver_type,
  393. palive->ver_subtype);
  394. priv->device_pointers.error_event_table =
  395. le32_to_cpu(palive->error_event_table_ptr);
  396. priv->device_pointers.log_event_table =
  397. le32_to_cpu(palive->log_event_table_ptr);
  398. alive_data->subtype = palive->ver_subtype;
  399. alive_data->valid = palive->is_valid == UCODE_VALID_OK;
  400. }
  401. #define UCODE_ALIVE_TIMEOUT HZ
  402. #define UCODE_CALIB_TIMEOUT (2*HZ)
  403. int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
  404. struct fw_img *image,
  405. enum iwlagn_ucode_type ucode_type)
  406. {
  407. struct iwl_notification_wait alive_wait;
  408. struct iwlagn_alive_data alive_data;
  409. int ret;
  410. enum iwlagn_ucode_type old_type;
  411. ret = trans_start_device(&priv->trans);
  412. if (ret)
  413. return ret;
  414. iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
  415. iwlagn_alive_fn, &alive_data);
  416. old_type = priv->ucode_type;
  417. priv->ucode_type = ucode_type;
  418. ret = iwlagn_load_given_ucode(priv, image);
  419. if (ret) {
  420. priv->ucode_type = old_type;
  421. iwlagn_remove_notification(priv, &alive_wait);
  422. return ret;
  423. }
  424. trans_kick_nic(&priv->trans);
  425. /*
  426. * Some things may run in the background now, but we
  427. * just wait for the ALIVE notification here.
  428. */
  429. ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
  430. if (ret) {
  431. priv->ucode_type = old_type;
  432. return ret;
  433. }
  434. if (!alive_data.valid) {
  435. IWL_ERR(priv, "Loaded ucode is not valid!\n");
  436. priv->ucode_type = old_type;
  437. return -EIO;
  438. }
  439. /*
  440. * This step takes a long time (60-80ms!!) and
  441. * WoWLAN image should be loaded quickly, so
  442. * skip it for WoWLAN.
  443. */
  444. if (ucode_type != IWL_UCODE_WOWLAN) {
  445. ret = iwl_verify_ucode(priv, image);
  446. if (ret) {
  447. priv->ucode_type = old_type;
  448. return ret;
  449. }
  450. /* delay a bit to give rfkill time to run */
  451. msleep(5);
  452. }
  453. ret = iwlagn_alive_notify(priv);
  454. if (ret) {
  455. IWL_WARN(priv,
  456. "Could not complete ALIVE transition: %d\n", ret);
  457. priv->ucode_type = old_type;
  458. return ret;
  459. }
  460. return 0;
  461. }
  462. int iwlagn_run_init_ucode(struct iwl_priv *priv)
  463. {
  464. struct iwl_notification_wait calib_wait;
  465. int ret;
  466. lockdep_assert_held(&priv->mutex);
  467. /* No init ucode required? Curious, but maybe ok */
  468. if (!priv->ucode_init.code.len)
  469. return 0;
  470. if (priv->ucode_type != IWL_UCODE_NONE)
  471. return 0;
  472. iwlagn_init_notification_wait(priv, &calib_wait,
  473. CALIBRATION_COMPLETE_NOTIFICATION,
  474. NULL, NULL);
  475. /* Will also start the device */
  476. ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
  477. IWL_UCODE_INIT);
  478. if (ret)
  479. goto error;
  480. ret = iwlagn_init_alive_start(priv);
  481. if (ret)
  482. goto error;
  483. /*
  484. * Some things may run in the background now, but we
  485. * just wait for the calibration complete notification.
  486. */
  487. ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
  488. goto out;
  489. error:
  490. iwlagn_remove_notification(priv, &calib_wait);
  491. out:
  492. /* Whatever happened, stop the device */
  493. trans_stop_device(&priv->trans);
  494. return ret;
  495. }