iwl-tx.c 19 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <linux/sched.h>
  31. #include <linux/slab.h>
  32. #include <net/mac80211.h>
  33. #include "iwl-eeprom.h"
  34. #include "iwl-dev.h"
  35. #include "iwl-core.h"
  36. #include "iwl-sta.h"
  37. #include "iwl-io.h"
  38. #include "iwl-helpers.h"
  39. /**
  40. * iwl_legacy_txq_update_write_ptr - Send new write index to hardware
  41. */
  42. void
  43. iwl_legacy_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  44. {
  45. u32 reg = 0;
  46. int txq_id = txq->q.id;
  47. if (txq->need_update == 0)
  48. return;
  49. /* if we're trying to save power */
  50. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  51. /* wake up nic if it's powered down ...
  52. * uCode will wake up, and interrupt us again, so next
  53. * time we'll skip this part. */
  54. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  55. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  56. IWL_DEBUG_INFO(priv,
  57. "Tx queue %d requesting wakeup,"
  58. " GP1 = 0x%x\n", txq_id, reg);
  59. iwl_legacy_set_bit(priv, CSR_GP_CNTRL,
  60. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  61. return;
  62. }
  63. iwl_legacy_write_direct32(priv, HBUS_TARG_WRPTR,
  64. txq->q.write_ptr | (txq_id << 8));
  65. /*
  66. * else not in power-save mode,
  67. * uCode will never sleep when we're
  68. * trying to tx (during RFKILL, we're not trying to tx).
  69. */
  70. } else
  71. iwl_write32(priv, HBUS_TARG_WRPTR,
  72. txq->q.write_ptr | (txq_id << 8));
  73. txq->need_update = 0;
  74. }
  75. EXPORT_SYMBOL(iwl_legacy_txq_update_write_ptr);
  76. /**
  77. * iwl_legacy_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
  78. */
  79. void iwl_legacy_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
  80. {
  81. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  82. struct iwl_queue *q = &txq->q;
  83. if (q->n_bd == 0)
  84. return;
  85. while (q->write_ptr != q->read_ptr) {
  86. priv->cfg->ops->lib->txq_free_tfd(priv, txq);
  87. q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd);
  88. }
  89. }
  90. EXPORT_SYMBOL(iwl_legacy_tx_queue_unmap);
  91. /**
  92. * iwl_legacy_tx_queue_free - Deallocate DMA queue.
  93. * @txq: Transmit queue to deallocate.
  94. *
  95. * Empty queue by removing and destroying all BD's.
  96. * Free all buffers.
  97. * 0-fill, but do not free "txq" descriptor structure.
  98. */
  99. void iwl_legacy_tx_queue_free(struct iwl_priv *priv, int txq_id)
  100. {
  101. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  102. struct device *dev = &priv->pci_dev->dev;
  103. int i;
  104. iwl_legacy_tx_queue_unmap(priv, txq_id);
  105. /* De-alloc array of command/tx buffers */
  106. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  107. kfree(txq->cmd[i]);
  108. /* De-alloc circular buffer of TFDs */
  109. if (txq->q.n_bd)
  110. dma_free_coherent(dev, priv->hw_params.tfd_size *
  111. txq->q.n_bd, txq->tfds, txq->q.dma_addr);
  112. /* De-alloc array of per-TFD driver data */
  113. kfree(txq->txb);
  114. txq->txb = NULL;
  115. /* deallocate arrays */
  116. kfree(txq->cmd);
  117. kfree(txq->meta);
  118. txq->cmd = NULL;
  119. txq->meta = NULL;
  120. /* 0-fill queue descriptor structure */
  121. memset(txq, 0, sizeof(*txq));
  122. }
  123. EXPORT_SYMBOL(iwl_legacy_tx_queue_free);
  124. /**
  125. * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
  126. */
  127. void iwl_legacy_cmd_queue_unmap(struct iwl_priv *priv)
  128. {
  129. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  130. struct iwl_queue *q = &txq->q;
  131. int i;
  132. if (q->n_bd == 0)
  133. return;
  134. while (q->read_ptr != q->write_ptr) {
  135. i = iwl_legacy_get_cmd_index(q, q->read_ptr, 0);
  136. if (txq->meta[i].flags & CMD_MAPPED) {
  137. pci_unmap_single(priv->pci_dev,
  138. dma_unmap_addr(&txq->meta[i], mapping),
  139. dma_unmap_len(&txq->meta[i], len),
  140. PCI_DMA_BIDIRECTIONAL);
  141. txq->meta[i].flags = 0;
  142. }
  143. q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd);
  144. }
  145. i = q->n_window;
  146. if (txq->meta[i].flags & CMD_MAPPED) {
  147. pci_unmap_single(priv->pci_dev,
  148. dma_unmap_addr(&txq->meta[i], mapping),
  149. dma_unmap_len(&txq->meta[i], len),
  150. PCI_DMA_BIDIRECTIONAL);
  151. txq->meta[i].flags = 0;
  152. }
  153. }
  154. EXPORT_SYMBOL(iwl_legacy_cmd_queue_unmap);
  155. /**
  156. * iwl_legacy_cmd_queue_free - Deallocate DMA queue.
  157. * @txq: Transmit queue to deallocate.
  158. *
  159. * Empty queue by removing and destroying all BD's.
  160. * Free all buffers.
  161. * 0-fill, but do not free "txq" descriptor structure.
  162. */
  163. void iwl_legacy_cmd_queue_free(struct iwl_priv *priv)
  164. {
  165. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  166. struct device *dev = &priv->pci_dev->dev;
  167. int i;
  168. iwl_legacy_cmd_queue_unmap(priv);
  169. /* De-alloc array of command/tx buffers */
  170. for (i = 0; i <= TFD_CMD_SLOTS; i++)
  171. kfree(txq->cmd[i]);
  172. /* De-alloc circular buffer of TFDs */
  173. if (txq->q.n_bd)
  174. dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
  175. txq->tfds, txq->q.dma_addr);
  176. /* deallocate arrays */
  177. kfree(txq->cmd);
  178. kfree(txq->meta);
  179. txq->cmd = NULL;
  180. txq->meta = NULL;
  181. /* 0-fill queue descriptor structure */
  182. memset(txq, 0, sizeof(*txq));
  183. }
  184. EXPORT_SYMBOL(iwl_legacy_cmd_queue_free);
  185. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  186. * DMA services
  187. *
  188. * Theory of operation
  189. *
  190. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  191. * of buffer descriptors, each of which points to one or more data buffers for
  192. * the device to read from or fill. Driver and device exchange status of each
  193. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  194. * entries in each circular buffer, to protect against confusing empty and full
  195. * queue states.
  196. *
  197. * The device reads or writes the data in the queues via the device's several
  198. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  199. *
  200. * For Tx queue, there are low mark and high mark limits. If, after queuing
  201. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  202. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  203. * Tx queue resumed.
  204. *
  205. * See more detailed info in iwl-4965-hw.h.
  206. ***************************************************/
  207. int iwl_legacy_queue_space(const struct iwl_queue *q)
  208. {
  209. int s = q->read_ptr - q->write_ptr;
  210. if (q->read_ptr > q->write_ptr)
  211. s -= q->n_bd;
  212. if (s <= 0)
  213. s += q->n_window;
  214. /* keep some reserve to not confuse empty and full situations */
  215. s -= 2;
  216. if (s < 0)
  217. s = 0;
  218. return s;
  219. }
  220. EXPORT_SYMBOL(iwl_legacy_queue_space);
  221. /**
  222. * iwl_legacy_queue_init - Initialize queue's high/low-water and read/write indexes
  223. */
  224. static int iwl_legacy_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  225. int count, int slots_num, u32 id)
  226. {
  227. q->n_bd = count;
  228. q->n_window = slots_num;
  229. q->id = id;
  230. /* count must be power-of-two size, otherwise iwl_legacy_queue_inc_wrap
  231. * and iwl_legacy_queue_dec_wrap are broken. */
  232. BUG_ON(!is_power_of_2(count));
  233. /* slots_num must be power-of-two size, otherwise
  234. * iwl_legacy_get_cmd_index is broken. */
  235. BUG_ON(!is_power_of_2(slots_num));
  236. q->low_mark = q->n_window / 4;
  237. if (q->low_mark < 4)
  238. q->low_mark = 4;
  239. q->high_mark = q->n_window / 8;
  240. if (q->high_mark < 2)
  241. q->high_mark = 2;
  242. q->write_ptr = q->read_ptr = 0;
  243. return 0;
  244. }
  245. /**
  246. * iwl_legacy_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  247. */
  248. static int iwl_legacy_tx_queue_alloc(struct iwl_priv *priv,
  249. struct iwl_tx_queue *txq, u32 id)
  250. {
  251. struct device *dev = &priv->pci_dev->dev;
  252. size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
  253. /* Driver private data, only for Tx (not command) queues,
  254. * not shared with device. */
  255. if (id != priv->cmd_queue) {
  256. txq->txb = kzalloc(sizeof(txq->txb[0]) *
  257. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  258. if (!txq->txb) {
  259. IWL_ERR(priv, "kmalloc for auxiliary BD "
  260. "structures failed\n");
  261. goto error;
  262. }
  263. } else {
  264. txq->txb = NULL;
  265. }
  266. /* Circular buffer of transmit frame descriptors (TFDs),
  267. * shared with device */
  268. txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
  269. GFP_KERNEL);
  270. if (!txq->tfds) {
  271. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
  272. goto error;
  273. }
  274. txq->q.id = id;
  275. return 0;
  276. error:
  277. kfree(txq->txb);
  278. txq->txb = NULL;
  279. return -ENOMEM;
  280. }
  281. /**
  282. * iwl_legacy_tx_queue_init - Allocate and initialize one tx/cmd queue
  283. */
  284. int iwl_legacy_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
  285. int slots_num, u32 txq_id)
  286. {
  287. int i, len;
  288. int ret;
  289. int actual_slots = slots_num;
  290. /*
  291. * Alloc buffer array for commands (Tx or other types of commands).
  292. * For the command queue (#4/#9), allocate command space + one big
  293. * command for scan, since scan command is very huge; the system will
  294. * not have two scans at the same time, so only one is needed.
  295. * For normal Tx queues (all other queues), no super-size command
  296. * space is needed.
  297. */
  298. if (txq_id == priv->cmd_queue)
  299. actual_slots++;
  300. txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
  301. GFP_KERNEL);
  302. txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
  303. GFP_KERNEL);
  304. if (!txq->meta || !txq->cmd)
  305. goto out_free_arrays;
  306. len = sizeof(struct iwl_device_cmd);
  307. for (i = 0; i < actual_slots; i++) {
  308. /* only happens for cmd queue */
  309. if (i == slots_num)
  310. len = IWL_MAX_CMD_SIZE;
  311. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  312. if (!txq->cmd[i])
  313. goto err;
  314. }
  315. /* Alloc driver data array and TFD circular buffer */
  316. ret = iwl_legacy_tx_queue_alloc(priv, txq, txq_id);
  317. if (ret)
  318. goto err;
  319. txq->need_update = 0;
  320. /*
  321. * For the default queues 0-3, set up the swq_id
  322. * already -- all others need to get one later
  323. * (if they need one at all).
  324. */
  325. if (txq_id < 4)
  326. iwl_legacy_set_swq_id(txq, txq_id, txq_id);
  327. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  328. * iwl_legacy_queue_inc_wrap and iwl_legacy_queue_dec_wrap are broken. */
  329. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  330. /* Initialize queue's high/low-water marks, and head/tail indexes */
  331. iwl_legacy_queue_init(priv, &txq->q,
  332. TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  333. /* Tell device where to find queue */
  334. priv->cfg->ops->lib->txq_init(priv, txq);
  335. return 0;
  336. err:
  337. for (i = 0; i < actual_slots; i++)
  338. kfree(txq->cmd[i]);
  339. out_free_arrays:
  340. kfree(txq->meta);
  341. kfree(txq->cmd);
  342. return -ENOMEM;
  343. }
  344. EXPORT_SYMBOL(iwl_legacy_tx_queue_init);
  345. void iwl_legacy_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
  346. int slots_num, u32 txq_id)
  347. {
  348. int actual_slots = slots_num;
  349. if (txq_id == priv->cmd_queue)
  350. actual_slots++;
  351. memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
  352. txq->need_update = 0;
  353. /* Initialize queue's high/low-water marks, and head/tail indexes */
  354. iwl_legacy_queue_init(priv, &txq->q,
  355. TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  356. /* Tell device where to find queue */
  357. priv->cfg->ops->lib->txq_init(priv, txq);
  358. }
  359. EXPORT_SYMBOL(iwl_legacy_tx_queue_reset);
  360. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  361. /**
  362. * iwl_legacy_enqueue_hcmd - enqueue a uCode command
  363. * @priv: device private data point
  364. * @cmd: a point to the ucode command structure
  365. *
  366. * The function returns < 0 values to indicate the operation is
  367. * failed. On success, it turns the index (> 0) of command in the
  368. * command queue.
  369. */
  370. int iwl_legacy_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  371. {
  372. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  373. struct iwl_queue *q = &txq->q;
  374. struct iwl_device_cmd *out_cmd;
  375. struct iwl_cmd_meta *out_meta;
  376. dma_addr_t phys_addr;
  377. unsigned long flags;
  378. int len;
  379. u32 idx;
  380. u16 fix_size;
  381. cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
  382. fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  383. /* If any of the command structures end up being larger than
  384. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  385. * we will need to increase the size of the TFD entries
  386. * Also, check to see if command buffer should not exceed the size
  387. * of device_cmd and max_cmd_size. */
  388. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  389. !(cmd->flags & CMD_SIZE_HUGE));
  390. BUG_ON(fix_size > IWL_MAX_CMD_SIZE);
  391. if (iwl_legacy_is_rfkill(priv) || iwl_legacy_is_ctkill(priv)) {
  392. IWL_WARN(priv, "Not sending command - %s KILL\n",
  393. iwl_legacy_is_rfkill(priv) ? "RF" : "CT");
  394. return -EIO;
  395. }
  396. spin_lock_irqsave(&priv->hcmd_lock, flags);
  397. if (iwl_legacy_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
  398. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  399. IWL_ERR(priv, "Restarting adapter due to command queue full\n");
  400. queue_work(priv->workqueue, &priv->restart);
  401. return -ENOSPC;
  402. }
  403. idx = iwl_legacy_get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
  404. out_cmd = txq->cmd[idx];
  405. out_meta = &txq->meta[idx];
  406. if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
  407. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  408. return -ENOSPC;
  409. }
  410. memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
  411. out_meta->flags = cmd->flags | CMD_MAPPED;
  412. if (cmd->flags & CMD_WANT_SKB)
  413. out_meta->source = cmd;
  414. if (cmd->flags & CMD_ASYNC)
  415. out_meta->callback = cmd->callback;
  416. out_cmd->hdr.cmd = cmd->id;
  417. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  418. /* At this point, the out_cmd now has all of the incoming cmd
  419. * information */
  420. out_cmd->hdr.flags = 0;
  421. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
  422. INDEX_TO_SEQ(q->write_ptr));
  423. if (cmd->flags & CMD_SIZE_HUGE)
  424. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  425. len = sizeof(struct iwl_device_cmd);
  426. if (idx == TFD_CMD_SLOTS)
  427. len = IWL_MAX_CMD_SIZE;
  428. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  429. switch (out_cmd->hdr.cmd) {
  430. case REPLY_TX_LINK_QUALITY_CMD:
  431. case SENSITIVITY_CMD:
  432. IWL_DEBUG_HC_DUMP(priv,
  433. "Sending command %s (#%x), seq: 0x%04X, "
  434. "%d bytes at %d[%d]:%d\n",
  435. iwl_legacy_get_cmd_string(out_cmd->hdr.cmd),
  436. out_cmd->hdr.cmd,
  437. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  438. q->write_ptr, idx, priv->cmd_queue);
  439. break;
  440. default:
  441. IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
  442. "%d bytes at %d[%d]:%d\n",
  443. iwl_legacy_get_cmd_string(out_cmd->hdr.cmd),
  444. out_cmd->hdr.cmd,
  445. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  446. q->write_ptr, idx, priv->cmd_queue);
  447. }
  448. #endif
  449. txq->need_update = 1;
  450. if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
  451. /* Set up entry in queue's byte count circular buffer */
  452. priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
  453. phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
  454. fix_size, PCI_DMA_BIDIRECTIONAL);
  455. dma_unmap_addr_set(out_meta, mapping, phys_addr);
  456. dma_unmap_len_set(out_meta, len, fix_size);
  457. trace_iwlwifi_legacy_dev_hcmd(priv, &out_cmd->hdr,
  458. fix_size, cmd->flags);
  459. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  460. phys_addr, fix_size, 1,
  461. U32_PAD(cmd->len));
  462. /* Increment and update queue's write index */
  463. q->write_ptr = iwl_legacy_queue_inc_wrap(q->write_ptr, q->n_bd);
  464. iwl_legacy_txq_update_write_ptr(priv, txq);
  465. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  466. return idx;
  467. }
  468. /**
  469. * iwl_legacy_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
  470. *
  471. * When FW advances 'R' index, all entries between old and new 'R' index
  472. * need to be reclaimed. As result, some free space forms. If there is
  473. * enough free space (> low mark), wake the stack that feeds us.
  474. */
  475. static void iwl_legacy_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
  476. int idx, int cmd_idx)
  477. {
  478. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  479. struct iwl_queue *q = &txq->q;
  480. int nfreed = 0;
  481. if ((idx >= q->n_bd) || (iwl_legacy_queue_used(q, idx) == 0)) {
  482. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  483. "is out of range [0-%d] %d %d.\n", txq_id,
  484. idx, q->n_bd, q->write_ptr, q->read_ptr);
  485. return;
  486. }
  487. for (idx = iwl_legacy_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
  488. q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  489. if (nfreed++ > 0) {
  490. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
  491. q->write_ptr, q->read_ptr);
  492. queue_work(priv->workqueue, &priv->restart);
  493. }
  494. }
  495. }
  496. /**
  497. * iwl_legacy_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  498. * @rxb: Rx buffer to reclaim
  499. *
  500. * If an Rx buffer has an async callback associated with it the callback
  501. * will be executed. The attached skb (if present) will only be freed
  502. * if the callback returns 1
  503. */
  504. void
  505. iwl_legacy_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  506. {
  507. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  508. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  509. int txq_id = SEQ_TO_QUEUE(sequence);
  510. int index = SEQ_TO_INDEX(sequence);
  511. int cmd_index;
  512. bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  513. struct iwl_device_cmd *cmd;
  514. struct iwl_cmd_meta *meta;
  515. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  516. unsigned long flags;
  517. /* If a Tx command is being handled and it isn't in the actual
  518. * command queue then there a command routing bug has been introduced
  519. * in the queue management code. */
  520. if (WARN(txq_id != priv->cmd_queue,
  521. "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
  522. txq_id, priv->cmd_queue, sequence,
  523. priv->txq[priv->cmd_queue].q.read_ptr,
  524. priv->txq[priv->cmd_queue].q.write_ptr)) {
  525. iwl_print_hex_error(priv, pkt, 32);
  526. return;
  527. }
  528. cmd_index = iwl_legacy_get_cmd_index(&txq->q, index, huge);
  529. cmd = txq->cmd[cmd_index];
  530. meta = &txq->meta[cmd_index];
  531. pci_unmap_single(priv->pci_dev,
  532. dma_unmap_addr(meta, mapping),
  533. dma_unmap_len(meta, len),
  534. PCI_DMA_BIDIRECTIONAL);
  535. /* Input error checking is done when commands are added to queue. */
  536. if (meta->flags & CMD_WANT_SKB) {
  537. meta->source->reply_page = (unsigned long)rxb_addr(rxb);
  538. rxb->page = NULL;
  539. } else if (meta->callback)
  540. meta->callback(priv, cmd, pkt);
  541. spin_lock_irqsave(&priv->hcmd_lock, flags);
  542. iwl_legacy_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
  543. if (!(meta->flags & CMD_ASYNC)) {
  544. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  545. IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
  546. iwl_legacy_get_cmd_string(cmd->hdr.cmd));
  547. wake_up_interruptible(&priv->wait_command_queue);
  548. }
  549. /* Mark as unmapped */
  550. meta->flags = 0;
  551. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  552. }
  553. EXPORT_SYMBOL(iwl_legacy_tx_cmd_complete);