ar5008_phy.c 47 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. #include "hw-ops.h"
  18. #include "../regd.h"
  19. #include "ar9002_phy.h"
  20. /* All code below is for AR5008, AR9001, AR9002 */
  21. static const int firstep_table[] =
  22. /* level: 0 1 2 3 4 5 6 7 8 */
  23. { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
  24. static const int cycpwrThr1_table[] =
  25. /* level: 0 1 2 3 4 5 6 7 8 */
  26. { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
  27. /*
  28. * register values to turn OFDM weak signal detection OFF
  29. */
  30. static const int m1ThreshLow_off = 127;
  31. static const int m2ThreshLow_off = 127;
  32. static const int m1Thresh_off = 127;
  33. static const int m2Thresh_off = 127;
  34. static const int m2CountThr_off = 31;
  35. static const int m2CountThrLow_off = 63;
  36. static const int m1ThreshLowExt_off = 127;
  37. static const int m2ThreshLowExt_off = 127;
  38. static const int m1ThreshExt_off = 127;
  39. static const int m2ThreshExt_off = 127;
  40. static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
  41. int col)
  42. {
  43. int i;
  44. for (i = 0; i < array->ia_rows; i++)
  45. bank[i] = INI_RA(array, i, col);
  46. }
  47. #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
  48. ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
  49. static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
  50. u32 *data, unsigned int *writecnt)
  51. {
  52. int r;
  53. ENABLE_REGWRITE_BUFFER(ah);
  54. for (r = 0; r < array->ia_rows; r++) {
  55. REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
  56. DO_DELAY(*writecnt);
  57. }
  58. REGWRITE_BUFFER_FLUSH(ah);
  59. }
  60. /**
  61. * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
  62. * @rfbuf:
  63. * @reg32:
  64. * @numBits:
  65. * @firstBit:
  66. * @column:
  67. *
  68. * Performs analog "swizzling" of parameters into their location.
  69. * Used on external AR2133/AR5133 radios.
  70. */
  71. static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
  72. u32 numBits, u32 firstBit,
  73. u32 column)
  74. {
  75. u32 tmp32, mask, arrayEntry, lastBit;
  76. int32_t bitPosition, bitsLeft;
  77. tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
  78. arrayEntry = (firstBit - 1) / 8;
  79. bitPosition = (firstBit - 1) % 8;
  80. bitsLeft = numBits;
  81. while (bitsLeft > 0) {
  82. lastBit = (bitPosition + bitsLeft > 8) ?
  83. 8 : bitPosition + bitsLeft;
  84. mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
  85. (column * 8);
  86. rfBuf[arrayEntry] &= ~mask;
  87. rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
  88. (column * 8)) & mask;
  89. bitsLeft -= 8 - bitPosition;
  90. tmp32 = tmp32 >> (8 - bitPosition);
  91. bitPosition = 0;
  92. arrayEntry++;
  93. }
  94. }
  95. /*
  96. * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
  97. * rf_pwd_icsyndiv.
  98. *
  99. * Theoretical Rules:
  100. * if 2 GHz band
  101. * if forceBiasAuto
  102. * if synth_freq < 2412
  103. * bias = 0
  104. * else if 2412 <= synth_freq <= 2422
  105. * bias = 1
  106. * else // synth_freq > 2422
  107. * bias = 2
  108. * else if forceBias > 0
  109. * bias = forceBias & 7
  110. * else
  111. * no change, use value from ini file
  112. * else
  113. * no change, invalid band
  114. *
  115. * 1st Mod:
  116. * 2422 also uses value of 2
  117. * <approved>
  118. *
  119. * 2nd Mod:
  120. * Less than 2412 uses value of 0, 2412 and above uses value of 2
  121. */
  122. static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
  123. {
  124. struct ath_common *common = ath9k_hw_common(ah);
  125. u32 tmp_reg;
  126. int reg_writes = 0;
  127. u32 new_bias = 0;
  128. if (!AR_SREV_5416(ah) || synth_freq >= 3000)
  129. return;
  130. BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
  131. if (synth_freq < 2412)
  132. new_bias = 0;
  133. else if (synth_freq < 2422)
  134. new_bias = 1;
  135. else
  136. new_bias = 2;
  137. /* pre-reverse this field */
  138. tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
  139. ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
  140. new_bias, synth_freq);
  141. /* swizzle rf_pwd_icsyndiv */
  142. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
  143. /* write Bank 6 with new params */
  144. REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
  145. }
  146. /**
  147. * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
  148. * @ah: atheros hardware structure
  149. * @chan:
  150. *
  151. * For the external AR2133/AR5133 radios, takes the MHz channel value and set
  152. * the channel value. Assumes writes enabled to analog bus and bank6 register
  153. * cache in ah->analogBank6Data.
  154. */
  155. static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  156. {
  157. struct ath_common *common = ath9k_hw_common(ah);
  158. u32 channelSel = 0;
  159. u32 bModeSynth = 0;
  160. u32 aModeRefSel = 0;
  161. u32 reg32 = 0;
  162. u16 freq;
  163. struct chan_centers centers;
  164. ath9k_hw_get_channel_centers(ah, chan, &centers);
  165. freq = centers.synth_center;
  166. if (freq < 4800) {
  167. u32 txctl;
  168. if (((freq - 2192) % 5) == 0) {
  169. channelSel = ((freq - 672) * 2 - 3040) / 10;
  170. bModeSynth = 0;
  171. } else if (((freq - 2224) % 5) == 0) {
  172. channelSel = ((freq - 704) * 2 - 3040) / 10;
  173. bModeSynth = 1;
  174. } else {
  175. ath_err(common, "Invalid channel %u MHz\n", freq);
  176. return -EINVAL;
  177. }
  178. channelSel = (channelSel << 2) & 0xff;
  179. channelSel = ath9k_hw_reverse_bits(channelSel, 8);
  180. txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
  181. if (freq == 2484) {
  182. REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  183. txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
  184. } else {
  185. REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  186. txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
  187. }
  188. } else if ((freq % 20) == 0 && freq >= 5120) {
  189. channelSel =
  190. ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
  191. aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  192. } else if ((freq % 10) == 0) {
  193. channelSel =
  194. ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
  195. if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
  196. aModeRefSel = ath9k_hw_reverse_bits(2, 2);
  197. else
  198. aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  199. } else if ((freq % 5) == 0) {
  200. channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
  201. aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  202. } else {
  203. ath_err(common, "Invalid channel %u MHz\n", freq);
  204. return -EINVAL;
  205. }
  206. ar5008_hw_force_bias(ah, freq);
  207. reg32 =
  208. (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
  209. (1 << 5) | 0x1;
  210. REG_WRITE(ah, AR_PHY(0x37), reg32);
  211. ah->curchan = chan;
  212. ah->curchan_rad_index = -1;
  213. return 0;
  214. }
  215. /**
  216. * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
  217. * @ah: atheros hardware structure
  218. * @chan:
  219. *
  220. * For non single-chip solutions. Converts to baseband spur frequency given the
  221. * input channel frequency and compute register settings below.
  222. */
  223. static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
  224. struct ath9k_channel *chan)
  225. {
  226. int bb_spur = AR_NO_SPUR;
  227. int bin, cur_bin;
  228. int spur_freq_sd;
  229. int spur_delta_phase;
  230. int denominator;
  231. int upper, lower, cur_vit_mask;
  232. int tmp, new;
  233. int i;
  234. static int pilot_mask_reg[4] = {
  235. AR_PHY_TIMING7, AR_PHY_TIMING8,
  236. AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
  237. };
  238. static int chan_mask_reg[4] = {
  239. AR_PHY_TIMING9, AR_PHY_TIMING10,
  240. AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
  241. };
  242. static int inc[4] = { 0, 100, 0, 0 };
  243. int8_t mask_m[123];
  244. int8_t mask_p[123];
  245. int8_t mask_amt;
  246. int tmp_mask;
  247. int cur_bb_spur;
  248. bool is2GHz = IS_CHAN_2GHZ(chan);
  249. memset(&mask_m, 0, sizeof(int8_t) * 123);
  250. memset(&mask_p, 0, sizeof(int8_t) * 123);
  251. for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
  252. cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
  253. if (AR_NO_SPUR == cur_bb_spur)
  254. break;
  255. cur_bb_spur = cur_bb_spur - (chan->channel * 10);
  256. if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
  257. bb_spur = cur_bb_spur;
  258. break;
  259. }
  260. }
  261. if (AR_NO_SPUR == bb_spur)
  262. return;
  263. bin = bb_spur * 32;
  264. tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
  265. new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
  266. AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
  267. AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
  268. AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
  269. REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
  270. new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
  271. AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
  272. AR_PHY_SPUR_REG_MASK_RATE_SELECT |
  273. AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
  274. SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
  275. REG_WRITE(ah, AR_PHY_SPUR_REG, new);
  276. spur_delta_phase = ((bb_spur * 524288) / 100) &
  277. AR_PHY_TIMING11_SPUR_DELTA_PHASE;
  278. denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
  279. spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
  280. new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
  281. SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
  282. SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
  283. REG_WRITE(ah, AR_PHY_TIMING11, new);
  284. cur_bin = -6000;
  285. upper = bin + 100;
  286. lower = bin - 100;
  287. for (i = 0; i < 4; i++) {
  288. int pilot_mask = 0;
  289. int chan_mask = 0;
  290. int bp = 0;
  291. for (bp = 0; bp < 30; bp++) {
  292. if ((cur_bin > lower) && (cur_bin < upper)) {
  293. pilot_mask = pilot_mask | 0x1 << bp;
  294. chan_mask = chan_mask | 0x1 << bp;
  295. }
  296. cur_bin += 100;
  297. }
  298. cur_bin += inc[i];
  299. REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
  300. REG_WRITE(ah, chan_mask_reg[i], chan_mask);
  301. }
  302. cur_vit_mask = 6100;
  303. upper = bin + 120;
  304. lower = bin - 120;
  305. for (i = 0; i < 123; i++) {
  306. if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
  307. /* workaround for gcc bug #37014 */
  308. volatile int tmp_v = abs(cur_vit_mask - bin);
  309. if (tmp_v < 75)
  310. mask_amt = 1;
  311. else
  312. mask_amt = 0;
  313. if (cur_vit_mask < 0)
  314. mask_m[abs(cur_vit_mask / 100)] = mask_amt;
  315. else
  316. mask_p[cur_vit_mask / 100] = mask_amt;
  317. }
  318. cur_vit_mask -= 100;
  319. }
  320. tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
  321. | (mask_m[48] << 26) | (mask_m[49] << 24)
  322. | (mask_m[50] << 22) | (mask_m[51] << 20)
  323. | (mask_m[52] << 18) | (mask_m[53] << 16)
  324. | (mask_m[54] << 14) | (mask_m[55] << 12)
  325. | (mask_m[56] << 10) | (mask_m[57] << 8)
  326. | (mask_m[58] << 6) | (mask_m[59] << 4)
  327. | (mask_m[60] << 2) | (mask_m[61] << 0);
  328. REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
  329. REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
  330. tmp_mask = (mask_m[31] << 28)
  331. | (mask_m[32] << 26) | (mask_m[33] << 24)
  332. | (mask_m[34] << 22) | (mask_m[35] << 20)
  333. | (mask_m[36] << 18) | (mask_m[37] << 16)
  334. | (mask_m[48] << 14) | (mask_m[39] << 12)
  335. | (mask_m[40] << 10) | (mask_m[41] << 8)
  336. | (mask_m[42] << 6) | (mask_m[43] << 4)
  337. | (mask_m[44] << 2) | (mask_m[45] << 0);
  338. REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
  339. REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
  340. tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
  341. | (mask_m[18] << 26) | (mask_m[18] << 24)
  342. | (mask_m[20] << 22) | (mask_m[20] << 20)
  343. | (mask_m[22] << 18) | (mask_m[22] << 16)
  344. | (mask_m[24] << 14) | (mask_m[24] << 12)
  345. | (mask_m[25] << 10) | (mask_m[26] << 8)
  346. | (mask_m[27] << 6) | (mask_m[28] << 4)
  347. | (mask_m[29] << 2) | (mask_m[30] << 0);
  348. REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
  349. REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
  350. tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
  351. | (mask_m[2] << 26) | (mask_m[3] << 24)
  352. | (mask_m[4] << 22) | (mask_m[5] << 20)
  353. | (mask_m[6] << 18) | (mask_m[7] << 16)
  354. | (mask_m[8] << 14) | (mask_m[9] << 12)
  355. | (mask_m[10] << 10) | (mask_m[11] << 8)
  356. | (mask_m[12] << 6) | (mask_m[13] << 4)
  357. | (mask_m[14] << 2) | (mask_m[15] << 0);
  358. REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
  359. REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
  360. tmp_mask = (mask_p[15] << 28)
  361. | (mask_p[14] << 26) | (mask_p[13] << 24)
  362. | (mask_p[12] << 22) | (mask_p[11] << 20)
  363. | (mask_p[10] << 18) | (mask_p[9] << 16)
  364. | (mask_p[8] << 14) | (mask_p[7] << 12)
  365. | (mask_p[6] << 10) | (mask_p[5] << 8)
  366. | (mask_p[4] << 6) | (mask_p[3] << 4)
  367. | (mask_p[2] << 2) | (mask_p[1] << 0);
  368. REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
  369. REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
  370. tmp_mask = (mask_p[30] << 28)
  371. | (mask_p[29] << 26) | (mask_p[28] << 24)
  372. | (mask_p[27] << 22) | (mask_p[26] << 20)
  373. | (mask_p[25] << 18) | (mask_p[24] << 16)
  374. | (mask_p[23] << 14) | (mask_p[22] << 12)
  375. | (mask_p[21] << 10) | (mask_p[20] << 8)
  376. | (mask_p[19] << 6) | (mask_p[18] << 4)
  377. | (mask_p[17] << 2) | (mask_p[16] << 0);
  378. REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
  379. REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
  380. tmp_mask = (mask_p[45] << 28)
  381. | (mask_p[44] << 26) | (mask_p[43] << 24)
  382. | (mask_p[42] << 22) | (mask_p[41] << 20)
  383. | (mask_p[40] << 18) | (mask_p[39] << 16)
  384. | (mask_p[38] << 14) | (mask_p[37] << 12)
  385. | (mask_p[36] << 10) | (mask_p[35] << 8)
  386. | (mask_p[34] << 6) | (mask_p[33] << 4)
  387. | (mask_p[32] << 2) | (mask_p[31] << 0);
  388. REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
  389. REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
  390. tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
  391. | (mask_p[59] << 26) | (mask_p[58] << 24)
  392. | (mask_p[57] << 22) | (mask_p[56] << 20)
  393. | (mask_p[55] << 18) | (mask_p[54] << 16)
  394. | (mask_p[53] << 14) | (mask_p[52] << 12)
  395. | (mask_p[51] << 10) | (mask_p[50] << 8)
  396. | (mask_p[49] << 6) | (mask_p[48] << 4)
  397. | (mask_p[47] << 2) | (mask_p[46] << 0);
  398. REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
  399. REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
  400. }
  401. /**
  402. * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
  403. * @ah: atheros hardware structure
  404. *
  405. * Only required for older devices with external AR2133/AR5133 radios.
  406. */
  407. static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
  408. {
  409. #define ATH_ALLOC_BANK(bank, size) do { \
  410. bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
  411. if (!bank) { \
  412. ath_err(common, "Cannot allocate RF banks\n"); \
  413. return -ENOMEM; \
  414. } \
  415. } while (0);
  416. struct ath_common *common = ath9k_hw_common(ah);
  417. BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
  418. ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
  419. ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
  420. ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
  421. ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
  422. ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
  423. ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
  424. ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
  425. ATH_ALLOC_BANK(ah->addac5416_21,
  426. ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
  427. ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
  428. return 0;
  429. #undef ATH_ALLOC_BANK
  430. }
  431. /**
  432. * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
  433. * @ah: atheros hardware struture
  434. * For the external AR2133/AR5133 radios banks.
  435. */
  436. static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
  437. {
  438. #define ATH_FREE_BANK(bank) do { \
  439. kfree(bank); \
  440. bank = NULL; \
  441. } while (0);
  442. BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
  443. ATH_FREE_BANK(ah->analogBank0Data);
  444. ATH_FREE_BANK(ah->analogBank1Data);
  445. ATH_FREE_BANK(ah->analogBank2Data);
  446. ATH_FREE_BANK(ah->analogBank3Data);
  447. ATH_FREE_BANK(ah->analogBank6Data);
  448. ATH_FREE_BANK(ah->analogBank6TPCData);
  449. ATH_FREE_BANK(ah->analogBank7Data);
  450. ATH_FREE_BANK(ah->addac5416_21);
  451. ATH_FREE_BANK(ah->bank6Temp);
  452. #undef ATH_FREE_BANK
  453. }
  454. /* *
  455. * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
  456. * @ah: atheros hardware structure
  457. * @chan:
  458. * @modesIndex:
  459. *
  460. * Used for the external AR2133/AR5133 radios.
  461. *
  462. * Reads the EEPROM header info from the device structure and programs
  463. * all rf registers. This routine requires access to the analog
  464. * rf device. This is not required for single-chip devices.
  465. */
  466. static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
  467. struct ath9k_channel *chan,
  468. u16 modesIndex)
  469. {
  470. u32 eepMinorRev;
  471. u32 ob5GHz = 0, db5GHz = 0;
  472. u32 ob2GHz = 0, db2GHz = 0;
  473. int regWrites = 0;
  474. /*
  475. * Software does not need to program bank data
  476. * for single chip devices, that is AR9280 or anything
  477. * after that.
  478. */
  479. if (AR_SREV_9280_20_OR_LATER(ah))
  480. return true;
  481. /* Setup rf parameters */
  482. eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
  483. /* Setup Bank 0 Write */
  484. ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
  485. /* Setup Bank 1 Write */
  486. ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
  487. /* Setup Bank 2 Write */
  488. ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
  489. /* Setup Bank 6 Write */
  490. ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
  491. modesIndex);
  492. {
  493. int i;
  494. for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
  495. ah->analogBank6Data[i] =
  496. INI_RA(&ah->iniBank6TPC, i, modesIndex);
  497. }
  498. }
  499. /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
  500. if (eepMinorRev >= 2) {
  501. if (IS_CHAN_2GHZ(chan)) {
  502. ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
  503. db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
  504. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
  505. ob2GHz, 3, 197, 0);
  506. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
  507. db2GHz, 3, 194, 0);
  508. } else {
  509. ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
  510. db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
  511. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
  512. ob5GHz, 3, 203, 0);
  513. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
  514. db5GHz, 3, 200, 0);
  515. }
  516. }
  517. /* Setup Bank 7 Setup */
  518. ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
  519. /* Write Analog registers */
  520. REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
  521. regWrites);
  522. REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
  523. regWrites);
  524. REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
  525. regWrites);
  526. REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
  527. regWrites);
  528. REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
  529. regWrites);
  530. REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
  531. regWrites);
  532. return true;
  533. }
  534. static void ar5008_hw_init_bb(struct ath_hw *ah,
  535. struct ath9k_channel *chan)
  536. {
  537. u32 synthDelay;
  538. synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
  539. if (IS_CHAN_B(chan))
  540. synthDelay = (4 * synthDelay) / 22;
  541. else
  542. synthDelay /= 10;
  543. if (IS_CHAN_HALF_RATE(chan))
  544. synthDelay *= 2;
  545. else if (IS_CHAN_QUARTER_RATE(chan))
  546. synthDelay *= 4;
  547. REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
  548. udelay(synthDelay + BASE_ACTIVATE_DELAY);
  549. }
  550. static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
  551. {
  552. int rx_chainmask, tx_chainmask;
  553. rx_chainmask = ah->rxchainmask;
  554. tx_chainmask = ah->txchainmask;
  555. switch (rx_chainmask) {
  556. case 0x5:
  557. REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
  558. AR_PHY_SWAP_ALT_CHAIN);
  559. case 0x3:
  560. if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
  561. REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
  562. REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
  563. break;
  564. }
  565. case 0x1:
  566. case 0x2:
  567. case 0x7:
  568. ENABLE_REGWRITE_BUFFER(ah);
  569. REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
  570. REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
  571. break;
  572. default:
  573. ENABLE_REGWRITE_BUFFER(ah);
  574. break;
  575. }
  576. REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
  577. REGWRITE_BUFFER_FLUSH(ah);
  578. if (tx_chainmask == 0x5) {
  579. REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
  580. AR_PHY_SWAP_ALT_CHAIN);
  581. }
  582. if (AR_SREV_9100(ah))
  583. REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
  584. REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
  585. }
  586. static void ar5008_hw_override_ini(struct ath_hw *ah,
  587. struct ath9k_channel *chan)
  588. {
  589. u32 val;
  590. /*
  591. * Set the RX_ABORT and RX_DIS and clear if off only after
  592. * RXE is set for MAC. This prevents frames with corrupted
  593. * descriptor status.
  594. */
  595. REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
  596. if (AR_SREV_9280_20_OR_LATER(ah)) {
  597. val = REG_READ(ah, AR_PCU_MISC_MODE2);
  598. if (!AR_SREV_9271(ah))
  599. val &= ~AR_PCU_MISC_MODE2_HWWAR1;
  600. if (AR_SREV_9287_11_OR_LATER(ah))
  601. val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
  602. REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
  603. }
  604. if (!AR_SREV_5416_20_OR_LATER(ah) ||
  605. AR_SREV_9280_20_OR_LATER(ah))
  606. return;
  607. /*
  608. * Disable BB clock gating
  609. * Necessary to avoid issues on AR5416 2.0
  610. */
  611. REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
  612. /*
  613. * Disable RIFS search on some chips to avoid baseband
  614. * hang issues.
  615. */
  616. if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
  617. val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
  618. val &= ~AR_PHY_RIFS_INIT_DELAY;
  619. REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
  620. }
  621. }
  622. static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
  623. struct ath9k_channel *chan)
  624. {
  625. u32 phymode;
  626. u32 enableDacFifo = 0;
  627. if (AR_SREV_9285_12_OR_LATER(ah))
  628. enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
  629. AR_PHY_FC_ENABLE_DAC_FIFO);
  630. phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
  631. | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
  632. if (IS_CHAN_HT40(chan)) {
  633. phymode |= AR_PHY_FC_DYN2040_EN;
  634. if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
  635. (chan->chanmode == CHANNEL_G_HT40PLUS))
  636. phymode |= AR_PHY_FC_DYN2040_PRI_CH;
  637. }
  638. REG_WRITE(ah, AR_PHY_TURBO, phymode);
  639. ath9k_hw_set11nmac2040(ah);
  640. ENABLE_REGWRITE_BUFFER(ah);
  641. REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
  642. REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
  643. REGWRITE_BUFFER_FLUSH(ah);
  644. }
  645. static int ar5008_hw_process_ini(struct ath_hw *ah,
  646. struct ath9k_channel *chan)
  647. {
  648. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  649. struct ath_common *common = ath9k_hw_common(ah);
  650. int i, regWrites = 0;
  651. struct ieee80211_channel *channel = chan->chan;
  652. u32 modesIndex, freqIndex;
  653. switch (chan->chanmode) {
  654. case CHANNEL_A:
  655. case CHANNEL_A_HT20:
  656. modesIndex = 1;
  657. freqIndex = 1;
  658. break;
  659. case CHANNEL_A_HT40PLUS:
  660. case CHANNEL_A_HT40MINUS:
  661. modesIndex = 2;
  662. freqIndex = 1;
  663. break;
  664. case CHANNEL_G:
  665. case CHANNEL_G_HT20:
  666. case CHANNEL_B:
  667. modesIndex = 4;
  668. freqIndex = 2;
  669. break;
  670. case CHANNEL_G_HT40PLUS:
  671. case CHANNEL_G_HT40MINUS:
  672. modesIndex = 3;
  673. freqIndex = 2;
  674. break;
  675. default:
  676. return -EINVAL;
  677. }
  678. /*
  679. * Set correct baseband to analog shift setting to
  680. * access analog chips.
  681. */
  682. REG_WRITE(ah, AR_PHY(0), 0x00000007);
  683. /* Write ADDAC shifts */
  684. REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
  685. ah->eep_ops->set_addac(ah, chan);
  686. if (AR_SREV_5416_22_OR_LATER(ah)) {
  687. REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
  688. } else {
  689. struct ar5416IniArray temp;
  690. u32 addacSize =
  691. sizeof(u32) * ah->iniAddac.ia_rows *
  692. ah->iniAddac.ia_columns;
  693. /* For AR5416 2.0/2.1 */
  694. memcpy(ah->addac5416_21,
  695. ah->iniAddac.ia_array, addacSize);
  696. /* override CLKDRV value at [row, column] = [31, 1] */
  697. (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
  698. temp.ia_array = ah->addac5416_21;
  699. temp.ia_columns = ah->iniAddac.ia_columns;
  700. temp.ia_rows = ah->iniAddac.ia_rows;
  701. REG_WRITE_ARRAY(&temp, 1, regWrites);
  702. }
  703. REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
  704. ENABLE_REGWRITE_BUFFER(ah);
  705. for (i = 0; i < ah->iniModes.ia_rows; i++) {
  706. u32 reg = INI_RA(&ah->iniModes, i, 0);
  707. u32 val = INI_RA(&ah->iniModes, i, modesIndex);
  708. if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
  709. val &= ~AR_AN_TOP2_PWDCLKIND;
  710. REG_WRITE(ah, reg, val);
  711. if (reg >= 0x7800 && reg < 0x78a0
  712. && ah->config.analog_shiftreg
  713. && (common->bus_ops->ath_bus_type != ATH_USB)) {
  714. udelay(100);
  715. }
  716. DO_DELAY(regWrites);
  717. }
  718. REGWRITE_BUFFER_FLUSH(ah);
  719. if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
  720. REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
  721. if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
  722. AR_SREV_9287_11_OR_LATER(ah))
  723. REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
  724. if (AR_SREV_9271_10(ah))
  725. REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
  726. modesIndex, regWrites);
  727. ENABLE_REGWRITE_BUFFER(ah);
  728. /* Write common array parameters */
  729. for (i = 0; i < ah->iniCommon.ia_rows; i++) {
  730. u32 reg = INI_RA(&ah->iniCommon, i, 0);
  731. u32 val = INI_RA(&ah->iniCommon, i, 1);
  732. REG_WRITE(ah, reg, val);
  733. if (reg >= 0x7800 && reg < 0x78a0
  734. && ah->config.analog_shiftreg
  735. && (common->bus_ops->ath_bus_type != ATH_USB)) {
  736. udelay(100);
  737. }
  738. DO_DELAY(regWrites);
  739. }
  740. REGWRITE_BUFFER_FLUSH(ah);
  741. if (AR_SREV_9271(ah)) {
  742. if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
  743. REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
  744. modesIndex, regWrites);
  745. else
  746. REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
  747. modesIndex, regWrites);
  748. }
  749. REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
  750. if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
  751. REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
  752. regWrites);
  753. }
  754. ar5008_hw_override_ini(ah, chan);
  755. ar5008_hw_set_channel_regs(ah, chan);
  756. ar5008_hw_init_chain_masks(ah);
  757. ath9k_olc_init(ah);
  758. /* Set TX power */
  759. ah->eep_ops->set_txpower(ah, chan,
  760. ath9k_regd_get_ctl(regulatory, chan),
  761. channel->max_antenna_gain * 2,
  762. channel->max_power * 2,
  763. min((u32) MAX_RATE_POWER,
  764. (u32) regulatory->power_limit), false);
  765. /* Write analog registers */
  766. if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
  767. ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
  768. return -EIO;
  769. }
  770. return 0;
  771. }
  772. static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
  773. {
  774. u32 rfMode = 0;
  775. if (chan == NULL)
  776. return;
  777. rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
  778. ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
  779. if (!AR_SREV_9280_20_OR_LATER(ah))
  780. rfMode |= (IS_CHAN_5GHZ(chan)) ?
  781. AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
  782. if (IS_CHAN_A_FAST_CLOCK(ah, chan))
  783. rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
  784. REG_WRITE(ah, AR_PHY_MODE, rfMode);
  785. }
  786. static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
  787. {
  788. REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
  789. }
  790. static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
  791. struct ath9k_channel *chan)
  792. {
  793. u32 coef_scaled, ds_coef_exp, ds_coef_man;
  794. u32 clockMhzScaled = 0x64000000;
  795. struct chan_centers centers;
  796. if (IS_CHAN_HALF_RATE(chan))
  797. clockMhzScaled = clockMhzScaled >> 1;
  798. else if (IS_CHAN_QUARTER_RATE(chan))
  799. clockMhzScaled = clockMhzScaled >> 2;
  800. ath9k_hw_get_channel_centers(ah, chan, &centers);
  801. coef_scaled = clockMhzScaled / centers.synth_center;
  802. ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
  803. &ds_coef_exp);
  804. REG_RMW_FIELD(ah, AR_PHY_TIMING3,
  805. AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
  806. REG_RMW_FIELD(ah, AR_PHY_TIMING3,
  807. AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
  808. coef_scaled = (9 * coef_scaled) / 10;
  809. ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
  810. &ds_coef_exp);
  811. REG_RMW_FIELD(ah, AR_PHY_HALFGI,
  812. AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
  813. REG_RMW_FIELD(ah, AR_PHY_HALFGI,
  814. AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
  815. }
  816. static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
  817. {
  818. REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
  819. return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
  820. AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
  821. }
  822. static void ar5008_hw_rfbus_done(struct ath_hw *ah)
  823. {
  824. u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
  825. if (IS_CHAN_B(ah->curchan))
  826. synthDelay = (4 * synthDelay) / 22;
  827. else
  828. synthDelay /= 10;
  829. udelay(synthDelay + BASE_ACTIVATE_DELAY);
  830. REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
  831. }
  832. static void ar5008_restore_chainmask(struct ath_hw *ah)
  833. {
  834. int rx_chainmask = ah->rxchainmask;
  835. if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
  836. REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
  837. REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
  838. }
  839. }
  840. static void ar5008_set_diversity(struct ath_hw *ah, bool value)
  841. {
  842. u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
  843. if (value)
  844. v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
  845. else
  846. v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
  847. REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
  848. }
  849. static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
  850. struct ath9k_channel *chan)
  851. {
  852. if (chan && IS_CHAN_5GHZ(chan))
  853. return 0x1450;
  854. return 0x1458;
  855. }
  856. static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
  857. struct ath9k_channel *chan)
  858. {
  859. u32 pll;
  860. pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
  861. if (chan && IS_CHAN_HALF_RATE(chan))
  862. pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
  863. else if (chan && IS_CHAN_QUARTER_RATE(chan))
  864. pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
  865. if (chan && IS_CHAN_5GHZ(chan))
  866. pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
  867. else
  868. pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
  869. return pll;
  870. }
  871. static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
  872. struct ath9k_channel *chan)
  873. {
  874. u32 pll;
  875. pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
  876. if (chan && IS_CHAN_HALF_RATE(chan))
  877. pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
  878. else if (chan && IS_CHAN_QUARTER_RATE(chan))
  879. pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
  880. if (chan && IS_CHAN_5GHZ(chan))
  881. pll |= SM(0xa, AR_RTC_PLL_DIV);
  882. else
  883. pll |= SM(0xb, AR_RTC_PLL_DIV);
  884. return pll;
  885. }
  886. static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
  887. enum ath9k_ani_cmd cmd,
  888. int param)
  889. {
  890. struct ar5416AniState *aniState = &ah->curchan->ani;
  891. struct ath_common *common = ath9k_hw_common(ah);
  892. switch (cmd & ah->ani_function) {
  893. case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
  894. u32 level = param;
  895. if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
  896. ath_dbg(common, ATH_DBG_ANI,
  897. "level out of range (%u > %zu)\n",
  898. level, ARRAY_SIZE(ah->totalSizeDesired));
  899. return false;
  900. }
  901. REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
  902. AR_PHY_DESIRED_SZ_TOT_DES,
  903. ah->totalSizeDesired[level]);
  904. REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
  905. AR_PHY_AGC_CTL1_COARSE_LOW,
  906. ah->coarse_low[level]);
  907. REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
  908. AR_PHY_AGC_CTL1_COARSE_HIGH,
  909. ah->coarse_high[level]);
  910. REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
  911. AR_PHY_FIND_SIG_FIRPWR,
  912. ah->firpwr[level]);
  913. if (level > aniState->noiseImmunityLevel)
  914. ah->stats.ast_ani_niup++;
  915. else if (level < aniState->noiseImmunityLevel)
  916. ah->stats.ast_ani_nidown++;
  917. aniState->noiseImmunityLevel = level;
  918. break;
  919. }
  920. case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
  921. static const int m1ThreshLow[] = { 127, 50 };
  922. static const int m2ThreshLow[] = { 127, 40 };
  923. static const int m1Thresh[] = { 127, 0x4d };
  924. static const int m2Thresh[] = { 127, 0x40 };
  925. static const int m2CountThr[] = { 31, 16 };
  926. static const int m2CountThrLow[] = { 63, 48 };
  927. u32 on = param ? 1 : 0;
  928. REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
  929. AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
  930. m1ThreshLow[on]);
  931. REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
  932. AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
  933. m2ThreshLow[on]);
  934. REG_RMW_FIELD(ah, AR_PHY_SFCORR,
  935. AR_PHY_SFCORR_M1_THRESH,
  936. m1Thresh[on]);
  937. REG_RMW_FIELD(ah, AR_PHY_SFCORR,
  938. AR_PHY_SFCORR_M2_THRESH,
  939. m2Thresh[on]);
  940. REG_RMW_FIELD(ah, AR_PHY_SFCORR,
  941. AR_PHY_SFCORR_M2COUNT_THR,
  942. m2CountThr[on]);
  943. REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
  944. AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
  945. m2CountThrLow[on]);
  946. REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
  947. AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
  948. m1ThreshLow[on]);
  949. REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
  950. AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
  951. m2ThreshLow[on]);
  952. REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
  953. AR_PHY_SFCORR_EXT_M1_THRESH,
  954. m1Thresh[on]);
  955. REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
  956. AR_PHY_SFCORR_EXT_M2_THRESH,
  957. m2Thresh[on]);
  958. if (on)
  959. REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
  960. AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
  961. else
  962. REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
  963. AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
  964. if (!on != aniState->ofdmWeakSigDetectOff) {
  965. if (on)
  966. ah->stats.ast_ani_ofdmon++;
  967. else
  968. ah->stats.ast_ani_ofdmoff++;
  969. aniState->ofdmWeakSigDetectOff = !on;
  970. }
  971. break;
  972. }
  973. case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
  974. static const int weakSigThrCck[] = { 8, 6 };
  975. u32 high = param ? 1 : 0;
  976. REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
  977. AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
  978. weakSigThrCck[high]);
  979. if (high != aniState->cckWeakSigThreshold) {
  980. if (high)
  981. ah->stats.ast_ani_cckhigh++;
  982. else
  983. ah->stats.ast_ani_ccklow++;
  984. aniState->cckWeakSigThreshold = high;
  985. }
  986. break;
  987. }
  988. case ATH9K_ANI_FIRSTEP_LEVEL:{
  989. static const int firstep[] = { 0, 4, 8 };
  990. u32 level = param;
  991. if (level >= ARRAY_SIZE(firstep)) {
  992. ath_dbg(common, ATH_DBG_ANI,
  993. "level out of range (%u > %zu)\n",
  994. level, ARRAY_SIZE(firstep));
  995. return false;
  996. }
  997. REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
  998. AR_PHY_FIND_SIG_FIRSTEP,
  999. firstep[level]);
  1000. if (level > aniState->firstepLevel)
  1001. ah->stats.ast_ani_stepup++;
  1002. else if (level < aniState->firstepLevel)
  1003. ah->stats.ast_ani_stepdown++;
  1004. aniState->firstepLevel = level;
  1005. break;
  1006. }
  1007. case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
  1008. static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
  1009. u32 level = param;
  1010. if (level >= ARRAY_SIZE(cycpwrThr1)) {
  1011. ath_dbg(common, ATH_DBG_ANI,
  1012. "level out of range (%u > %zu)\n",
  1013. level, ARRAY_SIZE(cycpwrThr1));
  1014. return false;
  1015. }
  1016. REG_RMW_FIELD(ah, AR_PHY_TIMING5,
  1017. AR_PHY_TIMING5_CYCPWR_THR1,
  1018. cycpwrThr1[level]);
  1019. if (level > aniState->spurImmunityLevel)
  1020. ah->stats.ast_ani_spurup++;
  1021. else if (level < aniState->spurImmunityLevel)
  1022. ah->stats.ast_ani_spurdown++;
  1023. aniState->spurImmunityLevel = level;
  1024. break;
  1025. }
  1026. case ATH9K_ANI_PRESENT:
  1027. break;
  1028. default:
  1029. ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
  1030. return false;
  1031. }
  1032. ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n");
  1033. ath_dbg(common, ATH_DBG_ANI,
  1034. "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
  1035. aniState->noiseImmunityLevel,
  1036. aniState->spurImmunityLevel,
  1037. !aniState->ofdmWeakSigDetectOff);
  1038. ath_dbg(common, ATH_DBG_ANI,
  1039. "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
  1040. aniState->cckWeakSigThreshold,
  1041. aniState->firstepLevel,
  1042. aniState->listenTime);
  1043. ath_dbg(common, ATH_DBG_ANI,
  1044. "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
  1045. aniState->ofdmPhyErrCount,
  1046. aniState->cckPhyErrCount);
  1047. return true;
  1048. }
  1049. static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
  1050. enum ath9k_ani_cmd cmd,
  1051. int param)
  1052. {
  1053. struct ath_common *common = ath9k_hw_common(ah);
  1054. struct ath9k_channel *chan = ah->curchan;
  1055. struct ar5416AniState *aniState = &chan->ani;
  1056. s32 value, value2;
  1057. switch (cmd & ah->ani_function) {
  1058. case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
  1059. /*
  1060. * on == 1 means ofdm weak signal detection is ON
  1061. * on == 1 is the default, for less noise immunity
  1062. *
  1063. * on == 0 means ofdm weak signal detection is OFF
  1064. * on == 0 means more noise imm
  1065. */
  1066. u32 on = param ? 1 : 0;
  1067. /*
  1068. * make register setting for default
  1069. * (weak sig detect ON) come from INI file
  1070. */
  1071. int m1ThreshLow = on ?
  1072. aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
  1073. int m2ThreshLow = on ?
  1074. aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
  1075. int m1Thresh = on ?
  1076. aniState->iniDef.m1Thresh : m1Thresh_off;
  1077. int m2Thresh = on ?
  1078. aniState->iniDef.m2Thresh : m2Thresh_off;
  1079. int m2CountThr = on ?
  1080. aniState->iniDef.m2CountThr : m2CountThr_off;
  1081. int m2CountThrLow = on ?
  1082. aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
  1083. int m1ThreshLowExt = on ?
  1084. aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
  1085. int m2ThreshLowExt = on ?
  1086. aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
  1087. int m1ThreshExt = on ?
  1088. aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
  1089. int m2ThreshExt = on ?
  1090. aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
  1091. REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
  1092. AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
  1093. m1ThreshLow);
  1094. REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
  1095. AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
  1096. m2ThreshLow);
  1097. REG_RMW_FIELD(ah, AR_PHY_SFCORR,
  1098. AR_PHY_SFCORR_M1_THRESH, m1Thresh);
  1099. REG_RMW_FIELD(ah, AR_PHY_SFCORR,
  1100. AR_PHY_SFCORR_M2_THRESH, m2Thresh);
  1101. REG_RMW_FIELD(ah, AR_PHY_SFCORR,
  1102. AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
  1103. REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
  1104. AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
  1105. m2CountThrLow);
  1106. REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
  1107. AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
  1108. REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
  1109. AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
  1110. REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
  1111. AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
  1112. REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
  1113. AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
  1114. if (on)
  1115. REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
  1116. AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
  1117. else
  1118. REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
  1119. AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
  1120. if (!on != aniState->ofdmWeakSigDetectOff) {
  1121. ath_dbg(common, ATH_DBG_ANI,
  1122. "** ch %d: ofdm weak signal: %s=>%s\n",
  1123. chan->channel,
  1124. !aniState->ofdmWeakSigDetectOff ?
  1125. "on" : "off",
  1126. on ? "on" : "off");
  1127. if (on)
  1128. ah->stats.ast_ani_ofdmon++;
  1129. else
  1130. ah->stats.ast_ani_ofdmoff++;
  1131. aniState->ofdmWeakSigDetectOff = !on;
  1132. }
  1133. break;
  1134. }
  1135. case ATH9K_ANI_FIRSTEP_LEVEL:{
  1136. u32 level = param;
  1137. if (level >= ARRAY_SIZE(firstep_table)) {
  1138. ath_dbg(common, ATH_DBG_ANI,
  1139. "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
  1140. level, ARRAY_SIZE(firstep_table));
  1141. return false;
  1142. }
  1143. /*
  1144. * make register setting relative to default
  1145. * from INI file & cap value
  1146. */
  1147. value = firstep_table[level] -
  1148. firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
  1149. aniState->iniDef.firstep;
  1150. if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
  1151. value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
  1152. if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
  1153. value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
  1154. REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
  1155. AR_PHY_FIND_SIG_FIRSTEP,
  1156. value);
  1157. /*
  1158. * we need to set first step low register too
  1159. * make register setting relative to default
  1160. * from INI file & cap value
  1161. */
  1162. value2 = firstep_table[level] -
  1163. firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
  1164. aniState->iniDef.firstepLow;
  1165. if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
  1166. value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
  1167. if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
  1168. value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
  1169. REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
  1170. AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
  1171. if (level != aniState->firstepLevel) {
  1172. ath_dbg(common, ATH_DBG_ANI,
  1173. "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
  1174. chan->channel,
  1175. aniState->firstepLevel,
  1176. level,
  1177. ATH9K_ANI_FIRSTEP_LVL_NEW,
  1178. value,
  1179. aniState->iniDef.firstep);
  1180. ath_dbg(common, ATH_DBG_ANI,
  1181. "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
  1182. chan->channel,
  1183. aniState->firstepLevel,
  1184. level,
  1185. ATH9K_ANI_FIRSTEP_LVL_NEW,
  1186. value2,
  1187. aniState->iniDef.firstepLow);
  1188. if (level > aniState->firstepLevel)
  1189. ah->stats.ast_ani_stepup++;
  1190. else if (level < aniState->firstepLevel)
  1191. ah->stats.ast_ani_stepdown++;
  1192. aniState->firstepLevel = level;
  1193. }
  1194. break;
  1195. }
  1196. case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
  1197. u32 level = param;
  1198. if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
  1199. ath_dbg(common, ATH_DBG_ANI,
  1200. "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
  1201. level, ARRAY_SIZE(cycpwrThr1_table));
  1202. return false;
  1203. }
  1204. /*
  1205. * make register setting relative to default
  1206. * from INI file & cap value
  1207. */
  1208. value = cycpwrThr1_table[level] -
  1209. cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
  1210. aniState->iniDef.cycpwrThr1;
  1211. if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
  1212. value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
  1213. if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
  1214. value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
  1215. REG_RMW_FIELD(ah, AR_PHY_TIMING5,
  1216. AR_PHY_TIMING5_CYCPWR_THR1,
  1217. value);
  1218. /*
  1219. * set AR_PHY_EXT_CCA for extension channel
  1220. * make register setting relative to default
  1221. * from INI file & cap value
  1222. */
  1223. value2 = cycpwrThr1_table[level] -
  1224. cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
  1225. aniState->iniDef.cycpwrThr1Ext;
  1226. if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
  1227. value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
  1228. if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
  1229. value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
  1230. REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
  1231. AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
  1232. if (level != aniState->spurImmunityLevel) {
  1233. ath_dbg(common, ATH_DBG_ANI,
  1234. "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
  1235. chan->channel,
  1236. aniState->spurImmunityLevel,
  1237. level,
  1238. ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
  1239. value,
  1240. aniState->iniDef.cycpwrThr1);
  1241. ath_dbg(common, ATH_DBG_ANI,
  1242. "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
  1243. chan->channel,
  1244. aniState->spurImmunityLevel,
  1245. level,
  1246. ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
  1247. value2,
  1248. aniState->iniDef.cycpwrThr1Ext);
  1249. if (level > aniState->spurImmunityLevel)
  1250. ah->stats.ast_ani_spurup++;
  1251. else if (level < aniState->spurImmunityLevel)
  1252. ah->stats.ast_ani_spurdown++;
  1253. aniState->spurImmunityLevel = level;
  1254. }
  1255. break;
  1256. }
  1257. case ATH9K_ANI_MRC_CCK:
  1258. /*
  1259. * You should not see this as AR5008, AR9001, AR9002
  1260. * does not have hardware support for MRC CCK.
  1261. */
  1262. WARN_ON(1);
  1263. break;
  1264. case ATH9K_ANI_PRESENT:
  1265. break;
  1266. default:
  1267. ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
  1268. return false;
  1269. }
  1270. ath_dbg(common, ATH_DBG_ANI,
  1271. "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
  1272. aniState->spurImmunityLevel,
  1273. !aniState->ofdmWeakSigDetectOff ? "on" : "off",
  1274. aniState->firstepLevel,
  1275. !aniState->mrcCCKOff ? "on" : "off",
  1276. aniState->listenTime,
  1277. aniState->ofdmPhyErrCount,
  1278. aniState->cckPhyErrCount);
  1279. return true;
  1280. }
  1281. static void ar5008_hw_do_getnf(struct ath_hw *ah,
  1282. int16_t nfarray[NUM_NF_READINGS])
  1283. {
  1284. int16_t nf;
  1285. nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
  1286. nfarray[0] = sign_extend32(nf, 8);
  1287. nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
  1288. nfarray[1] = sign_extend32(nf, 8);
  1289. nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
  1290. nfarray[2] = sign_extend32(nf, 8);
  1291. if (!IS_CHAN_HT40(ah->curchan))
  1292. return;
  1293. nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
  1294. nfarray[3] = sign_extend32(nf, 8);
  1295. nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
  1296. nfarray[4] = sign_extend32(nf, 8);
  1297. nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
  1298. nfarray[5] = sign_extend32(nf, 8);
  1299. }
  1300. /*
  1301. * Initialize the ANI register values with default (ini) values.
  1302. * This routine is called during a (full) hardware reset after
  1303. * all the registers are initialised from the INI.
  1304. */
  1305. static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
  1306. {
  1307. struct ath_common *common = ath9k_hw_common(ah);
  1308. struct ath9k_channel *chan = ah->curchan;
  1309. struct ar5416AniState *aniState = &chan->ani;
  1310. struct ath9k_ani_default *iniDef;
  1311. u32 val;
  1312. iniDef = &aniState->iniDef;
  1313. ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
  1314. ah->hw_version.macVersion,
  1315. ah->hw_version.macRev,
  1316. ah->opmode,
  1317. chan->channel,
  1318. chan->channelFlags);
  1319. val = REG_READ(ah, AR_PHY_SFCORR);
  1320. iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
  1321. iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
  1322. iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
  1323. val = REG_READ(ah, AR_PHY_SFCORR_LOW);
  1324. iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
  1325. iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
  1326. iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
  1327. val = REG_READ(ah, AR_PHY_SFCORR_EXT);
  1328. iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
  1329. iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
  1330. iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
  1331. iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
  1332. iniDef->firstep = REG_READ_FIELD(ah,
  1333. AR_PHY_FIND_SIG,
  1334. AR_PHY_FIND_SIG_FIRSTEP);
  1335. iniDef->firstepLow = REG_READ_FIELD(ah,
  1336. AR_PHY_FIND_SIG_LOW,
  1337. AR_PHY_FIND_SIG_FIRSTEP_LOW);
  1338. iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
  1339. AR_PHY_TIMING5,
  1340. AR_PHY_TIMING5_CYCPWR_THR1);
  1341. iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
  1342. AR_PHY_EXT_CCA,
  1343. AR_PHY_EXT_TIMING5_CYCPWR_THR1);
  1344. /* these levels just got reset to defaults by the INI */
  1345. aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
  1346. aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
  1347. aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
  1348. aniState->mrcCCKOff = true; /* not available on pre AR9003 */
  1349. }
  1350. static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
  1351. {
  1352. ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
  1353. ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
  1354. ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
  1355. ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
  1356. ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
  1357. ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
  1358. }
  1359. static void ar5008_hw_set_radar_params(struct ath_hw *ah,
  1360. struct ath_hw_radar_conf *conf)
  1361. {
  1362. u32 radar_0 = 0, radar_1 = 0;
  1363. if (!conf) {
  1364. REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
  1365. return;
  1366. }
  1367. radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
  1368. radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
  1369. radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
  1370. radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
  1371. radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
  1372. radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
  1373. radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
  1374. radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
  1375. radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
  1376. radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
  1377. radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
  1378. REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
  1379. REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
  1380. if (conf->ext_channel)
  1381. REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
  1382. else
  1383. REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
  1384. }
  1385. static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
  1386. {
  1387. struct ath_hw_radar_conf *conf = &ah->radar_conf;
  1388. conf->fir_power = -33;
  1389. conf->radar_rssi = 20;
  1390. conf->pulse_height = 10;
  1391. conf->pulse_rssi = 24;
  1392. conf->pulse_inband = 15;
  1393. conf->pulse_maxlen = 255;
  1394. conf->pulse_inband_step = 12;
  1395. conf->radar_inband = 8;
  1396. }
  1397. void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
  1398. {
  1399. struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  1400. static const u32 ar5416_cca_regs[6] = {
  1401. AR_PHY_CCA,
  1402. AR_PHY_CH1_CCA,
  1403. AR_PHY_CH2_CCA,
  1404. AR_PHY_EXT_CCA,
  1405. AR_PHY_CH1_EXT_CCA,
  1406. AR_PHY_CH2_EXT_CCA
  1407. };
  1408. priv_ops->rf_set_freq = ar5008_hw_set_channel;
  1409. priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
  1410. priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
  1411. priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
  1412. priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
  1413. priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
  1414. priv_ops->init_bb = ar5008_hw_init_bb;
  1415. priv_ops->process_ini = ar5008_hw_process_ini;
  1416. priv_ops->set_rfmode = ar5008_hw_set_rfmode;
  1417. priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
  1418. priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
  1419. priv_ops->rfbus_req = ar5008_hw_rfbus_req;
  1420. priv_ops->rfbus_done = ar5008_hw_rfbus_done;
  1421. priv_ops->restore_chainmask = ar5008_restore_chainmask;
  1422. priv_ops->set_diversity = ar5008_set_diversity;
  1423. priv_ops->do_getnf = ar5008_hw_do_getnf;
  1424. priv_ops->set_radar_params = ar5008_hw_set_radar_params;
  1425. if (modparam_force_new_ani) {
  1426. priv_ops->ani_control = ar5008_hw_ani_control_new;
  1427. priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
  1428. } else
  1429. priv_ops->ani_control = ar5008_hw_ani_control_old;
  1430. if (AR_SREV_9100(ah))
  1431. priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
  1432. else if (AR_SREV_9160_10_OR_LATER(ah))
  1433. priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
  1434. else
  1435. priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
  1436. ar5008_hw_set_nf_limits(ah);
  1437. ar5008_hw_set_radar_conf(ah);
  1438. memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
  1439. }