mcdi_pcol.h 60 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2009-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #ifndef MCDI_PCOL_H
  10. #define MCDI_PCOL_H
  11. /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
  12. /* Power-on reset state */
  13. #define MC_FW_STATE_POR (1)
  14. /* If this is set in MC_RESET_STATE_REG then it should be
  15. * possible to jump into IMEM without loading code from flash. */
  16. #define MC_FW_WARM_BOOT_OK (2)
  17. /* The MC main image has started to boot. */
  18. #define MC_FW_STATE_BOOTING (4)
  19. /* The Scheduler has started. */
  20. #define MC_FW_STATE_SCHED (8)
  21. /* Values to be written to the per-port status dword in shared
  22. * memory on reboot and assert */
  23. #define MC_STATUS_DWORD_REBOOT (0xb007b007)
  24. #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
  25. /* The current version of the MCDI protocol.
  26. *
  27. * Note that the ROM burnt into the card only talks V0, so at the very
  28. * least every driver must support version 0 and MCDI_PCOL_VERSION
  29. */
  30. #define MCDI_PCOL_VERSION 1
  31. /**
  32. * MCDI version 1
  33. *
  34. * Each MCDI request starts with an MCDI_HEADER, which is a 32byte
  35. * structure, filled in by the client.
  36. *
  37. * 0 7 8 16 20 22 23 24 31
  38. * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
  39. * | | |
  40. * | | \--- Response
  41. * | \------- Error
  42. * \------------------------------ Resync (always set)
  43. *
  44. * The client writes it's request into MC shared memory, and rings the
  45. * doorbell. Each request is completed by either by the MC writting
  46. * back into shared memory, or by writting out an event.
  47. *
  48. * All MCDI commands support completion by shared memory response. Each
  49. * request may also contain additional data (accounted for by HEADER.LEN),
  50. * and some response's may also contain additional data (again, accounted
  51. * for by HEADER.LEN).
  52. *
  53. * Some MCDI commands support completion by event, in which any associated
  54. * response data is included in the event.
  55. *
  56. * The protocol requires one response to be delivered for every request, a
  57. * request should not be sent unless the response for the previous request
  58. * has been received (either by polling shared memory, or by receiving
  59. * an event).
  60. */
  61. /** Request/Response structure */
  62. #define MCDI_HEADER_OFST 0
  63. #define MCDI_HEADER_CODE_LBN 0
  64. #define MCDI_HEADER_CODE_WIDTH 7
  65. #define MCDI_HEADER_RESYNC_LBN 7
  66. #define MCDI_HEADER_RESYNC_WIDTH 1
  67. #define MCDI_HEADER_DATALEN_LBN 8
  68. #define MCDI_HEADER_DATALEN_WIDTH 8
  69. #define MCDI_HEADER_SEQ_LBN 16
  70. #define MCDI_HEADER_RSVD_LBN 20
  71. #define MCDI_HEADER_RSVD_WIDTH 2
  72. #define MCDI_HEADER_SEQ_WIDTH 4
  73. #define MCDI_HEADER_ERROR_LBN 22
  74. #define MCDI_HEADER_ERROR_WIDTH 1
  75. #define MCDI_HEADER_RESPONSE_LBN 23
  76. #define MCDI_HEADER_RESPONSE_WIDTH 1
  77. #define MCDI_HEADER_XFLAGS_LBN 24
  78. #define MCDI_HEADER_XFLAGS_WIDTH 8
  79. /* Request response using event */
  80. #define MCDI_HEADER_XFLAGS_EVREQ 0x01
  81. /* Maximum number of payload bytes */
  82. #define MCDI_CTL_SDU_LEN_MAX 0xfc
  83. /* The MC can generate events for two reasons:
  84. * - To complete a shared memory request if XFLAGS_EVREQ was set
  85. * - As a notification (link state, i2c event), controlled
  86. * via MC_CMD_LOG_CTRL
  87. *
  88. * Both events share a common structure:
  89. *
  90. * 0 32 33 36 44 52 60
  91. * | Data | Cont | Level | Src | Code | Rsvd |
  92. * |
  93. * \ There is another event pending in this notification
  94. *
  95. * If Code==CMDDONE, then the fields are further interpreted as:
  96. *
  97. * - LEVEL==INFO Command succeeded
  98. * - LEVEL==ERR Command failed
  99. *
  100. * 0 8 16 24 32
  101. * | Seq | Datalen | Errno | Rsvd |
  102. *
  103. * These fields are taken directly out of the standard MCDI header, i.e.,
  104. * LEVEL==ERR, Datalen == 0 => Reboot
  105. *
  106. * Events can be squirted out of the UART (using LOG_CTRL) without a
  107. * MCDI header. An event can be distinguished from a MCDI response by
  108. * examining the first byte which is 0xc0. This corresponds to the
  109. * non-existent MCDI command MC_CMD_DEBUG_LOG.
  110. *
  111. * 0 7 8
  112. * | command | Resync | = 0xc0
  113. *
  114. * Since the event is written in big-endian byte order, this works
  115. * providing bits 56-63 of the event are 0xc0.
  116. *
  117. * 56 60 63
  118. * | Rsvd | Code | = 0xc0
  119. *
  120. * Which means for convenience the event code is 0xc for all MC
  121. * generated events.
  122. */
  123. #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
  124. #define MCDI_EVENT_DATA_LBN 0
  125. #define MCDI_EVENT_DATA_WIDTH 32
  126. #define MCDI_EVENT_CONT_LBN 32
  127. #define MCDI_EVENT_CONT_WIDTH 1
  128. #define MCDI_EVENT_LEVEL_LBN 33
  129. #define MCDI_EVENT_LEVEL_WIDTH 3
  130. #define MCDI_EVENT_LEVEL_INFO (0)
  131. #define MCDI_EVENT_LEVEL_WARN (1)
  132. #define MCDI_EVENT_LEVEL_ERR (2)
  133. #define MCDI_EVENT_LEVEL_FATAL (3)
  134. #define MCDI_EVENT_SRC_LBN 36
  135. #define MCDI_EVENT_SRC_WIDTH 8
  136. #define MCDI_EVENT_CODE_LBN 44
  137. #define MCDI_EVENT_CODE_WIDTH 8
  138. #define MCDI_EVENT_CODE_BADSSERT (1)
  139. #define MCDI_EVENT_CODE_PMNOTICE (2)
  140. #define MCDI_EVENT_CODE_CMDDONE (3)
  141. #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
  142. #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
  143. #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
  144. #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
  145. #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
  146. #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
  147. #define MCDI_EVENT_CODE_LINKCHANGE (4)
  148. #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
  149. #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
  150. #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
  151. #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
  152. #define MCDI_EVENT_LINKCHANGE_SPEED_100M 1
  153. #define MCDI_EVENT_LINKCHANGE_SPEED_1G 2
  154. #define MCDI_EVENT_LINKCHANGE_SPEED_10G 3
  155. #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
  156. #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
  157. #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
  158. #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
  159. #define MCDI_EVENT_CODE_SENSOREVT (5)
  160. #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
  161. #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
  162. #define MCDI_EVENT_SENSOREVT_STATE_LBN 8
  163. #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
  164. #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
  165. #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
  166. #define MCDI_EVENT_CODE_SCHEDERR (6)
  167. #define MCDI_EVENT_CODE_REBOOT (7)
  168. #define MCDI_EVENT_CODE_MAC_STATS_DMA (8)
  169. #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
  170. #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
  171. /* Non-existent command target */
  172. #define MC_CMD_ERR_ENOENT 2
  173. /* assert() has killed the MC */
  174. #define MC_CMD_ERR_EINTR 4
  175. /* Caller does not hold required locks */
  176. #define MC_CMD_ERR_EACCES 13
  177. /* Resource is currently unavailable (e.g. lock contention) */
  178. #define MC_CMD_ERR_EBUSY 16
  179. /* Invalid argument to target */
  180. #define MC_CMD_ERR_EINVAL 22
  181. /* Non-recursive resource is already acquired */
  182. #define MC_CMD_ERR_EDEADLK 35
  183. /* Operation not implemented */
  184. #define MC_CMD_ERR_ENOSYS 38
  185. /* Operation timed out */
  186. #define MC_CMD_ERR_ETIME 62
  187. #define MC_CMD_ERR_CODE_OFST 0
  188. /* MC_CMD_READ32: (debug, variadic out)
  189. * Read multiple 32byte words from MC memory
  190. */
  191. #define MC_CMD_READ32 0x01
  192. #define MC_CMD_READ32_IN_LEN 8
  193. #define MC_CMD_READ32_IN_ADDR_OFST 0
  194. #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
  195. #define MC_CMD_READ32_OUT_LEN(_numwords) \
  196. (4 * (_numwords))
  197. #define MC_CMD_READ32_OUT_BUFFER_OFST 0
  198. /* MC_CMD_WRITE32: (debug, variadic in)
  199. * Write multiple 32byte words to MC memory
  200. */
  201. #define MC_CMD_WRITE32 0x02
  202. #define MC_CMD_WRITE32_IN_LEN(_numwords) (((_numwords) * 4) + 4)
  203. #define MC_CMD_WRITE32_IN_ADDR_OFST 0
  204. #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
  205. #define MC_CMD_WRITE32_OUT_LEN 0
  206. /* MC_CMD_COPYCODE: (debug)
  207. * Copy MC code between two locations and jump
  208. */
  209. #define MC_CMD_COPYCODE 0x03
  210. #define MC_CMD_COPYCODE_IN_LEN 16
  211. #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
  212. #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
  213. #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
  214. #define MC_CMD_COPYCODE_IN_JUMP_OFST 12
  215. /* Control should return to the caller rather than jumping */
  216. #define MC_CMD_COPYCODE_JUMP_NONE 1
  217. #define MC_CMD_COPYCODE_OUT_LEN 0
  218. /* MC_CMD_SET_FUNC: (debug)
  219. * Select function for function-specific commands.
  220. */
  221. #define MC_CMD_SET_FUNC 0x04
  222. #define MC_CMD_SET_FUNC_IN_LEN 4
  223. #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
  224. #define MC_CMD_SET_FUNC_OUT_LEN 0
  225. /* MC_CMD_GET_BOOT_STATUS:
  226. * Get the instruction address from which the MC booted.
  227. */
  228. #define MC_CMD_GET_BOOT_STATUS 0x05
  229. #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
  230. #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
  231. #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
  232. #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
  233. /* Reboot caused by watchdog */
  234. #define MC_CMD_GET_BOOT_STATUS_FLAGS_WATCHDOG_LBN (0)
  235. #define MC_CMD_GET_BOOT_STATUS_FLAGS_WATCHDOG_WIDTH (1)
  236. /* MC booted from primary flash partition */
  237. #define MC_CMD_GET_BOOT_STATUS_FLAGS_PRIMARY_LBN (1)
  238. #define MC_CMD_GET_BOOT_STATUS_FLAGS_PRIMARY_WIDTH (1)
  239. /* MC booted from backup flash partition */
  240. #define MC_CMD_GET_BOOT_STATUS_FLAGS_BACKUP_LBN (2)
  241. #define MC_CMD_GET_BOOT_STATUS_FLAGS_BACKUP_WIDTH (1)
  242. /* MC_CMD_GET_ASSERTS: (debug, variadic out)
  243. * Get (and optionally clear) the current assertion status.
  244. *
  245. * Only OUT.GLOBAL_FLAGS is guaranteed to exist in the completion
  246. * payload. The other fields will only be present if
  247. * OUT.GLOBAL_FLAGS != NO_FAILS
  248. */
  249. #define MC_CMD_GET_ASSERTS 0x06
  250. #define MC_CMD_GET_ASSERTS_IN_LEN 4
  251. #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
  252. #define MC_CMD_GET_ASSERTS_OUT_LEN 140
  253. /* Assertion status flag */
  254. #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
  255. /*! No assertions have failed. */
  256. #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 1
  257. /*! A system-level assertion has failed. */
  258. #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 2
  259. /*! A thread-level assertion has failed. */
  260. #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 3
  261. /*! The system was reset by the watchdog. */
  262. #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 4
  263. /* Failing PC value */
  264. #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
  265. /* Saved GP regs */
  266. #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
  267. #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_LEN 124
  268. /* Failing thread address */
  269. #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
  270. /* MC_CMD_LOG_CTRL:
  271. * Determine the output stream for various events and messages
  272. */
  273. #define MC_CMD_LOG_CTRL 0x07
  274. #define MC_CMD_LOG_CTRL_IN_LEN 8
  275. #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
  276. #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART (1)
  277. #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ (2)
  278. #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
  279. #define MC_CMD_LOG_CTRL_OUT_LEN 0
  280. /* MC_CMD_GET_VERSION:
  281. * Get version information about the MC firmware
  282. */
  283. #define MC_CMD_GET_VERSION 0x08
  284. #define MC_CMD_GET_VERSION_IN_LEN 0
  285. #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
  286. #define MC_CMD_GET_VERSION_V1_OUT_LEN 32
  287. #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
  288. /* Reserved version number to indicate "any" version. */
  289. #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
  290. /* The version response of a boot ROM awaiting rescue */
  291. #define MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000
  292. #define MC_CMD_GET_VERSION_V1_OUT_PCOL_OFST 4
  293. /* 128bit mask of functions supported by the current firmware */
  294. #define MC_CMD_GET_VERSION_V1_OUT_SUPPORTED_FUNCS_OFST 8
  295. /* The command set exported by the boot ROM (MCDI v0) */
  296. #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
  297. (1 << MC_CMD_READ32) | \
  298. (1 << MC_CMD_WRITE32) | \
  299. (1 << MC_CMD_COPYCODE) | \
  300. (1 << MC_CMD_GET_VERSION), \
  301. 0, 0, 0 }
  302. #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
  303. /* Vectors in the boot ROM */
  304. /* Point to the copycode entry point. */
  305. #define MC_BOOTROM_COPYCODE_VEC (0x7f4)
  306. /* Points to the recovery mode entry point. */
  307. #define MC_BOOTROM_NOFLASH_VEC (0x7f8)
  308. /* Test execution limits */
  309. #define MC_TESTEXEC_VARIANT_COUNT 16
  310. #define MC_TESTEXEC_RESULT_COUNT 7
  311. /* MC_CMD_SET_TESTVARS: (debug, variadic in)
  312. * Write variant words for test.
  313. *
  314. * The user supplies a bitmap of the variants they wish to set.
  315. * They must ensure that IN.LEN >= 4 + 4 * ffs(BITMAP)
  316. */
  317. #define MC_CMD_SET_TESTVARS 0x09
  318. #define MC_CMD_SET_TESTVARS_IN_LEN(_numwords) \
  319. (4 + 4*(_numwords))
  320. #define MC_CMD_SET_TESTVARS_IN_ARGS_BITMAP_OFST 0
  321. /* Up to MC_TESTEXEC_VARIANT_COUNT of 32byte words start here */
  322. #define MC_CMD_SET_TESTVARS_IN_ARGS_BUFFER_OFST 4
  323. #define MC_CMD_SET_TESTVARS_OUT_LEN 0
  324. /* MC_CMD_GET_TESTRCS: (debug, variadic out)
  325. * Return result words from test.
  326. */
  327. #define MC_CMD_GET_TESTRCS 0x0a
  328. #define MC_CMD_GET_TESTRCS_IN_LEN 4
  329. #define MC_CMD_GET_TESTRCS_IN_NUMWORDS_OFST 0
  330. #define MC_CMD_GET_TESTRCS_OUT_LEN(_numwords) \
  331. (4 * (_numwords))
  332. #define MC_CMD_GET_TESTRCS_OUT_BUFFER_OFST 0
  333. /* MC_CMD_RUN_TEST: (debug)
  334. * Run the test exported by this firmware image
  335. */
  336. #define MC_CMD_RUN_TEST 0x0b
  337. #define MC_CMD_RUN_TEST_IN_LEN 0
  338. #define MC_CMD_RUN_TEST_OUT_LEN 0
  339. /* MC_CMD_CSR_READ32: (debug, variadic out)
  340. * Read 32bit words from the indirect memory map
  341. */
  342. #define MC_CMD_CSR_READ32 0x0c
  343. #define MC_CMD_CSR_READ32_IN_LEN 12
  344. #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
  345. #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
  346. #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
  347. #define MC_CMD_CSR_READ32_OUT_LEN(_numwords) \
  348. (((_numwords) * 4) + 4)
  349. /* IN.NUMWORDS of 32bit words start here */
  350. #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
  351. #define MC_CMD_CSR_READ32_OUT_IREG_STATUS_OFST(_numwords) \
  352. ((_numwords) * 4)
  353. /* MC_CMD_CSR_WRITE32: (debug, variadic in)
  354. * Write 32bit dwords to the indirect memory map
  355. */
  356. #define MC_CMD_CSR_WRITE32 0x0d
  357. #define MC_CMD_CSR_WRITE32_IN_LEN(_numwords) \
  358. (((_numwords) * 4) + 8)
  359. #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
  360. #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
  361. /* Multiple 32bit words of data to write start here */
  362. #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
  363. #define MC_CMD_CSR_WRITE32_OUT_LEN 4
  364. #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
  365. /* MC_CMD_JTAG_WORK: (debug, fpga only)
  366. * Process JTAG work buffer for RBF acceleration.
  367. *
  368. * Host: bit count, (up to) 32 words of data to clock out to JTAG
  369. * (bits 1,0=TMS,TDO for first bit; bits 3,2=TMS,TDO for second bit, etc.)
  370. * MC: bit count, (up to) 32 words of data clocked in from JTAG
  371. * (bit 0=TDI for first bit, bit 1=TDI for second bit, etc.; [31:16] unused)
  372. */
  373. #define MC_CMD_JTAG_WORK 0x0e
  374. /* MC_CMD_STACKINFO: (debug, variadic out)
  375. * Get stack information
  376. *
  377. * Host: nothing
  378. * MC: (thread ptr, stack size, free space) for each thread in system
  379. */
  380. #define MC_CMD_STACKINFO 0x0f
  381. /* MC_CMD_MDIO_READ:
  382. * MDIO register read
  383. */
  384. #define MC_CMD_MDIO_READ 0x10
  385. #define MC_CMD_MDIO_READ_IN_LEN 16
  386. #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
  387. #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
  388. #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
  389. #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12
  390. #define MC_CMD_MDIO_READ_OUT_LEN 8
  391. #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
  392. #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
  393. /* MC_CMD_MDIO_WRITE:
  394. * MDIO register write
  395. */
  396. #define MC_CMD_MDIO_WRITE 0x11
  397. #define MC_CMD_MDIO_WRITE_IN_LEN 20
  398. #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
  399. #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
  400. #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
  401. #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
  402. #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
  403. #define MC_CMD_MDIO_WRITE_OUT_LEN 4
  404. #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
  405. /* By default all the MCDI MDIO operations perform clause45 mode.
  406. * If you want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
  407. */
  408. #define MC_CMD_MDIO_CLAUSE22 32
  409. /* There are two MDIO buses: one for the internal PHY, and one for external
  410. * devices.
  411. */
  412. #define MC_CMD_MDIO_BUS_INTERNAL 0
  413. #define MC_CMD_MDIO_BUS_EXTERNAL 1
  414. /* The MDIO commands return the raw status bits from the MDIO block. A "good"
  415. * transaction should have the DONE bit set and all other bits clear.
  416. */
  417. #define MC_CMD_MDIO_STATUS_GOOD 0x08
  418. /* MC_CMD_DBI_WRITE: (debug)
  419. * Write DBI register(s)
  420. *
  421. * Host: address, byte-enables (and VF selection, and cs2 flag),
  422. * value [,address ...]
  423. * MC: nothing
  424. */
  425. #define MC_CMD_DBI_WRITE 0x12
  426. #define MC_CMD_DBI_WRITE_IN_LEN(_numwords) \
  427. (12 * (_numwords))
  428. #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(_word) \
  429. (((_word) * 12) + 0)
  430. #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(_word) \
  431. (((_word) * 12) + 4)
  432. #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(_word) \
  433. (((_word) * 12) + 8)
  434. #define MC_CMD_DBI_WRITE_OUT_LEN 0
  435. /* MC_CMD_DBI_READ: (debug)
  436. * Read DBI register(s)
  437. *
  438. * Host: address, [,address ...]
  439. * MC: value [,value ...]
  440. * (note: this does not support reading from VFs, but is retained for backwards
  441. * compatibility; see MC_CMD_DBI_READX below)
  442. */
  443. #define MC_CMD_DBI_READ 0x13
  444. #define MC_CMD_DBI_READ_IN_LEN(_numwords) \
  445. (4 * (_numwords))
  446. #define MC_CMD_DBI_READ_OUT_LEN(_numwords) \
  447. (4 * (_numwords))
  448. /* MC_CMD_PORT_READ32: (debug)
  449. * Read a 32-bit register from the indirect port register map.
  450. *
  451. * The port to access is implied by the Shared memory channel used.
  452. */
  453. #define MC_CMD_PORT_READ32 0x14
  454. #define MC_CMD_PORT_READ32_IN_LEN 4
  455. #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
  456. #define MC_CMD_PORT_READ32_OUT_LEN 8
  457. #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
  458. #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
  459. /* MC_CMD_PORT_WRITE32: (debug)
  460. * Write a 32-bit register to the indirect port register map.
  461. *
  462. * The port to access is implied by the Shared memory channel used.
  463. */
  464. #define MC_CMD_PORT_WRITE32 0x15
  465. #define MC_CMD_PORT_WRITE32_IN_LEN 8
  466. #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
  467. #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
  468. #define MC_CMD_PORT_WRITE32_OUT_LEN 4
  469. #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
  470. /* MC_CMD_PORT_READ128: (debug)
  471. * Read a 128-bit register from indirect port register map
  472. *
  473. * The port to access is implied by the Shared memory channel used.
  474. */
  475. #define MC_CMD_PORT_READ128 0x16
  476. #define MC_CMD_PORT_READ128_IN_LEN 4
  477. #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
  478. #define MC_CMD_PORT_READ128_OUT_LEN 20
  479. #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
  480. #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
  481. /* MC_CMD_PORT_WRITE128: (debug)
  482. * Write a 128-bit register to indirect port register map.
  483. *
  484. * The port to access is implied by the Shared memory channel used.
  485. */
  486. #define MC_CMD_PORT_WRITE128 0x17
  487. #define MC_CMD_PORT_WRITE128_IN_LEN 20
  488. #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
  489. #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
  490. #define MC_CMD_PORT_WRITE128_OUT_LEN 4
  491. #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
  492. /* MC_CMD_GET_BOARD_CFG:
  493. * Returns the MC firmware configuration structure
  494. *
  495. * The FW_SUBTYPE_LIST contains a 16-bit value for each of the 12 types of
  496. * NVRAM area. The values are defined in the firmware/mc/platform/<xxx>.c file
  497. * for a specific board type, but otherwise have no meaning to the MC; they
  498. * are used by the driver to manage selection of appropriate firmware updates.
  499. */
  500. #define MC_CMD_GET_BOARD_CFG 0x18
  501. #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
  502. #define MC_CMD_GET_BOARD_CFG_OUT_LEN 96
  503. #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
  504. #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
  505. #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
  506. #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
  507. #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
  508. #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
  509. #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
  510. #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
  511. #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
  512. #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
  513. #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
  514. #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
  515. #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
  516. #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
  517. #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 24
  518. /* MC_CMD_DBI_READX: (debug)
  519. * Read DBI register(s) -- extended functionality
  520. *
  521. * Host: vf selection, address, [,vf selection ...]
  522. * MC: value [,value ...]
  523. */
  524. #define MC_CMD_DBI_READX 0x19
  525. #define MC_CMD_DBI_READX_IN_LEN(_numwords) \
  526. (8*(_numwords))
  527. #define MC_CMD_DBI_READX_OUT_LEN(_numwords) \
  528. (4*(_numwords))
  529. /* MC_CMD_SET_RAND_SEED:
  530. * Set the 16byte seed for the MC pseudo-random generator
  531. */
  532. #define MC_CMD_SET_RAND_SEED 0x1a
  533. #define MC_CMD_SET_RAND_SEED_IN_LEN 16
  534. #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
  535. #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
  536. /* MC_CMD_LTSSM_HIST: (debug)
  537. * Retrieve the history of the LTSSM, if the build supports it.
  538. *
  539. * Host: nothing
  540. * MC: variable number of LTSSM values, as bytes
  541. * The history is read-to-clear.
  542. */
  543. #define MC_CMD_LTSSM_HIST 0x1b
  544. /* MC_CMD_DRV_ATTACH:
  545. * Inform MCPU that this port is managed on the host (i.e. driver active)
  546. */
  547. #define MC_CMD_DRV_ATTACH 0x1c
  548. #define MC_CMD_DRV_ATTACH_IN_LEN 8
  549. #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
  550. #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
  551. #define MC_CMD_DRV_ATTACH_OUT_LEN 4
  552. #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
  553. /* MC_CMD_NCSI_PROD: (debug)
  554. * Trigger an NC-SI event (and possibly an AEN in response)
  555. */
  556. #define MC_CMD_NCSI_PROD 0x1d
  557. #define MC_CMD_NCSI_PROD_IN_LEN 4
  558. #define MC_CMD_NCSI_PROD_IN_EVENTS_OFST 0
  559. #define MC_CMD_NCSI_PROD_LINKCHANGE_LBN 0
  560. #define MC_CMD_NCSI_PROD_LINKCHANGE_WIDTH 1
  561. #define MC_CMD_NCSI_PROD_RESET_LBN 1
  562. #define MC_CMD_NCSI_PROD_RESET_WIDTH 1
  563. #define MC_CMD_NCSI_PROD_DRVATTACH_LBN 2
  564. #define MC_CMD_NCSI_PROD_DRVATTACH_WIDTH 1
  565. #define MC_CMD_NCSI_PROD_OUT_LEN 0
  566. /* Enumeration */
  567. #define MC_CMD_NCSI_PROD_LINKCHANGE 0
  568. #define MC_CMD_NCSI_PROD_RESET 1
  569. #define MC_CMD_NCSI_PROD_DRVATTACH 2
  570. /* MC_CMD_DEVEL: (debug)
  571. * Reserved for development
  572. */
  573. #define MC_CMD_DEVEL 0x1e
  574. /* MC_CMD_SHMUART: (debug)
  575. * Route UART output to circular buffer in shared memory instead.
  576. */
  577. #define MC_CMD_SHMUART 0x1f
  578. #define MC_CMD_SHMUART_IN_FLAG_OFST 0
  579. #define MC_CMD_SHMUART_IN_LEN 4
  580. #define MC_CMD_SHMUART_OUT_LEN 0
  581. /* MC_CMD_PORT_RESET:
  582. * Generic per-port reset. There is no equivalent for per-board reset.
  583. *
  584. * Locks required: None
  585. * Return code: 0, ETIME
  586. */
  587. #define MC_CMD_PORT_RESET 0x20
  588. #define MC_CMD_PORT_RESET_IN_LEN 0
  589. #define MC_CMD_PORT_RESET_OUT_LEN 0
  590. /* MC_CMD_RESOURCE_LOCK:
  591. * Generic resource lock/unlock interface.
  592. *
  593. * Locks required: None
  594. * Return code: 0,
  595. * EBUSY (if trylock is contended by other port),
  596. * EDEADLK (if trylock is already acquired by this port)
  597. * EINVAL (if unlock doesn't own the lock)
  598. */
  599. #define MC_CMD_RESOURCE_LOCK 0x21
  600. #define MC_CMD_RESOURCE_LOCK_IN_LEN 8
  601. #define MC_CMD_RESOURCE_LOCK_IN_ACTION_OFST 0
  602. #define MC_CMD_RESOURCE_LOCK_ACTION_TRYLOCK 1
  603. #define MC_CMD_RESOURCE_LOCK_ACTION_UNLOCK 0
  604. #define MC_CMD_RESOURCE_LOCK_IN_RESOURCE_OFST 4
  605. #define MC_CMD_RESOURCE_LOCK_I2C 2
  606. #define MC_CMD_RESOURCE_LOCK_PHY 3
  607. #define MC_CMD_RESOURCE_LOCK_OUT_LEN 0
  608. /* MC_CMD_SPI_COMMAND: (variadic in, variadic out)
  609. * Read/Write to/from the SPI device.
  610. *
  611. * Locks required: SPI_LOCK
  612. * Return code: 0, ETIME, EINVAL, EACCES (if SPI_LOCK is not held)
  613. */
  614. #define MC_CMD_SPI_COMMAND 0x22
  615. #define MC_CMD_SPI_COMMAND_IN_LEN(_write_bytes) (12 + (_write_bytes))
  616. #define MC_CMD_SPI_COMMAND_IN_ARGS_OFST 0
  617. #define MC_CMD_SPI_COMMAND_IN_ARGS_ADDRESS_OFST 0
  618. #define MC_CMD_SPI_COMMAND_IN_ARGS_READ_BYTES_OFST 4
  619. #define MC_CMD_SPI_COMMAND_IN_ARGS_CHIP_SELECT_OFST 8
  620. /* Data to write here */
  621. #define MC_CMD_SPI_COMMAND_IN_WRITE_BUFFER_OFST 12
  622. #define MC_CMD_SPI_COMMAND_OUT_LEN(_read_bytes) (_read_bytes)
  623. /* Data read here */
  624. #define MC_CMD_SPI_COMMAND_OUT_READ_BUFFER_OFST 0
  625. /* MC_CMD_I2C_READ_WRITE: (variadic in, variadic out)
  626. * Read/Write to/from the I2C bus.
  627. *
  628. * Locks required: I2C_LOCK
  629. * Return code: 0, ETIME, EINVAL, EACCES (if I2C_LOCK is not held)
  630. */
  631. #define MC_CMD_I2C_RW 0x23
  632. #define MC_CMD_I2C_RW_IN_LEN(_write_bytes) (8 + (_write_bytes))
  633. #define MC_CMD_I2C_RW_IN_ARGS_OFST 0
  634. #define MC_CMD_I2C_RW_IN_ARGS_ADDR_OFST 0
  635. #define MC_CMD_I2C_RW_IN_ARGS_READ_BYTES_OFST 4
  636. /* Data to write here */
  637. #define MC_CMD_I2C_RW_IN_WRITE_BUFFER_OFSET 8
  638. #define MC_CMD_I2C_RW_OUT_LEN(_read_bytes) (_read_bytes)
  639. /* Data read here */
  640. #define MC_CMD_I2C_RW_OUT_READ_BUFFER_OFST 0
  641. /* Generic phy capability bitmask */
  642. #define MC_CMD_PHY_CAP_10HDX_LBN 1
  643. #define MC_CMD_PHY_CAP_10HDX_WIDTH 1
  644. #define MC_CMD_PHY_CAP_10FDX_LBN 2
  645. #define MC_CMD_PHY_CAP_10FDX_WIDTH 1
  646. #define MC_CMD_PHY_CAP_100HDX_LBN 3
  647. #define MC_CMD_PHY_CAP_100HDX_WIDTH 1
  648. #define MC_CMD_PHY_CAP_100FDX_LBN 4
  649. #define MC_CMD_PHY_CAP_100FDX_WIDTH 1
  650. #define MC_CMD_PHY_CAP_1000HDX_LBN 5
  651. #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
  652. #define MC_CMD_PHY_CAP_1000FDX_LBN 6
  653. #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
  654. #define MC_CMD_PHY_CAP_10000FDX_LBN 7
  655. #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
  656. #define MC_CMD_PHY_CAP_PAUSE_LBN 8
  657. #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
  658. #define MC_CMD_PHY_CAP_ASYM_LBN 9
  659. #define MC_CMD_PHY_CAP_ASYM_WIDTH 1
  660. #define MC_CMD_PHY_CAP_AN_LBN 10
  661. #define MC_CMD_PHY_CAP_AN_WIDTH 1
  662. /* Generic loopback enumeration */
  663. #define MC_CMD_LOOPBACK_NONE 0
  664. #define MC_CMD_LOOPBACK_DATA 1
  665. #define MC_CMD_LOOPBACK_GMAC 2
  666. #define MC_CMD_LOOPBACK_XGMII 3
  667. #define MC_CMD_LOOPBACK_XGXS 4
  668. #define MC_CMD_LOOPBACK_XAUI 5
  669. #define MC_CMD_LOOPBACK_GMII 6
  670. #define MC_CMD_LOOPBACK_SGMII 7
  671. #define MC_CMD_LOOPBACK_XGBR 8
  672. #define MC_CMD_LOOPBACK_XFI 9
  673. #define MC_CMD_LOOPBACK_XAUI_FAR 10
  674. #define MC_CMD_LOOPBACK_GMII_FAR 11
  675. #define MC_CMD_LOOPBACK_SGMII_FAR 12
  676. #define MC_CMD_LOOPBACK_XFI_FAR 13
  677. #define MC_CMD_LOOPBACK_GPHY 14
  678. #define MC_CMD_LOOPBACK_PHYXS 15
  679. #define MC_CMD_LOOPBACK_PCS 16
  680. #define MC_CMD_LOOPBACK_PMAPMD 17
  681. #define MC_CMD_LOOPBACK_XPORT 18
  682. #define MC_CMD_LOOPBACK_XGMII_WS 19
  683. #define MC_CMD_LOOPBACK_XAUI_WS 20
  684. #define MC_CMD_LOOPBACK_XAUI_WS_FAR 21
  685. #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 22
  686. #define MC_CMD_LOOPBACK_GMII_WS 23
  687. #define MC_CMD_LOOPBACK_XFI_WS 24
  688. #define MC_CMD_LOOPBACK_XFI_WS_FAR 25
  689. #define MC_CMD_LOOPBACK_PHYXS_WS 26
  690. /* Generic PHY statistics enumeration */
  691. #define MC_CMD_OUI 0
  692. #define MC_CMD_PMA_PMD_LINK_UP 1
  693. #define MC_CMD_PMA_PMD_RX_FAULT 2
  694. #define MC_CMD_PMA_PMD_TX_FAULT 3
  695. #define MC_CMD_PMA_PMD_SIGNAL 4
  696. #define MC_CMD_PMA_PMD_SNR_A 5
  697. #define MC_CMD_PMA_PMD_SNR_B 6
  698. #define MC_CMD_PMA_PMD_SNR_C 7
  699. #define MC_CMD_PMA_PMD_SNR_D 8
  700. #define MC_CMD_PCS_LINK_UP 9
  701. #define MC_CMD_PCS_RX_FAULT 10
  702. #define MC_CMD_PCS_TX_FAULT 11
  703. #define MC_CMD_PCS_BER 12
  704. #define MC_CMD_PCS_BLOCK_ERRORS 13
  705. #define MC_CMD_PHYXS_LINK_UP 14
  706. #define MC_CMD_PHYXS_RX_FAULT 15
  707. #define MC_CMD_PHYXS_TX_FAULT 16
  708. #define MC_CMD_PHYXS_ALIGN 17
  709. #define MC_CMD_PHYXS_SYNC 18
  710. #define MC_CMD_AN_LINK_UP 19
  711. #define MC_CMD_AN_COMPLETE 20
  712. #define MC_CMD_AN_10GBT_STATUS 21
  713. #define MC_CMD_CL22_LINK_UP 22
  714. #define MC_CMD_PHY_NSTATS 23
  715. /* MC_CMD_GET_PHY_CFG:
  716. * Report PHY configuration. This guarantees to succeed even if the PHY is in
  717. * a "zombie" state.
  718. *
  719. * Locks required: None
  720. * Return code: 0
  721. */
  722. #define MC_CMD_GET_PHY_CFG 0x24
  723. #define MC_CMD_GET_PHY_CFG_IN_LEN 0
  724. #define MC_CMD_GET_PHY_CFG_OUT_LEN 72
  725. #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
  726. #define MC_CMD_GET_PHY_CFG_PRESENT_LBN 0
  727. #define MC_CMD_GET_PHY_CFG_PRESENT_WIDTH 1
  728. #define MC_CMD_GET_PHY_CFG_BIST_CABLE_SHORT_LBN 1
  729. #define MC_CMD_GET_PHY_CFG_BIST_CABLE_SHORT_WIDTH 1
  730. #define MC_CMD_GET_PHY_CFG_BIST_CABLE_LONG_LBN 2
  731. #define MC_CMD_GET_PHY_CFG_BIST_CABLE_LONG_WIDTH 1
  732. #define MC_CMD_GET_PHY_CFG_LOWPOWER_LBN 3
  733. #define MC_CMD_GET_PHY_CFG_LOWPOWER_WIDTH 1
  734. #define MC_CMD_GET_PHY_CFG_POWEROFF_LBN 4
  735. #define MC_CMD_GET_PHY_CFG_POWEROFF_WIDTH 1
  736. #define MC_CMD_GET_PHY_CFG_TXDIS_LBN 5
  737. #define MC_CMD_GET_PHY_CFG_TXDIS_WIDTH 1
  738. #define MC_CMD_GET_PHY_CFG_BIST_LBN 6
  739. #define MC_CMD_GET_PHY_CFG_BIST_WIDTH 1
  740. #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
  741. /* Bitmask of supported capabilities */
  742. #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
  743. #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
  744. #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
  745. /* PHY statistics bitmap */
  746. #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
  747. /* PHY type/name string */
  748. #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
  749. #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
  750. #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
  751. #define MC_CMD_MEDIA_XAUI 1
  752. #define MC_CMD_MEDIA_CX4 2
  753. #define MC_CMD_MEDIA_KX4 3
  754. #define MC_CMD_MEDIA_XFP 4
  755. #define MC_CMD_MEDIA_SFP_PLUS 5
  756. #define MC_CMD_MEDIA_BASE_T 6
  757. /* MDIO "MMDS" supported */
  758. #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
  759. /* Native clause 22 */
  760. #define MC_CMD_MMD_CLAUSE22 0
  761. #define MC_CMD_MMD_CLAUSE45_PMAPMD 1
  762. #define MC_CMD_MMD_CLAUSE45_WIS 2
  763. #define MC_CMD_MMD_CLAUSE45_PCS 3
  764. #define MC_CMD_MMD_CLAUSE45_PHYXS 4
  765. #define MC_CMD_MMD_CLAUSE45_DTEXS 5
  766. #define MC_CMD_MMD_CLAUSE45_TC 6
  767. #define MC_CMD_MMD_CLAUSE45_AN 7
  768. /* Clause22 proxied over clause45 by PHY */
  769. #define MC_CMD_MMD_CLAUSE45_C22EXT 29
  770. #define MC_CMD_MMD_CLAUSE45_VEND1 30
  771. #define MC_CMD_MMD_CLAUSE45_VEND2 31
  772. /* PHY stepping version */
  773. #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
  774. #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
  775. /* MC_CMD_START_BIST:
  776. * Start a BIST test on the PHY.
  777. *
  778. * Locks required: PHY_LOCK if doing a PHY BIST
  779. * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
  780. */
  781. #define MC_CMD_START_BIST 0x25
  782. #define MC_CMD_START_BIST_IN_LEN 4
  783. #define MC_CMD_START_BIST_IN_TYPE_OFST 0
  784. #define MC_CMD_START_BIST_OUT_LEN 0
  785. /* Run the PHY's short cable BIST */
  786. #define MC_CMD_PHY_BIST_CABLE_SHORT 1
  787. /* Run the PHY's long cable BIST */
  788. #define MC_CMD_PHY_BIST_CABLE_LONG 2
  789. /* Run BIST on the currently selected BPX Serdes (XAUI or XFI) */
  790. #define MC_CMD_BPX_SERDES_BIST 3
  791. /* Run the MC loopback tests */
  792. #define MC_CMD_MC_LOOPBACK_BIST 4
  793. /* Run the PHY's standard BIST */
  794. #define MC_CMD_PHY_BIST 5
  795. /* MC_CMD_POLL_PHY_BIST: (variadic output)
  796. * Poll for BIST completion
  797. *
  798. * Returns a single status code, and optionally some PHY specific
  799. * bist output. The driver should only consume the BIST output
  800. * after validating OUTLEN and PHY_CFG.PHY_TYPE.
  801. *
  802. * If a driver can't successfully parse the BIST output, it should
  803. * still respect the pass/Fail in OUT.RESULT
  804. *
  805. * Locks required: PHY_LOCK if doing a PHY BIST
  806. * Return code: 0, EACCES (if PHY_LOCK is not held)
  807. */
  808. #define MC_CMD_POLL_BIST 0x26
  809. #define MC_CMD_POLL_BIST_IN_LEN 0
  810. #define MC_CMD_POLL_BIST_OUT_LEN UNKNOWN
  811. #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
  812. #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
  813. #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
  814. #define MC_CMD_POLL_BIST_RUNNING 1
  815. #define MC_CMD_POLL_BIST_PASSED 2
  816. #define MC_CMD_POLL_BIST_FAILED 3
  817. #define MC_CMD_POLL_BIST_TIMEOUT 4
  818. /* Generic: */
  819. #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
  820. /* SFT9001-specific: */
  821. #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
  822. #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
  823. #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
  824. #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
  825. #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
  826. #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
  827. #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
  828. #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
  829. #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 1
  830. #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 2
  831. #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 3
  832. #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 4
  833. #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 9
  834. /* mrsfp "PHY" driver: */
  835. #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
  836. #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0
  837. #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 1
  838. #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 2
  839. #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 3
  840. #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 4
  841. #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 5
  842. #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 6
  843. #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 7
  844. #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 8
  845. /* MC_CMD_PHY_SPI: (variadic in, variadic out)
  846. * Read/Write/Erase the PHY SPI device
  847. *
  848. * Locks required: PHY_LOCK
  849. * Return code: 0, ETIME, EINVAL, EACCES (if PHY_LOCK is not held)
  850. */
  851. #define MC_CMD_PHY_SPI 0x27
  852. #define MC_CMD_PHY_SPI_IN_LEN(_write_bytes) (12 + (_write_bytes))
  853. #define MC_CMD_PHY_SPI_IN_ARGS_OFST 0
  854. #define MC_CMD_PHY_SPI_IN_ARGS_ADDR_OFST 0
  855. #define MC_CMD_PHY_SPI_IN_ARGS_READ_BYTES_OFST 4
  856. #define MC_CMD_PHY_SPI_IN_ARGS_ERASE_ALL_OFST 8
  857. /* Data to write here */
  858. #define MC_CMD_PHY_SPI_IN_WRITE_BUFFER_OFSET 12
  859. #define MC_CMD_PHY_SPI_OUT_LEN(_read_bytes) (_read_bytes)
  860. /* Data read here */
  861. #define MC_CMD_PHY_SPI_OUT_READ_BUFFER_OFST 0
  862. /* MC_CMD_GET_LOOPBACK_MODES:
  863. * Returns a bitmask of loopback modes evailable at each speed.
  864. *
  865. * Locks required: None
  866. * Return code: 0
  867. */
  868. #define MC_CMD_GET_LOOPBACK_MODES 0x28
  869. #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
  870. #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32
  871. #define MC_CMD_GET_LOOPBACK_MODES_100M_OFST 0
  872. #define MC_CMD_GET_LOOPBACK_MODES_1G_OFST 8
  873. #define MC_CMD_GET_LOOPBACK_MODES_10G_OFST 16
  874. #define MC_CMD_GET_LOOPBACK_MODES_SUGGESTED_OFST 24
  875. /* Flow control enumeration */
  876. #define MC_CMD_FCNTL_OFF 0
  877. #define MC_CMD_FCNTL_RESPOND 1
  878. #define MC_CMD_FCNTL_BIDIR 2
  879. /* Auto - Use what the link has autonegotiated
  880. * - The driver should modify the advertised capabilities via SET_LINK.CAP
  881. * to control the negotiated flow control mode.
  882. * - Can only be set if the PHY supports PAUSE+ASYM capabilities
  883. * - Never returned by GET_LINK as the value programmed into the MAC
  884. */
  885. #define MC_CMD_FCNTL_AUTO 3
  886. /* Generic mac fault bitmask */
  887. #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
  888. #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
  889. #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
  890. #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
  891. #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
  892. #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
  893. /* MC_CMD_GET_LINK:
  894. * Read the unified MAC/PHY link state
  895. *
  896. * Locks required: None
  897. * Return code: 0, ETIME
  898. */
  899. #define MC_CMD_GET_LINK 0x29
  900. #define MC_CMD_GET_LINK_IN_LEN 0
  901. #define MC_CMD_GET_LINK_OUT_LEN 28
  902. /* near-side and link-partner advertised capabilities */
  903. #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
  904. #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
  905. /* Autonegotiated speed in mbit/s. The link may still be down
  906. * even if this reads non-zero */
  907. #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
  908. #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
  909. #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
  910. /* Whether we have overall link up */
  911. #define MC_CMD_GET_LINK_LINK_UP_LBN 0
  912. #define MC_CMD_GET_LINK_LINK_UP_WIDTH 1
  913. #define MC_CMD_GET_LINK_FULL_DUPLEX_LBN 1
  914. #define MC_CMD_GET_LINK_FULL_DUPLEX_WIDTH 1
  915. /* Whether we have link at the layers provided by the BPX */
  916. #define MC_CMD_GET_LINK_BPX_LINK_LBN 2
  917. #define MC_CMD_GET_LINK_BPX_LINK_WIDTH 1
  918. /* Whether the PHY has external link */
  919. #define MC_CMD_GET_LINK_PHY_LINK_LBN 3
  920. #define MC_CMD_GET_LINK_PHY_LINK_WIDTH 1
  921. #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
  922. #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
  923. /* MC_CMD_SET_LINK:
  924. * Write the unified MAC/PHY link configuration
  925. *
  926. * A loopback speed of "0" is supported, and means
  927. * (choose any available speed)
  928. *
  929. * Locks required: None
  930. * Return code: 0, EINVAL, ETIME
  931. */
  932. #define MC_CMD_SET_LINK 0x2a
  933. #define MC_CMD_SET_LINK_IN_LEN 16
  934. #define MC_CMD_SET_LINK_IN_CAP_OFST 0
  935. #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
  936. #define MC_CMD_SET_LINK_LOWPOWER_LBN 0
  937. #define MC_CMD_SET_LINK_LOWPOWER_WIDTH 1
  938. #define MC_CMD_SET_LINK_POWEROFF_LBN 1
  939. #define MC_CMD_SET_LINK_POWEROFF_WIDTH 1
  940. #define MC_CMD_SET_LINK_TXDIS_LBN 2
  941. #define MC_CMD_SET_LINK_TXDIS_WIDTH 1
  942. #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
  943. #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
  944. #define MC_CMD_SET_LINK_OUT_LEN 0
  945. /* MC_CMD_SET_ID_LED:
  946. * Set indentification LED state
  947. *
  948. * Locks required: None
  949. * Return code: 0, EINVAL
  950. */
  951. #define MC_CMD_SET_ID_LED 0x2b
  952. #define MC_CMD_SET_ID_LED_IN_LEN 4
  953. #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
  954. #define MC_CMD_LED_OFF 0
  955. #define MC_CMD_LED_ON 1
  956. #define MC_CMD_LED_DEFAULT 2
  957. #define MC_CMD_SET_ID_LED_OUT_LEN 0
  958. /* MC_CMD_SET_MAC:
  959. * Set MAC configuration
  960. *
  961. * The MTU is the MTU programmed directly into the XMAC/GMAC
  962. * (inclusive of EtherII, VLAN, bug16011 padding)
  963. *
  964. * Locks required: None
  965. * Return code: 0, EINVAL
  966. */
  967. #define MC_CMD_SET_MAC 0x2c
  968. #define MC_CMD_SET_MAC_IN_LEN 24
  969. #define MC_CMD_SET_MAC_IN_MTU_OFST 0
  970. #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
  971. #define MC_CMD_SET_MAC_IN_ADDR_OFST 8
  972. #define MC_CMD_SET_MAC_IN_REJECT_OFST 16
  973. #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
  974. #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
  975. #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
  976. #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
  977. #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
  978. #define MC_CMD_SET_MAC_OUT_LEN 0
  979. /* MC_CMD_PHY_STATS:
  980. * Get generic PHY statistics
  981. *
  982. * This call returns the statistics for a generic PHY in a sparse
  983. * array (indexed by the enumerate). Each value is represented by
  984. * a 32bit number.
  985. *
  986. * If the DMA_ADDR is 0, then no DMA is performed, and the statistics
  987. * may be read directly out of shared memory. If DMA_ADDR != 0, then
  988. * the statistics are dmad to that (page-aligned location)
  989. *
  990. * Locks required: None
  991. * Returns: 0, ETIME
  992. * Response methods: shared memory, event
  993. */
  994. #define MC_CMD_PHY_STATS 0x2d
  995. #define MC_CMD_PHY_STATS_IN_LEN 8
  996. #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
  997. #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
  998. #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
  999. #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (MC_CMD_PHY_NSTATS * 4)
  1000. /* Unified MAC statistics enumeration */
  1001. #define MC_CMD_MAC_GENERATION_START 0
  1002. #define MC_CMD_MAC_TX_PKTS 1
  1003. #define MC_CMD_MAC_TX_PAUSE_PKTS 2
  1004. #define MC_CMD_MAC_TX_CONTROL_PKTS 3
  1005. #define MC_CMD_MAC_TX_UNICAST_PKTS 4
  1006. #define MC_CMD_MAC_TX_MULTICAST_PKTS 5
  1007. #define MC_CMD_MAC_TX_BROADCAST_PKTS 6
  1008. #define MC_CMD_MAC_TX_BYTES 7
  1009. #define MC_CMD_MAC_TX_BAD_BYTES 8
  1010. #define MC_CMD_MAC_TX_LT64_PKTS 9
  1011. #define MC_CMD_MAC_TX_64_PKTS 10
  1012. #define MC_CMD_MAC_TX_65_TO_127_PKTS 11
  1013. #define MC_CMD_MAC_TX_128_TO_255_PKTS 12
  1014. #define MC_CMD_MAC_TX_256_TO_511_PKTS 13
  1015. #define MC_CMD_MAC_TX_512_TO_1023_PKTS 14
  1016. #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 15
  1017. #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 16
  1018. #define MC_CMD_MAC_TX_GTJUMBO_PKTS 17
  1019. #define MC_CMD_MAC_TX_BAD_FCS_PKTS 18
  1020. #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 19
  1021. #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 20
  1022. #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 21
  1023. #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 22
  1024. #define MC_CMD_MAC_TX_DEFERRED_PKTS 23
  1025. #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 24
  1026. #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 25
  1027. #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 26
  1028. #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 27
  1029. #define MC_CMD_MAC_RX_PKTS 28
  1030. #define MC_CMD_MAC_RX_PAUSE_PKTS 29
  1031. #define MC_CMD_MAC_RX_GOOD_PKTS 30
  1032. #define MC_CMD_MAC_RX_CONTROL_PKTS 31
  1033. #define MC_CMD_MAC_RX_UNICAST_PKTS 32
  1034. #define MC_CMD_MAC_RX_MULTICAST_PKTS 33
  1035. #define MC_CMD_MAC_RX_BROADCAST_PKTS 34
  1036. #define MC_CMD_MAC_RX_BYTES 35
  1037. #define MC_CMD_MAC_RX_BAD_BYTES 36
  1038. #define MC_CMD_MAC_RX_64_PKTS 37
  1039. #define MC_CMD_MAC_RX_65_TO_127_PKTS 38
  1040. #define MC_CMD_MAC_RX_128_TO_255_PKTS 39
  1041. #define MC_CMD_MAC_RX_256_TO_511_PKTS 40
  1042. #define MC_CMD_MAC_RX_512_TO_1023_PKTS 41
  1043. #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 42
  1044. #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 43
  1045. #define MC_CMD_MAC_RX_GTJUMBO_PKTS 44
  1046. #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 45
  1047. #define MC_CMD_MAC_RX_BAD_FCS_PKTS 46
  1048. #define MC_CMD_MAC_RX_OVERFLOW_PKTS 47
  1049. #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 48
  1050. #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 49
  1051. #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 50
  1052. #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 51
  1053. #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 52
  1054. #define MC_CMD_MAC_RX_JABBER_PKTS 53
  1055. #define MC_CMD_MAC_RX_NODESC_DROPS 54
  1056. #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 55
  1057. #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 56
  1058. #define MC_CMD_MAC_RX_LANES01_DISP_ERR 57
  1059. #define MC_CMD_MAC_RX_LANES23_DISP_ERR 58
  1060. #define MC_CMD_MAC_RX_MATCH_FAULT 59
  1061. #define MC_CMD_GMAC_DMABUF_START 64
  1062. #define MC_CMD_GMAC_DMABUF_END 95
  1063. /* Insert new members here. */
  1064. #define MC_CMD_MAC_GENERATION_END 96
  1065. #define MC_CMD_MAC_NSTATS (MC_CMD_MAC_GENERATION_END+1)
  1066. /* MC_CMD_MAC_STATS:
  1067. * Get unified GMAC/XMAC statistics
  1068. *
  1069. * This call returns unified statistics maintained by the MC as it
  1070. * switches between the GMAC and XMAC. The MC will write out all
  1071. * supported stats. The driver should zero initialise the buffer to
  1072. * guarantee consistent results.
  1073. *
  1074. * Locks required: None
  1075. * Returns: 0
  1076. * Response methods: shared memory, event
  1077. */
  1078. #define MC_CMD_MAC_STATS 0x2e
  1079. #define MC_CMD_MAC_STATS_IN_LEN 16
  1080. #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
  1081. #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
  1082. #define MC_CMD_MAC_STATS_IN_CMD_OFST 8
  1083. #define MC_CMD_MAC_STATS_CMD_DMA_LBN 0
  1084. #define MC_CMD_MAC_STATS_CMD_DMA_WIDTH 1
  1085. #define MC_CMD_MAC_STATS_CMD_CLEAR_LBN 1
  1086. #define MC_CMD_MAC_STATS_CMD_CLEAR_WIDTH 1
  1087. #define MC_CMD_MAC_STATS_CMD_PERIODIC_CHANGE_LBN 2
  1088. #define MC_CMD_MAC_STATS_CMD_PERIODIC_CHANGE_WIDTH 1
  1089. /* Remaining PERIOD* fields only relevant when PERIODIC_CHANGE is set */
  1090. #define MC_CMD_MAC_STATS_CMD_PERIODIC_ENABLE_LBN 3
  1091. #define MC_CMD_MAC_STATS_CMD_PERIODIC_ENABLE_WIDTH 1
  1092. #define MC_CMD_MAC_STATS_CMD_PERIODIC_CLEAR_LBN 4
  1093. #define MC_CMD_MAC_STATS_CMD_PERIODIC_CLEAR_WIDTH 1
  1094. #define MC_CMD_MAC_STATS_CMD_PERIODIC_NOEVENT_LBN 5
  1095. #define MC_CMD_MAC_STATS_CMD_PERIODIC_NOEVENT_WIDTH 1
  1096. #define MC_CMD_MAC_STATS_CMD_PERIOD_MS_LBN 16
  1097. #define MC_CMD_MAC_STATS_CMD_PERIOD_MS_WIDTH 16
  1098. #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
  1099. #define MC_CMD_MAC_STATS_OUT_LEN 0
  1100. /* Callisto flags */
  1101. #define MC_CMD_SFT9001_ROBUST_LBN 0
  1102. #define MC_CMD_SFT9001_ROBUST_WIDTH 1
  1103. #define MC_CMD_SFT9001_SHORT_REACH_LBN 1
  1104. #define MC_CMD_SFT9001_SHORT_REACH_WIDTH 1
  1105. /* MC_CMD_SFT9001_GET:
  1106. * Read current callisto specific setting
  1107. *
  1108. * Locks required: None
  1109. * Returns: 0, ETIME
  1110. */
  1111. #define MC_CMD_SFT9001_GET 0x30
  1112. #define MC_CMD_SFT9001_GET_IN_LEN 0
  1113. #define MC_CMD_SFT9001_GET_OUT_LEN 4
  1114. #define MC_CMD_SFT9001_GET_OUT_FLAGS_OFST 0
  1115. /* MC_CMD_SFT9001_SET:
  1116. * Write current callisto specific setting
  1117. *
  1118. * Locks required: None
  1119. * Returns: 0, ETIME, EINVAL
  1120. */
  1121. #define MC_CMD_SFT9001_SET 0x31
  1122. #define MC_CMD_SFT9001_SET_IN_LEN 4
  1123. #define MC_CMD_SFT9001_SET_IN_FLAGS_OFST 0
  1124. #define MC_CMD_SFT9001_SET_OUT_LEN 0
  1125. /* MC_CMD_WOL_FILTER_SET:
  1126. * Set a WoL filter
  1127. *
  1128. * Locks required: None
  1129. * Returns: 0, EBUSY, EINVAL, ENOSYS
  1130. */
  1131. #define MC_CMD_WOL_FILTER_SET 0x32
  1132. #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 /* 190 rounded up to a word */
  1133. #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
  1134. #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
  1135. /* There is a union at offset 8, following defines overlap due to
  1136. * this */
  1137. #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
  1138. #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST \
  1139. MC_CMD_WOL_FILTER_SET_IN_DATA_OFST
  1140. #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST \
  1141. MC_CMD_WOL_FILTER_SET_IN_DATA_OFST
  1142. #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST \
  1143. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 4)
  1144. #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST \
  1145. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 8)
  1146. #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST \
  1147. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 10)
  1148. #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST \
  1149. MC_CMD_WOL_FILTER_SET_IN_DATA_OFST
  1150. #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST \
  1151. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 16)
  1152. #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST \
  1153. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 32)
  1154. #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST \
  1155. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 34)
  1156. #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST \
  1157. MC_CMD_WOL_FILTER_SET_IN_DATA_OFST
  1158. #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_OFST \
  1159. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 48)
  1160. #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST \
  1161. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 176)
  1162. #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST \
  1163. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 177)
  1164. #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST \
  1165. (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 178)
  1166. #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST \
  1167. MC_CMD_WOL_FILTER_SET_IN_DATA_OFST
  1168. #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
  1169. #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
  1170. #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
  1171. #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
  1172. #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
  1173. #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
  1174. /* WOL Filter types enumeration */
  1175. #define MC_CMD_WOL_TYPE_MAGIC 0x0
  1176. /* unused 0x1 */
  1177. #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
  1178. #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
  1179. #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
  1180. #define MC_CMD_WOL_TYPE_BITMAP 0x5
  1181. #define MC_CMD_WOL_TYPE_LINK 0x6
  1182. #define MC_CMD_WOL_TYPE_MAX 0x7
  1183. #define MC_CMD_FILTER_MODE_SIMPLE 0x0
  1184. #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff
  1185. /* MC_CMD_WOL_FILTER_REMOVE:
  1186. * Remove a WoL filter
  1187. *
  1188. * Locks required: None
  1189. * Returns: 0, EINVAL, ENOSYS
  1190. */
  1191. #define MC_CMD_WOL_FILTER_REMOVE 0x33
  1192. #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
  1193. #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
  1194. #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
  1195. /* MC_CMD_WOL_FILTER_RESET:
  1196. * Reset (i.e. remove all) WoL filters
  1197. *
  1198. * Locks required: None
  1199. * Returns: 0, ENOSYS
  1200. */
  1201. #define MC_CMD_WOL_FILTER_RESET 0x34
  1202. #define MC_CMD_WOL_FILTER_RESET_IN_LEN 0
  1203. #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
  1204. /* MC_CMD_SET_MCAST_HASH:
  1205. * Set the MCASH hash value without otherwise
  1206. * reconfiguring the MAC
  1207. */
  1208. #define MC_CMD_SET_MCAST_HASH 0x35
  1209. #define MC_CMD_SET_MCAST_HASH_IN_LEN 32
  1210. #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
  1211. #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
  1212. #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
  1213. /* MC_CMD_NVRAM_TYPES:
  1214. * Return bitfield indicating available types of virtual NVRAM partitions
  1215. *
  1216. * Locks required: none
  1217. * Returns: 0
  1218. */
  1219. #define MC_CMD_NVRAM_TYPES 0x36
  1220. #define MC_CMD_NVRAM_TYPES_IN_LEN 0
  1221. #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
  1222. #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
  1223. /* Supported NVRAM types */
  1224. #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0
  1225. #define MC_CMD_NVRAM_TYPE_MC_FW 1
  1226. #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 2
  1227. #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 3
  1228. #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 4
  1229. #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 5
  1230. #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 6
  1231. #define MC_CMD_NVRAM_TYPE_EXP_ROM 7
  1232. #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 8
  1233. #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 9
  1234. #define MC_CMD_NVRAM_TYPE_PHY_PORT0 10
  1235. #define MC_CMD_NVRAM_TYPE_PHY_PORT1 11
  1236. #define MC_CMD_NVRAM_TYPE_LOG 12
  1237. /* MC_CMD_NVRAM_INFO:
  1238. * Read info about a virtual NVRAM partition
  1239. *
  1240. * Locks required: none
  1241. * Returns: 0, EINVAL (bad type)
  1242. */
  1243. #define MC_CMD_NVRAM_INFO 0x37
  1244. #define MC_CMD_NVRAM_INFO_IN_LEN 4
  1245. #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
  1246. #define MC_CMD_NVRAM_INFO_OUT_LEN 24
  1247. #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
  1248. #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
  1249. #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
  1250. #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
  1251. #define MC_CMD_NVRAM_PROTECTED_LBN 0
  1252. #define MC_CMD_NVRAM_PROTECTED_WIDTH 1
  1253. #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
  1254. #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
  1255. /* MC_CMD_NVRAM_UPDATE_START:
  1256. * Start a group of update operations on a virtual NVRAM partition
  1257. *
  1258. * Locks required: PHY_LOCK if type==*PHY*
  1259. * Returns: 0, EINVAL (bad type), EACCES (if PHY_LOCK required and not held)
  1260. */
  1261. #define MC_CMD_NVRAM_UPDATE_START 0x38
  1262. #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
  1263. #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
  1264. #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
  1265. /* MC_CMD_NVRAM_READ:
  1266. * Read data from a virtual NVRAM partition
  1267. *
  1268. * Locks required: PHY_LOCK if type==*PHY*
  1269. * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held)
  1270. */
  1271. #define MC_CMD_NVRAM_READ 0x39
  1272. #define MC_CMD_NVRAM_READ_IN_LEN 12
  1273. #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
  1274. #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
  1275. #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
  1276. #define MC_CMD_NVRAM_READ_OUT_LEN(_read_bytes) (_read_bytes)
  1277. #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
  1278. /* MC_CMD_NVRAM_WRITE:
  1279. * Write data to a virtual NVRAM partition
  1280. *
  1281. * Locks required: PHY_LOCK if type==*PHY*
  1282. * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held)
  1283. */
  1284. #define MC_CMD_NVRAM_WRITE 0x3a
  1285. #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
  1286. #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
  1287. #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
  1288. #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
  1289. #define MC_CMD_NVRAM_WRITE_IN_LEN(_write_bytes) (12 + _write_bytes)
  1290. #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
  1291. /* MC_CMD_NVRAM_ERASE:
  1292. * Erase sector(s) from a virtual NVRAM partition
  1293. *
  1294. * Locks required: PHY_LOCK if type==*PHY*
  1295. * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held)
  1296. */
  1297. #define MC_CMD_NVRAM_ERASE 0x3b
  1298. #define MC_CMD_NVRAM_ERASE_IN_LEN 12
  1299. #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
  1300. #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
  1301. #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
  1302. #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
  1303. /* MC_CMD_NVRAM_UPDATE_FINISH:
  1304. * Finish a group of update operations on a virtual NVRAM partition
  1305. *
  1306. * Locks required: PHY_LOCK if type==*PHY*
  1307. * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held)
  1308. */
  1309. #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
  1310. #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
  1311. #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
  1312. #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
  1313. #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
  1314. /* MC_CMD_REBOOT:
  1315. * Reboot the MC.
  1316. *
  1317. * The AFTER_ASSERTION flag is intended to be used when the driver notices
  1318. * an assertion failure (at which point it is expected to perform a complete
  1319. * tear down and reinitialise), to allow both ports to reset the MC once
  1320. * in an atomic fashion.
  1321. *
  1322. * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
  1323. * which means that they will automatically reboot out of the assertion
  1324. * handler, so this is in practise an optional operation. It is still
  1325. * recommended that drivers execute this to support custom firmwares
  1326. * with REBOOT_ON_ASSERT=0.
  1327. *
  1328. * Locks required: NONE
  1329. * Returns: Nothing. You get back a response with ERR=1, DATALEN=0
  1330. */
  1331. #define MC_CMD_REBOOT 0x3d
  1332. #define MC_CMD_REBOOT_IN_LEN 4
  1333. #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
  1334. #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 1
  1335. #define MC_CMD_REBOOT_OUT_LEN 0
  1336. /* MC_CMD_SCHEDINFO:
  1337. * Request scheduler info. from the MC.
  1338. *
  1339. * Locks required: NONE
  1340. * Returns: An array of (timeslice,maximum overrun), one for each thread,
  1341. * in ascending order of thread address.s
  1342. */
  1343. #define MC_CMD_SCHEDINFO 0x3e
  1344. #define MC_CMD_SCHEDINFO_IN_LEN 0
  1345. /* MC_CMD_SET_REBOOT_MODE: (debug)
  1346. * Set the mode for the next MC reboot.
  1347. *
  1348. * Locks required: NONE
  1349. *
  1350. * Sets the reboot mode to the specified value. Returns the old mode.
  1351. */
  1352. #define MC_CMD_REBOOT_MODE 0x3f
  1353. #define MC_CMD_REBOOT_MODE_IN_LEN 4
  1354. #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
  1355. #define MC_CMD_REBOOT_MODE_OUT_LEN 4
  1356. #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
  1357. #define MC_CMD_REBOOT_MODE_NORMAL 0
  1358. #define MC_CMD_REBOOT_MODE_SNAPPER 3
  1359. /* MC_CMD_DEBUG_LOG:
  1360. * Null request/response command (debug)
  1361. * - sequence number is always zero
  1362. * - only supported on the UART interface
  1363. * (the same set of bytes is delivered as an
  1364. * event over PCI)
  1365. */
  1366. #define MC_CMD_DEBUG_LOG 0x40
  1367. #define MC_CMD_DEBUG_LOG_IN_LEN 0
  1368. #define MC_CMD_DEBUG_LOG_OUT_LEN 0
  1369. /* Generic sensor enumeration. Note that a dual port NIC
  1370. * will EITHER expose PHY_COMMON_TEMP OR PHY0_TEMP and
  1371. * PHY1_TEMP depending on whether there is a single sensor
  1372. * in the vicinity of the two port, or one per port.
  1373. */
  1374. #define MC_CMD_SENSOR_CONTROLLER_TEMP 0 /* degC */
  1375. #define MC_CMD_SENSOR_PHY_COMMON_TEMP 1 /* degC */
  1376. #define MC_CMD_SENSOR_CONTROLLER_COOLING 2 /* bool */
  1377. #define MC_CMD_SENSOR_PHY0_TEMP 3 /* degC */
  1378. #define MC_CMD_SENSOR_PHY0_COOLING 4 /* bool */
  1379. #define MC_CMD_SENSOR_PHY1_TEMP 5 /* degC */
  1380. #define MC_CMD_SENSOR_PHY1_COOLING 6 /* bool */
  1381. #define MC_CMD_SENSOR_IN_1V0 7 /* mV */
  1382. #define MC_CMD_SENSOR_IN_1V2 8 /* mV */
  1383. #define MC_CMD_SENSOR_IN_1V8 9 /* mV */
  1384. #define MC_CMD_SENSOR_IN_2V5 10 /* mV */
  1385. #define MC_CMD_SENSOR_IN_3V3 11 /* mV */
  1386. #define MC_CMD_SENSOR_IN_12V0 12 /* mV */
  1387. /* Sensor state */
  1388. #define MC_CMD_SENSOR_STATE_OK 0
  1389. #define MC_CMD_SENSOR_STATE_WARNING 1
  1390. #define MC_CMD_SENSOR_STATE_FATAL 2
  1391. #define MC_CMD_SENSOR_STATE_BROKEN 3
  1392. /* MC_CMD_SENSOR_INFO:
  1393. * Returns information about every available sensor.
  1394. *
  1395. * Each sensor has a single (16bit) value, and a corresponding state.
  1396. * The mapping between value and sensor is nominally determined by the
  1397. * MC, but in practise is implemented as zero (BROKEN), one (TEMPERATURE),
  1398. * or two (VOLTAGE) ranges per sensor per state.
  1399. *
  1400. * This call returns a mask (32bit) of the sensors that are supported
  1401. * by this platform, then an array (indexed by MC_CMD_SENSOR) of byte
  1402. * offsets to the per-sensor arrays. Each sensor array has four 16bit
  1403. * numbers, min1, max1, min2, max2.
  1404. *
  1405. * Locks required: None
  1406. * Returns: 0
  1407. */
  1408. #define MC_CMD_SENSOR_INFO 0x41
  1409. #define MC_CMD_SENSOR_INFO_IN_LEN 0
  1410. #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
  1411. #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
  1412. (4 + (_x))
  1413. #define MC_CMD_SENSOR_INFO_OUT_MIN1_OFST(_ofst) \
  1414. ((_ofst) + 0)
  1415. #define MC_CMD_SENSOR_INFO_OUT_MAX1_OFST(_ofst) \
  1416. ((_ofst) + 2)
  1417. #define MC_CMD_SENSOR_INFO_OUT_MIN2_OFST(_ofst) \
  1418. ((_ofst) + 4)
  1419. #define MC_CMD_SENSOR_INFO_OUT_MAX2_OFST(_ofst) \
  1420. ((_ofst) + 6)
  1421. /* MC_CMD_READ_SENSORS
  1422. * Returns the current reading from each sensor
  1423. *
  1424. * Returns a sparse array of sensor readings (indexed by the sensor
  1425. * type) into host memory. Each array element is a dword.
  1426. *
  1427. * The MC will send a SENSOREVT event every time any sensor changes state. The
  1428. * driver is responsible for ensuring that it doesn't miss any events. The board
  1429. * will function normally if all sensors are in STATE_OK or state_WARNING.
  1430. * Otherwise the board should not be expected to function.
  1431. */
  1432. #define MC_CMD_READ_SENSORS 0x42
  1433. #define MC_CMD_READ_SENSORS_IN_LEN 8
  1434. #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
  1435. #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
  1436. #define MC_CMD_READ_SENSORS_OUT_LEN 0
  1437. /* Sensor reading fields */
  1438. #define MC_CMD_READ_SENSOR_VALUE_LBN 0
  1439. #define MC_CMD_READ_SENSOR_VALUE_WIDTH 16
  1440. #define MC_CMD_READ_SENSOR_STATE_LBN 16
  1441. #define MC_CMD_READ_SENSOR_STATE_WIDTH 8
  1442. /* MC_CMD_GET_PHY_STATE:
  1443. * Report current state of PHY. A "zombie" PHY is a PHY that has failed to
  1444. * boot (e.g. due to missing or corrupted firmware).
  1445. *
  1446. * Locks required: None
  1447. * Return code: 0
  1448. */
  1449. #define MC_CMD_GET_PHY_STATE 0x43
  1450. #define MC_CMD_GET_PHY_STATE_IN_LEN 0
  1451. #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
  1452. #define MC_CMD_GET_PHY_STATE_STATE_OFST 0
  1453. /* PHY state enumeration: */
  1454. #define MC_CMD_PHY_STATE_OK 1
  1455. #define MC_CMD_PHY_STATE_ZOMBIE 2
  1456. /* 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
  1457. * disable 802.Qbb for a given priority. */
  1458. #define MC_CMD_SETUP_8021QBB 0x44
  1459. #define MC_CMD_SETUP_8021QBB_IN_LEN 32
  1460. #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
  1461. #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFFST 0
  1462. /* MC_CMD_WOL_FILTER_GET:
  1463. * Retrieve ID of any WoL filters
  1464. *
  1465. * Locks required: None
  1466. * Returns: 0, ENOSYS
  1467. */
  1468. #define MC_CMD_WOL_FILTER_GET 0x45
  1469. #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
  1470. #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
  1471. #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
  1472. /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD:
  1473. * Offload a protocol to NIC for lights-out state
  1474. *
  1475. * Locks required: None
  1476. * Returns: 0, ENOSYS
  1477. */
  1478. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
  1479. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN 16
  1480. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
  1481. /* There is a union at offset 4, following defines overlap due to
  1482. * this */
  1483. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
  1484. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARPMAC_OFST 4
  1485. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARPIP_OFST 10
  1486. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NSMAC_OFST 4
  1487. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NSSNIPV6_OFST 10
  1488. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NSIPV6_OFST 26
  1489. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
  1490. #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
  1491. /* MC_CMD_REMOVE_LIGHTSOUT_PROTOCOL_OFFLOAD:
  1492. * Offload a protocol to NIC for lights-out state
  1493. *
  1494. * Locks required: None
  1495. * Returns: 0, ENOSYS
  1496. */
  1497. #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
  1498. #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
  1499. #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
  1500. #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
  1501. #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
  1502. /* Lights-out offload protocols enumeration */
  1503. #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1
  1504. #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2
  1505. /* MC_CMD_MAC_RESET_RESTORE:
  1506. * Restore MAC after block reset
  1507. *
  1508. * Locks required: None
  1509. * Returns: 0
  1510. */
  1511. #define MC_CMD_MAC_RESET_RESTORE 0x48
  1512. #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
  1513. #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
  1514. /* MC_CMD_TEST_ASSERT:
  1515. * Deliberately trigger an assert-detonation in the firmware for testing
  1516. * purposes (i.e. to allow tests that the driver copes gracefully).
  1517. *
  1518. * Locks required: None
  1519. * Returns: 0
  1520. */
  1521. #define MC_CMD_TESTASSERT 0x49
  1522. #define MC_CMD_TESTASSERT_IN_LEN 0
  1523. #define MC_CMD_TESTASSERT_OUT_LEN 0
  1524. /* MC_CMD_WORKAROUND 0x4a
  1525. *
  1526. * Enable/Disable a given workaround. The mcfw will return EINVAL if it
  1527. * doesn't understand the given workaround number - which should not
  1528. * be treated as a hard error by client code.
  1529. *
  1530. * This op does not imply any semantics about each workaround, that's between
  1531. * the driver and the mcfw on a per-workaround basis.
  1532. *
  1533. * Locks required: None
  1534. * Returns: 0, EINVAL
  1535. */
  1536. #define MC_CMD_WORKAROUND 0x4a
  1537. #define MC_CMD_WORKAROUND_IN_LEN 8
  1538. #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
  1539. #define MC_CMD_WORKAROUND_BUG17230 1
  1540. #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
  1541. #define MC_CMD_WORKAROUND_OUT_LEN 0
  1542. /* MC_CMD_GET_PHY_MEDIA_INFO:
  1543. * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
  1544. * SFP+ PHYs).
  1545. *
  1546. * The "media type" can be found via GET_PHY_CFG (GET_PHY_CFG_OUT_MEDIA_TYPE);
  1547. * the valid "page number" input values, and the output data, are interpreted
  1548. * on a per-type basis.
  1549. *
  1550. * For SFP+: PAGE=0 or 1 returns a 128-byte block read from module I2C address
  1551. * 0xA0 offset 0 or 0x80.
  1552. * Anything else: currently undefined.
  1553. *
  1554. * Locks required: None
  1555. * Return code: 0
  1556. */
  1557. #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
  1558. #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
  1559. #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
  1560. #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(_num_bytes) (4 + (_num_bytes))
  1561. #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
  1562. #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
  1563. /* MC_CMD_NVRAM_TEST:
  1564. * Test a particular NVRAM partition for valid contents (where "valid"
  1565. * depends on the type of partition).
  1566. *
  1567. * Locks required: None
  1568. * Return code: 0
  1569. */
  1570. #define MC_CMD_NVRAM_TEST 0x4c
  1571. #define MC_CMD_NVRAM_TEST_IN_LEN 4
  1572. #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
  1573. #define MC_CMD_NVRAM_TEST_OUT_LEN 4
  1574. #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
  1575. #define MC_CMD_NVRAM_TEST_PASS 0
  1576. #define MC_CMD_NVRAM_TEST_FAIL 1
  1577. #define MC_CMD_NVRAM_TEST_NOTSUPP 2
  1578. /* MC_CMD_MRSFP_TWEAK: (debug)
  1579. * Read status and/or set parameters for the "mrsfp" driver in mr_rusty builds.
  1580. * I2C I/O expander bits are always read; if equaliser parameters are supplied,
  1581. * they are configured first.
  1582. *
  1583. * Locks required: None
  1584. * Return code: 0, EINVAL
  1585. */
  1586. #define MC_CMD_MRSFP_TWEAK 0x4d
  1587. #define MC_CMD_MRSFP_TWEAK_IN_LEN_READ_ONLY 0
  1588. #define MC_CMD_MRSFP_TWEAK_IN_LEN_EQ_CONFIG 16
  1589. #define MC_CMD_MRSFP_TWEAK_IN_TXEQ_LEVEL_OFST 0 /* 0-6 low->high de-emph. */
  1590. #define MC_CMD_MRSFP_TWEAK_IN_TXEQ_DT_CFG_OFST 4 /* 0-8 low->high ref.V */
  1591. #define MC_CMD_MRSFP_TWEAK_IN_RXEQ_BOOST_OFST 8 /* 0-8 low->high boost */
  1592. #define MC_CMD_MRSFP_TWEAK_IN_RXEQ_DT_CFG_OFST 12 /* 0-8 low->high ref.V */
  1593. #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12
  1594. #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 /* input bits */
  1595. #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 /* output bits */
  1596. #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 /* dirs: 0=out, 1=in */
  1597. /* MC_CMD_TEST_HACK: (debug (unsurprisingly))
  1598. * Change bits of network port state for test purposes in ways that would never be
  1599. * useful in normal operation and so need a special command to change. */
  1600. #define MC_CMD_TEST_HACK 0x2f
  1601. #define MC_CMD_TEST_HACK_IN_LEN 8
  1602. #define MC_CMD_TEST_HACK_IN_TXPAD_OFST 0
  1603. #define MC_CMD_TEST_HACK_IN_TXPAD_AUTO 0 /* Let the MC manage things */
  1604. #define MC_CMD_TEST_HACK_IN_TXPAD_ON 1 /* Force on */
  1605. #define MC_CMD_TEST_HACK_IN_TXPAD_OFF 2 /* Force on */
  1606. #define MC_CMD_TEST_HACK_IN_IPG_OFST 4 /* Takes a value in bits */
  1607. #define MC_CMD_TEST_HACK_IN_IPG_AUTO 0 /* The MC picks the value */
  1608. #define MC_CMD_TEST_HACK_OUT_LEN 0
  1609. /* MC_CMD_SENSOR_SET_LIMS: (debug) (mostly) adjust the sensor limits. This
  1610. * is a warranty-voiding operation.
  1611. *
  1612. * IN: sensor identifier (one of the enumeration starting with MC_CMD_SENSOR_CONTROLLER_TEMP
  1613. * followed by 4 32-bit values: min(warning) max(warning), min(fatal), max(fatal). Which
  1614. * of these limits are meaningful and what their interpretation is is sensor-specific.
  1615. *
  1616. * OUT: nothing
  1617. *
  1618. * Returns: ENOENT if the sensor specified does not exist, EINVAL if the limits are
  1619. * out of range.
  1620. */
  1621. #define MC_CMD_SENSOR_SET_LIMS 0x4e
  1622. #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
  1623. #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
  1624. #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
  1625. #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
  1626. #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
  1627. #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
  1628. /* Do NOT add new commands beyond 0x4f as part of 3.0 : 0x50 - 0x7f will be
  1629. * used for post-3.0 extensions. If you run out of space, look for gaps or
  1630. * commands that are unused in the existing range. */
  1631. #endif /* MCDI_PCOL_H */