mcdi.c 31 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. /* Software-defined structure to the shared-memory */
  23. #define CMD_NOTIFY_PORT0 0
  24. #define CMD_NOTIFY_PORT1 4
  25. #define CMD_PDU_PORT0 0x008
  26. #define CMD_PDU_PORT1 0x108
  27. #define REBOOT_FLAG_PORT0 0x3f8
  28. #define REBOOT_FLAG_PORT1 0x3fc
  29. #define MCDI_RPC_TIMEOUT 10 /*seconds */
  30. #define MCDI_PDU(efx) \
  31. (efx_port_num(efx) ? CMD_PDU_PORT1 : CMD_PDU_PORT0)
  32. #define MCDI_DOORBELL(efx) \
  33. (efx_port_num(efx) ? CMD_NOTIFY_PORT1 : CMD_NOTIFY_PORT0)
  34. #define MCDI_REBOOT_FLAG(efx) \
  35. (efx_port_num(efx) ? REBOOT_FLAG_PORT1 : REBOOT_FLAG_PORT0)
  36. #define SEQ_MASK \
  37. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  38. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  39. {
  40. struct siena_nic_data *nic_data;
  41. EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  42. nic_data = efx->nic_data;
  43. return &nic_data->mcdi;
  44. }
  45. static inline void
  46. efx_mcdi_readd(struct efx_nic *efx, efx_dword_t *value, unsigned reg)
  47. {
  48. struct siena_nic_data *nic_data = efx->nic_data;
  49. value->u32[0] = (__force __le32)__raw_readl(nic_data->mcdi_smem + reg);
  50. }
  51. static inline void
  52. efx_mcdi_writed(struct efx_nic *efx, const efx_dword_t *value, unsigned reg)
  53. {
  54. struct siena_nic_data *nic_data = efx->nic_data;
  55. __raw_writel((__force u32)value->u32[0], nic_data->mcdi_smem + reg);
  56. }
  57. void efx_mcdi_init(struct efx_nic *efx)
  58. {
  59. struct efx_mcdi_iface *mcdi;
  60. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  61. return;
  62. mcdi = efx_mcdi(efx);
  63. init_waitqueue_head(&mcdi->wq);
  64. spin_lock_init(&mcdi->iface_lock);
  65. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  66. mcdi->mode = MCDI_MODE_POLL;
  67. (void) efx_mcdi_poll_reboot(efx);
  68. }
  69. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  70. const u8 *inbuf, size_t inlen)
  71. {
  72. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  73. unsigned pdu = MCDI_PDU(efx);
  74. unsigned doorbell = MCDI_DOORBELL(efx);
  75. unsigned int i;
  76. efx_dword_t hdr;
  77. u32 xflags, seqno;
  78. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  79. BUG_ON(inlen & 3 || inlen >= 0x100);
  80. seqno = mcdi->seqno & SEQ_MASK;
  81. xflags = 0;
  82. if (mcdi->mode == MCDI_MODE_EVENTS)
  83. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  84. EFX_POPULATE_DWORD_6(hdr,
  85. MCDI_HEADER_RESPONSE, 0,
  86. MCDI_HEADER_RESYNC, 1,
  87. MCDI_HEADER_CODE, cmd,
  88. MCDI_HEADER_DATALEN, inlen,
  89. MCDI_HEADER_SEQ, seqno,
  90. MCDI_HEADER_XFLAGS, xflags);
  91. efx_mcdi_writed(efx, &hdr, pdu);
  92. for (i = 0; i < inlen; i += 4)
  93. efx_mcdi_writed(efx, (const efx_dword_t *)(inbuf + i),
  94. pdu + 4 + i);
  95. /* ring the doorbell with a distinctive value */
  96. EFX_POPULATE_DWORD_1(hdr, EFX_DWORD_0, 0x45789abc);
  97. efx_mcdi_writed(efx, &hdr, doorbell);
  98. }
  99. static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
  100. {
  101. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  102. unsigned int pdu = MCDI_PDU(efx);
  103. int i;
  104. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  105. BUG_ON(outlen & 3 || outlen >= 0x100);
  106. for (i = 0; i < outlen; i += 4)
  107. efx_mcdi_readd(efx, (efx_dword_t *)(outbuf + i), pdu + 4 + i);
  108. }
  109. static int efx_mcdi_poll(struct efx_nic *efx)
  110. {
  111. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  112. unsigned int time, finish;
  113. unsigned int respseq, respcmd, error;
  114. unsigned int pdu = MCDI_PDU(efx);
  115. unsigned int rc, spins;
  116. efx_dword_t reg;
  117. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  118. rc = -efx_mcdi_poll_reboot(efx);
  119. if (rc)
  120. goto out;
  121. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  122. * because generally mcdi responses are fast. After that, back off
  123. * and poll once a jiffy (approximately)
  124. */
  125. spins = TICK_USEC;
  126. finish = get_seconds() + MCDI_RPC_TIMEOUT;
  127. while (1) {
  128. if (spins != 0) {
  129. --spins;
  130. udelay(1);
  131. } else {
  132. schedule_timeout_uninterruptible(1);
  133. }
  134. time = get_seconds();
  135. efx_mcdi_readd(efx, &reg, pdu);
  136. /* All 1's indicates that shared memory is in reset (and is
  137. * not a valid header). Wait for it to come out reset before
  138. * completing the command */
  139. if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
  140. EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
  141. break;
  142. if (time >= finish)
  143. return -ETIMEDOUT;
  144. }
  145. mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
  146. respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
  147. respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
  148. error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
  149. if (error && mcdi->resplen == 0) {
  150. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  151. rc = EIO;
  152. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  153. netif_err(efx, hw, efx->net_dev,
  154. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  155. respseq, mcdi->seqno);
  156. rc = EIO;
  157. } else if (error) {
  158. efx_mcdi_readd(efx, &reg, pdu + 4);
  159. switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
  160. #define TRANSLATE_ERROR(name) \
  161. case MC_CMD_ERR_ ## name: \
  162. rc = name; \
  163. break
  164. TRANSLATE_ERROR(ENOENT);
  165. TRANSLATE_ERROR(EINTR);
  166. TRANSLATE_ERROR(EACCES);
  167. TRANSLATE_ERROR(EBUSY);
  168. TRANSLATE_ERROR(EINVAL);
  169. TRANSLATE_ERROR(EDEADLK);
  170. TRANSLATE_ERROR(ENOSYS);
  171. TRANSLATE_ERROR(ETIME);
  172. #undef TRANSLATE_ERROR
  173. default:
  174. rc = EIO;
  175. break;
  176. }
  177. } else
  178. rc = 0;
  179. out:
  180. mcdi->resprc = rc;
  181. if (rc)
  182. mcdi->resplen = 0;
  183. /* Return rc=0 like wait_event_timeout() */
  184. return 0;
  185. }
  186. /* Test and clear MC-rebooted flag for this port/function */
  187. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  188. {
  189. unsigned int addr = MCDI_REBOOT_FLAG(efx);
  190. efx_dword_t reg;
  191. uint32_t value;
  192. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  193. return false;
  194. efx_mcdi_readd(efx, &reg, addr);
  195. value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
  196. if (value == 0)
  197. return 0;
  198. EFX_ZERO_DWORD(reg);
  199. efx_mcdi_writed(efx, &reg, addr);
  200. if (value == MC_STATUS_DWORD_ASSERT)
  201. return -EINTR;
  202. else
  203. return -EIO;
  204. }
  205. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  206. {
  207. /* Wait until the interface becomes QUIESCENT and we win the race
  208. * to mark it RUNNING. */
  209. wait_event(mcdi->wq,
  210. atomic_cmpxchg(&mcdi->state,
  211. MCDI_STATE_QUIESCENT,
  212. MCDI_STATE_RUNNING)
  213. == MCDI_STATE_QUIESCENT);
  214. }
  215. static int efx_mcdi_await_completion(struct efx_nic *efx)
  216. {
  217. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  218. if (wait_event_timeout(
  219. mcdi->wq,
  220. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  221. msecs_to_jiffies(MCDI_RPC_TIMEOUT * 1000)) == 0)
  222. return -ETIMEDOUT;
  223. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  224. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  225. * completed the request first, then we'll just end up completing the
  226. * request again, which is safe.
  227. *
  228. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  229. * wait_event_timeout() implicitly provides.
  230. */
  231. if (mcdi->mode == MCDI_MODE_POLL)
  232. return efx_mcdi_poll(efx);
  233. return 0;
  234. }
  235. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  236. {
  237. /* If the interface is RUNNING, then move to COMPLETED and wake any
  238. * waiters. If the interface isn't in RUNNING then we've received a
  239. * duplicate completion after we've already transitioned back to
  240. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  241. * have failed the seqno check].
  242. */
  243. if (atomic_cmpxchg(&mcdi->state,
  244. MCDI_STATE_RUNNING,
  245. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  246. wake_up(&mcdi->wq);
  247. return true;
  248. }
  249. return false;
  250. }
  251. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  252. {
  253. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  254. wake_up(&mcdi->wq);
  255. }
  256. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  257. unsigned int datalen, unsigned int errno)
  258. {
  259. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  260. bool wake = false;
  261. spin_lock(&mcdi->iface_lock);
  262. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  263. if (mcdi->credits)
  264. /* The request has been cancelled */
  265. --mcdi->credits;
  266. else
  267. netif_err(efx, hw, efx->net_dev,
  268. "MC response mismatch tx seq 0x%x rx "
  269. "seq 0x%x\n", seqno, mcdi->seqno);
  270. } else {
  271. mcdi->resprc = errno;
  272. mcdi->resplen = datalen;
  273. wake = true;
  274. }
  275. spin_unlock(&mcdi->iface_lock);
  276. if (wake)
  277. efx_mcdi_complete(mcdi);
  278. }
  279. /* Issue the given command by writing the data into the shared memory PDU,
  280. * ring the doorbell and wait for completion. Copyout the result. */
  281. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  282. const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
  283. size_t *outlen_actual)
  284. {
  285. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  286. int rc;
  287. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  288. efx_mcdi_acquire(mcdi);
  289. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  290. spin_lock_bh(&mcdi->iface_lock);
  291. ++mcdi->seqno;
  292. spin_unlock_bh(&mcdi->iface_lock);
  293. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  294. if (mcdi->mode == MCDI_MODE_POLL)
  295. rc = efx_mcdi_poll(efx);
  296. else
  297. rc = efx_mcdi_await_completion(efx);
  298. if (rc != 0) {
  299. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  300. * and completing a request we've just cancelled, by ensuring
  301. * that the seqno check therein fails.
  302. */
  303. spin_lock_bh(&mcdi->iface_lock);
  304. ++mcdi->seqno;
  305. ++mcdi->credits;
  306. spin_unlock_bh(&mcdi->iface_lock);
  307. netif_err(efx, hw, efx->net_dev,
  308. "MC command 0x%x inlen %d mode %d timed out\n",
  309. cmd, (int)inlen, mcdi->mode);
  310. } else {
  311. size_t resplen;
  312. /* At the very least we need a memory barrier here to ensure
  313. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  314. * a spurious efx_mcdi_ev_cpl() running concurrently by
  315. * acquiring the iface_lock. */
  316. spin_lock_bh(&mcdi->iface_lock);
  317. rc = -mcdi->resprc;
  318. resplen = mcdi->resplen;
  319. spin_unlock_bh(&mcdi->iface_lock);
  320. if (rc == 0) {
  321. efx_mcdi_copyout(efx, outbuf,
  322. min(outlen, mcdi->resplen + 3) & ~0x3);
  323. if (outlen_actual != NULL)
  324. *outlen_actual = resplen;
  325. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  326. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  327. else if (rc == -EIO || rc == -EINTR) {
  328. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  329. -rc);
  330. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  331. } else
  332. netif_dbg(efx, hw, efx->net_dev,
  333. "MC command 0x%x inlen %d failed rc=%d\n",
  334. cmd, (int)inlen, -rc);
  335. }
  336. efx_mcdi_release(mcdi);
  337. return rc;
  338. }
  339. void efx_mcdi_mode_poll(struct efx_nic *efx)
  340. {
  341. struct efx_mcdi_iface *mcdi;
  342. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  343. return;
  344. mcdi = efx_mcdi(efx);
  345. if (mcdi->mode == MCDI_MODE_POLL)
  346. return;
  347. /* We can switch from event completion to polled completion, because
  348. * mcdi requests are always completed in shared memory. We do this by
  349. * switching the mode to POLL'd then completing the request.
  350. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  351. *
  352. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  353. * which efx_mcdi_complete() provides for us.
  354. */
  355. mcdi->mode = MCDI_MODE_POLL;
  356. efx_mcdi_complete(mcdi);
  357. }
  358. void efx_mcdi_mode_event(struct efx_nic *efx)
  359. {
  360. struct efx_mcdi_iface *mcdi;
  361. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  362. return;
  363. mcdi = efx_mcdi(efx);
  364. if (mcdi->mode == MCDI_MODE_EVENTS)
  365. return;
  366. /* We can't switch from polled to event completion in the middle of a
  367. * request, because the completion method is specified in the request.
  368. * So acquire the interface to serialise the requestors. We don't need
  369. * to acquire the iface_lock to change the mode here, but we do need a
  370. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  371. * efx_mcdi_acquire() provides.
  372. */
  373. efx_mcdi_acquire(mcdi);
  374. mcdi->mode = MCDI_MODE_EVENTS;
  375. efx_mcdi_release(mcdi);
  376. }
  377. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  378. {
  379. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  380. /* If there is an outstanding MCDI request, it has been terminated
  381. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  382. * in polled mode, then do nothing because the MC reboot handler will
  383. * set the header correctly. However, if the mcdi interface is waiting
  384. * for a CMDDONE event it won't receive it [and since all MCDI events
  385. * are sent to the same queue, we can't be racing with
  386. * efx_mcdi_ev_cpl()]
  387. *
  388. * There's a race here with efx_mcdi_rpc(), because we might receive
  389. * a REBOOT event *before* the request has been copied out. In polled
  390. * mode (during startup) this is irrelevant, because efx_mcdi_complete()
  391. * is ignored. In event mode, this condition is just an edge-case of
  392. * receiving a REBOOT event after posting the MCDI request. Did the mc
  393. * reboot before or after the copyout? The best we can do always is
  394. * just return failure.
  395. */
  396. spin_lock(&mcdi->iface_lock);
  397. if (efx_mcdi_complete(mcdi)) {
  398. if (mcdi->mode == MCDI_MODE_EVENTS) {
  399. mcdi->resprc = rc;
  400. mcdi->resplen = 0;
  401. ++mcdi->credits;
  402. }
  403. } else
  404. /* Nobody was waiting for an MCDI request, so trigger a reset */
  405. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  406. spin_unlock(&mcdi->iface_lock);
  407. }
  408. static unsigned int efx_mcdi_event_link_speed[] = {
  409. [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
  410. [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
  411. [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
  412. };
  413. static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
  414. {
  415. u32 flags, fcntl, speed, lpa;
  416. speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
  417. EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
  418. speed = efx_mcdi_event_link_speed[speed];
  419. flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
  420. fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
  421. lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
  422. /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
  423. * which is only run after flushing the event queues. Therefore, it
  424. * is safe to modify the link state outside of the mac_lock here.
  425. */
  426. efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
  427. efx_mcdi_phy_check_fcntl(efx, lpa);
  428. efx_link_status_changed(efx);
  429. }
  430. static const char *sensor_names[] = {
  431. [MC_CMD_SENSOR_CONTROLLER_TEMP] = "Controller temp. sensor",
  432. [MC_CMD_SENSOR_PHY_COMMON_TEMP] = "PHY shared temp. sensor",
  433. [MC_CMD_SENSOR_CONTROLLER_COOLING] = "Controller cooling",
  434. [MC_CMD_SENSOR_PHY0_TEMP] = "PHY 0 temp. sensor",
  435. [MC_CMD_SENSOR_PHY0_COOLING] = "PHY 0 cooling",
  436. [MC_CMD_SENSOR_PHY1_TEMP] = "PHY 1 temp. sensor",
  437. [MC_CMD_SENSOR_PHY1_COOLING] = "PHY 1 cooling",
  438. [MC_CMD_SENSOR_IN_1V0] = "1.0V supply sensor",
  439. [MC_CMD_SENSOR_IN_1V2] = "1.2V supply sensor",
  440. [MC_CMD_SENSOR_IN_1V8] = "1.8V supply sensor",
  441. [MC_CMD_SENSOR_IN_2V5] = "2.5V supply sensor",
  442. [MC_CMD_SENSOR_IN_3V3] = "3.3V supply sensor",
  443. [MC_CMD_SENSOR_IN_12V0] = "12V supply sensor"
  444. };
  445. static const char *sensor_status_names[] = {
  446. [MC_CMD_SENSOR_STATE_OK] = "OK",
  447. [MC_CMD_SENSOR_STATE_WARNING] = "Warning",
  448. [MC_CMD_SENSOR_STATE_FATAL] = "Fatal",
  449. [MC_CMD_SENSOR_STATE_BROKEN] = "Device failure",
  450. };
  451. static void efx_mcdi_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
  452. {
  453. unsigned int monitor, state, value;
  454. const char *name, *state_txt;
  455. monitor = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_MONITOR);
  456. state = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_STATE);
  457. value = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_VALUE);
  458. /* Deal gracefully with the board having more drivers than we
  459. * know about, but do not expect new sensor states. */
  460. name = (monitor >= ARRAY_SIZE(sensor_names))
  461. ? "No sensor name available" :
  462. sensor_names[monitor];
  463. EFX_BUG_ON_PARANOID(state >= ARRAY_SIZE(sensor_status_names));
  464. state_txt = sensor_status_names[state];
  465. netif_err(efx, hw, efx->net_dev,
  466. "Sensor %d (%s) reports condition '%s' for raw value %d\n",
  467. monitor, name, state_txt, value);
  468. }
  469. /* Called from falcon_process_eventq for MCDI events */
  470. void efx_mcdi_process_event(struct efx_channel *channel,
  471. efx_qword_t *event)
  472. {
  473. struct efx_nic *efx = channel->efx;
  474. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  475. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  476. switch (code) {
  477. case MCDI_EVENT_CODE_BADSSERT:
  478. netif_err(efx, hw, efx->net_dev,
  479. "MC watchdog or assertion failure at 0x%x\n", data);
  480. efx_mcdi_ev_death(efx, EINTR);
  481. break;
  482. case MCDI_EVENT_CODE_PMNOTICE:
  483. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  484. break;
  485. case MCDI_EVENT_CODE_CMDDONE:
  486. efx_mcdi_ev_cpl(efx,
  487. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  488. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  489. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  490. break;
  491. case MCDI_EVENT_CODE_LINKCHANGE:
  492. efx_mcdi_process_link_change(efx, event);
  493. break;
  494. case MCDI_EVENT_CODE_SENSOREVT:
  495. efx_mcdi_sensor_event(efx, event);
  496. break;
  497. case MCDI_EVENT_CODE_SCHEDERR:
  498. netif_info(efx, hw, efx->net_dev,
  499. "MC Scheduler error address=0x%x\n", data);
  500. break;
  501. case MCDI_EVENT_CODE_REBOOT:
  502. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  503. efx_mcdi_ev_death(efx, EIO);
  504. break;
  505. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  506. /* MAC stats are gather lazily. We can ignore this. */
  507. break;
  508. default:
  509. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  510. code);
  511. }
  512. }
  513. /**************************************************************************
  514. *
  515. * Specific request functions
  516. *
  517. **************************************************************************
  518. */
  519. void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
  520. {
  521. u8 outbuf[ALIGN(MC_CMD_GET_VERSION_V1_OUT_LEN, 4)];
  522. size_t outlength;
  523. const __le16 *ver_words;
  524. int rc;
  525. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  526. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  527. outbuf, sizeof(outbuf), &outlength);
  528. if (rc)
  529. goto fail;
  530. if (outlength < MC_CMD_GET_VERSION_V1_OUT_LEN) {
  531. rc = -EIO;
  532. goto fail;
  533. }
  534. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  535. snprintf(buf, len, "%u.%u.%u.%u",
  536. le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
  537. le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
  538. return;
  539. fail:
  540. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  541. buf[0] = 0;
  542. }
  543. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  544. bool *was_attached)
  545. {
  546. u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
  547. u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
  548. size_t outlen;
  549. int rc;
  550. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  551. driver_operating ? 1 : 0);
  552. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  553. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  554. outbuf, sizeof(outbuf), &outlen);
  555. if (rc)
  556. goto fail;
  557. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  558. rc = -EIO;
  559. goto fail;
  560. }
  561. if (was_attached != NULL)
  562. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  563. return 0;
  564. fail:
  565. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  566. return rc;
  567. }
  568. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  569. u16 *fw_subtype_list)
  570. {
  571. uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LEN];
  572. size_t outlen;
  573. int port_num = efx_port_num(efx);
  574. int offset;
  575. int rc;
  576. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  577. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  578. outbuf, sizeof(outbuf), &outlen);
  579. if (rc)
  580. goto fail;
  581. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LEN) {
  582. rc = -EIO;
  583. goto fail;
  584. }
  585. offset = (port_num)
  586. ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
  587. : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
  588. if (mac_address)
  589. memcpy(mac_address, outbuf + offset, ETH_ALEN);
  590. if (fw_subtype_list)
  591. memcpy(fw_subtype_list,
  592. outbuf + MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST,
  593. MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN);
  594. return 0;
  595. fail:
  596. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  597. __func__, rc, (int)outlen);
  598. return rc;
  599. }
  600. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  601. {
  602. u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
  603. u32 dest = 0;
  604. int rc;
  605. if (uart)
  606. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  607. if (evq)
  608. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  609. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  610. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  611. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  612. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  613. NULL, 0, NULL);
  614. if (rc)
  615. goto fail;
  616. return 0;
  617. fail:
  618. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  619. return rc;
  620. }
  621. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  622. {
  623. u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
  624. size_t outlen;
  625. int rc;
  626. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  627. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  628. outbuf, sizeof(outbuf), &outlen);
  629. if (rc)
  630. goto fail;
  631. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  632. rc = -EIO;
  633. goto fail;
  634. }
  635. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  636. return 0;
  637. fail:
  638. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  639. __func__, rc);
  640. return rc;
  641. }
  642. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  643. size_t *size_out, size_t *erase_size_out,
  644. bool *protected_out)
  645. {
  646. u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
  647. u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
  648. size_t outlen;
  649. int rc;
  650. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  651. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  652. outbuf, sizeof(outbuf), &outlen);
  653. if (rc)
  654. goto fail;
  655. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  656. rc = -EIO;
  657. goto fail;
  658. }
  659. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  660. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  661. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  662. (1 << MC_CMD_NVRAM_PROTECTED_LBN));
  663. return 0;
  664. fail:
  665. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  666. return rc;
  667. }
  668. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  669. {
  670. u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
  671. int rc;
  672. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  673. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  674. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  675. NULL, 0, NULL);
  676. if (rc)
  677. goto fail;
  678. return 0;
  679. fail:
  680. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  681. return rc;
  682. }
  683. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  684. loff_t offset, u8 *buffer, size_t length)
  685. {
  686. u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
  687. u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  688. size_t outlen;
  689. int rc;
  690. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  691. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  692. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  693. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  694. outbuf, sizeof(outbuf), &outlen);
  695. if (rc)
  696. goto fail;
  697. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  698. return 0;
  699. fail:
  700. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  701. return rc;
  702. }
  703. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  704. loff_t offset, const u8 *buffer, size_t length)
  705. {
  706. u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  707. int rc;
  708. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  709. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  710. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  711. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  712. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  713. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  714. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  715. NULL, 0, NULL);
  716. if (rc)
  717. goto fail;
  718. return 0;
  719. fail:
  720. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  721. return rc;
  722. }
  723. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  724. loff_t offset, size_t length)
  725. {
  726. u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
  727. int rc;
  728. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  729. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  730. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  731. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  732. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  733. NULL, 0, NULL);
  734. if (rc)
  735. goto fail;
  736. return 0;
  737. fail:
  738. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  739. return rc;
  740. }
  741. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  742. {
  743. u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
  744. int rc;
  745. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  746. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  747. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  748. NULL, 0, NULL);
  749. if (rc)
  750. goto fail;
  751. return 0;
  752. fail:
  753. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  754. return rc;
  755. }
  756. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  757. {
  758. u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
  759. u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
  760. int rc;
  761. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  762. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  763. outbuf, sizeof(outbuf), NULL);
  764. if (rc)
  765. return rc;
  766. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  767. case MC_CMD_NVRAM_TEST_PASS:
  768. case MC_CMD_NVRAM_TEST_NOTSUPP:
  769. return 0;
  770. default:
  771. return -EIO;
  772. }
  773. }
  774. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  775. {
  776. u32 nvram_types;
  777. unsigned int type;
  778. int rc;
  779. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  780. if (rc)
  781. goto fail1;
  782. type = 0;
  783. while (nvram_types != 0) {
  784. if (nvram_types & 1) {
  785. rc = efx_mcdi_nvram_test(efx, type);
  786. if (rc)
  787. goto fail2;
  788. }
  789. type++;
  790. nvram_types >>= 1;
  791. }
  792. return 0;
  793. fail2:
  794. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  795. __func__, type);
  796. fail1:
  797. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  798. return rc;
  799. }
  800. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  801. {
  802. u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
  803. u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
  804. unsigned int flags, index, ofst;
  805. const char *reason;
  806. size_t outlen;
  807. int retry;
  808. int rc;
  809. /* Attempt to read any stored assertion state before we reboot
  810. * the mcfw out of the assertion handler. Retry twice, once
  811. * because a boot-time assertion might cause this command to fail
  812. * with EINTR. And once again because GET_ASSERTS can race with
  813. * MC_CMD_REBOOT running on the other port. */
  814. retry = 2;
  815. do {
  816. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  817. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  818. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  819. outbuf, sizeof(outbuf), &outlen);
  820. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  821. if (rc)
  822. return rc;
  823. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  824. return -EIO;
  825. /* Print out any recorded assertion state */
  826. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  827. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  828. return 0;
  829. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  830. ? "system-level assertion"
  831. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  832. ? "thread-level assertion"
  833. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  834. ? "watchdog reset"
  835. : "unknown assertion";
  836. netif_err(efx, hw, efx->net_dev,
  837. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  838. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  839. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  840. /* Print out the registers */
  841. ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
  842. for (index = 1; index < 32; index++) {
  843. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
  844. MCDI_DWORD2(outbuf, ofst));
  845. ofst += sizeof(efx_dword_t);
  846. }
  847. return 0;
  848. }
  849. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  850. {
  851. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  852. /* Atomically reboot the mcfw out of the assertion handler */
  853. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  854. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  855. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  856. efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  857. NULL, 0, NULL);
  858. }
  859. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  860. {
  861. int rc;
  862. rc = efx_mcdi_read_assertion(efx);
  863. if (rc)
  864. return rc;
  865. efx_mcdi_exit_assertion(efx);
  866. return 0;
  867. }
  868. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  869. {
  870. u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
  871. int rc;
  872. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  873. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  874. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  875. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  876. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  877. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  878. NULL, 0, NULL);
  879. if (rc)
  880. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  881. __func__, rc);
  882. }
  883. int efx_mcdi_reset_port(struct efx_nic *efx)
  884. {
  885. int rc = efx_mcdi_rpc(efx, MC_CMD_PORT_RESET, NULL, 0, NULL, 0, NULL);
  886. if (rc)
  887. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  888. __func__, rc);
  889. return rc;
  890. }
  891. int efx_mcdi_reset_mc(struct efx_nic *efx)
  892. {
  893. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  894. int rc;
  895. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  896. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  897. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  898. NULL, 0, NULL);
  899. /* White is black, and up is down */
  900. if (rc == -EIO)
  901. return 0;
  902. if (rc == 0)
  903. rc = -EIO;
  904. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  905. return rc;
  906. }
  907. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  908. const u8 *mac, int *id_out)
  909. {
  910. u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
  911. u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
  912. size_t outlen;
  913. int rc;
  914. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  915. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  916. MC_CMD_FILTER_MODE_SIMPLE);
  917. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  918. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  919. outbuf, sizeof(outbuf), &outlen);
  920. if (rc)
  921. goto fail;
  922. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  923. rc = -EIO;
  924. goto fail;
  925. }
  926. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  927. return 0;
  928. fail:
  929. *id_out = -1;
  930. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  931. return rc;
  932. }
  933. int
  934. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  935. {
  936. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  937. }
  938. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  939. {
  940. u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
  941. size_t outlen;
  942. int rc;
  943. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  944. outbuf, sizeof(outbuf), &outlen);
  945. if (rc)
  946. goto fail;
  947. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  948. rc = -EIO;
  949. goto fail;
  950. }
  951. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  952. return 0;
  953. fail:
  954. *id_out = -1;
  955. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  956. return rc;
  957. }
  958. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  959. {
  960. u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
  961. int rc;
  962. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  963. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  964. NULL, 0, NULL);
  965. if (rc)
  966. goto fail;
  967. return 0;
  968. fail:
  969. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  970. return rc;
  971. }
  972. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  973. {
  974. int rc;
  975. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  976. if (rc)
  977. goto fail;
  978. return 0;
  979. fail:
  980. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  981. return rc;
  982. }