gianfar.h 39 KB

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  1. /*
  2. * drivers/net/gianfar.h
  3. *
  4. * Gianfar Ethernet Driver
  5. * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
  6. * Based on 8260_io/fcc_enet.c
  7. *
  8. * Author: Andy Fleming
  9. * Maintainer: Kumar Gala
  10. * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11. *
  12. * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License as published by the
  16. * Free Software Foundation; either version 2 of the License, or (at your
  17. * option) any later version.
  18. *
  19. * Still left to do:
  20. * -Add support for module parameters
  21. * -Add patch for ethtool phys id
  22. */
  23. #ifndef __GIANFAR_H
  24. #define __GIANFAR_H
  25. #include <linux/kernel.h>
  26. #include <linux/sched.h>
  27. #include <linux/string.h>
  28. #include <linux/errno.h>
  29. #include <linux/slab.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/init.h>
  32. #include <linux/delay.h>
  33. #include <linux/netdevice.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/spinlock.h>
  37. #include <linux/mm.h>
  38. #include <linux/mii.h>
  39. #include <linux/phy.h>
  40. #include <asm/io.h>
  41. #include <asm/irq.h>
  42. #include <asm/uaccess.h>
  43. #include <linux/module.h>
  44. #include <linux/crc32.h>
  45. #include <linux/workqueue.h>
  46. #include <linux/ethtool.h>
  47. struct ethtool_flow_spec_container {
  48. struct ethtool_rx_flow_spec fs;
  49. struct list_head list;
  50. };
  51. struct ethtool_rx_list {
  52. struct list_head list;
  53. unsigned int count;
  54. };
  55. /* The maximum number of packets to be handled in one call of gfar_poll */
  56. #define GFAR_DEV_WEIGHT 64
  57. /* Length for FCB */
  58. #define GMAC_FCB_LEN 8
  59. /* Default padding amount */
  60. #define DEFAULT_PADDING 2
  61. /* Number of bytes to align the rx bufs to */
  62. #define RXBUF_ALIGNMENT 64
  63. /* The number of bytes which composes a unit for the purpose of
  64. * allocating data buffers. ie-for any given MTU, the data buffer
  65. * will be the next highest multiple of 512 bytes. */
  66. #define INCREMENTAL_BUFFER_SIZE 512
  67. #define MAC_ADDR_LEN 6
  68. #define PHY_INIT_TIMEOUT 100000
  69. #define GFAR_PHY_CHANGE_TIME 2
  70. #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
  71. #define DRV_NAME "gfar-enet"
  72. extern const char gfar_driver_name[];
  73. extern const char gfar_driver_version[];
  74. /* MAXIMUM NUMBER OF QUEUES SUPPORTED */
  75. #define MAX_TX_QS 0x8
  76. #define MAX_RX_QS 0x8
  77. /* MAXIMUM NUMBER OF GROUPS SUPPORTED */
  78. #define MAXGROUPS 0x2
  79. /* These need to be powers of 2 for this driver */
  80. #define DEFAULT_TX_RING_SIZE 256
  81. #define DEFAULT_RX_RING_SIZE 256
  82. #define GFAR_RX_MAX_RING_SIZE 256
  83. #define GFAR_TX_MAX_RING_SIZE 256
  84. #define GFAR_MAX_FIFO_THRESHOLD 511
  85. #define GFAR_MAX_FIFO_STARVE 511
  86. #define GFAR_MAX_FIFO_STARVE_OFF 511
  87. #define DEFAULT_RX_BUFFER_SIZE 1536
  88. #define TX_RING_MOD_MASK(size) (size-1)
  89. #define RX_RING_MOD_MASK(size) (size-1)
  90. #define JUMBO_BUFFER_SIZE 9728
  91. #define JUMBO_FRAME_SIZE 9600
  92. #define DEFAULT_FIFO_TX_THR 0x100
  93. #define DEFAULT_FIFO_TX_STARVE 0x40
  94. #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
  95. #define DEFAULT_BD_STASH 1
  96. #define DEFAULT_STASH_LENGTH 96
  97. #define DEFAULT_STASH_INDEX 0
  98. /* The number of Exact Match registers */
  99. #define GFAR_EM_NUM 15
  100. /* Latency of interface clock in nanoseconds */
  101. /* Interface clock latency , in this case, means the
  102. * time described by a value of 1 in the interrupt
  103. * coalescing registers' time fields. Since those fields
  104. * refer to the time it takes for 64 clocks to pass, the
  105. * latencies are as such:
  106. * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
  107. * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
  108. * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
  109. */
  110. #define GFAR_GBIT_TIME 512
  111. #define GFAR_100_TIME 2560
  112. #define GFAR_10_TIME 25600
  113. #define DEFAULT_TX_COALESCE 1
  114. #define DEFAULT_TXCOUNT 16
  115. #define DEFAULT_TXTIME 21
  116. #define DEFAULT_RXTIME 21
  117. #define DEFAULT_RX_COALESCE 0
  118. #define DEFAULT_RXCOUNT 0
  119. #define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
  120. | SUPPORTED_10baseT_Full \
  121. | SUPPORTED_100baseT_Half \
  122. | SUPPORTED_100baseT_Full \
  123. | SUPPORTED_Autoneg \
  124. | SUPPORTED_MII)
  125. /* TBI register addresses */
  126. #define MII_TBICON 0x11
  127. /* TBICON register bit fields */
  128. #define TBICON_CLK_SELECT 0x0020
  129. /* MAC register bits */
  130. #define MACCFG1_SOFT_RESET 0x80000000
  131. #define MACCFG1_RESET_RX_MC 0x00080000
  132. #define MACCFG1_RESET_TX_MC 0x00040000
  133. #define MACCFG1_RESET_RX_FUN 0x00020000
  134. #define MACCFG1_RESET_TX_FUN 0x00010000
  135. #define MACCFG1_LOOPBACK 0x00000100
  136. #define MACCFG1_RX_FLOW 0x00000020
  137. #define MACCFG1_TX_FLOW 0x00000010
  138. #define MACCFG1_SYNCD_RX_EN 0x00000008
  139. #define MACCFG1_RX_EN 0x00000004
  140. #define MACCFG1_SYNCD_TX_EN 0x00000002
  141. #define MACCFG1_TX_EN 0x00000001
  142. #define MACCFG2_INIT_SETTINGS 0x00007205
  143. #define MACCFG2_FULL_DUPLEX 0x00000001
  144. #define MACCFG2_IF 0x00000300
  145. #define MACCFG2_MII 0x00000100
  146. #define MACCFG2_GMII 0x00000200
  147. #define MACCFG2_HUGEFRAME 0x00000020
  148. #define MACCFG2_LENGTHCHECK 0x00000010
  149. #define MACCFG2_MPEN 0x00000008
  150. #define ECNTRL_FIFM 0x00008000
  151. #define ECNTRL_INIT_SETTINGS 0x00001000
  152. #define ECNTRL_TBI_MODE 0x00000020
  153. #define ECNTRL_REDUCED_MODE 0x00000010
  154. #define ECNTRL_R100 0x00000008
  155. #define ECNTRL_REDUCED_MII_MODE 0x00000004
  156. #define ECNTRL_SGMII_MODE 0x00000002
  157. #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
  158. #define MINFLR_INIT_SETTINGS 0x00000040
  159. /* Tqueue control */
  160. #define TQUEUE_EN0 0x00008000
  161. #define TQUEUE_EN1 0x00004000
  162. #define TQUEUE_EN2 0x00002000
  163. #define TQUEUE_EN3 0x00001000
  164. #define TQUEUE_EN4 0x00000800
  165. #define TQUEUE_EN5 0x00000400
  166. #define TQUEUE_EN6 0x00000200
  167. #define TQUEUE_EN7 0x00000100
  168. #define TQUEUE_EN_ALL 0x0000FF00
  169. #define TR03WT_WT0_MASK 0xFF000000
  170. #define TR03WT_WT1_MASK 0x00FF0000
  171. #define TR03WT_WT2_MASK 0x0000FF00
  172. #define TR03WT_WT3_MASK 0x000000FF
  173. #define TR47WT_WT4_MASK 0xFF000000
  174. #define TR47WT_WT5_MASK 0x00FF0000
  175. #define TR47WT_WT6_MASK 0x0000FF00
  176. #define TR47WT_WT7_MASK 0x000000FF
  177. /* Rqueue control */
  178. #define RQUEUE_EX0 0x00800000
  179. #define RQUEUE_EX1 0x00400000
  180. #define RQUEUE_EX2 0x00200000
  181. #define RQUEUE_EX3 0x00100000
  182. #define RQUEUE_EX4 0x00080000
  183. #define RQUEUE_EX5 0x00040000
  184. #define RQUEUE_EX6 0x00020000
  185. #define RQUEUE_EX7 0x00010000
  186. #define RQUEUE_EX_ALL 0x00FF0000
  187. #define RQUEUE_EN0 0x00000080
  188. #define RQUEUE_EN1 0x00000040
  189. #define RQUEUE_EN2 0x00000020
  190. #define RQUEUE_EN3 0x00000010
  191. #define RQUEUE_EN4 0x00000008
  192. #define RQUEUE_EN5 0x00000004
  193. #define RQUEUE_EN6 0x00000002
  194. #define RQUEUE_EN7 0x00000001
  195. #define RQUEUE_EN_ALL 0x000000FF
  196. /* Init to do tx snooping for buffers and descriptors */
  197. #define DMACTRL_INIT_SETTINGS 0x000000c3
  198. #define DMACTRL_GRS 0x00000010
  199. #define DMACTRL_GTS 0x00000008
  200. #define TSTAT_CLEAR_THALT_ALL 0xFF000000
  201. #define TSTAT_CLEAR_THALT 0x80000000
  202. #define TSTAT_CLEAR_THALT0 0x80000000
  203. #define TSTAT_CLEAR_THALT1 0x40000000
  204. #define TSTAT_CLEAR_THALT2 0x20000000
  205. #define TSTAT_CLEAR_THALT3 0x10000000
  206. #define TSTAT_CLEAR_THALT4 0x08000000
  207. #define TSTAT_CLEAR_THALT5 0x04000000
  208. #define TSTAT_CLEAR_THALT6 0x02000000
  209. #define TSTAT_CLEAR_THALT7 0x01000000
  210. /* Interrupt coalescing macros */
  211. #define IC_ICEN 0x80000000
  212. #define IC_ICFT_MASK 0x1fe00000
  213. #define IC_ICFT_SHIFT 21
  214. #define mk_ic_icft(x) \
  215. (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
  216. #define IC_ICTT_MASK 0x0000ffff
  217. #define mk_ic_ictt(x) (x&IC_ICTT_MASK)
  218. #define mk_ic_value(count, time) (IC_ICEN | \
  219. mk_ic_icft(count) | \
  220. mk_ic_ictt(time))
  221. #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
  222. IC_ICFT_SHIFT)
  223. #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
  224. #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
  225. #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
  226. #define skip_bd(bdp, stride, base, ring_size) ({ \
  227. typeof(bdp) new_bd = (bdp) + (stride); \
  228. (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
  229. #define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
  230. #define RCTRL_TS_ENABLE 0x01000000
  231. #define RCTRL_PAL_MASK 0x001f0000
  232. #define RCTRL_VLEX 0x00002000
  233. #define RCTRL_FILREN 0x00001000
  234. #define RCTRL_GHTX 0x00000400
  235. #define RCTRL_IPCSEN 0x00000200
  236. #define RCTRL_TUCSEN 0x00000100
  237. #define RCTRL_PRSDEP_MASK 0x000000c0
  238. #define RCTRL_PRSDEP_INIT 0x000000c0
  239. #define RCTRL_PRSFM 0x00000020
  240. #define RCTRL_PROM 0x00000008
  241. #define RCTRL_EMEN 0x00000002
  242. #define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
  243. RCTRL_TUCSEN | RCTRL_FILREN)
  244. #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
  245. RCTRL_PRSDEP_INIT)
  246. #define RCTRL_EXTHASH (RCTRL_GHTX)
  247. #define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
  248. #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
  249. #define RSTAT_CLEAR_RHALT 0x00800000
  250. #define TCTRL_IPCSEN 0x00004000
  251. #define TCTRL_TUCSEN 0x00002000
  252. #define TCTRL_VLINS 0x00001000
  253. #define TCTRL_THDF 0x00000800
  254. #define TCTRL_RFCPAUSE 0x00000010
  255. #define TCTRL_TFCPAUSE 0x00000008
  256. #define TCTRL_TXSCHED_MASK 0x00000006
  257. #define TCTRL_TXSCHED_INIT 0x00000000
  258. #define TCTRL_TXSCHED_PRIO 0x00000002
  259. #define TCTRL_TXSCHED_WRRS 0x00000004
  260. #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
  261. #define IEVENT_INIT_CLEAR 0xffffffff
  262. #define IEVENT_BABR 0x80000000
  263. #define IEVENT_RXC 0x40000000
  264. #define IEVENT_BSY 0x20000000
  265. #define IEVENT_EBERR 0x10000000
  266. #define IEVENT_MSRO 0x04000000
  267. #define IEVENT_GTSC 0x02000000
  268. #define IEVENT_BABT 0x01000000
  269. #define IEVENT_TXC 0x00800000
  270. #define IEVENT_TXE 0x00400000
  271. #define IEVENT_TXB 0x00200000
  272. #define IEVENT_TXF 0x00100000
  273. #define IEVENT_LC 0x00040000
  274. #define IEVENT_CRL 0x00020000
  275. #define IEVENT_XFUN 0x00010000
  276. #define IEVENT_RXB0 0x00008000
  277. #define IEVENT_MAG 0x00000800
  278. #define IEVENT_GRSC 0x00000100
  279. #define IEVENT_RXF0 0x00000080
  280. #define IEVENT_FIR 0x00000008
  281. #define IEVENT_FIQ 0x00000004
  282. #define IEVENT_DPE 0x00000002
  283. #define IEVENT_PERR 0x00000001
  284. #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
  285. #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
  286. #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
  287. #define IEVENT_ERR_MASK \
  288. (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
  289. IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
  290. | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
  291. | IEVENT_MAG | IEVENT_BABR)
  292. #define IMASK_INIT_CLEAR 0x00000000
  293. #define IMASK_BABR 0x80000000
  294. #define IMASK_RXC 0x40000000
  295. #define IMASK_BSY 0x20000000
  296. #define IMASK_EBERR 0x10000000
  297. #define IMASK_MSRO 0x04000000
  298. #define IMASK_GTSC 0x02000000
  299. #define IMASK_BABT 0x01000000
  300. #define IMASK_TXC 0x00800000
  301. #define IMASK_TXEEN 0x00400000
  302. #define IMASK_TXBEN 0x00200000
  303. #define IMASK_TXFEN 0x00100000
  304. #define IMASK_LC 0x00040000
  305. #define IMASK_CRL 0x00020000
  306. #define IMASK_XFUN 0x00010000
  307. #define IMASK_RXB0 0x00008000
  308. #define IMASK_MAG 0x00000800
  309. #define IMASK_GRSC 0x00000100
  310. #define IMASK_RXFEN0 0x00000080
  311. #define IMASK_FIR 0x00000008
  312. #define IMASK_FIQ 0x00000004
  313. #define IMASK_DPE 0x00000002
  314. #define IMASK_PERR 0x00000001
  315. #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
  316. IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
  317. IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
  318. | IMASK_PERR)
  319. #define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
  320. & IMASK_DEFAULT)
  321. /* Fifo management */
  322. #define FIFO_TX_THR_MASK 0x01ff
  323. #define FIFO_TX_STARVE_MASK 0x01ff
  324. #define FIFO_TX_STARVE_OFF_MASK 0x01ff
  325. /* Attribute fields */
  326. /* This enables rx snooping for buffers and descriptors */
  327. #define ATTR_BDSTASH 0x00000800
  328. #define ATTR_BUFSTASH 0x00004000
  329. #define ATTR_SNOOPING 0x000000c0
  330. #define ATTR_INIT_SETTINGS ATTR_SNOOPING
  331. #define ATTRELI_INIT_SETTINGS 0x0
  332. #define ATTRELI_EL_MASK 0x3fff0000
  333. #define ATTRELI_EL(x) (x << 16)
  334. #define ATTRELI_EI_MASK 0x00003fff
  335. #define ATTRELI_EI(x) (x)
  336. #define BD_LFLAG(flags) ((flags) << 16)
  337. #define BD_LENGTH_MASK 0x0000ffff
  338. #define FPR_FILER_MASK 0xFFFFFFFF
  339. #define MAX_FILER_IDX 0xFF
  340. /* This default RIR value directly corresponds
  341. * to the 3-bit hash value generated */
  342. #define DEFAULT_RIR0 0x05397700
  343. /* RQFCR register bits */
  344. #define RQFCR_GPI 0x80000000
  345. #define RQFCR_HASHTBL_Q 0x00000000
  346. #define RQFCR_HASHTBL_0 0x00020000
  347. #define RQFCR_HASHTBL_1 0x00040000
  348. #define RQFCR_HASHTBL_2 0x00060000
  349. #define RQFCR_HASHTBL_3 0x00080000
  350. #define RQFCR_HASH 0x00010000
  351. #define RQFCR_QUEUE 0x0000FC00
  352. #define RQFCR_CLE 0x00000200
  353. #define RQFCR_RJE 0x00000100
  354. #define RQFCR_AND 0x00000080
  355. #define RQFCR_CMP_EXACT 0x00000000
  356. #define RQFCR_CMP_MATCH 0x00000020
  357. #define RQFCR_CMP_NOEXACT 0x00000040
  358. #define RQFCR_CMP_NOMATCH 0x00000060
  359. /* RQFCR PID values */
  360. #define RQFCR_PID_MASK 0x00000000
  361. #define RQFCR_PID_PARSE 0x00000001
  362. #define RQFCR_PID_ARB 0x00000002
  363. #define RQFCR_PID_DAH 0x00000003
  364. #define RQFCR_PID_DAL 0x00000004
  365. #define RQFCR_PID_SAH 0x00000005
  366. #define RQFCR_PID_SAL 0x00000006
  367. #define RQFCR_PID_ETY 0x00000007
  368. #define RQFCR_PID_VID 0x00000008
  369. #define RQFCR_PID_PRI 0x00000009
  370. #define RQFCR_PID_TOS 0x0000000A
  371. #define RQFCR_PID_L4P 0x0000000B
  372. #define RQFCR_PID_DIA 0x0000000C
  373. #define RQFCR_PID_SIA 0x0000000D
  374. #define RQFCR_PID_DPT 0x0000000E
  375. #define RQFCR_PID_SPT 0x0000000F
  376. /* RQFPR when PID is 0x0001 */
  377. #define RQFPR_HDR_GE_512 0x00200000
  378. #define RQFPR_LERR 0x00100000
  379. #define RQFPR_RAR 0x00080000
  380. #define RQFPR_RARQ 0x00040000
  381. #define RQFPR_AR 0x00020000
  382. #define RQFPR_ARQ 0x00010000
  383. #define RQFPR_EBC 0x00008000
  384. #define RQFPR_VLN 0x00004000
  385. #define RQFPR_CFI 0x00002000
  386. #define RQFPR_JUM 0x00001000
  387. #define RQFPR_IPF 0x00000800
  388. #define RQFPR_FIF 0x00000400
  389. #define RQFPR_IPV4 0x00000200
  390. #define RQFPR_IPV6 0x00000100
  391. #define RQFPR_ICC 0x00000080
  392. #define RQFPR_ICV 0x00000040
  393. #define RQFPR_TCP 0x00000020
  394. #define RQFPR_UDP 0x00000010
  395. #define RQFPR_TUC 0x00000008
  396. #define RQFPR_TUV 0x00000004
  397. #define RQFPR_PER 0x00000002
  398. #define RQFPR_EER 0x00000001
  399. /* TxBD status field bits */
  400. #define TXBD_READY 0x8000
  401. #define TXBD_PADCRC 0x4000
  402. #define TXBD_WRAP 0x2000
  403. #define TXBD_INTERRUPT 0x1000
  404. #define TXBD_LAST 0x0800
  405. #define TXBD_CRC 0x0400
  406. #define TXBD_DEF 0x0200
  407. #define TXBD_HUGEFRAME 0x0080
  408. #define TXBD_LATECOLLISION 0x0080
  409. #define TXBD_RETRYLIMIT 0x0040
  410. #define TXBD_RETRYCOUNTMASK 0x003c
  411. #define TXBD_UNDERRUN 0x0002
  412. #define TXBD_TOE 0x0002
  413. /* Tx FCB param bits */
  414. #define TXFCB_VLN 0x80
  415. #define TXFCB_IP 0x40
  416. #define TXFCB_IP6 0x20
  417. #define TXFCB_TUP 0x10
  418. #define TXFCB_UDP 0x08
  419. #define TXFCB_CIP 0x04
  420. #define TXFCB_CTU 0x02
  421. #define TXFCB_NPH 0x01
  422. #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
  423. /* RxBD status field bits */
  424. #define RXBD_EMPTY 0x8000
  425. #define RXBD_RO1 0x4000
  426. #define RXBD_WRAP 0x2000
  427. #define RXBD_INTERRUPT 0x1000
  428. #define RXBD_LAST 0x0800
  429. #define RXBD_FIRST 0x0400
  430. #define RXBD_MISS 0x0100
  431. #define RXBD_BROADCAST 0x0080
  432. #define RXBD_MULTICAST 0x0040
  433. #define RXBD_LARGE 0x0020
  434. #define RXBD_NONOCTET 0x0010
  435. #define RXBD_SHORT 0x0008
  436. #define RXBD_CRCERR 0x0004
  437. #define RXBD_OVERRUN 0x0002
  438. #define RXBD_TRUNCATED 0x0001
  439. #define RXBD_STATS 0x01ff
  440. #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
  441. | RXBD_CRCERR | RXBD_OVERRUN \
  442. | RXBD_TRUNCATED)
  443. /* Rx FCB status field bits */
  444. #define RXFCB_VLN 0x8000
  445. #define RXFCB_IP 0x4000
  446. #define RXFCB_IP6 0x2000
  447. #define RXFCB_TUP 0x1000
  448. #define RXFCB_CIP 0x0800
  449. #define RXFCB_CTU 0x0400
  450. #define RXFCB_EIP 0x0200
  451. #define RXFCB_ETU 0x0100
  452. #define RXFCB_CSUM_MASK 0x0f00
  453. #define RXFCB_PERR_MASK 0x000c
  454. #define RXFCB_PERR_BADL3 0x0008
  455. #define GFAR_INT_NAME_MAX IFNAMSIZ + 4
  456. struct txbd8
  457. {
  458. union {
  459. struct {
  460. u16 status; /* Status Fields */
  461. u16 length; /* Buffer length */
  462. };
  463. u32 lstatus;
  464. };
  465. u32 bufPtr; /* Buffer Pointer */
  466. };
  467. struct txfcb {
  468. u8 flags;
  469. u8 ptp; /* Flag to enable tx timestamping */
  470. u8 l4os; /* Level 4 Header Offset */
  471. u8 l3os; /* Level 3 Header Offset */
  472. u16 phcs; /* Pseudo-header Checksum */
  473. u16 vlctl; /* VLAN control word */
  474. };
  475. struct rxbd8
  476. {
  477. union {
  478. struct {
  479. u16 status; /* Status Fields */
  480. u16 length; /* Buffer Length */
  481. };
  482. u32 lstatus;
  483. };
  484. u32 bufPtr; /* Buffer Pointer */
  485. };
  486. struct rxfcb {
  487. u16 flags;
  488. u8 rq; /* Receive Queue index */
  489. u8 pro; /* Layer 4 Protocol */
  490. u16 reserved;
  491. u16 vlctl; /* VLAN control word */
  492. };
  493. struct gianfar_skb_cb {
  494. int alignamount;
  495. };
  496. #define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
  497. struct rmon_mib
  498. {
  499. u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
  500. u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
  501. u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
  502. u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
  503. u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
  504. u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
  505. u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
  506. u32 rbyt; /* 0x.69c - Receive Byte Counter */
  507. u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
  508. u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
  509. u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
  510. u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
  511. u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
  512. u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
  513. u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
  514. u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
  515. u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
  516. u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
  517. u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
  518. u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
  519. u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
  520. u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
  521. u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
  522. u32 rdrp; /* 0x.6dc - Receive Drop Counter */
  523. u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
  524. u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
  525. u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
  526. u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
  527. u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
  528. u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
  529. u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
  530. u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
  531. u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
  532. u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
  533. u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
  534. u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
  535. u8 res1[4];
  536. u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
  537. u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
  538. u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
  539. u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
  540. u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
  541. u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
  542. u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
  543. u32 car1; /* 0x.730 - Carry Register One */
  544. u32 car2; /* 0x.734 - Carry Register Two */
  545. u32 cam1; /* 0x.738 - Carry Mask Register One */
  546. u32 cam2; /* 0x.73c - Carry Mask Register Two */
  547. };
  548. struct gfar_extra_stats {
  549. u64 kernel_dropped;
  550. u64 rx_large;
  551. u64 rx_short;
  552. u64 rx_nonoctet;
  553. u64 rx_crcerr;
  554. u64 rx_overrun;
  555. u64 rx_bsy;
  556. u64 rx_babr;
  557. u64 rx_trunc;
  558. u64 eberr;
  559. u64 tx_babt;
  560. u64 tx_underrun;
  561. u64 rx_skbmissing;
  562. u64 tx_timeout;
  563. };
  564. #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
  565. #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
  566. /* Number of stats in the stats structure (ignore car and cam regs)*/
  567. #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
  568. #define GFAR_INFOSTR_LEN 32
  569. struct gfar_stats {
  570. u64 extra[GFAR_EXTRA_STATS_LEN];
  571. u64 rmon[GFAR_RMON_LEN];
  572. };
  573. struct gfar {
  574. u32 tsec_id; /* 0x.000 - Controller ID register */
  575. u32 tsec_id2; /* 0x.004 - Controller ID2 register */
  576. u8 res1[8];
  577. u32 ievent; /* 0x.010 - Interrupt Event Register */
  578. u32 imask; /* 0x.014 - Interrupt Mask Register */
  579. u32 edis; /* 0x.018 - Error Disabled Register */
  580. u32 emapg; /* 0x.01c - Group Error mapping register */
  581. u32 ecntrl; /* 0x.020 - Ethernet Control Register */
  582. u32 minflr; /* 0x.024 - Minimum Frame Length Register */
  583. u32 ptv; /* 0x.028 - Pause Time Value Register */
  584. u32 dmactrl; /* 0x.02c - DMA Control Register */
  585. u32 tbipa; /* 0x.030 - TBI PHY Address Register */
  586. u8 res2[28];
  587. u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
  588. register */
  589. u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
  590. register */
  591. u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
  592. register */
  593. u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
  594. shutoff register */
  595. u8 res3[44];
  596. u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
  597. u8 res4[8];
  598. u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
  599. u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
  600. u8 res5[96];
  601. u32 tctrl; /* 0x.100 - Transmit Control Register */
  602. u32 tstat; /* 0x.104 - Transmit Status Register */
  603. u32 dfvlan; /* 0x.108 - Default VLAN Control word */
  604. u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
  605. u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
  606. u32 tqueue; /* 0x.114 - Transmit queue control register */
  607. u8 res7[40];
  608. u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
  609. u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
  610. u8 res8[52];
  611. u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
  612. u8 res9a[4];
  613. u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
  614. u8 res9b[4];
  615. u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
  616. u8 res9c[4];
  617. u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
  618. u8 res9d[4];
  619. u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
  620. u8 res9e[4];
  621. u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
  622. u8 res9f[4];
  623. u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
  624. u8 res9g[4];
  625. u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
  626. u8 res9h[4];
  627. u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
  628. u8 res9[64];
  629. u32 tbaseh; /* 0x.200 - TxBD base address high */
  630. u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
  631. u8 res10a[4];
  632. u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
  633. u8 res10b[4];
  634. u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
  635. u8 res10c[4];
  636. u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
  637. u8 res10d[4];
  638. u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
  639. u8 res10e[4];
  640. u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
  641. u8 res10f[4];
  642. u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
  643. u8 res10g[4];
  644. u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
  645. u8 res10[192];
  646. u32 rctrl; /* 0x.300 - Receive Control Register */
  647. u32 rstat; /* 0x.304 - Receive Status Register */
  648. u8 res12[8];
  649. u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
  650. u32 rqueue; /* 0x.314 - Receive queue control register */
  651. u32 rir0; /* 0x.318 - Ring mapping register 0 */
  652. u32 rir1; /* 0x.31c - Ring mapping register 1 */
  653. u32 rir2; /* 0x.320 - Ring mapping register 2 */
  654. u32 rir3; /* 0x.324 - Ring mapping register 3 */
  655. u8 res13[8];
  656. u32 rbifx; /* 0x.330 - Receive bit field extract control register */
  657. u32 rqfar; /* 0x.334 - Receive queue filing table address register */
  658. u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
  659. u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
  660. u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
  661. u8 res14[56];
  662. u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
  663. u8 res15a[4];
  664. u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
  665. u8 res15b[4];
  666. u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
  667. u8 res15c[4];
  668. u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
  669. u8 res15d[4];
  670. u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
  671. u8 res15e[4];
  672. u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
  673. u8 res15f[4];
  674. u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
  675. u8 res15g[4];
  676. u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
  677. u8 res15h[4];
  678. u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
  679. u8 res16[64];
  680. u32 rbaseh; /* 0x.400 - RxBD base address high */
  681. u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
  682. u8 res17a[4];
  683. u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
  684. u8 res17b[4];
  685. u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
  686. u8 res17c[4];
  687. u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
  688. u8 res17d[4];
  689. u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
  690. u8 res17e[4];
  691. u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
  692. u8 res17f[4];
  693. u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
  694. u8 res17g[4];
  695. u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
  696. u8 res17[192];
  697. u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
  698. u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
  699. u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
  700. u32 hafdup; /* 0x.50c - Half Duplex Register */
  701. u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
  702. u8 res18[12];
  703. u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
  704. u32 ifctrl; /* 0x.538 - Interface control register */
  705. u32 ifstat; /* 0x.53c - Interface Status Register */
  706. u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
  707. u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
  708. u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
  709. u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
  710. u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
  711. u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
  712. u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
  713. u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
  714. u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
  715. u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
  716. u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
  717. u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
  718. u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
  719. u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
  720. u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
  721. u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
  722. u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
  723. u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
  724. u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
  725. u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
  726. u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
  727. u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
  728. u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
  729. u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
  730. u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
  731. u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
  732. u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
  733. u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
  734. u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
  735. u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
  736. u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
  737. u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
  738. u8 res20[192];
  739. struct rmon_mib rmon; /* 0x.680-0x.73c */
  740. u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
  741. u8 res21[188];
  742. u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
  743. u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
  744. u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
  745. u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
  746. u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
  747. u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
  748. u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
  749. u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
  750. u8 res22[96];
  751. u32 gaddr0; /* 0x.880 - Group address register 0 */
  752. u32 gaddr1; /* 0x.884 - Group address register 1 */
  753. u32 gaddr2; /* 0x.888 - Group address register 2 */
  754. u32 gaddr3; /* 0x.88c - Group address register 3 */
  755. u32 gaddr4; /* 0x.890 - Group address register 4 */
  756. u32 gaddr5; /* 0x.894 - Group address register 5 */
  757. u32 gaddr6; /* 0x.898 - Group address register 6 */
  758. u32 gaddr7; /* 0x.89c - Group address register 7 */
  759. u8 res23a[352];
  760. u32 fifocfg; /* 0x.a00 - FIFO interface config register */
  761. u8 res23b[252];
  762. u8 res23c[248];
  763. u32 attr; /* 0x.bf8 - Attributes Register */
  764. u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
  765. u8 res24[688];
  766. u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
  767. u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
  768. u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
  769. u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
  770. u8 res25[16];
  771. u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
  772. u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
  773. u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
  774. u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
  775. u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
  776. u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
  777. u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
  778. u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
  779. u8 res26[32];
  780. u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
  781. u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
  782. u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
  783. u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
  784. u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
  785. u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
  786. u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
  787. u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
  788. u8 res27[208];
  789. };
  790. /* Flags related to gianfar device features */
  791. #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
  792. #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
  793. #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
  794. #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
  795. #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
  796. #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
  797. #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
  798. #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
  799. #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
  800. #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
  801. #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
  802. #define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
  803. #if (MAXGROUPS == 2)
  804. #define DEFAULT_MAPPING 0xAA
  805. #else
  806. #define DEFAULT_MAPPING 0xFF
  807. #endif
  808. #define ISRG_SHIFT_TX 0x10
  809. #define ISRG_SHIFT_RX 0x18
  810. /* The same driver can operate in two modes */
  811. /* SQ_SG_MODE: Single Queue Single Group Mode
  812. * (Backward compatible mode)
  813. * MQ_MG_MODE: Multi Queue Multi Group mode
  814. */
  815. enum {
  816. SQ_SG_MODE = 0,
  817. MQ_MG_MODE
  818. };
  819. /*
  820. * Per TX queue stats
  821. */
  822. struct tx_q_stats {
  823. unsigned long tx_packets;
  824. unsigned long tx_bytes;
  825. };
  826. /**
  827. * struct gfar_priv_tx_q - per tx queue structure
  828. * @txlock: per queue tx spin lock
  829. * @tx_skbuff:skb pointers
  830. * @skb_curtx: to be used skb pointer
  831. * @skb_dirtytx:the last used skb pointer
  832. * @stats: bytes/packets stats
  833. * @qindex: index of this queue
  834. * @dev: back pointer to the dev structure
  835. * @grp: back pointer to the group to which this queue belongs
  836. * @tx_bd_base: First tx buffer descriptor
  837. * @cur_tx: Next free ring entry
  838. * @dirty_tx: First buffer in line to be transmitted
  839. * @tx_ring_size: Tx ring size
  840. * @num_txbdfree: number of free TxBds
  841. * @txcoalescing: enable/disable tx coalescing
  842. * @txic: transmit interrupt coalescing value
  843. * @txcount: coalescing value if based on tx frame count
  844. * @txtime: coalescing value if based on time
  845. */
  846. struct gfar_priv_tx_q {
  847. spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
  848. struct sk_buff ** tx_skbuff;
  849. /* Buffer descriptor pointers */
  850. dma_addr_t tx_bd_dma_base;
  851. struct txbd8 *tx_bd_base;
  852. struct txbd8 *cur_tx;
  853. struct txbd8 *dirty_tx;
  854. struct tx_q_stats stats;
  855. struct net_device *dev;
  856. struct gfar_priv_grp *grp;
  857. u16 skb_curtx;
  858. u16 skb_dirtytx;
  859. u16 qindex;
  860. unsigned int tx_ring_size;
  861. unsigned int num_txbdfree;
  862. /* Configuration info for the coalescing features */
  863. unsigned char txcoalescing;
  864. unsigned long txic;
  865. unsigned short txcount;
  866. unsigned short txtime;
  867. };
  868. /*
  869. * Per RX queue stats
  870. */
  871. struct rx_q_stats {
  872. unsigned long rx_packets;
  873. unsigned long rx_bytes;
  874. unsigned long rx_dropped;
  875. };
  876. /**
  877. * struct gfar_priv_rx_q - per rx queue structure
  878. * @rxlock: per queue rx spin lock
  879. * @rx_skbuff: skb pointers
  880. * @skb_currx: currently use skb pointer
  881. * @rx_bd_base: First rx buffer descriptor
  882. * @cur_rx: Next free rx ring entry
  883. * @qindex: index of this queue
  884. * @dev: back pointer to the dev structure
  885. * @rx_ring_size: Rx ring size
  886. * @rxcoalescing: enable/disable rx-coalescing
  887. * @rxic: receive interrupt coalescing vlaue
  888. */
  889. struct gfar_priv_rx_q {
  890. spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
  891. struct sk_buff ** rx_skbuff;
  892. dma_addr_t rx_bd_dma_base;
  893. struct rxbd8 *rx_bd_base;
  894. struct rxbd8 *cur_rx;
  895. struct net_device *dev;
  896. struct gfar_priv_grp *grp;
  897. struct rx_q_stats stats;
  898. u16 skb_currx;
  899. u16 qindex;
  900. unsigned int rx_ring_size;
  901. /* RX Coalescing values */
  902. unsigned char rxcoalescing;
  903. unsigned long rxic;
  904. };
  905. /**
  906. * struct gfar_priv_grp - per group structure
  907. * @napi: the napi poll function
  908. * @priv: back pointer to the priv structure
  909. * @regs: the ioremapped register space for this group
  910. * @grp_id: group id for this group
  911. * @interruptTransmit: The TX interrupt number for this group
  912. * @interruptReceive: The RX interrupt number for this group
  913. * @interruptError: The ERROR interrupt number for this group
  914. * @int_name_tx: tx interrupt name for this group
  915. * @int_name_rx: rx interrupt name for this group
  916. * @int_name_er: er interrupt name for this group
  917. */
  918. struct gfar_priv_grp {
  919. spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
  920. struct napi_struct napi;
  921. struct gfar_private *priv;
  922. struct gfar __iomem *regs;
  923. unsigned int grp_id;
  924. unsigned long rx_bit_map;
  925. unsigned long tx_bit_map;
  926. unsigned long num_tx_queues;
  927. unsigned long num_rx_queues;
  928. unsigned int rstat;
  929. unsigned int tstat;
  930. unsigned int imask;
  931. unsigned int ievent;
  932. unsigned int interruptTransmit;
  933. unsigned int interruptReceive;
  934. unsigned int interruptError;
  935. char int_name_tx[GFAR_INT_NAME_MAX];
  936. char int_name_rx[GFAR_INT_NAME_MAX];
  937. char int_name_er[GFAR_INT_NAME_MAX];
  938. };
  939. enum gfar_errata {
  940. GFAR_ERRATA_74 = 0x01,
  941. GFAR_ERRATA_76 = 0x02,
  942. GFAR_ERRATA_A002 = 0x04,
  943. GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */
  944. };
  945. /* Struct stolen almost completely (and shamelessly) from the FCC enet source
  946. * (Ok, that's not so true anymore, but there is a family resemblance)
  947. * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
  948. * and tx_bd_base always point to the currently available buffer.
  949. * The dirty_tx tracks the current buffer that is being sent by the
  950. * controller. The cur_tx and dirty_tx are equal under both completely
  951. * empty and completely full conditions. The empty/ready indicator in
  952. * the buffer descriptor determines the actual condition.
  953. */
  954. struct gfar_private {
  955. /* Indicates how many tx, rx queues are enabled */
  956. unsigned int num_tx_queues;
  957. unsigned int num_rx_queues;
  958. unsigned int num_grps;
  959. unsigned int mode;
  960. /* The total tx and rx ring size for the enabled queues */
  961. unsigned int total_tx_ring_size;
  962. unsigned int total_rx_ring_size;
  963. struct device_node *node;
  964. struct net_device *ndev;
  965. struct platform_device *ofdev;
  966. enum gfar_errata errata;
  967. struct gfar_priv_grp gfargrp[MAXGROUPS];
  968. struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
  969. struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
  970. /* RX per device parameters */
  971. unsigned int rx_buffer_size;
  972. unsigned int rx_stash_size;
  973. unsigned int rx_stash_index;
  974. u32 cur_filer_idx;
  975. struct sk_buff_head rx_recycle;
  976. /* RX queue filer rule set*/
  977. struct ethtool_rx_list rx_list;
  978. struct mutex rx_queue_access;
  979. /* Hash registers and their width */
  980. u32 __iomem *hash_regs[16];
  981. int hash_width;
  982. /* global parameters */
  983. unsigned int fifo_threshold;
  984. unsigned int fifo_starve;
  985. unsigned int fifo_starve_off;
  986. /* Bitfield update lock */
  987. spinlock_t bflock;
  988. phy_interface_t interface;
  989. struct device_node *phy_node;
  990. struct device_node *tbi_node;
  991. u32 device_flags;
  992. unsigned char
  993. extended_hash:1,
  994. bd_stash_en:1,
  995. rx_filer_enable:1,
  996. wol_en:1; /* Wake-on-LAN enabled */
  997. unsigned short padding;
  998. /* PHY stuff */
  999. struct phy_device *phydev;
  1000. struct mii_bus *mii_bus;
  1001. int oldspeed;
  1002. int oldduplex;
  1003. int oldlink;
  1004. uint32_t msg_enable;
  1005. struct work_struct reset_task;
  1006. /* Network Statistics */
  1007. struct gfar_extra_stats extra_stats;
  1008. /* HW time stamping enabled flag */
  1009. int hwts_rx_en;
  1010. int hwts_tx_en;
  1011. /*Filer table*/
  1012. unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
  1013. unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
  1014. };
  1015. static inline int gfar_has_errata(struct gfar_private *priv,
  1016. enum gfar_errata err)
  1017. {
  1018. return priv->errata & err;
  1019. }
  1020. static inline u32 gfar_read(volatile unsigned __iomem *addr)
  1021. {
  1022. u32 val;
  1023. val = in_be32(addr);
  1024. return val;
  1025. }
  1026. static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
  1027. {
  1028. out_be32(addr, val);
  1029. }
  1030. static inline void gfar_write_filer(struct gfar_private *priv,
  1031. unsigned int far, unsigned int fcr, unsigned int fpr)
  1032. {
  1033. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1034. gfar_write(&regs->rqfar, far);
  1035. gfar_write(&regs->rqfcr, fcr);
  1036. gfar_write(&regs->rqfpr, fpr);
  1037. }
  1038. static inline void gfar_read_filer(struct gfar_private *priv,
  1039. unsigned int far, unsigned int *fcr, unsigned int *fpr)
  1040. {
  1041. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1042. gfar_write(&regs->rqfar, far);
  1043. *fcr = gfar_read(&regs->rqfcr);
  1044. *fpr = gfar_read(&regs->rqfpr);
  1045. }
  1046. extern void lock_rx_qs(struct gfar_private *priv);
  1047. extern void lock_tx_qs(struct gfar_private *priv);
  1048. extern void unlock_rx_qs(struct gfar_private *priv);
  1049. extern void unlock_tx_qs(struct gfar_private *priv);
  1050. extern irqreturn_t gfar_receive(int irq, void *dev_id);
  1051. extern int startup_gfar(struct net_device *dev);
  1052. extern void stop_gfar(struct net_device *dev);
  1053. extern void gfar_halt(struct net_device *dev);
  1054. extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
  1055. int enable, u32 regnum, u32 read);
  1056. extern void gfar_configure_coalescing(struct gfar_private *priv,
  1057. unsigned long tx_mask, unsigned long rx_mask);
  1058. void gfar_init_sysfs(struct net_device *dev);
  1059. int gfar_set_features(struct net_device *dev, u32 features);
  1060. extern void gfar_check_rx_parser_mode(struct gfar_private *priv);
  1061. extern void gfar_vlan_mode(struct net_device *dev, u32 features);
  1062. extern const struct ethtool_ops gfar_ethtool_ops;
  1063. #define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
  1064. #define RQFCR_PID_PRI_MASK 0xFFFFFFF8
  1065. #define RQFCR_PID_L4P_MASK 0xFFFFFF00
  1066. #define RQFCR_PID_VID_MASK 0xFFFFF000
  1067. #define RQFCR_PID_PORT_MASK 0xFFFF0000
  1068. #define RQFCR_PID_MAC_MASK 0xFF000000
  1069. struct gfar_mask_entry {
  1070. unsigned int mask; /* The mask value which is valid form start to end */
  1071. unsigned int start;
  1072. unsigned int end;
  1073. unsigned int block; /* Same block values indicate depended entries */
  1074. };
  1075. /* Represents a receive filer table entry */
  1076. struct gfar_filer_entry {
  1077. u32 ctrl;
  1078. u32 prop;
  1079. };
  1080. /* The 20 additional entries are a shadow for one extra element */
  1081. struct filer_table {
  1082. u32 index;
  1083. struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
  1084. };
  1085. #endif /* __GIANFAR_H */