cnic.c 140 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2011 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "cnic.h"
  47. #include "cnic_defs.h"
  48. #define DRV_MODULE_NAME "cnic"
  49. static char version[] __devinitdata =
  50. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  51. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  52. "Chen (zongxi@broadcom.com");
  53. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  54. MODULE_LICENSE("GPL");
  55. MODULE_VERSION(CNIC_MODULE_VERSION);
  56. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  57. static LIST_HEAD(cnic_dev_list);
  58. static LIST_HEAD(cnic_udev_list);
  59. static DEFINE_RWLOCK(cnic_dev_lock);
  60. static DEFINE_MUTEX(cnic_lock);
  61. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  62. /* helper function, assuming cnic_lock is held */
  63. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  64. {
  65. return rcu_dereference_protected(cnic_ulp_tbl[type],
  66. lockdep_is_held(&cnic_lock));
  67. }
  68. static int cnic_service_bnx2(void *, void *);
  69. static int cnic_service_bnx2x(void *, void *);
  70. static int cnic_ctl(void *, struct cnic_ctl_info *);
  71. static struct cnic_ops cnic_bnx2_ops = {
  72. .cnic_owner = THIS_MODULE,
  73. .cnic_handler = cnic_service_bnx2,
  74. .cnic_ctl = cnic_ctl,
  75. };
  76. static struct cnic_ops cnic_bnx2x_ops = {
  77. .cnic_owner = THIS_MODULE,
  78. .cnic_handler = cnic_service_bnx2x,
  79. .cnic_ctl = cnic_ctl,
  80. };
  81. static struct workqueue_struct *cnic_wq;
  82. static void cnic_shutdown_rings(struct cnic_dev *);
  83. static void cnic_init_rings(struct cnic_dev *);
  84. static int cnic_cm_set_pg(struct cnic_sock *);
  85. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  86. {
  87. struct cnic_uio_dev *udev = uinfo->priv;
  88. struct cnic_dev *dev;
  89. if (!capable(CAP_NET_ADMIN))
  90. return -EPERM;
  91. if (udev->uio_dev != -1)
  92. return -EBUSY;
  93. rtnl_lock();
  94. dev = udev->dev;
  95. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  96. rtnl_unlock();
  97. return -ENODEV;
  98. }
  99. udev->uio_dev = iminor(inode);
  100. cnic_shutdown_rings(dev);
  101. cnic_init_rings(dev);
  102. rtnl_unlock();
  103. return 0;
  104. }
  105. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  106. {
  107. struct cnic_uio_dev *udev = uinfo->priv;
  108. udev->uio_dev = -1;
  109. return 0;
  110. }
  111. static inline void cnic_hold(struct cnic_dev *dev)
  112. {
  113. atomic_inc(&dev->ref_count);
  114. }
  115. static inline void cnic_put(struct cnic_dev *dev)
  116. {
  117. atomic_dec(&dev->ref_count);
  118. }
  119. static inline void csk_hold(struct cnic_sock *csk)
  120. {
  121. atomic_inc(&csk->ref_count);
  122. }
  123. static inline void csk_put(struct cnic_sock *csk)
  124. {
  125. atomic_dec(&csk->ref_count);
  126. }
  127. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  128. {
  129. struct cnic_dev *cdev;
  130. read_lock(&cnic_dev_lock);
  131. list_for_each_entry(cdev, &cnic_dev_list, list) {
  132. if (netdev == cdev->netdev) {
  133. cnic_hold(cdev);
  134. read_unlock(&cnic_dev_lock);
  135. return cdev;
  136. }
  137. }
  138. read_unlock(&cnic_dev_lock);
  139. return NULL;
  140. }
  141. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  142. {
  143. atomic_inc(&ulp_ops->ref_count);
  144. }
  145. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  146. {
  147. atomic_dec(&ulp_ops->ref_count);
  148. }
  149. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  150. {
  151. struct cnic_local *cp = dev->cnic_priv;
  152. struct cnic_eth_dev *ethdev = cp->ethdev;
  153. struct drv_ctl_info info;
  154. struct drv_ctl_io *io = &info.data.io;
  155. info.cmd = DRV_CTL_CTX_WR_CMD;
  156. io->cid_addr = cid_addr;
  157. io->offset = off;
  158. io->data = val;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_io *io = &info.data.io;
  167. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  168. io->offset = off;
  169. io->dma_addr = addr;
  170. ethdev->drv_ctl(dev->netdev, &info);
  171. }
  172. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  173. {
  174. struct cnic_local *cp = dev->cnic_priv;
  175. struct cnic_eth_dev *ethdev = cp->ethdev;
  176. struct drv_ctl_info info;
  177. struct drv_ctl_l2_ring *ring = &info.data.ring;
  178. if (start)
  179. info.cmd = DRV_CTL_START_L2_CMD;
  180. else
  181. info.cmd = DRV_CTL_STOP_L2_CMD;
  182. ring->cid = cid;
  183. ring->client_id = cl_id;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_WR_CMD;
  193. io->offset = off;
  194. io->data = val;
  195. ethdev->drv_ctl(dev->netdev, &info);
  196. }
  197. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  198. {
  199. struct cnic_local *cp = dev->cnic_priv;
  200. struct cnic_eth_dev *ethdev = cp->ethdev;
  201. struct drv_ctl_info info;
  202. struct drv_ctl_io *io = &info.data.io;
  203. info.cmd = DRV_CTL_IO_RD_CMD;
  204. io->offset = off;
  205. ethdev->drv_ctl(dev->netdev, &info);
  206. return io->data;
  207. }
  208. static int cnic_in_use(struct cnic_sock *csk)
  209. {
  210. return test_bit(SK_F_INUSE, &csk->flags);
  211. }
  212. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  213. {
  214. struct cnic_local *cp = dev->cnic_priv;
  215. struct cnic_eth_dev *ethdev = cp->ethdev;
  216. struct drv_ctl_info info;
  217. info.cmd = cmd;
  218. info.data.credit.credit_count = count;
  219. ethdev->drv_ctl(dev->netdev, &info);
  220. }
  221. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  222. {
  223. u32 i;
  224. for (i = 0; i < cp->max_cid_space; i++) {
  225. if (cp->ctx_tbl[i].cid == cid) {
  226. *l5_cid = i;
  227. return 0;
  228. }
  229. }
  230. return -EINVAL;
  231. }
  232. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  233. struct cnic_sock *csk)
  234. {
  235. struct iscsi_path path_req;
  236. char *buf = NULL;
  237. u16 len = 0;
  238. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  239. struct cnic_ulp_ops *ulp_ops;
  240. struct cnic_uio_dev *udev = cp->udev;
  241. int rc = 0, retry = 0;
  242. if (!udev || udev->uio_dev == -1)
  243. return -ENODEV;
  244. if (csk) {
  245. len = sizeof(path_req);
  246. buf = (char *) &path_req;
  247. memset(&path_req, 0, len);
  248. msg_type = ISCSI_KEVENT_PATH_REQ;
  249. path_req.handle = (u64) csk->l5_cid;
  250. if (test_bit(SK_F_IPV6, &csk->flags)) {
  251. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  252. sizeof(struct in6_addr));
  253. path_req.ip_addr_len = 16;
  254. } else {
  255. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  256. sizeof(struct in_addr));
  257. path_req.ip_addr_len = 4;
  258. }
  259. path_req.vlan_id = csk->vlan_id;
  260. path_req.pmtu = csk->mtu;
  261. }
  262. while (retry < 3) {
  263. rc = 0;
  264. rcu_read_lock();
  265. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  266. if (ulp_ops)
  267. rc = ulp_ops->iscsi_nl_send_msg(
  268. cp->ulp_handle[CNIC_ULP_ISCSI],
  269. msg_type, buf, len);
  270. rcu_read_unlock();
  271. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  272. break;
  273. msleep(100);
  274. retry++;
  275. }
  276. return rc;
  277. }
  278. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  279. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  280. char *buf, u16 len)
  281. {
  282. int rc = -EINVAL;
  283. switch (msg_type) {
  284. case ISCSI_UEVENT_PATH_UPDATE: {
  285. struct cnic_local *cp;
  286. u32 l5_cid;
  287. struct cnic_sock *csk;
  288. struct iscsi_path *path_resp;
  289. if (len < sizeof(*path_resp))
  290. break;
  291. path_resp = (struct iscsi_path *) buf;
  292. cp = dev->cnic_priv;
  293. l5_cid = (u32) path_resp->handle;
  294. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  295. break;
  296. rcu_read_lock();
  297. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  298. rc = -ENODEV;
  299. rcu_read_unlock();
  300. break;
  301. }
  302. csk = &cp->csk_tbl[l5_cid];
  303. csk_hold(csk);
  304. if (cnic_in_use(csk) &&
  305. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  306. memcpy(csk->ha, path_resp->mac_addr, 6);
  307. if (test_bit(SK_F_IPV6, &csk->flags))
  308. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  309. sizeof(struct in6_addr));
  310. else
  311. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  312. sizeof(struct in_addr));
  313. if (is_valid_ether_addr(csk->ha)) {
  314. cnic_cm_set_pg(csk);
  315. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  316. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  317. cnic_cm_upcall(cp, csk,
  318. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  319. clear_bit(SK_F_CONNECT_START, &csk->flags);
  320. }
  321. }
  322. csk_put(csk);
  323. rcu_read_unlock();
  324. rc = 0;
  325. }
  326. }
  327. return rc;
  328. }
  329. static int cnic_offld_prep(struct cnic_sock *csk)
  330. {
  331. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  332. return 0;
  333. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  334. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  335. return 0;
  336. }
  337. return 1;
  338. }
  339. static int cnic_close_prep(struct cnic_sock *csk)
  340. {
  341. clear_bit(SK_F_CONNECT_START, &csk->flags);
  342. smp_mb__after_clear_bit();
  343. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  344. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  345. msleep(1);
  346. return 1;
  347. }
  348. return 0;
  349. }
  350. static int cnic_abort_prep(struct cnic_sock *csk)
  351. {
  352. clear_bit(SK_F_CONNECT_START, &csk->flags);
  353. smp_mb__after_clear_bit();
  354. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  355. msleep(1);
  356. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  357. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  358. return 1;
  359. }
  360. return 0;
  361. }
  362. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  363. {
  364. struct cnic_dev *dev;
  365. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  366. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  367. return -EINVAL;
  368. }
  369. mutex_lock(&cnic_lock);
  370. if (cnic_ulp_tbl_prot(ulp_type)) {
  371. pr_err("%s: Type %d has already been registered\n",
  372. __func__, ulp_type);
  373. mutex_unlock(&cnic_lock);
  374. return -EBUSY;
  375. }
  376. read_lock(&cnic_dev_lock);
  377. list_for_each_entry(dev, &cnic_dev_list, list) {
  378. struct cnic_local *cp = dev->cnic_priv;
  379. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  380. }
  381. read_unlock(&cnic_dev_lock);
  382. atomic_set(&ulp_ops->ref_count, 0);
  383. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  384. mutex_unlock(&cnic_lock);
  385. /* Prevent race conditions with netdev_event */
  386. rtnl_lock();
  387. list_for_each_entry(dev, &cnic_dev_list, list) {
  388. struct cnic_local *cp = dev->cnic_priv;
  389. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  390. ulp_ops->cnic_init(dev);
  391. }
  392. rtnl_unlock();
  393. return 0;
  394. }
  395. int cnic_unregister_driver(int ulp_type)
  396. {
  397. struct cnic_dev *dev;
  398. struct cnic_ulp_ops *ulp_ops;
  399. int i = 0;
  400. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  401. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  402. return -EINVAL;
  403. }
  404. mutex_lock(&cnic_lock);
  405. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  406. if (!ulp_ops) {
  407. pr_err("%s: Type %d has not been registered\n",
  408. __func__, ulp_type);
  409. goto out_unlock;
  410. }
  411. read_lock(&cnic_dev_lock);
  412. list_for_each_entry(dev, &cnic_dev_list, list) {
  413. struct cnic_local *cp = dev->cnic_priv;
  414. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  415. pr_err("%s: Type %d still has devices registered\n",
  416. __func__, ulp_type);
  417. read_unlock(&cnic_dev_lock);
  418. goto out_unlock;
  419. }
  420. }
  421. read_unlock(&cnic_dev_lock);
  422. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  423. mutex_unlock(&cnic_lock);
  424. synchronize_rcu();
  425. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  426. msleep(100);
  427. i++;
  428. }
  429. if (atomic_read(&ulp_ops->ref_count) != 0)
  430. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  431. return 0;
  432. out_unlock:
  433. mutex_unlock(&cnic_lock);
  434. return -EINVAL;
  435. }
  436. static int cnic_start_hw(struct cnic_dev *);
  437. static void cnic_stop_hw(struct cnic_dev *);
  438. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  439. void *ulp_ctx)
  440. {
  441. struct cnic_local *cp = dev->cnic_priv;
  442. struct cnic_ulp_ops *ulp_ops;
  443. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  444. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  445. return -EINVAL;
  446. }
  447. mutex_lock(&cnic_lock);
  448. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  449. pr_err("%s: Driver with type %d has not been registered\n",
  450. __func__, ulp_type);
  451. mutex_unlock(&cnic_lock);
  452. return -EAGAIN;
  453. }
  454. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  455. pr_err("%s: Type %d has already been registered to this device\n",
  456. __func__, ulp_type);
  457. mutex_unlock(&cnic_lock);
  458. return -EBUSY;
  459. }
  460. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  461. cp->ulp_handle[ulp_type] = ulp_ctx;
  462. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  463. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  464. cnic_hold(dev);
  465. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  466. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  467. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  468. mutex_unlock(&cnic_lock);
  469. return 0;
  470. }
  471. EXPORT_SYMBOL(cnic_register_driver);
  472. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  473. {
  474. struct cnic_local *cp = dev->cnic_priv;
  475. int i = 0;
  476. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  477. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  478. return -EINVAL;
  479. }
  480. mutex_lock(&cnic_lock);
  481. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  482. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  483. cnic_put(dev);
  484. } else {
  485. pr_err("%s: device not registered to this ulp type %d\n",
  486. __func__, ulp_type);
  487. mutex_unlock(&cnic_lock);
  488. return -EINVAL;
  489. }
  490. mutex_unlock(&cnic_lock);
  491. if (ulp_type == CNIC_ULP_ISCSI)
  492. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  493. synchronize_rcu();
  494. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  495. i < 20) {
  496. msleep(100);
  497. i++;
  498. }
  499. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  500. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  501. return 0;
  502. }
  503. EXPORT_SYMBOL(cnic_unregister_driver);
  504. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  505. u32 next)
  506. {
  507. id_tbl->start = start_id;
  508. id_tbl->max = size;
  509. id_tbl->next = next;
  510. spin_lock_init(&id_tbl->lock);
  511. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  512. if (!id_tbl->table)
  513. return -ENOMEM;
  514. return 0;
  515. }
  516. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  517. {
  518. kfree(id_tbl->table);
  519. id_tbl->table = NULL;
  520. }
  521. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  522. {
  523. int ret = -1;
  524. id -= id_tbl->start;
  525. if (id >= id_tbl->max)
  526. return ret;
  527. spin_lock(&id_tbl->lock);
  528. if (!test_bit(id, id_tbl->table)) {
  529. set_bit(id, id_tbl->table);
  530. ret = 0;
  531. }
  532. spin_unlock(&id_tbl->lock);
  533. return ret;
  534. }
  535. /* Returns -1 if not successful */
  536. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  537. {
  538. u32 id;
  539. spin_lock(&id_tbl->lock);
  540. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  541. if (id >= id_tbl->max) {
  542. id = -1;
  543. if (id_tbl->next != 0) {
  544. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  545. if (id >= id_tbl->next)
  546. id = -1;
  547. }
  548. }
  549. if (id < id_tbl->max) {
  550. set_bit(id, id_tbl->table);
  551. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  552. id += id_tbl->start;
  553. }
  554. spin_unlock(&id_tbl->lock);
  555. return id;
  556. }
  557. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  558. {
  559. if (id == -1)
  560. return;
  561. id -= id_tbl->start;
  562. if (id >= id_tbl->max)
  563. return;
  564. clear_bit(id, id_tbl->table);
  565. }
  566. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  567. {
  568. int i;
  569. if (!dma->pg_arr)
  570. return;
  571. for (i = 0; i < dma->num_pages; i++) {
  572. if (dma->pg_arr[i]) {
  573. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  574. dma->pg_arr[i], dma->pg_map_arr[i]);
  575. dma->pg_arr[i] = NULL;
  576. }
  577. }
  578. if (dma->pgtbl) {
  579. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  580. dma->pgtbl, dma->pgtbl_map);
  581. dma->pgtbl = NULL;
  582. }
  583. kfree(dma->pg_arr);
  584. dma->pg_arr = NULL;
  585. dma->num_pages = 0;
  586. }
  587. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  588. {
  589. int i;
  590. __le32 *page_table = (__le32 *) dma->pgtbl;
  591. for (i = 0; i < dma->num_pages; i++) {
  592. /* Each entry needs to be in big endian format. */
  593. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  594. page_table++;
  595. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  596. page_table++;
  597. }
  598. }
  599. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  600. {
  601. int i;
  602. __le32 *page_table = (__le32 *) dma->pgtbl;
  603. for (i = 0; i < dma->num_pages; i++) {
  604. /* Each entry needs to be in little endian format. */
  605. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  606. page_table++;
  607. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  608. page_table++;
  609. }
  610. }
  611. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  612. int pages, int use_pg_tbl)
  613. {
  614. int i, size;
  615. struct cnic_local *cp = dev->cnic_priv;
  616. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  617. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  618. if (dma->pg_arr == NULL)
  619. return -ENOMEM;
  620. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  621. dma->num_pages = pages;
  622. for (i = 0; i < pages; i++) {
  623. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  624. BCM_PAGE_SIZE,
  625. &dma->pg_map_arr[i],
  626. GFP_ATOMIC);
  627. if (dma->pg_arr[i] == NULL)
  628. goto error;
  629. }
  630. if (!use_pg_tbl)
  631. return 0;
  632. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  633. ~(BCM_PAGE_SIZE - 1);
  634. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  635. &dma->pgtbl_map, GFP_ATOMIC);
  636. if (dma->pgtbl == NULL)
  637. goto error;
  638. cp->setup_pgtbl(dev, dma);
  639. return 0;
  640. error:
  641. cnic_free_dma(dev, dma);
  642. return -ENOMEM;
  643. }
  644. static void cnic_free_context(struct cnic_dev *dev)
  645. {
  646. struct cnic_local *cp = dev->cnic_priv;
  647. int i;
  648. for (i = 0; i < cp->ctx_blks; i++) {
  649. if (cp->ctx_arr[i].ctx) {
  650. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  651. cp->ctx_arr[i].ctx,
  652. cp->ctx_arr[i].mapping);
  653. cp->ctx_arr[i].ctx = NULL;
  654. }
  655. }
  656. }
  657. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  658. {
  659. uio_unregister_device(&udev->cnic_uinfo);
  660. if (udev->l2_buf) {
  661. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  662. udev->l2_buf, udev->l2_buf_map);
  663. udev->l2_buf = NULL;
  664. }
  665. if (udev->l2_ring) {
  666. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  667. udev->l2_ring, udev->l2_ring_map);
  668. udev->l2_ring = NULL;
  669. }
  670. pci_dev_put(udev->pdev);
  671. kfree(udev);
  672. }
  673. static void cnic_free_uio(struct cnic_uio_dev *udev)
  674. {
  675. if (!udev)
  676. return;
  677. write_lock(&cnic_dev_lock);
  678. list_del_init(&udev->list);
  679. write_unlock(&cnic_dev_lock);
  680. __cnic_free_uio(udev);
  681. }
  682. static void cnic_free_resc(struct cnic_dev *dev)
  683. {
  684. struct cnic_local *cp = dev->cnic_priv;
  685. struct cnic_uio_dev *udev = cp->udev;
  686. if (udev) {
  687. udev->dev = NULL;
  688. cp->udev = NULL;
  689. }
  690. cnic_free_context(dev);
  691. kfree(cp->ctx_arr);
  692. cp->ctx_arr = NULL;
  693. cp->ctx_blks = 0;
  694. cnic_free_dma(dev, &cp->gbl_buf_info);
  695. cnic_free_dma(dev, &cp->kwq_info);
  696. cnic_free_dma(dev, &cp->kwq_16_data_info);
  697. cnic_free_dma(dev, &cp->kcq2.dma);
  698. cnic_free_dma(dev, &cp->kcq1.dma);
  699. kfree(cp->iscsi_tbl);
  700. cp->iscsi_tbl = NULL;
  701. kfree(cp->ctx_tbl);
  702. cp->ctx_tbl = NULL;
  703. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  704. cnic_free_id_tbl(&cp->cid_tbl);
  705. }
  706. static int cnic_alloc_context(struct cnic_dev *dev)
  707. {
  708. struct cnic_local *cp = dev->cnic_priv;
  709. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  710. int i, k, arr_size;
  711. cp->ctx_blk_size = BCM_PAGE_SIZE;
  712. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  713. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  714. sizeof(struct cnic_ctx);
  715. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  716. if (cp->ctx_arr == NULL)
  717. return -ENOMEM;
  718. k = 0;
  719. for (i = 0; i < 2; i++) {
  720. u32 j, reg, off, lo, hi;
  721. if (i == 0)
  722. off = BNX2_PG_CTX_MAP;
  723. else
  724. off = BNX2_ISCSI_CTX_MAP;
  725. reg = cnic_reg_rd_ind(dev, off);
  726. lo = reg >> 16;
  727. hi = reg & 0xffff;
  728. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  729. cp->ctx_arr[k].cid = j;
  730. }
  731. cp->ctx_blks = k;
  732. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  733. cp->ctx_blks = 0;
  734. return -ENOMEM;
  735. }
  736. for (i = 0; i < cp->ctx_blks; i++) {
  737. cp->ctx_arr[i].ctx =
  738. dma_alloc_coherent(&dev->pcidev->dev,
  739. BCM_PAGE_SIZE,
  740. &cp->ctx_arr[i].mapping,
  741. GFP_KERNEL);
  742. if (cp->ctx_arr[i].ctx == NULL)
  743. return -ENOMEM;
  744. }
  745. }
  746. return 0;
  747. }
  748. static u16 cnic_bnx2_next_idx(u16 idx)
  749. {
  750. return idx + 1;
  751. }
  752. static u16 cnic_bnx2_hw_idx(u16 idx)
  753. {
  754. return idx;
  755. }
  756. static u16 cnic_bnx2x_next_idx(u16 idx)
  757. {
  758. idx++;
  759. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  760. idx++;
  761. return idx;
  762. }
  763. static u16 cnic_bnx2x_hw_idx(u16 idx)
  764. {
  765. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  766. idx++;
  767. return idx;
  768. }
  769. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  770. bool use_pg_tbl)
  771. {
  772. int err, i, use_page_tbl = 0;
  773. struct kcqe **kcq;
  774. if (use_pg_tbl)
  775. use_page_tbl = 1;
  776. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  777. if (err)
  778. return err;
  779. kcq = (struct kcqe **) info->dma.pg_arr;
  780. info->kcq = kcq;
  781. info->next_idx = cnic_bnx2_next_idx;
  782. info->hw_idx = cnic_bnx2_hw_idx;
  783. if (use_pg_tbl)
  784. return 0;
  785. info->next_idx = cnic_bnx2x_next_idx;
  786. info->hw_idx = cnic_bnx2x_hw_idx;
  787. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  788. struct bnx2x_bd_chain_next *next =
  789. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  790. int j = i + 1;
  791. if (j >= KCQ_PAGE_CNT)
  792. j = 0;
  793. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  794. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  795. }
  796. return 0;
  797. }
  798. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  799. {
  800. struct cnic_local *cp = dev->cnic_priv;
  801. struct cnic_uio_dev *udev;
  802. read_lock(&cnic_dev_lock);
  803. list_for_each_entry(udev, &cnic_udev_list, list) {
  804. if (udev->pdev == dev->pcidev) {
  805. udev->dev = dev;
  806. cp->udev = udev;
  807. read_unlock(&cnic_dev_lock);
  808. return 0;
  809. }
  810. }
  811. read_unlock(&cnic_dev_lock);
  812. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  813. if (!udev)
  814. return -ENOMEM;
  815. udev->uio_dev = -1;
  816. udev->dev = dev;
  817. udev->pdev = dev->pcidev;
  818. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  819. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  820. &udev->l2_ring_map,
  821. GFP_KERNEL | __GFP_COMP);
  822. if (!udev->l2_ring)
  823. goto err_udev;
  824. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  825. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  826. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  827. &udev->l2_buf_map,
  828. GFP_KERNEL | __GFP_COMP);
  829. if (!udev->l2_buf)
  830. goto err_dma;
  831. write_lock(&cnic_dev_lock);
  832. list_add(&udev->list, &cnic_udev_list);
  833. write_unlock(&cnic_dev_lock);
  834. pci_dev_get(udev->pdev);
  835. cp->udev = udev;
  836. return 0;
  837. err_dma:
  838. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  839. udev->l2_ring, udev->l2_ring_map);
  840. err_udev:
  841. kfree(udev);
  842. return -ENOMEM;
  843. }
  844. static int cnic_init_uio(struct cnic_dev *dev)
  845. {
  846. struct cnic_local *cp = dev->cnic_priv;
  847. struct cnic_uio_dev *udev = cp->udev;
  848. struct uio_info *uinfo;
  849. int ret = 0;
  850. if (!udev)
  851. return -ENOMEM;
  852. uinfo = &udev->cnic_uinfo;
  853. uinfo->mem[0].addr = dev->netdev->base_addr;
  854. uinfo->mem[0].internal_addr = dev->regview;
  855. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  856. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  857. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  858. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  859. PAGE_MASK;
  860. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  861. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  862. else
  863. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  864. uinfo->name = "bnx2_cnic";
  865. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  866. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  867. PAGE_MASK;
  868. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  869. uinfo->name = "bnx2x_cnic";
  870. }
  871. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  872. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  873. uinfo->mem[2].size = udev->l2_ring_size;
  874. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  875. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  876. uinfo->mem[3].size = udev->l2_buf_size;
  877. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  878. uinfo->version = CNIC_MODULE_VERSION;
  879. uinfo->irq = UIO_IRQ_CUSTOM;
  880. uinfo->open = cnic_uio_open;
  881. uinfo->release = cnic_uio_close;
  882. if (udev->uio_dev == -1) {
  883. if (!uinfo->priv) {
  884. uinfo->priv = udev;
  885. ret = uio_register_device(&udev->pdev->dev, uinfo);
  886. }
  887. } else {
  888. cnic_init_rings(dev);
  889. }
  890. return ret;
  891. }
  892. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  893. {
  894. struct cnic_local *cp = dev->cnic_priv;
  895. int ret;
  896. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  897. if (ret)
  898. goto error;
  899. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  900. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  901. if (ret)
  902. goto error;
  903. ret = cnic_alloc_context(dev);
  904. if (ret)
  905. goto error;
  906. ret = cnic_alloc_uio_rings(dev, 2);
  907. if (ret)
  908. goto error;
  909. ret = cnic_init_uio(dev);
  910. if (ret)
  911. goto error;
  912. return 0;
  913. error:
  914. cnic_free_resc(dev);
  915. return ret;
  916. }
  917. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  918. {
  919. struct cnic_local *cp = dev->cnic_priv;
  920. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  921. int total_mem, blks, i;
  922. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  923. blks = total_mem / ctx_blk_size;
  924. if (total_mem % ctx_blk_size)
  925. blks++;
  926. if (blks > cp->ethdev->ctx_tbl_len)
  927. return -ENOMEM;
  928. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  929. if (cp->ctx_arr == NULL)
  930. return -ENOMEM;
  931. cp->ctx_blks = blks;
  932. cp->ctx_blk_size = ctx_blk_size;
  933. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  934. cp->ctx_align = 0;
  935. else
  936. cp->ctx_align = ctx_blk_size;
  937. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  938. for (i = 0; i < blks; i++) {
  939. cp->ctx_arr[i].ctx =
  940. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  941. &cp->ctx_arr[i].mapping,
  942. GFP_KERNEL);
  943. if (cp->ctx_arr[i].ctx == NULL)
  944. return -ENOMEM;
  945. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  946. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  947. cnic_free_context(dev);
  948. cp->ctx_blk_size += cp->ctx_align;
  949. i = -1;
  950. continue;
  951. }
  952. }
  953. }
  954. return 0;
  955. }
  956. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  957. {
  958. struct cnic_local *cp = dev->cnic_priv;
  959. struct cnic_eth_dev *ethdev = cp->ethdev;
  960. u32 start_cid = ethdev->starting_cid;
  961. int i, j, n, ret, pages;
  962. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  963. cp->iro_arr = ethdev->iro_arr;
  964. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  965. cp->iscsi_start_cid = start_cid;
  966. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  967. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  968. cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
  969. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  970. if (!cp->fcoe_init_cid)
  971. cp->fcoe_init_cid = 0x10;
  972. }
  973. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  974. GFP_KERNEL);
  975. if (!cp->iscsi_tbl)
  976. goto error;
  977. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  978. cp->max_cid_space, GFP_KERNEL);
  979. if (!cp->ctx_tbl)
  980. goto error;
  981. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  982. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  983. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  984. }
  985. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  986. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  987. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  988. PAGE_SIZE;
  989. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  990. if (ret)
  991. return -ENOMEM;
  992. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  993. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  994. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  995. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  996. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  997. off;
  998. if ((i % n) == (n - 1))
  999. j++;
  1000. }
  1001. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1002. if (ret)
  1003. goto error;
  1004. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1005. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1006. if (ret)
  1007. goto error;
  1008. }
  1009. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1010. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1011. if (ret)
  1012. goto error;
  1013. ret = cnic_alloc_bnx2x_context(dev);
  1014. if (ret)
  1015. goto error;
  1016. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1017. cp->l2_rx_ring_size = 15;
  1018. ret = cnic_alloc_uio_rings(dev, 4);
  1019. if (ret)
  1020. goto error;
  1021. ret = cnic_init_uio(dev);
  1022. if (ret)
  1023. goto error;
  1024. return 0;
  1025. error:
  1026. cnic_free_resc(dev);
  1027. return -ENOMEM;
  1028. }
  1029. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1030. {
  1031. return cp->max_kwq_idx -
  1032. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1033. }
  1034. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1035. u32 num_wqes)
  1036. {
  1037. struct cnic_local *cp = dev->cnic_priv;
  1038. struct kwqe *prod_qe;
  1039. u16 prod, sw_prod, i;
  1040. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1041. return -EAGAIN; /* bnx2 is down */
  1042. spin_lock_bh(&cp->cnic_ulp_lock);
  1043. if (num_wqes > cnic_kwq_avail(cp) &&
  1044. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1045. spin_unlock_bh(&cp->cnic_ulp_lock);
  1046. return -EAGAIN;
  1047. }
  1048. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1049. prod = cp->kwq_prod_idx;
  1050. sw_prod = prod & MAX_KWQ_IDX;
  1051. for (i = 0; i < num_wqes; i++) {
  1052. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1053. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1054. prod++;
  1055. sw_prod = prod & MAX_KWQ_IDX;
  1056. }
  1057. cp->kwq_prod_idx = prod;
  1058. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1059. spin_unlock_bh(&cp->cnic_ulp_lock);
  1060. return 0;
  1061. }
  1062. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1063. union l5cm_specific_data *l5_data)
  1064. {
  1065. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1066. dma_addr_t map;
  1067. map = ctx->kwqe_data_mapping;
  1068. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1069. l5_data->phy_address.hi = (u64) map >> 32;
  1070. return ctx->kwqe_data;
  1071. }
  1072. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1073. u32 type, union l5cm_specific_data *l5_data)
  1074. {
  1075. struct cnic_local *cp = dev->cnic_priv;
  1076. struct l5cm_spe kwqe;
  1077. struct kwqe_16 *kwq[1];
  1078. u16 type_16;
  1079. int ret;
  1080. kwqe.hdr.conn_and_cmd_data =
  1081. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1082. BNX2X_HW_CID(cp, cid)));
  1083. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1084. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1085. SPE_HDR_FUNCTION_ID;
  1086. kwqe.hdr.type = cpu_to_le16(type_16);
  1087. kwqe.hdr.reserved1 = 0;
  1088. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1089. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1090. kwq[0] = (struct kwqe_16 *) &kwqe;
  1091. spin_lock_bh(&cp->cnic_ulp_lock);
  1092. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1093. spin_unlock_bh(&cp->cnic_ulp_lock);
  1094. if (ret == 1)
  1095. return 0;
  1096. return -EBUSY;
  1097. }
  1098. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1099. struct kcqe *cqes[], u32 num_cqes)
  1100. {
  1101. struct cnic_local *cp = dev->cnic_priv;
  1102. struct cnic_ulp_ops *ulp_ops;
  1103. rcu_read_lock();
  1104. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1105. if (likely(ulp_ops)) {
  1106. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1107. cqes, num_cqes);
  1108. }
  1109. rcu_read_unlock();
  1110. }
  1111. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1112. {
  1113. struct cnic_local *cp = dev->cnic_priv;
  1114. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1115. int hq_bds, pages;
  1116. u32 pfid = cp->pfid;
  1117. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1118. cp->num_ccells = req1->num_ccells_per_conn;
  1119. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1120. cp->num_iscsi_tasks;
  1121. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1122. BNX2X_ISCSI_R2TQE_SIZE;
  1123. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1124. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1125. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1126. cp->num_cqs = req1->num_cqs;
  1127. if (!dev->max_iscsi_conn)
  1128. return 0;
  1129. /* init Tstorm RAM */
  1130. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1131. req1->rq_num_wqes);
  1132. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1133. PAGE_SIZE);
  1134. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1135. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1136. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1137. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1138. req1->num_tasks_per_conn);
  1139. /* init Ustorm RAM */
  1140. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1141. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1142. req1->rq_buffer_size);
  1143. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1144. PAGE_SIZE);
  1145. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1146. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1147. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1148. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1149. req1->num_tasks_per_conn);
  1150. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1151. req1->rq_num_wqes);
  1152. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1153. req1->cq_num_wqes);
  1154. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1155. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1156. /* init Xstorm RAM */
  1157. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1158. PAGE_SIZE);
  1159. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1160. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1161. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1162. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1163. req1->num_tasks_per_conn);
  1164. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1165. hq_bds);
  1166. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1167. req1->num_tasks_per_conn);
  1168. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1169. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1170. /* init Cstorm RAM */
  1171. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1172. PAGE_SIZE);
  1173. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1174. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1175. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1176. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1177. req1->num_tasks_per_conn);
  1178. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1179. req1->cq_num_wqes);
  1180. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1181. hq_bds);
  1182. return 0;
  1183. }
  1184. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1185. {
  1186. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1187. struct cnic_local *cp = dev->cnic_priv;
  1188. u32 pfid = cp->pfid;
  1189. struct iscsi_kcqe kcqe;
  1190. struct kcqe *cqes[1];
  1191. memset(&kcqe, 0, sizeof(kcqe));
  1192. if (!dev->max_iscsi_conn) {
  1193. kcqe.completion_status =
  1194. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1195. goto done;
  1196. }
  1197. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1198. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1199. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1200. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1201. req2->error_bit_map[1]);
  1202. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1203. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1204. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1205. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1206. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1207. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1208. req2->error_bit_map[1]);
  1209. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1210. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1211. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1212. done:
  1213. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1214. cqes[0] = (struct kcqe *) &kcqe;
  1215. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1216. return 0;
  1217. }
  1218. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1219. {
  1220. struct cnic_local *cp = dev->cnic_priv;
  1221. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1222. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1223. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1224. cnic_free_dma(dev, &iscsi->hq_info);
  1225. cnic_free_dma(dev, &iscsi->r2tq_info);
  1226. cnic_free_dma(dev, &iscsi->task_array_info);
  1227. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1228. } else {
  1229. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1230. }
  1231. ctx->cid = 0;
  1232. }
  1233. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1234. {
  1235. u32 cid;
  1236. int ret, pages;
  1237. struct cnic_local *cp = dev->cnic_priv;
  1238. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1239. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1240. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1241. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1242. if (cid == -1) {
  1243. ret = -ENOMEM;
  1244. goto error;
  1245. }
  1246. ctx->cid = cid;
  1247. return 0;
  1248. }
  1249. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1250. if (cid == -1) {
  1251. ret = -ENOMEM;
  1252. goto error;
  1253. }
  1254. ctx->cid = cid;
  1255. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1256. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1257. if (ret)
  1258. goto error;
  1259. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1260. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1261. if (ret)
  1262. goto error;
  1263. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1264. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1265. if (ret)
  1266. goto error;
  1267. return 0;
  1268. error:
  1269. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1270. return ret;
  1271. }
  1272. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1273. struct regpair *ctx_addr)
  1274. {
  1275. struct cnic_local *cp = dev->cnic_priv;
  1276. struct cnic_eth_dev *ethdev = cp->ethdev;
  1277. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1278. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1279. unsigned long align_off = 0;
  1280. dma_addr_t ctx_map;
  1281. void *ctx;
  1282. if (cp->ctx_align) {
  1283. unsigned long mask = cp->ctx_align - 1;
  1284. if (cp->ctx_arr[blk].mapping & mask)
  1285. align_off = cp->ctx_align -
  1286. (cp->ctx_arr[blk].mapping & mask);
  1287. }
  1288. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1289. (off * BNX2X_CONTEXT_MEM_SIZE);
  1290. ctx = cp->ctx_arr[blk].ctx + align_off +
  1291. (off * BNX2X_CONTEXT_MEM_SIZE);
  1292. if (init)
  1293. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1294. ctx_addr->lo = ctx_map & 0xffffffff;
  1295. ctx_addr->hi = (u64) ctx_map >> 32;
  1296. return ctx;
  1297. }
  1298. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1299. u32 num)
  1300. {
  1301. struct cnic_local *cp = dev->cnic_priv;
  1302. struct iscsi_kwqe_conn_offload1 *req1 =
  1303. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1304. struct iscsi_kwqe_conn_offload2 *req2 =
  1305. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1306. struct iscsi_kwqe_conn_offload3 *req3;
  1307. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1308. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1309. u32 cid = ctx->cid;
  1310. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1311. struct iscsi_context *ictx;
  1312. struct regpair context_addr;
  1313. int i, j, n = 2, n_max;
  1314. u8 port = CNIC_PORT(cp);
  1315. ctx->ctx_flags = 0;
  1316. if (!req2->num_additional_wqes)
  1317. return -EINVAL;
  1318. n_max = req2->num_additional_wqes + 2;
  1319. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1320. if (ictx == NULL)
  1321. return -ENOMEM;
  1322. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1323. ictx->xstorm_ag_context.hq_prod = 1;
  1324. ictx->xstorm_st_context.iscsi.first_burst_length =
  1325. ISCSI_DEF_FIRST_BURST_LEN;
  1326. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1327. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1328. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1329. req1->sq_page_table_addr_lo;
  1330. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1331. req1->sq_page_table_addr_hi;
  1332. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1333. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1334. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1335. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1336. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1337. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1338. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1339. iscsi->hq_info.pgtbl[0];
  1340. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1341. iscsi->hq_info.pgtbl[1];
  1342. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1343. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1344. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1345. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1346. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1347. iscsi->r2tq_info.pgtbl[0];
  1348. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1349. iscsi->r2tq_info.pgtbl[1];
  1350. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1351. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1352. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1353. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1354. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1355. BNX2X_ISCSI_PBL_NOT_CACHED;
  1356. ictx->xstorm_st_context.iscsi.flags.flags |=
  1357. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1358. ictx->xstorm_st_context.iscsi.flags.flags |=
  1359. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1360. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1361. ETH_P_8021Q;
  1362. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1363. cp->port_mode == CHIP_2_PORT_MODE) {
  1364. port = 0;
  1365. }
  1366. ictx->xstorm_st_context.common.flags =
  1367. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1368. ictx->xstorm_st_context.common.flags =
  1369. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1370. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1371. /* TSTORM requires the base address of RQ DB & not PTE */
  1372. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1373. req2->rq_page_table_addr_lo & PAGE_MASK;
  1374. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1375. req2->rq_page_table_addr_hi;
  1376. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1377. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1378. ictx->tstorm_st_context.tcp.flags2 |=
  1379. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1380. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1381. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1382. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1383. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1384. req2->rq_page_table_addr_lo;
  1385. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1386. req2->rq_page_table_addr_hi;
  1387. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1388. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1389. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1390. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1391. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1392. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1393. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1394. iscsi->r2tq_info.pgtbl[0];
  1395. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1396. iscsi->r2tq_info.pgtbl[1];
  1397. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1398. req1->cq_page_table_addr_lo;
  1399. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1400. req1->cq_page_table_addr_hi;
  1401. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1402. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1403. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1404. ictx->ustorm_st_context.task_pbe_cache_index =
  1405. BNX2X_ISCSI_PBL_NOT_CACHED;
  1406. ictx->ustorm_st_context.task_pdu_cache_index =
  1407. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1408. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1409. if (j == 3) {
  1410. if (n >= n_max)
  1411. break;
  1412. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1413. j = 0;
  1414. }
  1415. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1416. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1417. req3->qp_first_pte[j].hi;
  1418. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1419. req3->qp_first_pte[j].lo;
  1420. }
  1421. ictx->ustorm_st_context.task_pbl_base.lo =
  1422. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1423. ictx->ustorm_st_context.task_pbl_base.hi =
  1424. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1425. ictx->ustorm_st_context.tce_phy_addr.lo =
  1426. iscsi->task_array_info.pgtbl[0];
  1427. ictx->ustorm_st_context.tce_phy_addr.hi =
  1428. iscsi->task_array_info.pgtbl[1];
  1429. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1430. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1431. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1432. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1433. ISCSI_DEF_MAX_BURST_LEN;
  1434. ictx->ustorm_st_context.negotiated_rx |=
  1435. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1436. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1437. ictx->cstorm_st_context.hq_pbl_base.lo =
  1438. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1439. ictx->cstorm_st_context.hq_pbl_base.hi =
  1440. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1441. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1442. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1443. ictx->cstorm_st_context.task_pbl_base.lo =
  1444. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1445. ictx->cstorm_st_context.task_pbl_base.hi =
  1446. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1447. /* CSTORM and USTORM initialization is different, CSTORM requires
  1448. * CQ DB base & not PTE addr */
  1449. ictx->cstorm_st_context.cq_db_base.lo =
  1450. req1->cq_page_table_addr_lo & PAGE_MASK;
  1451. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1452. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1453. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1454. for (i = 0; i < cp->num_cqs; i++) {
  1455. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1456. ISCSI_INITIAL_SN;
  1457. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1458. ISCSI_INITIAL_SN;
  1459. }
  1460. ictx->xstorm_ag_context.cdu_reserved =
  1461. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1462. ISCSI_CONNECTION_TYPE);
  1463. ictx->ustorm_ag_context.cdu_usage =
  1464. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1465. ISCSI_CONNECTION_TYPE);
  1466. return 0;
  1467. }
  1468. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1469. u32 num, int *work)
  1470. {
  1471. struct iscsi_kwqe_conn_offload1 *req1;
  1472. struct iscsi_kwqe_conn_offload2 *req2;
  1473. struct cnic_local *cp = dev->cnic_priv;
  1474. struct cnic_context *ctx;
  1475. struct iscsi_kcqe kcqe;
  1476. struct kcqe *cqes[1];
  1477. u32 l5_cid;
  1478. int ret = 0;
  1479. if (num < 2) {
  1480. *work = num;
  1481. return -EINVAL;
  1482. }
  1483. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1484. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1485. if ((num - 2) < req2->num_additional_wqes) {
  1486. *work = num;
  1487. return -EINVAL;
  1488. }
  1489. *work = 2 + req2->num_additional_wqes;
  1490. l5_cid = req1->iscsi_conn_id;
  1491. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1492. return -EINVAL;
  1493. memset(&kcqe, 0, sizeof(kcqe));
  1494. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1495. kcqe.iscsi_conn_id = l5_cid;
  1496. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1497. ctx = &cp->ctx_tbl[l5_cid];
  1498. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1499. kcqe.completion_status =
  1500. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1501. goto done;
  1502. }
  1503. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1504. atomic_dec(&cp->iscsi_conn);
  1505. goto done;
  1506. }
  1507. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1508. if (ret) {
  1509. atomic_dec(&cp->iscsi_conn);
  1510. ret = 0;
  1511. goto done;
  1512. }
  1513. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1514. if (ret < 0) {
  1515. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1516. atomic_dec(&cp->iscsi_conn);
  1517. goto done;
  1518. }
  1519. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1520. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1521. done:
  1522. cqes[0] = (struct kcqe *) &kcqe;
  1523. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1524. return ret;
  1525. }
  1526. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1527. {
  1528. struct cnic_local *cp = dev->cnic_priv;
  1529. struct iscsi_kwqe_conn_update *req =
  1530. (struct iscsi_kwqe_conn_update *) kwqe;
  1531. void *data;
  1532. union l5cm_specific_data l5_data;
  1533. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1534. int ret;
  1535. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1536. return -EINVAL;
  1537. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1538. if (!data)
  1539. return -ENOMEM;
  1540. memcpy(data, kwqe, sizeof(struct kwqe));
  1541. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1542. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1543. return ret;
  1544. }
  1545. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1546. {
  1547. struct cnic_local *cp = dev->cnic_priv;
  1548. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1549. union l5cm_specific_data l5_data;
  1550. int ret;
  1551. u32 hw_cid;
  1552. init_waitqueue_head(&ctx->waitq);
  1553. ctx->wait_cond = 0;
  1554. memset(&l5_data, 0, sizeof(l5_data));
  1555. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1556. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1557. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1558. if (ret == 0) {
  1559. wait_event(ctx->waitq, ctx->wait_cond);
  1560. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1561. return -EBUSY;
  1562. }
  1563. return ret;
  1564. }
  1565. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1566. {
  1567. struct cnic_local *cp = dev->cnic_priv;
  1568. struct iscsi_kwqe_conn_destroy *req =
  1569. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1570. u32 l5_cid = req->reserved0;
  1571. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1572. int ret = 0;
  1573. struct iscsi_kcqe kcqe;
  1574. struct kcqe *cqes[1];
  1575. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1576. goto skip_cfc_delete;
  1577. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1578. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1579. if (delta > (2 * HZ))
  1580. delta = 0;
  1581. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1582. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1583. goto destroy_reply;
  1584. }
  1585. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1586. skip_cfc_delete:
  1587. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1588. if (!ret) {
  1589. atomic_dec(&cp->iscsi_conn);
  1590. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1591. }
  1592. destroy_reply:
  1593. memset(&kcqe, 0, sizeof(kcqe));
  1594. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1595. kcqe.iscsi_conn_id = l5_cid;
  1596. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1597. kcqe.iscsi_conn_context_id = req->context_id;
  1598. cqes[0] = (struct kcqe *) &kcqe;
  1599. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1600. return ret;
  1601. }
  1602. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1603. struct l4_kwq_connect_req1 *kwqe1,
  1604. struct l4_kwq_connect_req3 *kwqe3,
  1605. struct l5cm_active_conn_buffer *conn_buf)
  1606. {
  1607. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1608. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1609. &conn_buf->xstorm_conn_buffer;
  1610. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1611. &conn_buf->tstorm_conn_buffer;
  1612. struct regpair context_addr;
  1613. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1614. struct in6_addr src_ip, dst_ip;
  1615. int i;
  1616. u32 *addrp;
  1617. addrp = (u32 *) &conn_addr->local_ip_addr;
  1618. for (i = 0; i < 4; i++, addrp++)
  1619. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1620. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1621. for (i = 0; i < 4; i++, addrp++)
  1622. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1623. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1624. xstorm_buf->context_addr.hi = context_addr.hi;
  1625. xstorm_buf->context_addr.lo = context_addr.lo;
  1626. xstorm_buf->mss = 0xffff;
  1627. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1628. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1629. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1630. xstorm_buf->pseudo_header_checksum =
  1631. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1632. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1633. tstorm_buf->params |=
  1634. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1635. if (kwqe3->ka_timeout) {
  1636. tstorm_buf->ka_enable = 1;
  1637. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1638. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1639. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1640. }
  1641. tstorm_buf->max_rt_time = 0xffffffff;
  1642. }
  1643. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1644. {
  1645. struct cnic_local *cp = dev->cnic_priv;
  1646. u32 pfid = cp->pfid;
  1647. u8 *mac = dev->mac_addr;
  1648. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1649. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1650. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1651. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1652. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1653. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1654. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1655. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1656. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1657. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1658. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1659. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1660. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1661. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1662. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1663. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1664. mac[4]);
  1665. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1666. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1667. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1668. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1669. mac[2]);
  1670. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1671. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1672. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1673. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1674. mac[0]);
  1675. }
  1676. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1677. {
  1678. struct cnic_local *cp = dev->cnic_priv;
  1679. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1680. u16 tstorm_flags = 0;
  1681. if (tcp_ts) {
  1682. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1683. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1684. }
  1685. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1686. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1687. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1688. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1689. }
  1690. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1691. u32 num, int *work)
  1692. {
  1693. struct cnic_local *cp = dev->cnic_priv;
  1694. struct l4_kwq_connect_req1 *kwqe1 =
  1695. (struct l4_kwq_connect_req1 *) wqes[0];
  1696. struct l4_kwq_connect_req3 *kwqe3;
  1697. struct l5cm_active_conn_buffer *conn_buf;
  1698. struct l5cm_conn_addr_params *conn_addr;
  1699. union l5cm_specific_data l5_data;
  1700. u32 l5_cid = kwqe1->pg_cid;
  1701. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1702. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1703. int ret;
  1704. if (num < 2) {
  1705. *work = num;
  1706. return -EINVAL;
  1707. }
  1708. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1709. *work = 3;
  1710. else
  1711. *work = 2;
  1712. if (num < *work) {
  1713. *work = num;
  1714. return -EINVAL;
  1715. }
  1716. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1717. netdev_err(dev->netdev, "conn_buf size too big\n");
  1718. return -ENOMEM;
  1719. }
  1720. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1721. if (!conn_buf)
  1722. return -ENOMEM;
  1723. memset(conn_buf, 0, sizeof(*conn_buf));
  1724. conn_addr = &conn_buf->conn_addr_buf;
  1725. conn_addr->remote_addr_0 = csk->ha[0];
  1726. conn_addr->remote_addr_1 = csk->ha[1];
  1727. conn_addr->remote_addr_2 = csk->ha[2];
  1728. conn_addr->remote_addr_3 = csk->ha[3];
  1729. conn_addr->remote_addr_4 = csk->ha[4];
  1730. conn_addr->remote_addr_5 = csk->ha[5];
  1731. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1732. struct l4_kwq_connect_req2 *kwqe2 =
  1733. (struct l4_kwq_connect_req2 *) wqes[1];
  1734. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1735. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1736. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1737. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1738. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1739. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1740. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1741. }
  1742. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1743. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1744. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1745. conn_addr->local_tcp_port = kwqe1->src_port;
  1746. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1747. conn_addr->pmtu = kwqe3->pmtu;
  1748. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1749. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1750. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1751. cnic_bnx2x_set_tcp_timestamp(dev,
  1752. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1753. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1754. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1755. if (!ret)
  1756. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1757. return ret;
  1758. }
  1759. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1760. {
  1761. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1762. union l5cm_specific_data l5_data;
  1763. int ret;
  1764. memset(&l5_data, 0, sizeof(l5_data));
  1765. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1766. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1767. return ret;
  1768. }
  1769. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1770. {
  1771. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1772. union l5cm_specific_data l5_data;
  1773. int ret;
  1774. memset(&l5_data, 0, sizeof(l5_data));
  1775. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1776. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1777. return ret;
  1778. }
  1779. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1780. {
  1781. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1782. struct l4_kcq kcqe;
  1783. struct kcqe *cqes[1];
  1784. memset(&kcqe, 0, sizeof(kcqe));
  1785. kcqe.pg_host_opaque = req->host_opaque;
  1786. kcqe.pg_cid = req->host_opaque;
  1787. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1788. cqes[0] = (struct kcqe *) &kcqe;
  1789. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1790. return 0;
  1791. }
  1792. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1793. {
  1794. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1795. struct l4_kcq kcqe;
  1796. struct kcqe *cqes[1];
  1797. memset(&kcqe, 0, sizeof(kcqe));
  1798. kcqe.pg_host_opaque = req->pg_host_opaque;
  1799. kcqe.pg_cid = req->pg_cid;
  1800. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1801. cqes[0] = (struct kcqe *) &kcqe;
  1802. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1803. return 0;
  1804. }
  1805. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1806. {
  1807. struct fcoe_kwqe_stat *req;
  1808. struct fcoe_stat_ramrod_params *fcoe_stat;
  1809. union l5cm_specific_data l5_data;
  1810. struct cnic_local *cp = dev->cnic_priv;
  1811. int ret;
  1812. u32 cid;
  1813. req = (struct fcoe_kwqe_stat *) kwqe;
  1814. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1815. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1816. if (!fcoe_stat)
  1817. return -ENOMEM;
  1818. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1819. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1820. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1821. FCOE_CONNECTION_TYPE, &l5_data);
  1822. return ret;
  1823. }
  1824. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1825. u32 num, int *work)
  1826. {
  1827. int ret;
  1828. struct cnic_local *cp = dev->cnic_priv;
  1829. u32 cid;
  1830. struct fcoe_init_ramrod_params *fcoe_init;
  1831. struct fcoe_kwqe_init1 *req1;
  1832. struct fcoe_kwqe_init2 *req2;
  1833. struct fcoe_kwqe_init3 *req3;
  1834. union l5cm_specific_data l5_data;
  1835. if (num < 3) {
  1836. *work = num;
  1837. return -EINVAL;
  1838. }
  1839. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1840. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1841. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1842. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1843. *work = 1;
  1844. return -EINVAL;
  1845. }
  1846. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1847. *work = 2;
  1848. return -EINVAL;
  1849. }
  1850. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1851. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1852. return -ENOMEM;
  1853. }
  1854. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1855. if (!fcoe_init)
  1856. return -ENOMEM;
  1857. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1858. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1859. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1860. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1861. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1862. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1863. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1864. fcoe_init->sb_num = cp->status_blk_num;
  1865. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1866. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1867. cp->kcq2.sw_prod_idx = 0;
  1868. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1869. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1870. FCOE_CONNECTION_TYPE, &l5_data);
  1871. *work = 3;
  1872. return ret;
  1873. }
  1874. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1875. u32 num, int *work)
  1876. {
  1877. int ret = 0;
  1878. u32 cid = -1, l5_cid;
  1879. struct cnic_local *cp = dev->cnic_priv;
  1880. struct fcoe_kwqe_conn_offload1 *req1;
  1881. struct fcoe_kwqe_conn_offload2 *req2;
  1882. struct fcoe_kwqe_conn_offload3 *req3;
  1883. struct fcoe_kwqe_conn_offload4 *req4;
  1884. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1885. struct cnic_context *ctx;
  1886. struct fcoe_context *fctx;
  1887. struct regpair ctx_addr;
  1888. union l5cm_specific_data l5_data;
  1889. struct fcoe_kcqe kcqe;
  1890. struct kcqe *cqes[1];
  1891. if (num < 4) {
  1892. *work = num;
  1893. return -EINVAL;
  1894. }
  1895. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1896. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1897. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1898. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1899. *work = 4;
  1900. l5_cid = req1->fcoe_conn_id;
  1901. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1902. goto err_reply;
  1903. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1904. ctx = &cp->ctx_tbl[l5_cid];
  1905. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1906. goto err_reply;
  1907. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1908. if (ret) {
  1909. ret = 0;
  1910. goto err_reply;
  1911. }
  1912. cid = ctx->cid;
  1913. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1914. if (fctx) {
  1915. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1916. u32 val;
  1917. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1918. FCOE_CONNECTION_TYPE);
  1919. fctx->xstorm_ag_context.cdu_reserved = val;
  1920. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1921. FCOE_CONNECTION_TYPE);
  1922. fctx->ustorm_ag_context.cdu_usage = val;
  1923. }
  1924. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1925. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1926. goto err_reply;
  1927. }
  1928. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1929. if (!fcoe_offload)
  1930. goto err_reply;
  1931. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1932. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1933. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1934. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1935. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1936. cid = BNX2X_HW_CID(cp, cid);
  1937. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1938. FCOE_CONNECTION_TYPE, &l5_data);
  1939. if (!ret)
  1940. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1941. return ret;
  1942. err_reply:
  1943. if (cid != -1)
  1944. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1945. memset(&kcqe, 0, sizeof(kcqe));
  1946. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1947. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1948. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1949. cqes[0] = (struct kcqe *) &kcqe;
  1950. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1951. return ret;
  1952. }
  1953. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1954. {
  1955. struct fcoe_kwqe_conn_enable_disable *req;
  1956. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1957. union l5cm_specific_data l5_data;
  1958. int ret;
  1959. u32 cid, l5_cid;
  1960. struct cnic_local *cp = dev->cnic_priv;
  1961. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1962. cid = req->context_id;
  1963. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1964. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1965. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1966. return -ENOMEM;
  1967. }
  1968. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1969. if (!fcoe_enable)
  1970. return -ENOMEM;
  1971. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1972. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1973. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1974. FCOE_CONNECTION_TYPE, &l5_data);
  1975. return ret;
  1976. }
  1977. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1978. {
  1979. struct fcoe_kwqe_conn_enable_disable *req;
  1980. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1981. union l5cm_specific_data l5_data;
  1982. int ret;
  1983. u32 cid, l5_cid;
  1984. struct cnic_local *cp = dev->cnic_priv;
  1985. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1986. cid = req->context_id;
  1987. l5_cid = req->conn_id;
  1988. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1989. return -EINVAL;
  1990. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1991. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  1992. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  1993. return -ENOMEM;
  1994. }
  1995. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1996. if (!fcoe_disable)
  1997. return -ENOMEM;
  1998. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  1999. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2000. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2001. FCOE_CONNECTION_TYPE, &l5_data);
  2002. return ret;
  2003. }
  2004. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2005. {
  2006. struct fcoe_kwqe_conn_destroy *req;
  2007. union l5cm_specific_data l5_data;
  2008. int ret;
  2009. u32 cid, l5_cid;
  2010. struct cnic_local *cp = dev->cnic_priv;
  2011. struct cnic_context *ctx;
  2012. struct fcoe_kcqe kcqe;
  2013. struct kcqe *cqes[1];
  2014. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2015. cid = req->context_id;
  2016. l5_cid = req->conn_id;
  2017. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  2018. return -EINVAL;
  2019. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2020. ctx = &cp->ctx_tbl[l5_cid];
  2021. init_waitqueue_head(&ctx->waitq);
  2022. ctx->wait_cond = 0;
  2023. memset(&l5_data, 0, sizeof(l5_data));
  2024. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2025. FCOE_CONNECTION_TYPE, &l5_data);
  2026. if (ret == 0) {
  2027. wait_event(ctx->waitq, ctx->wait_cond);
  2028. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2029. queue_delayed_work(cnic_wq, &cp->delete_task,
  2030. msecs_to_jiffies(2000));
  2031. }
  2032. memset(&kcqe, 0, sizeof(kcqe));
  2033. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2034. kcqe.fcoe_conn_id = req->conn_id;
  2035. kcqe.fcoe_conn_context_id = cid;
  2036. cqes[0] = (struct kcqe *) &kcqe;
  2037. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2038. return ret;
  2039. }
  2040. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2041. {
  2042. struct cnic_local *cp = dev->cnic_priv;
  2043. u32 i;
  2044. for (i = start_cid; i < cp->max_cid_space; i++) {
  2045. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2046. int j;
  2047. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2048. msleep(10);
  2049. for (j = 0; j < 5; j++) {
  2050. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2051. break;
  2052. msleep(20);
  2053. }
  2054. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2055. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2056. ctx->cid);
  2057. }
  2058. }
  2059. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2060. {
  2061. struct fcoe_kwqe_destroy *req;
  2062. union l5cm_specific_data l5_data;
  2063. struct cnic_local *cp = dev->cnic_priv;
  2064. int ret;
  2065. u32 cid;
  2066. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2067. req = (struct fcoe_kwqe_destroy *) kwqe;
  2068. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2069. memset(&l5_data, 0, sizeof(l5_data));
  2070. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2071. FCOE_CONNECTION_TYPE, &l5_data);
  2072. return ret;
  2073. }
  2074. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2075. struct kwqe *wqes[], u32 num_wqes)
  2076. {
  2077. int i, work, ret;
  2078. u32 opcode;
  2079. struct kwqe *kwqe;
  2080. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2081. return -EAGAIN; /* bnx2 is down */
  2082. for (i = 0; i < num_wqes; ) {
  2083. kwqe = wqes[i];
  2084. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2085. work = 1;
  2086. switch (opcode) {
  2087. case ISCSI_KWQE_OPCODE_INIT1:
  2088. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2089. break;
  2090. case ISCSI_KWQE_OPCODE_INIT2:
  2091. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2092. break;
  2093. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2094. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2095. num_wqes - i, &work);
  2096. break;
  2097. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2098. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2099. break;
  2100. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2101. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2102. break;
  2103. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2104. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2105. &work);
  2106. break;
  2107. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2108. ret = cnic_bnx2x_close(dev, kwqe);
  2109. break;
  2110. case L4_KWQE_OPCODE_VALUE_RESET:
  2111. ret = cnic_bnx2x_reset(dev, kwqe);
  2112. break;
  2113. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2114. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2115. break;
  2116. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2117. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2118. break;
  2119. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2120. ret = 0;
  2121. break;
  2122. default:
  2123. ret = 0;
  2124. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2125. opcode);
  2126. break;
  2127. }
  2128. if (ret < 0)
  2129. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2130. opcode);
  2131. i += work;
  2132. }
  2133. return 0;
  2134. }
  2135. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2136. struct kwqe *wqes[], u32 num_wqes)
  2137. {
  2138. struct cnic_local *cp = dev->cnic_priv;
  2139. int i, work, ret;
  2140. u32 opcode;
  2141. struct kwqe *kwqe;
  2142. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2143. return -EAGAIN; /* bnx2 is down */
  2144. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2145. return -EINVAL;
  2146. for (i = 0; i < num_wqes; ) {
  2147. kwqe = wqes[i];
  2148. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2149. work = 1;
  2150. switch (opcode) {
  2151. case FCOE_KWQE_OPCODE_INIT1:
  2152. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2153. num_wqes - i, &work);
  2154. break;
  2155. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2156. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2157. num_wqes - i, &work);
  2158. break;
  2159. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2160. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2161. break;
  2162. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2163. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2164. break;
  2165. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2166. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2167. break;
  2168. case FCOE_KWQE_OPCODE_DESTROY:
  2169. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2170. break;
  2171. case FCOE_KWQE_OPCODE_STAT:
  2172. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2173. break;
  2174. default:
  2175. ret = 0;
  2176. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2177. opcode);
  2178. break;
  2179. }
  2180. if (ret < 0)
  2181. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2182. opcode);
  2183. i += work;
  2184. }
  2185. return 0;
  2186. }
  2187. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2188. u32 num_wqes)
  2189. {
  2190. int ret = -EINVAL;
  2191. u32 layer_code;
  2192. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2193. return -EAGAIN; /* bnx2x is down */
  2194. if (!num_wqes)
  2195. return 0;
  2196. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2197. switch (layer_code) {
  2198. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2199. case KWQE_FLAGS_LAYER_MASK_L4:
  2200. case KWQE_FLAGS_LAYER_MASK_L2:
  2201. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2202. break;
  2203. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2204. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2205. break;
  2206. }
  2207. return ret;
  2208. }
  2209. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2210. {
  2211. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2212. return KCQE_FLAGS_LAYER_MASK_L4;
  2213. return opflag & KCQE_FLAGS_LAYER_MASK;
  2214. }
  2215. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2216. {
  2217. struct cnic_local *cp = dev->cnic_priv;
  2218. int i, j, comp = 0;
  2219. i = 0;
  2220. j = 1;
  2221. while (num_cqes) {
  2222. struct cnic_ulp_ops *ulp_ops;
  2223. int ulp_type;
  2224. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2225. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2226. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2227. comp++;
  2228. while (j < num_cqes) {
  2229. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2230. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2231. break;
  2232. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2233. comp++;
  2234. j++;
  2235. }
  2236. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2237. ulp_type = CNIC_ULP_RDMA;
  2238. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2239. ulp_type = CNIC_ULP_ISCSI;
  2240. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2241. ulp_type = CNIC_ULP_FCOE;
  2242. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2243. ulp_type = CNIC_ULP_L4;
  2244. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2245. goto end;
  2246. else {
  2247. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2248. kcqe_op_flag);
  2249. goto end;
  2250. }
  2251. rcu_read_lock();
  2252. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2253. if (likely(ulp_ops)) {
  2254. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2255. cp->completed_kcq + i, j);
  2256. }
  2257. rcu_read_unlock();
  2258. end:
  2259. num_cqes -= j;
  2260. i += j;
  2261. j = 1;
  2262. }
  2263. if (unlikely(comp))
  2264. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2265. }
  2266. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2267. {
  2268. struct cnic_local *cp = dev->cnic_priv;
  2269. u16 i, ri, hw_prod, last;
  2270. struct kcqe *kcqe;
  2271. int kcqe_cnt = 0, last_cnt = 0;
  2272. i = ri = last = info->sw_prod_idx;
  2273. ri &= MAX_KCQ_IDX;
  2274. hw_prod = *info->hw_prod_idx_ptr;
  2275. hw_prod = info->hw_idx(hw_prod);
  2276. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2277. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2278. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2279. i = info->next_idx(i);
  2280. ri = i & MAX_KCQ_IDX;
  2281. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2282. last_cnt = kcqe_cnt;
  2283. last = i;
  2284. }
  2285. }
  2286. info->sw_prod_idx = last;
  2287. return last_cnt;
  2288. }
  2289. static int cnic_l2_completion(struct cnic_local *cp)
  2290. {
  2291. u16 hw_cons, sw_cons;
  2292. struct cnic_uio_dev *udev = cp->udev;
  2293. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2294. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2295. u32 cmd;
  2296. int comp = 0;
  2297. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2298. return 0;
  2299. hw_cons = *cp->rx_cons_ptr;
  2300. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2301. hw_cons++;
  2302. sw_cons = cp->rx_cons;
  2303. while (sw_cons != hw_cons) {
  2304. u8 cqe_fp_flags;
  2305. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2306. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2307. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2308. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2309. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2310. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2311. cmd == RAMROD_CMD_ID_ETH_HALT)
  2312. comp++;
  2313. }
  2314. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2315. }
  2316. return comp;
  2317. }
  2318. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2319. {
  2320. u16 rx_cons, tx_cons;
  2321. int comp = 0;
  2322. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2323. return;
  2324. rx_cons = *cp->rx_cons_ptr;
  2325. tx_cons = *cp->tx_cons_ptr;
  2326. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2327. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2328. comp = cnic_l2_completion(cp);
  2329. cp->tx_cons = tx_cons;
  2330. cp->rx_cons = rx_cons;
  2331. if (cp->udev)
  2332. uio_event_notify(&cp->udev->cnic_uinfo);
  2333. }
  2334. if (comp)
  2335. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2336. }
  2337. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2338. {
  2339. struct cnic_local *cp = dev->cnic_priv;
  2340. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2341. int kcqe_cnt;
  2342. /* status block index must be read before reading other fields */
  2343. rmb();
  2344. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2345. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2346. service_kcqes(dev, kcqe_cnt);
  2347. /* Tell compiler that status_blk fields can change. */
  2348. barrier();
  2349. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2350. /* status block index must be read first */
  2351. rmb();
  2352. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2353. }
  2354. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2355. cnic_chk_pkt_rings(cp);
  2356. return status_idx;
  2357. }
  2358. static int cnic_service_bnx2(void *data, void *status_blk)
  2359. {
  2360. struct cnic_dev *dev = data;
  2361. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2362. struct status_block *sblk = status_blk;
  2363. return sblk->status_idx;
  2364. }
  2365. return cnic_service_bnx2_queues(dev);
  2366. }
  2367. static void cnic_service_bnx2_msix(unsigned long data)
  2368. {
  2369. struct cnic_dev *dev = (struct cnic_dev *) data;
  2370. struct cnic_local *cp = dev->cnic_priv;
  2371. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2372. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2373. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2374. }
  2375. static void cnic_doirq(struct cnic_dev *dev)
  2376. {
  2377. struct cnic_local *cp = dev->cnic_priv;
  2378. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2379. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2380. prefetch(cp->status_blk.gen);
  2381. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2382. tasklet_schedule(&cp->cnic_irq_task);
  2383. }
  2384. }
  2385. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2386. {
  2387. struct cnic_dev *dev = dev_instance;
  2388. struct cnic_local *cp = dev->cnic_priv;
  2389. if (cp->ack_int)
  2390. cp->ack_int(dev);
  2391. cnic_doirq(dev);
  2392. return IRQ_HANDLED;
  2393. }
  2394. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2395. u16 index, u8 op, u8 update)
  2396. {
  2397. struct cnic_local *cp = dev->cnic_priv;
  2398. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2399. COMMAND_REG_INT_ACK);
  2400. struct igu_ack_register igu_ack;
  2401. igu_ack.status_block_index = index;
  2402. igu_ack.sb_id_and_flags =
  2403. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2404. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2405. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2406. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2407. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2408. }
  2409. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2410. u16 index, u8 op, u8 update)
  2411. {
  2412. struct igu_regular cmd_data;
  2413. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2414. cmd_data.sb_id_and_flags =
  2415. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2416. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2417. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2418. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2419. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2420. }
  2421. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2422. {
  2423. struct cnic_local *cp = dev->cnic_priv;
  2424. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2425. IGU_INT_DISABLE, 0);
  2426. }
  2427. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2428. {
  2429. struct cnic_local *cp = dev->cnic_priv;
  2430. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2431. IGU_INT_DISABLE, 0);
  2432. }
  2433. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2434. {
  2435. u32 last_status = *info->status_idx_ptr;
  2436. int kcqe_cnt;
  2437. /* status block index must be read before reading the KCQ */
  2438. rmb();
  2439. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2440. service_kcqes(dev, kcqe_cnt);
  2441. /* Tell compiler that sblk fields can change. */
  2442. barrier();
  2443. last_status = *info->status_idx_ptr;
  2444. /* status block index must be read before reading the KCQ */
  2445. rmb();
  2446. }
  2447. return last_status;
  2448. }
  2449. static void cnic_service_bnx2x_bh(unsigned long data)
  2450. {
  2451. struct cnic_dev *dev = (struct cnic_dev *) data;
  2452. struct cnic_local *cp = dev->cnic_priv;
  2453. u32 status_idx, new_status_idx;
  2454. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2455. return;
  2456. while (1) {
  2457. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2458. CNIC_WR16(dev, cp->kcq1.io_addr,
  2459. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2460. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  2461. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2462. status_idx, IGU_INT_ENABLE, 1);
  2463. break;
  2464. }
  2465. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2466. if (new_status_idx != status_idx)
  2467. continue;
  2468. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2469. MAX_KCQ_IDX);
  2470. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2471. status_idx, IGU_INT_ENABLE, 1);
  2472. break;
  2473. }
  2474. }
  2475. static int cnic_service_bnx2x(void *data, void *status_blk)
  2476. {
  2477. struct cnic_dev *dev = data;
  2478. struct cnic_local *cp = dev->cnic_priv;
  2479. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2480. cnic_doirq(dev);
  2481. cnic_chk_pkt_rings(cp);
  2482. return 0;
  2483. }
  2484. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2485. {
  2486. struct cnic_ulp_ops *ulp_ops;
  2487. if (if_type == CNIC_ULP_ISCSI)
  2488. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2489. mutex_lock(&cnic_lock);
  2490. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2491. lockdep_is_held(&cnic_lock));
  2492. if (!ulp_ops) {
  2493. mutex_unlock(&cnic_lock);
  2494. return;
  2495. }
  2496. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2497. mutex_unlock(&cnic_lock);
  2498. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2499. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2500. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2501. }
  2502. static void cnic_ulp_stop(struct cnic_dev *dev)
  2503. {
  2504. struct cnic_local *cp = dev->cnic_priv;
  2505. int if_type;
  2506. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2507. cnic_ulp_stop_one(cp, if_type);
  2508. }
  2509. static void cnic_ulp_start(struct cnic_dev *dev)
  2510. {
  2511. struct cnic_local *cp = dev->cnic_priv;
  2512. int if_type;
  2513. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2514. struct cnic_ulp_ops *ulp_ops;
  2515. mutex_lock(&cnic_lock);
  2516. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2517. lockdep_is_held(&cnic_lock));
  2518. if (!ulp_ops || !ulp_ops->cnic_start) {
  2519. mutex_unlock(&cnic_lock);
  2520. continue;
  2521. }
  2522. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2523. mutex_unlock(&cnic_lock);
  2524. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2525. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2526. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2527. }
  2528. }
  2529. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2530. {
  2531. struct cnic_dev *dev = data;
  2532. switch (info->cmd) {
  2533. case CNIC_CTL_STOP_CMD:
  2534. cnic_hold(dev);
  2535. cnic_ulp_stop(dev);
  2536. cnic_stop_hw(dev);
  2537. cnic_put(dev);
  2538. break;
  2539. case CNIC_CTL_START_CMD:
  2540. cnic_hold(dev);
  2541. if (!cnic_start_hw(dev))
  2542. cnic_ulp_start(dev);
  2543. cnic_put(dev);
  2544. break;
  2545. case CNIC_CTL_STOP_ISCSI_CMD: {
  2546. struct cnic_local *cp = dev->cnic_priv;
  2547. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2548. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2549. break;
  2550. }
  2551. case CNIC_CTL_COMPLETION_CMD: {
  2552. struct cnic_ctl_completion *comp = &info->data.comp;
  2553. u32 cid = BNX2X_SW_CID(comp->cid);
  2554. u32 l5_cid;
  2555. struct cnic_local *cp = dev->cnic_priv;
  2556. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2557. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2558. if (unlikely(comp->error)) {
  2559. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2560. netdev_err(dev->netdev,
  2561. "CID %x CFC delete comp error %x\n",
  2562. cid, comp->error);
  2563. }
  2564. ctx->wait_cond = 1;
  2565. wake_up(&ctx->waitq);
  2566. }
  2567. break;
  2568. }
  2569. default:
  2570. return -EINVAL;
  2571. }
  2572. return 0;
  2573. }
  2574. static void cnic_ulp_init(struct cnic_dev *dev)
  2575. {
  2576. int i;
  2577. struct cnic_local *cp = dev->cnic_priv;
  2578. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2579. struct cnic_ulp_ops *ulp_ops;
  2580. mutex_lock(&cnic_lock);
  2581. ulp_ops = cnic_ulp_tbl_prot(i);
  2582. if (!ulp_ops || !ulp_ops->cnic_init) {
  2583. mutex_unlock(&cnic_lock);
  2584. continue;
  2585. }
  2586. ulp_get(ulp_ops);
  2587. mutex_unlock(&cnic_lock);
  2588. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2589. ulp_ops->cnic_init(dev);
  2590. ulp_put(ulp_ops);
  2591. }
  2592. }
  2593. static void cnic_ulp_exit(struct cnic_dev *dev)
  2594. {
  2595. int i;
  2596. struct cnic_local *cp = dev->cnic_priv;
  2597. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2598. struct cnic_ulp_ops *ulp_ops;
  2599. mutex_lock(&cnic_lock);
  2600. ulp_ops = cnic_ulp_tbl_prot(i);
  2601. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2602. mutex_unlock(&cnic_lock);
  2603. continue;
  2604. }
  2605. ulp_get(ulp_ops);
  2606. mutex_unlock(&cnic_lock);
  2607. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2608. ulp_ops->cnic_exit(dev);
  2609. ulp_put(ulp_ops);
  2610. }
  2611. }
  2612. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2613. {
  2614. struct cnic_dev *dev = csk->dev;
  2615. struct l4_kwq_offload_pg *l4kwqe;
  2616. struct kwqe *wqes[1];
  2617. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2618. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2619. wqes[0] = (struct kwqe *) l4kwqe;
  2620. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2621. l4kwqe->flags =
  2622. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2623. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2624. l4kwqe->da0 = csk->ha[0];
  2625. l4kwqe->da1 = csk->ha[1];
  2626. l4kwqe->da2 = csk->ha[2];
  2627. l4kwqe->da3 = csk->ha[3];
  2628. l4kwqe->da4 = csk->ha[4];
  2629. l4kwqe->da5 = csk->ha[5];
  2630. l4kwqe->sa0 = dev->mac_addr[0];
  2631. l4kwqe->sa1 = dev->mac_addr[1];
  2632. l4kwqe->sa2 = dev->mac_addr[2];
  2633. l4kwqe->sa3 = dev->mac_addr[3];
  2634. l4kwqe->sa4 = dev->mac_addr[4];
  2635. l4kwqe->sa5 = dev->mac_addr[5];
  2636. l4kwqe->etype = ETH_P_IP;
  2637. l4kwqe->ipid_start = DEF_IPID_START;
  2638. l4kwqe->host_opaque = csk->l5_cid;
  2639. if (csk->vlan_id) {
  2640. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2641. l4kwqe->vlan_tag = csk->vlan_id;
  2642. l4kwqe->l2hdr_nbytes += 4;
  2643. }
  2644. return dev->submit_kwqes(dev, wqes, 1);
  2645. }
  2646. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2647. {
  2648. struct cnic_dev *dev = csk->dev;
  2649. struct l4_kwq_update_pg *l4kwqe;
  2650. struct kwqe *wqes[1];
  2651. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2652. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2653. wqes[0] = (struct kwqe *) l4kwqe;
  2654. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2655. l4kwqe->flags =
  2656. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2657. l4kwqe->pg_cid = csk->pg_cid;
  2658. l4kwqe->da0 = csk->ha[0];
  2659. l4kwqe->da1 = csk->ha[1];
  2660. l4kwqe->da2 = csk->ha[2];
  2661. l4kwqe->da3 = csk->ha[3];
  2662. l4kwqe->da4 = csk->ha[4];
  2663. l4kwqe->da5 = csk->ha[5];
  2664. l4kwqe->pg_host_opaque = csk->l5_cid;
  2665. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2666. return dev->submit_kwqes(dev, wqes, 1);
  2667. }
  2668. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2669. {
  2670. struct cnic_dev *dev = csk->dev;
  2671. struct l4_kwq_upload *l4kwqe;
  2672. struct kwqe *wqes[1];
  2673. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2674. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2675. wqes[0] = (struct kwqe *) l4kwqe;
  2676. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2677. l4kwqe->flags =
  2678. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2679. l4kwqe->cid = csk->pg_cid;
  2680. return dev->submit_kwqes(dev, wqes, 1);
  2681. }
  2682. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2683. {
  2684. struct cnic_dev *dev = csk->dev;
  2685. struct l4_kwq_connect_req1 *l4kwqe1;
  2686. struct l4_kwq_connect_req2 *l4kwqe2;
  2687. struct l4_kwq_connect_req3 *l4kwqe3;
  2688. struct kwqe *wqes[3];
  2689. u8 tcp_flags = 0;
  2690. int num_wqes = 2;
  2691. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2692. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2693. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2694. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2695. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2696. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2697. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2698. l4kwqe3->flags =
  2699. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2700. l4kwqe3->ka_timeout = csk->ka_timeout;
  2701. l4kwqe3->ka_interval = csk->ka_interval;
  2702. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2703. l4kwqe3->tos = csk->tos;
  2704. l4kwqe3->ttl = csk->ttl;
  2705. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2706. l4kwqe3->pmtu = csk->mtu;
  2707. l4kwqe3->rcv_buf = csk->rcv_buf;
  2708. l4kwqe3->snd_buf = csk->snd_buf;
  2709. l4kwqe3->seed = csk->seed;
  2710. wqes[0] = (struct kwqe *) l4kwqe1;
  2711. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2712. wqes[1] = (struct kwqe *) l4kwqe2;
  2713. wqes[2] = (struct kwqe *) l4kwqe3;
  2714. num_wqes = 3;
  2715. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2716. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2717. l4kwqe2->flags =
  2718. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2719. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2720. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2721. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2722. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2723. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2724. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2725. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2726. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2727. sizeof(struct tcphdr);
  2728. } else {
  2729. wqes[1] = (struct kwqe *) l4kwqe3;
  2730. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2731. sizeof(struct tcphdr);
  2732. }
  2733. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2734. l4kwqe1->flags =
  2735. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2736. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2737. l4kwqe1->cid = csk->cid;
  2738. l4kwqe1->pg_cid = csk->pg_cid;
  2739. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2740. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2741. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2742. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2743. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2744. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2745. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2746. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2747. if (csk->tcp_flags & SK_TCP_NAGLE)
  2748. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2749. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2750. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2751. if (csk->tcp_flags & SK_TCP_SACK)
  2752. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2753. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2754. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2755. l4kwqe1->tcp_flags = tcp_flags;
  2756. return dev->submit_kwqes(dev, wqes, num_wqes);
  2757. }
  2758. static int cnic_cm_close_req(struct cnic_sock *csk)
  2759. {
  2760. struct cnic_dev *dev = csk->dev;
  2761. struct l4_kwq_close_req *l4kwqe;
  2762. struct kwqe *wqes[1];
  2763. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2764. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2765. wqes[0] = (struct kwqe *) l4kwqe;
  2766. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2767. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2768. l4kwqe->cid = csk->cid;
  2769. return dev->submit_kwqes(dev, wqes, 1);
  2770. }
  2771. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2772. {
  2773. struct cnic_dev *dev = csk->dev;
  2774. struct l4_kwq_reset_req *l4kwqe;
  2775. struct kwqe *wqes[1];
  2776. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2777. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2778. wqes[0] = (struct kwqe *) l4kwqe;
  2779. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2780. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2781. l4kwqe->cid = csk->cid;
  2782. return dev->submit_kwqes(dev, wqes, 1);
  2783. }
  2784. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2785. u32 l5_cid, struct cnic_sock **csk, void *context)
  2786. {
  2787. struct cnic_local *cp = dev->cnic_priv;
  2788. struct cnic_sock *csk1;
  2789. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2790. return -EINVAL;
  2791. if (cp->ctx_tbl) {
  2792. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2793. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2794. return -EAGAIN;
  2795. }
  2796. csk1 = &cp->csk_tbl[l5_cid];
  2797. if (atomic_read(&csk1->ref_count))
  2798. return -EAGAIN;
  2799. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2800. return -EBUSY;
  2801. csk1->dev = dev;
  2802. csk1->cid = cid;
  2803. csk1->l5_cid = l5_cid;
  2804. csk1->ulp_type = ulp_type;
  2805. csk1->context = context;
  2806. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2807. csk1->ka_interval = DEF_KA_INTERVAL;
  2808. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2809. csk1->tos = DEF_TOS;
  2810. csk1->ttl = DEF_TTL;
  2811. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2812. csk1->rcv_buf = DEF_RCV_BUF;
  2813. csk1->snd_buf = DEF_SND_BUF;
  2814. csk1->seed = DEF_SEED;
  2815. *csk = csk1;
  2816. return 0;
  2817. }
  2818. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2819. {
  2820. if (csk->src_port) {
  2821. struct cnic_dev *dev = csk->dev;
  2822. struct cnic_local *cp = dev->cnic_priv;
  2823. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2824. csk->src_port = 0;
  2825. }
  2826. }
  2827. static void cnic_close_conn(struct cnic_sock *csk)
  2828. {
  2829. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2830. cnic_cm_upload_pg(csk);
  2831. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2832. }
  2833. cnic_cm_cleanup(csk);
  2834. }
  2835. static int cnic_cm_destroy(struct cnic_sock *csk)
  2836. {
  2837. if (!cnic_in_use(csk))
  2838. return -EINVAL;
  2839. csk_hold(csk);
  2840. clear_bit(SK_F_INUSE, &csk->flags);
  2841. smp_mb__after_clear_bit();
  2842. while (atomic_read(&csk->ref_count) != 1)
  2843. msleep(1);
  2844. cnic_cm_cleanup(csk);
  2845. csk->flags = 0;
  2846. csk_put(csk);
  2847. return 0;
  2848. }
  2849. static inline u16 cnic_get_vlan(struct net_device *dev,
  2850. struct net_device **vlan_dev)
  2851. {
  2852. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2853. *vlan_dev = vlan_dev_real_dev(dev);
  2854. return vlan_dev_vlan_id(dev);
  2855. }
  2856. *vlan_dev = dev;
  2857. return 0;
  2858. }
  2859. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2860. struct dst_entry **dst)
  2861. {
  2862. #if defined(CONFIG_INET)
  2863. struct rtable *rt;
  2864. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2865. if (!IS_ERR(rt)) {
  2866. *dst = &rt->dst;
  2867. return 0;
  2868. }
  2869. return PTR_ERR(rt);
  2870. #else
  2871. return -ENETUNREACH;
  2872. #endif
  2873. }
  2874. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2875. struct dst_entry **dst)
  2876. {
  2877. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2878. struct flowi6 fl6;
  2879. memset(&fl6, 0, sizeof(fl6));
  2880. ipv6_addr_copy(&fl6.daddr, &dst_addr->sin6_addr);
  2881. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2882. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  2883. *dst = ip6_route_output(&init_net, NULL, &fl6);
  2884. if (*dst)
  2885. return 0;
  2886. #endif
  2887. return -ENETUNREACH;
  2888. }
  2889. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2890. int ulp_type)
  2891. {
  2892. struct cnic_dev *dev = NULL;
  2893. struct dst_entry *dst;
  2894. struct net_device *netdev = NULL;
  2895. int err = -ENETUNREACH;
  2896. if (dst_addr->sin_family == AF_INET)
  2897. err = cnic_get_v4_route(dst_addr, &dst);
  2898. else if (dst_addr->sin_family == AF_INET6) {
  2899. struct sockaddr_in6 *dst_addr6 =
  2900. (struct sockaddr_in6 *) dst_addr;
  2901. err = cnic_get_v6_route(dst_addr6, &dst);
  2902. } else
  2903. return NULL;
  2904. if (err)
  2905. return NULL;
  2906. if (!dst->dev)
  2907. goto done;
  2908. cnic_get_vlan(dst->dev, &netdev);
  2909. dev = cnic_from_netdev(netdev);
  2910. done:
  2911. dst_release(dst);
  2912. if (dev)
  2913. cnic_put(dev);
  2914. return dev;
  2915. }
  2916. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2917. {
  2918. struct cnic_dev *dev = csk->dev;
  2919. struct cnic_local *cp = dev->cnic_priv;
  2920. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2921. }
  2922. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2923. {
  2924. struct cnic_dev *dev = csk->dev;
  2925. struct cnic_local *cp = dev->cnic_priv;
  2926. int is_v6, rc = 0;
  2927. struct dst_entry *dst = NULL;
  2928. struct net_device *realdev;
  2929. __be16 local_port;
  2930. u32 port_id;
  2931. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2932. saddr->remote.v6.sin6_family == AF_INET6)
  2933. is_v6 = 1;
  2934. else if (saddr->local.v4.sin_family == AF_INET &&
  2935. saddr->remote.v4.sin_family == AF_INET)
  2936. is_v6 = 0;
  2937. else
  2938. return -EINVAL;
  2939. clear_bit(SK_F_IPV6, &csk->flags);
  2940. if (is_v6) {
  2941. set_bit(SK_F_IPV6, &csk->flags);
  2942. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2943. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2944. sizeof(struct in6_addr));
  2945. csk->dst_port = saddr->remote.v6.sin6_port;
  2946. local_port = saddr->local.v6.sin6_port;
  2947. } else {
  2948. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2949. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2950. csk->dst_port = saddr->remote.v4.sin_port;
  2951. local_port = saddr->local.v4.sin_port;
  2952. }
  2953. csk->vlan_id = 0;
  2954. csk->mtu = dev->netdev->mtu;
  2955. if (dst && dst->dev) {
  2956. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2957. if (realdev == dev->netdev) {
  2958. csk->vlan_id = vlan;
  2959. csk->mtu = dst_mtu(dst);
  2960. }
  2961. }
  2962. port_id = be16_to_cpu(local_port);
  2963. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2964. port_id < CNIC_LOCAL_PORT_MAX) {
  2965. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2966. port_id = 0;
  2967. } else
  2968. port_id = 0;
  2969. if (!port_id) {
  2970. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2971. if (port_id == -1) {
  2972. rc = -ENOMEM;
  2973. goto err_out;
  2974. }
  2975. local_port = cpu_to_be16(port_id);
  2976. }
  2977. csk->src_port = local_port;
  2978. err_out:
  2979. dst_release(dst);
  2980. return rc;
  2981. }
  2982. static void cnic_init_csk_state(struct cnic_sock *csk)
  2983. {
  2984. csk->state = 0;
  2985. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2986. clear_bit(SK_F_CLOSING, &csk->flags);
  2987. }
  2988. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2989. {
  2990. struct cnic_local *cp = csk->dev->cnic_priv;
  2991. int err = 0;
  2992. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  2993. return -EOPNOTSUPP;
  2994. if (!cnic_in_use(csk))
  2995. return -EINVAL;
  2996. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2997. return -EINVAL;
  2998. cnic_init_csk_state(csk);
  2999. err = cnic_get_route(csk, saddr);
  3000. if (err)
  3001. goto err_out;
  3002. err = cnic_resolve_addr(csk, saddr);
  3003. if (!err)
  3004. return 0;
  3005. err_out:
  3006. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3007. return err;
  3008. }
  3009. static int cnic_cm_abort(struct cnic_sock *csk)
  3010. {
  3011. struct cnic_local *cp = csk->dev->cnic_priv;
  3012. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3013. if (!cnic_in_use(csk))
  3014. return -EINVAL;
  3015. if (cnic_abort_prep(csk))
  3016. return cnic_cm_abort_req(csk);
  3017. /* Getting here means that we haven't started connect, or
  3018. * connect was not successful.
  3019. */
  3020. cp->close_conn(csk, opcode);
  3021. if (csk->state != opcode)
  3022. return -EALREADY;
  3023. return 0;
  3024. }
  3025. static int cnic_cm_close(struct cnic_sock *csk)
  3026. {
  3027. if (!cnic_in_use(csk))
  3028. return -EINVAL;
  3029. if (cnic_close_prep(csk)) {
  3030. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3031. return cnic_cm_close_req(csk);
  3032. } else {
  3033. return -EALREADY;
  3034. }
  3035. return 0;
  3036. }
  3037. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3038. u8 opcode)
  3039. {
  3040. struct cnic_ulp_ops *ulp_ops;
  3041. int ulp_type = csk->ulp_type;
  3042. rcu_read_lock();
  3043. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3044. if (ulp_ops) {
  3045. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3046. ulp_ops->cm_connect_complete(csk);
  3047. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3048. ulp_ops->cm_close_complete(csk);
  3049. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3050. ulp_ops->cm_remote_abort(csk);
  3051. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3052. ulp_ops->cm_abort_complete(csk);
  3053. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3054. ulp_ops->cm_remote_close(csk);
  3055. }
  3056. rcu_read_unlock();
  3057. }
  3058. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3059. {
  3060. if (cnic_offld_prep(csk)) {
  3061. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3062. cnic_cm_update_pg(csk);
  3063. else
  3064. cnic_cm_offload_pg(csk);
  3065. }
  3066. return 0;
  3067. }
  3068. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3069. {
  3070. struct cnic_local *cp = dev->cnic_priv;
  3071. u32 l5_cid = kcqe->pg_host_opaque;
  3072. u8 opcode = kcqe->op_code;
  3073. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3074. csk_hold(csk);
  3075. if (!cnic_in_use(csk))
  3076. goto done;
  3077. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3078. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3079. goto done;
  3080. }
  3081. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3082. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3083. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3084. cnic_cm_upcall(cp, csk,
  3085. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3086. goto done;
  3087. }
  3088. csk->pg_cid = kcqe->pg_cid;
  3089. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3090. cnic_cm_conn_req(csk);
  3091. done:
  3092. csk_put(csk);
  3093. }
  3094. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3095. {
  3096. struct cnic_local *cp = dev->cnic_priv;
  3097. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3098. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3099. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3100. ctx->timestamp = jiffies;
  3101. ctx->wait_cond = 1;
  3102. wake_up(&ctx->waitq);
  3103. }
  3104. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3105. {
  3106. struct cnic_local *cp = dev->cnic_priv;
  3107. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3108. u8 opcode = l4kcqe->op_code;
  3109. u32 l5_cid;
  3110. struct cnic_sock *csk;
  3111. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3112. cnic_process_fcoe_term_conn(dev, kcqe);
  3113. return;
  3114. }
  3115. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3116. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3117. cnic_cm_process_offld_pg(dev, l4kcqe);
  3118. return;
  3119. }
  3120. l5_cid = l4kcqe->conn_id;
  3121. if (opcode & 0x80)
  3122. l5_cid = l4kcqe->cid;
  3123. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3124. return;
  3125. csk = &cp->csk_tbl[l5_cid];
  3126. csk_hold(csk);
  3127. if (!cnic_in_use(csk)) {
  3128. csk_put(csk);
  3129. return;
  3130. }
  3131. switch (opcode) {
  3132. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3133. if (l4kcqe->status != 0) {
  3134. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3135. cnic_cm_upcall(cp, csk,
  3136. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3137. }
  3138. break;
  3139. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3140. if (l4kcqe->status == 0)
  3141. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3142. smp_mb__before_clear_bit();
  3143. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3144. cnic_cm_upcall(cp, csk, opcode);
  3145. break;
  3146. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3147. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3148. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3149. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3150. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3151. cp->close_conn(csk, opcode);
  3152. break;
  3153. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3154. /* after we already sent CLOSE_REQ */
  3155. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3156. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3157. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3158. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3159. else
  3160. cnic_cm_upcall(cp, csk, opcode);
  3161. break;
  3162. }
  3163. csk_put(csk);
  3164. }
  3165. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3166. {
  3167. struct cnic_dev *dev = data;
  3168. int i;
  3169. for (i = 0; i < num; i++)
  3170. cnic_cm_process_kcqe(dev, kcqe[i]);
  3171. }
  3172. static struct cnic_ulp_ops cm_ulp_ops = {
  3173. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3174. };
  3175. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3176. {
  3177. struct cnic_local *cp = dev->cnic_priv;
  3178. kfree(cp->csk_tbl);
  3179. cp->csk_tbl = NULL;
  3180. cnic_free_id_tbl(&cp->csk_port_tbl);
  3181. }
  3182. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3183. {
  3184. struct cnic_local *cp = dev->cnic_priv;
  3185. u32 port_id;
  3186. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3187. GFP_KERNEL);
  3188. if (!cp->csk_tbl)
  3189. return -ENOMEM;
  3190. port_id = random32();
  3191. port_id %= CNIC_LOCAL_PORT_RANGE;
  3192. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3193. CNIC_LOCAL_PORT_MIN, port_id)) {
  3194. cnic_cm_free_mem(dev);
  3195. return -ENOMEM;
  3196. }
  3197. return 0;
  3198. }
  3199. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3200. {
  3201. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3202. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3203. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3204. csk->state = opcode;
  3205. }
  3206. /* 1. If event opcode matches the expected event in csk->state
  3207. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3208. * event
  3209. * 3. If the expected event is 0, meaning the connection was never
  3210. * never established, we accept the opcode from cm_abort.
  3211. */
  3212. if (opcode == csk->state || csk->state == 0 ||
  3213. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3214. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3215. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3216. if (csk->state == 0)
  3217. csk->state = opcode;
  3218. return 1;
  3219. }
  3220. }
  3221. return 0;
  3222. }
  3223. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3224. {
  3225. struct cnic_dev *dev = csk->dev;
  3226. struct cnic_local *cp = dev->cnic_priv;
  3227. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3228. cnic_cm_upcall(cp, csk, opcode);
  3229. return;
  3230. }
  3231. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3232. cnic_close_conn(csk);
  3233. csk->state = opcode;
  3234. cnic_cm_upcall(cp, csk, opcode);
  3235. }
  3236. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3237. {
  3238. }
  3239. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3240. {
  3241. u32 seed;
  3242. seed = random32();
  3243. cnic_ctx_wr(dev, 45, 0, seed);
  3244. return 0;
  3245. }
  3246. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3247. {
  3248. struct cnic_dev *dev = csk->dev;
  3249. struct cnic_local *cp = dev->cnic_priv;
  3250. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3251. union l5cm_specific_data l5_data;
  3252. u32 cmd = 0;
  3253. int close_complete = 0;
  3254. switch (opcode) {
  3255. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3256. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3257. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3258. if (cnic_ready_to_close(csk, opcode)) {
  3259. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3260. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3261. else
  3262. close_complete = 1;
  3263. }
  3264. break;
  3265. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3266. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3267. break;
  3268. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3269. close_complete = 1;
  3270. break;
  3271. }
  3272. if (cmd) {
  3273. memset(&l5_data, 0, sizeof(l5_data));
  3274. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3275. &l5_data);
  3276. } else if (close_complete) {
  3277. ctx->timestamp = jiffies;
  3278. cnic_close_conn(csk);
  3279. cnic_cm_upcall(cp, csk, csk->state);
  3280. }
  3281. }
  3282. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3283. {
  3284. struct cnic_local *cp = dev->cnic_priv;
  3285. if (!cp->ctx_tbl)
  3286. return;
  3287. if (!netif_running(dev->netdev))
  3288. return;
  3289. cnic_bnx2x_delete_wait(dev, 0);
  3290. cancel_delayed_work(&cp->delete_task);
  3291. flush_workqueue(cnic_wq);
  3292. if (atomic_read(&cp->iscsi_conn) != 0)
  3293. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3294. atomic_read(&cp->iscsi_conn));
  3295. }
  3296. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3297. {
  3298. struct cnic_local *cp = dev->cnic_priv;
  3299. u32 pfid = cp->pfid;
  3300. u32 port = CNIC_PORT(cp);
  3301. cnic_init_bnx2x_mac(dev);
  3302. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3303. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3304. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3305. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3306. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3307. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3308. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3309. DEF_MAX_DA_COUNT);
  3310. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3311. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3312. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3313. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3314. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3315. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3316. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3317. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3318. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3319. DEF_MAX_CWND);
  3320. return 0;
  3321. }
  3322. static void cnic_delete_task(struct work_struct *work)
  3323. {
  3324. struct cnic_local *cp;
  3325. struct cnic_dev *dev;
  3326. u32 i;
  3327. int need_resched = 0;
  3328. cp = container_of(work, struct cnic_local, delete_task.work);
  3329. dev = cp->dev;
  3330. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3331. struct drv_ctl_info info;
  3332. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3333. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3334. cp->ethdev->drv_ctl(dev->netdev, &info);
  3335. }
  3336. for (i = 0; i < cp->max_cid_space; i++) {
  3337. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3338. int err;
  3339. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3340. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3341. continue;
  3342. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3343. need_resched = 1;
  3344. continue;
  3345. }
  3346. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3347. continue;
  3348. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3349. cnic_free_bnx2x_conn_resc(dev, i);
  3350. if (!err) {
  3351. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3352. atomic_dec(&cp->iscsi_conn);
  3353. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3354. }
  3355. }
  3356. if (need_resched)
  3357. queue_delayed_work(cnic_wq, &cp->delete_task,
  3358. msecs_to_jiffies(10));
  3359. }
  3360. static int cnic_cm_open(struct cnic_dev *dev)
  3361. {
  3362. struct cnic_local *cp = dev->cnic_priv;
  3363. int err;
  3364. err = cnic_cm_alloc_mem(dev);
  3365. if (err)
  3366. return err;
  3367. err = cp->start_cm(dev);
  3368. if (err)
  3369. goto err_out;
  3370. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3371. dev->cm_create = cnic_cm_create;
  3372. dev->cm_destroy = cnic_cm_destroy;
  3373. dev->cm_connect = cnic_cm_connect;
  3374. dev->cm_abort = cnic_cm_abort;
  3375. dev->cm_close = cnic_cm_close;
  3376. dev->cm_select_dev = cnic_cm_select_dev;
  3377. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3378. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3379. return 0;
  3380. err_out:
  3381. cnic_cm_free_mem(dev);
  3382. return err;
  3383. }
  3384. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3385. {
  3386. struct cnic_local *cp = dev->cnic_priv;
  3387. int i;
  3388. cp->stop_cm(dev);
  3389. if (!cp->csk_tbl)
  3390. return 0;
  3391. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3392. struct cnic_sock *csk = &cp->csk_tbl[i];
  3393. clear_bit(SK_F_INUSE, &csk->flags);
  3394. cnic_cm_cleanup(csk);
  3395. }
  3396. cnic_cm_free_mem(dev);
  3397. return 0;
  3398. }
  3399. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3400. {
  3401. u32 cid_addr;
  3402. int i;
  3403. cid_addr = GET_CID_ADDR(cid);
  3404. for (i = 0; i < CTX_SIZE; i += 4)
  3405. cnic_ctx_wr(dev, cid_addr, i, 0);
  3406. }
  3407. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3408. {
  3409. struct cnic_local *cp = dev->cnic_priv;
  3410. int ret = 0, i;
  3411. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3412. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3413. return 0;
  3414. for (i = 0; i < cp->ctx_blks; i++) {
  3415. int j;
  3416. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3417. u32 val;
  3418. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3419. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3420. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3421. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3422. (u64) cp->ctx_arr[i].mapping >> 32);
  3423. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3424. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3425. for (j = 0; j < 10; j++) {
  3426. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3427. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3428. break;
  3429. udelay(5);
  3430. }
  3431. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3432. ret = -EBUSY;
  3433. break;
  3434. }
  3435. }
  3436. return ret;
  3437. }
  3438. static void cnic_free_irq(struct cnic_dev *dev)
  3439. {
  3440. struct cnic_local *cp = dev->cnic_priv;
  3441. struct cnic_eth_dev *ethdev = cp->ethdev;
  3442. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3443. cp->disable_int_sync(dev);
  3444. tasklet_kill(&cp->cnic_irq_task);
  3445. free_irq(ethdev->irq_arr[0].vector, dev);
  3446. }
  3447. }
  3448. static int cnic_request_irq(struct cnic_dev *dev)
  3449. {
  3450. struct cnic_local *cp = dev->cnic_priv;
  3451. struct cnic_eth_dev *ethdev = cp->ethdev;
  3452. int err;
  3453. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3454. if (err)
  3455. tasklet_disable(&cp->cnic_irq_task);
  3456. return err;
  3457. }
  3458. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3459. {
  3460. struct cnic_local *cp = dev->cnic_priv;
  3461. struct cnic_eth_dev *ethdev = cp->ethdev;
  3462. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3463. int err, i = 0;
  3464. int sblk_num = cp->status_blk_num;
  3465. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3466. BNX2_HC_SB_CONFIG_1;
  3467. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3468. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3469. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3470. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3471. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3472. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3473. (unsigned long) dev);
  3474. err = cnic_request_irq(dev);
  3475. if (err)
  3476. return err;
  3477. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3478. i < 10) {
  3479. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3480. 1 << (11 + sblk_num));
  3481. udelay(10);
  3482. i++;
  3483. barrier();
  3484. }
  3485. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3486. cnic_free_irq(dev);
  3487. goto failed;
  3488. }
  3489. } else {
  3490. struct status_block *sblk = cp->status_blk.gen;
  3491. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3492. int i = 0;
  3493. while (sblk->status_completion_producer_index && i < 10) {
  3494. CNIC_WR(dev, BNX2_HC_COMMAND,
  3495. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3496. udelay(10);
  3497. i++;
  3498. barrier();
  3499. }
  3500. if (sblk->status_completion_producer_index)
  3501. goto failed;
  3502. }
  3503. return 0;
  3504. failed:
  3505. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3506. return -EBUSY;
  3507. }
  3508. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3509. {
  3510. struct cnic_local *cp = dev->cnic_priv;
  3511. struct cnic_eth_dev *ethdev = cp->ethdev;
  3512. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3513. return;
  3514. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3515. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3516. }
  3517. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3518. {
  3519. struct cnic_local *cp = dev->cnic_priv;
  3520. struct cnic_eth_dev *ethdev = cp->ethdev;
  3521. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3522. return;
  3523. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3524. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3525. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3526. synchronize_irq(ethdev->irq_arr[0].vector);
  3527. }
  3528. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3529. {
  3530. struct cnic_local *cp = dev->cnic_priv;
  3531. struct cnic_eth_dev *ethdev = cp->ethdev;
  3532. struct cnic_uio_dev *udev = cp->udev;
  3533. u32 cid_addr, tx_cid, sb_id;
  3534. u32 val, offset0, offset1, offset2, offset3;
  3535. int i;
  3536. struct tx_bd *txbd;
  3537. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3538. struct status_block *s_blk = cp->status_blk.gen;
  3539. sb_id = cp->status_blk_num;
  3540. tx_cid = 20;
  3541. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3542. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3543. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3544. tx_cid = TX_TSS_CID + sb_id - 1;
  3545. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3546. (TX_TSS_CID << 7));
  3547. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3548. }
  3549. cp->tx_cons = *cp->tx_cons_ptr;
  3550. cid_addr = GET_CID_ADDR(tx_cid);
  3551. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3552. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3553. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3554. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3555. offset0 = BNX2_L2CTX_TYPE_XI;
  3556. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3557. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3558. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3559. } else {
  3560. cnic_init_context(dev, tx_cid);
  3561. cnic_init_context(dev, tx_cid + 1);
  3562. offset0 = BNX2_L2CTX_TYPE;
  3563. offset1 = BNX2_L2CTX_CMD_TYPE;
  3564. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3565. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3566. }
  3567. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3568. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3569. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3570. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3571. txbd = udev->l2_ring;
  3572. buf_map = udev->l2_buf_map;
  3573. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3574. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3575. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3576. }
  3577. val = (u64) ring_map >> 32;
  3578. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3579. txbd->tx_bd_haddr_hi = val;
  3580. val = (u64) ring_map & 0xffffffff;
  3581. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3582. txbd->tx_bd_haddr_lo = val;
  3583. }
  3584. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3585. {
  3586. struct cnic_local *cp = dev->cnic_priv;
  3587. struct cnic_eth_dev *ethdev = cp->ethdev;
  3588. struct cnic_uio_dev *udev = cp->udev;
  3589. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3590. int i;
  3591. struct rx_bd *rxbd;
  3592. struct status_block *s_blk = cp->status_blk.gen;
  3593. dma_addr_t ring_map = udev->l2_ring_map;
  3594. sb_id = cp->status_blk_num;
  3595. cnic_init_context(dev, 2);
  3596. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3597. coal_reg = BNX2_HC_COMMAND;
  3598. coal_val = CNIC_RD(dev, coal_reg);
  3599. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3600. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3601. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3602. coal_reg = BNX2_HC_COALESCE_NOW;
  3603. coal_val = 1 << (11 + sb_id);
  3604. }
  3605. i = 0;
  3606. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3607. CNIC_WR(dev, coal_reg, coal_val);
  3608. udelay(10);
  3609. i++;
  3610. barrier();
  3611. }
  3612. cp->rx_cons = *cp->rx_cons_ptr;
  3613. cid_addr = GET_CID_ADDR(2);
  3614. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3615. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3616. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3617. if (sb_id == 0)
  3618. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3619. else
  3620. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3621. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3622. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3623. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3624. dma_addr_t buf_map;
  3625. int n = (i % cp->l2_rx_ring_size) + 1;
  3626. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3627. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3628. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3629. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3630. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3631. }
  3632. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3633. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3634. rxbd->rx_bd_haddr_hi = val;
  3635. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3636. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3637. rxbd->rx_bd_haddr_lo = val;
  3638. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3639. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3640. }
  3641. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3642. {
  3643. struct kwqe *wqes[1], l2kwqe;
  3644. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3645. wqes[0] = &l2kwqe;
  3646. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3647. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3648. KWQE_OPCODE_SHIFT) | 2;
  3649. dev->submit_kwqes(dev, wqes, 1);
  3650. }
  3651. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3652. {
  3653. struct cnic_local *cp = dev->cnic_priv;
  3654. u32 val;
  3655. val = cp->func << 2;
  3656. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3657. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3658. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3659. dev->mac_addr[0] = (u8) (val >> 8);
  3660. dev->mac_addr[1] = (u8) val;
  3661. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3662. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3663. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3664. dev->mac_addr[2] = (u8) (val >> 24);
  3665. dev->mac_addr[3] = (u8) (val >> 16);
  3666. dev->mac_addr[4] = (u8) (val >> 8);
  3667. dev->mac_addr[5] = (u8) val;
  3668. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3669. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3670. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3671. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3672. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3673. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3674. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3675. }
  3676. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3677. {
  3678. struct cnic_local *cp = dev->cnic_priv;
  3679. struct cnic_eth_dev *ethdev = cp->ethdev;
  3680. struct status_block *sblk = cp->status_blk.gen;
  3681. u32 val, kcq_cid_addr, kwq_cid_addr;
  3682. int err;
  3683. cnic_set_bnx2_mac(dev);
  3684. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3685. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3686. if (BCM_PAGE_BITS > 12)
  3687. val |= (12 - 8) << 4;
  3688. else
  3689. val |= (BCM_PAGE_BITS - 8) << 4;
  3690. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3691. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3692. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3693. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3694. err = cnic_setup_5709_context(dev, 1);
  3695. if (err)
  3696. return err;
  3697. cnic_init_context(dev, KWQ_CID);
  3698. cnic_init_context(dev, KCQ_CID);
  3699. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3700. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3701. cp->max_kwq_idx = MAX_KWQ_IDX;
  3702. cp->kwq_prod_idx = 0;
  3703. cp->kwq_con_idx = 0;
  3704. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3705. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3706. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3707. else
  3708. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3709. /* Initialize the kernel work queue context. */
  3710. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3711. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3712. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3713. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3714. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3715. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3716. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3717. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3718. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3719. val = (u32) cp->kwq_info.pgtbl_map;
  3720. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3721. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3722. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3723. cp->kcq1.sw_prod_idx = 0;
  3724. cp->kcq1.hw_prod_idx_ptr =
  3725. (u16 *) &sblk->status_completion_producer_index;
  3726. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3727. /* Initialize the kernel complete queue context. */
  3728. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3729. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3730. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3731. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3732. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3733. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3734. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3735. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3736. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3737. val = (u32) cp->kcq1.dma.pgtbl_map;
  3738. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3739. cp->int_num = 0;
  3740. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3741. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3742. u32 sb_id = cp->status_blk_num;
  3743. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3744. cp->kcq1.hw_prod_idx_ptr =
  3745. (u16 *) &msblk->status_completion_producer_index;
  3746. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3747. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3748. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3749. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3750. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3751. }
  3752. /* Enable Commnad Scheduler notification when we write to the
  3753. * host producer index of the kernel contexts. */
  3754. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3755. /* Enable Command Scheduler notification when we write to either
  3756. * the Send Queue or Receive Queue producer indexes of the kernel
  3757. * bypass contexts. */
  3758. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3759. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3760. /* Notify COM when the driver post an application buffer. */
  3761. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3762. /* Set the CP and COM doorbells. These two processors polls the
  3763. * doorbell for a non zero value before running. This must be done
  3764. * after setting up the kernel queue contexts. */
  3765. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3766. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3767. cnic_init_bnx2_tx_ring(dev);
  3768. cnic_init_bnx2_rx_ring(dev);
  3769. err = cnic_init_bnx2_irq(dev);
  3770. if (err) {
  3771. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3772. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3773. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3774. return err;
  3775. }
  3776. return 0;
  3777. }
  3778. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3779. {
  3780. struct cnic_local *cp = dev->cnic_priv;
  3781. struct cnic_eth_dev *ethdev = cp->ethdev;
  3782. u32 start_offset = ethdev->ctx_tbl_offset;
  3783. int i;
  3784. for (i = 0; i < cp->ctx_blks; i++) {
  3785. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3786. dma_addr_t map = ctx->mapping;
  3787. if (cp->ctx_align) {
  3788. unsigned long mask = cp->ctx_align - 1;
  3789. map = (map + mask) & ~mask;
  3790. }
  3791. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3792. }
  3793. }
  3794. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3795. {
  3796. struct cnic_local *cp = dev->cnic_priv;
  3797. struct cnic_eth_dev *ethdev = cp->ethdev;
  3798. int err = 0;
  3799. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3800. (unsigned long) dev);
  3801. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3802. err = cnic_request_irq(dev);
  3803. return err;
  3804. }
  3805. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3806. u16 sb_id, u8 sb_index,
  3807. u8 disable)
  3808. {
  3809. u32 addr = BAR_CSTRORM_INTMEM +
  3810. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3811. offsetof(struct hc_status_block_data_e1x, index_data) +
  3812. sizeof(struct hc_index_data)*sb_index +
  3813. offsetof(struct hc_index_data, flags);
  3814. u16 flags = CNIC_RD16(dev, addr);
  3815. /* clear and set */
  3816. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3817. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3818. HC_INDEX_DATA_HC_ENABLED);
  3819. CNIC_WR16(dev, addr, flags);
  3820. }
  3821. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3822. {
  3823. struct cnic_local *cp = dev->cnic_priv;
  3824. u8 sb_id = cp->status_blk_num;
  3825. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3826. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3827. offsetof(struct hc_status_block_data_e1x, index_data) +
  3828. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3829. offsetof(struct hc_index_data, timeout), 64 / 4);
  3830. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3831. }
  3832. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3833. {
  3834. }
  3835. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3836. struct client_init_ramrod_data *data)
  3837. {
  3838. struct cnic_local *cp = dev->cnic_priv;
  3839. struct cnic_uio_dev *udev = cp->udev;
  3840. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3841. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3842. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3843. int i;
  3844. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3845. u32 val;
  3846. memset(txbd, 0, BCM_PAGE_SIZE);
  3847. buf_map = udev->l2_buf_map;
  3848. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3849. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3850. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3851. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3852. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3853. reg_bd->addr_hi = start_bd->addr_hi;
  3854. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3855. start_bd->nbytes = cpu_to_le16(0x10);
  3856. start_bd->nbd = cpu_to_le16(3);
  3857. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3858. start_bd->general_data = (UNICAST_ADDRESS <<
  3859. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3860. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3861. }
  3862. val = (u64) ring_map >> 32;
  3863. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3864. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3865. val = (u64) ring_map & 0xffffffff;
  3866. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3867. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3868. /* Other ramrod params */
  3869. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3870. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3871. /* reset xstorm per client statistics */
  3872. if (cli < MAX_STAT_COUNTER_ID) {
  3873. data->general.statistics_zero_flg = 1;
  3874. data->general.statistics_en_flg = 1;
  3875. data->general.statistics_counter_id = cli;
  3876. }
  3877. cp->tx_cons_ptr =
  3878. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3879. }
  3880. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3881. struct client_init_ramrod_data *data)
  3882. {
  3883. struct cnic_local *cp = dev->cnic_priv;
  3884. struct cnic_uio_dev *udev = cp->udev;
  3885. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3886. BCM_PAGE_SIZE);
  3887. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3888. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3889. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3890. int i;
  3891. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3892. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3893. u32 val;
  3894. dma_addr_t ring_map = udev->l2_ring_map;
  3895. /* General data */
  3896. data->general.client_id = cli;
  3897. data->general.activate_flg = 1;
  3898. data->general.sp_client_id = cli;
  3899. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3900. data->general.func_id = cp->pfid;
  3901. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3902. dma_addr_t buf_map;
  3903. int n = (i % cp->l2_rx_ring_size) + 1;
  3904. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3905. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3906. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3907. }
  3908. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3909. rxbd->addr_hi = cpu_to_le32(val);
  3910. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3911. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3912. rxbd->addr_lo = cpu_to_le32(val);
  3913. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3914. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3915. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3916. rxcqe->addr_hi = cpu_to_le32(val);
  3917. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3918. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3919. rxcqe->addr_lo = cpu_to_le32(val);
  3920. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3921. /* Other ramrod params */
  3922. data->rx.client_qzone_id = cl_qzone_id;
  3923. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3924. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3925. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3926. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  3927. data->rx.outer_vlan_removal_enable_flg = 1;
  3928. data->rx.silent_vlan_removal_flg = 1;
  3929. data->rx.silent_vlan_value = 0;
  3930. data->rx.silent_vlan_mask = 0xffff;
  3931. cp->rx_cons_ptr =
  3932. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3933. cp->rx_cons = *cp->rx_cons_ptr;
  3934. }
  3935. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3936. {
  3937. struct cnic_local *cp = dev->cnic_priv;
  3938. u32 pfid = cp->pfid;
  3939. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3940. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3941. cp->kcq1.sw_prod_idx = 0;
  3942. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3943. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3944. cp->kcq1.hw_prod_idx_ptr =
  3945. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3946. cp->kcq1.status_idx_ptr =
  3947. &sb->sb.running_index[SM_RX_ID];
  3948. } else {
  3949. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3950. cp->kcq1.hw_prod_idx_ptr =
  3951. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3952. cp->kcq1.status_idx_ptr =
  3953. &sb->sb.running_index[SM_RX_ID];
  3954. }
  3955. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3956. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3957. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  3958. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  3959. cp->kcq2.sw_prod_idx = 0;
  3960. cp->kcq2.hw_prod_idx_ptr =
  3961. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  3962. cp->kcq2.status_idx_ptr =
  3963. &sb->sb.running_index[SM_RX_ID];
  3964. }
  3965. }
  3966. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3967. {
  3968. struct cnic_local *cp = dev->cnic_priv;
  3969. struct cnic_eth_dev *ethdev = cp->ethdev;
  3970. int func = CNIC_FUNC(cp), ret;
  3971. u32 pfid;
  3972. cp->port_mode = CHIP_PORT_MODE_NONE;
  3973. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3974. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3975. if (!(val & 1))
  3976. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3977. else
  3978. val = (val >> 1) & 1;
  3979. if (val) {
  3980. cp->port_mode = CHIP_4_PORT_MODE;
  3981. cp->pfid = func >> 1;
  3982. } else {
  3983. cp->port_mode = CHIP_2_PORT_MODE;
  3984. cp->pfid = func & 0x6;
  3985. }
  3986. } else {
  3987. cp->pfid = func;
  3988. }
  3989. pfid = cp->pfid;
  3990. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3991. cp->iscsi_start_cid, 0);
  3992. if (ret)
  3993. return -ENOMEM;
  3994. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3995. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
  3996. BNX2X_FCOE_NUM_CONNECTIONS,
  3997. cp->fcoe_start_cid, 0);
  3998. if (ret)
  3999. return -ENOMEM;
  4000. }
  4001. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4002. cnic_init_bnx2x_kcq(dev);
  4003. /* Only 1 EQ */
  4004. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4005. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4006. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4007. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4008. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4009. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4010. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4011. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4012. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4013. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4014. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4015. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4016. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4017. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4018. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4019. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4020. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4021. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4022. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4023. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4024. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4025. HC_INDEX_ISCSI_EQ_CONS);
  4026. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4027. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4028. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4029. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4030. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4031. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4032. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4033. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4034. cnic_setup_bnx2x_context(dev);
  4035. ret = cnic_init_bnx2x_irq(dev);
  4036. if (ret)
  4037. return ret;
  4038. return 0;
  4039. }
  4040. static void cnic_init_rings(struct cnic_dev *dev)
  4041. {
  4042. struct cnic_local *cp = dev->cnic_priv;
  4043. struct cnic_uio_dev *udev = cp->udev;
  4044. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4045. return;
  4046. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4047. cnic_init_bnx2_tx_ring(dev);
  4048. cnic_init_bnx2_rx_ring(dev);
  4049. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4050. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4051. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4052. u32 cid = cp->ethdev->iscsi_l2_cid;
  4053. u32 cl_qzone_id;
  4054. struct client_init_ramrod_data *data;
  4055. union l5cm_specific_data l5_data;
  4056. struct ustorm_eth_rx_producers rx_prods = {0};
  4057. u32 off, i, *cid_ptr;
  4058. rx_prods.bd_prod = 0;
  4059. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4060. barrier();
  4061. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4062. off = BAR_USTRORM_INTMEM +
  4063. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4064. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4065. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4066. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4067. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4068. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4069. data = udev->l2_buf;
  4070. cid_ptr = udev->l2_buf + 12;
  4071. memset(data, 0, sizeof(*data));
  4072. cnic_init_bnx2x_tx_ring(dev, data);
  4073. cnic_init_bnx2x_rx_ring(dev, data);
  4074. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4075. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4076. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4077. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4078. cid, ETH_CONNECTION_TYPE, &l5_data);
  4079. i = 0;
  4080. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4081. ++i < 10)
  4082. msleep(1);
  4083. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4084. netdev_err(dev->netdev,
  4085. "iSCSI CLIENT_SETUP did not complete\n");
  4086. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4087. cnic_ring_ctl(dev, cid, cli, 1);
  4088. *cid_ptr = cid;
  4089. }
  4090. }
  4091. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4092. {
  4093. struct cnic_local *cp = dev->cnic_priv;
  4094. struct cnic_uio_dev *udev = cp->udev;
  4095. void *rx_ring;
  4096. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4097. return;
  4098. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4099. cnic_shutdown_bnx2_rx_ring(dev);
  4100. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4101. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4102. u32 cid = cp->ethdev->iscsi_l2_cid;
  4103. union l5cm_specific_data l5_data;
  4104. int i;
  4105. cnic_ring_ctl(dev, cid, cli, 0);
  4106. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4107. l5_data.phy_address.lo = cli;
  4108. l5_data.phy_address.hi = 0;
  4109. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4110. cid, ETH_CONNECTION_TYPE, &l5_data);
  4111. i = 0;
  4112. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4113. ++i < 10)
  4114. msleep(1);
  4115. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4116. netdev_err(dev->netdev,
  4117. "iSCSI CLIENT_HALT did not complete\n");
  4118. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4119. memset(&l5_data, 0, sizeof(l5_data));
  4120. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4121. cid, NONE_CONNECTION_TYPE, &l5_data);
  4122. msleep(10);
  4123. }
  4124. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4125. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4126. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4127. }
  4128. static int cnic_register_netdev(struct cnic_dev *dev)
  4129. {
  4130. struct cnic_local *cp = dev->cnic_priv;
  4131. struct cnic_eth_dev *ethdev = cp->ethdev;
  4132. int err;
  4133. if (!ethdev)
  4134. return -ENODEV;
  4135. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4136. return 0;
  4137. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4138. if (err)
  4139. netdev_err(dev->netdev, "register_cnic failed\n");
  4140. return err;
  4141. }
  4142. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4143. {
  4144. struct cnic_local *cp = dev->cnic_priv;
  4145. struct cnic_eth_dev *ethdev = cp->ethdev;
  4146. if (!ethdev)
  4147. return;
  4148. ethdev->drv_unregister_cnic(dev->netdev);
  4149. }
  4150. static int cnic_start_hw(struct cnic_dev *dev)
  4151. {
  4152. struct cnic_local *cp = dev->cnic_priv;
  4153. struct cnic_eth_dev *ethdev = cp->ethdev;
  4154. int err;
  4155. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4156. return -EALREADY;
  4157. dev->regview = ethdev->io_base;
  4158. pci_dev_get(dev->pcidev);
  4159. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4160. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4161. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4162. err = cp->alloc_resc(dev);
  4163. if (err) {
  4164. netdev_err(dev->netdev, "allocate resource failure\n");
  4165. goto err1;
  4166. }
  4167. err = cp->start_hw(dev);
  4168. if (err)
  4169. goto err1;
  4170. err = cnic_cm_open(dev);
  4171. if (err)
  4172. goto err1;
  4173. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4174. cp->enable_int(dev);
  4175. return 0;
  4176. err1:
  4177. cp->free_resc(dev);
  4178. pci_dev_put(dev->pcidev);
  4179. return err;
  4180. }
  4181. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4182. {
  4183. cnic_disable_bnx2_int_sync(dev);
  4184. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4185. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4186. cnic_init_context(dev, KWQ_CID);
  4187. cnic_init_context(dev, KCQ_CID);
  4188. cnic_setup_5709_context(dev, 0);
  4189. cnic_free_irq(dev);
  4190. cnic_free_resc(dev);
  4191. }
  4192. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4193. {
  4194. struct cnic_local *cp = dev->cnic_priv;
  4195. cnic_free_irq(dev);
  4196. *cp->kcq1.hw_prod_idx_ptr = 0;
  4197. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4198. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4199. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4200. cnic_free_resc(dev);
  4201. }
  4202. static void cnic_stop_hw(struct cnic_dev *dev)
  4203. {
  4204. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4205. struct cnic_local *cp = dev->cnic_priv;
  4206. int i = 0;
  4207. /* Need to wait for the ring shutdown event to complete
  4208. * before clearing the CNIC_UP flag.
  4209. */
  4210. while (cp->udev->uio_dev != -1 && i < 15) {
  4211. msleep(100);
  4212. i++;
  4213. }
  4214. cnic_shutdown_rings(dev);
  4215. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4216. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4217. synchronize_rcu();
  4218. cnic_cm_shutdown(dev);
  4219. cp->stop_hw(dev);
  4220. pci_dev_put(dev->pcidev);
  4221. }
  4222. }
  4223. static void cnic_free_dev(struct cnic_dev *dev)
  4224. {
  4225. int i = 0;
  4226. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4227. msleep(100);
  4228. i++;
  4229. }
  4230. if (atomic_read(&dev->ref_count) != 0)
  4231. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4232. netdev_info(dev->netdev, "Removed CNIC device\n");
  4233. dev_put(dev->netdev);
  4234. kfree(dev);
  4235. }
  4236. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4237. struct pci_dev *pdev)
  4238. {
  4239. struct cnic_dev *cdev;
  4240. struct cnic_local *cp;
  4241. int alloc_size;
  4242. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4243. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4244. if (cdev == NULL) {
  4245. netdev_err(dev, "allocate dev struct failure\n");
  4246. return NULL;
  4247. }
  4248. cdev->netdev = dev;
  4249. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4250. cdev->register_device = cnic_register_device;
  4251. cdev->unregister_device = cnic_unregister_device;
  4252. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4253. cp = cdev->cnic_priv;
  4254. cp->dev = cdev;
  4255. cp->l2_single_buf_size = 0x400;
  4256. cp->l2_rx_ring_size = 3;
  4257. spin_lock_init(&cp->cnic_ulp_lock);
  4258. netdev_info(dev, "Added CNIC device\n");
  4259. return cdev;
  4260. }
  4261. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4262. {
  4263. struct pci_dev *pdev;
  4264. struct cnic_dev *cdev;
  4265. struct cnic_local *cp;
  4266. struct cnic_eth_dev *ethdev = NULL;
  4267. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4268. probe = symbol_get(bnx2_cnic_probe);
  4269. if (probe) {
  4270. ethdev = (*probe)(dev);
  4271. symbol_put(bnx2_cnic_probe);
  4272. }
  4273. if (!ethdev)
  4274. return NULL;
  4275. pdev = ethdev->pdev;
  4276. if (!pdev)
  4277. return NULL;
  4278. dev_hold(dev);
  4279. pci_dev_get(pdev);
  4280. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4281. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4282. (pdev->revision < 0x10)) {
  4283. pci_dev_put(pdev);
  4284. goto cnic_err;
  4285. }
  4286. pci_dev_put(pdev);
  4287. cdev = cnic_alloc_dev(dev, pdev);
  4288. if (cdev == NULL)
  4289. goto cnic_err;
  4290. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4291. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4292. cp = cdev->cnic_priv;
  4293. cp->ethdev = ethdev;
  4294. cdev->pcidev = pdev;
  4295. cp->chip_id = ethdev->chip_id;
  4296. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4297. cp->cnic_ops = &cnic_bnx2_ops;
  4298. cp->start_hw = cnic_start_bnx2_hw;
  4299. cp->stop_hw = cnic_stop_bnx2_hw;
  4300. cp->setup_pgtbl = cnic_setup_page_tbl;
  4301. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4302. cp->free_resc = cnic_free_resc;
  4303. cp->start_cm = cnic_cm_init_bnx2_hw;
  4304. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4305. cp->enable_int = cnic_enable_bnx2_int;
  4306. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4307. cp->close_conn = cnic_close_bnx2_conn;
  4308. return cdev;
  4309. cnic_err:
  4310. dev_put(dev);
  4311. return NULL;
  4312. }
  4313. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4314. {
  4315. struct pci_dev *pdev;
  4316. struct cnic_dev *cdev;
  4317. struct cnic_local *cp;
  4318. struct cnic_eth_dev *ethdev = NULL;
  4319. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4320. probe = symbol_get(bnx2x_cnic_probe);
  4321. if (probe) {
  4322. ethdev = (*probe)(dev);
  4323. symbol_put(bnx2x_cnic_probe);
  4324. }
  4325. if (!ethdev)
  4326. return NULL;
  4327. pdev = ethdev->pdev;
  4328. if (!pdev)
  4329. return NULL;
  4330. dev_hold(dev);
  4331. cdev = cnic_alloc_dev(dev, pdev);
  4332. if (cdev == NULL) {
  4333. dev_put(dev);
  4334. return NULL;
  4335. }
  4336. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4337. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4338. cp = cdev->cnic_priv;
  4339. cp->ethdev = ethdev;
  4340. cdev->pcidev = pdev;
  4341. cp->chip_id = ethdev->chip_id;
  4342. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4343. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4344. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  4345. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4346. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4347. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4348. cp->cnic_ops = &cnic_bnx2x_ops;
  4349. cp->start_hw = cnic_start_bnx2x_hw;
  4350. cp->stop_hw = cnic_stop_bnx2x_hw;
  4351. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4352. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4353. cp->free_resc = cnic_free_resc;
  4354. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4355. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4356. cp->enable_int = cnic_enable_bnx2x_int;
  4357. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4358. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4359. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4360. else
  4361. cp->ack_int = cnic_ack_bnx2x_msix;
  4362. cp->close_conn = cnic_close_bnx2x_conn;
  4363. return cdev;
  4364. }
  4365. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4366. {
  4367. struct ethtool_drvinfo drvinfo;
  4368. struct cnic_dev *cdev = NULL;
  4369. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4370. memset(&drvinfo, 0, sizeof(drvinfo));
  4371. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4372. if (!strcmp(drvinfo.driver, "bnx2"))
  4373. cdev = init_bnx2_cnic(dev);
  4374. if (!strcmp(drvinfo.driver, "bnx2x"))
  4375. cdev = init_bnx2x_cnic(dev);
  4376. if (cdev) {
  4377. write_lock(&cnic_dev_lock);
  4378. list_add(&cdev->list, &cnic_dev_list);
  4379. write_unlock(&cnic_dev_lock);
  4380. }
  4381. }
  4382. return cdev;
  4383. }
  4384. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4385. u16 vlan_id)
  4386. {
  4387. int if_type;
  4388. rcu_read_lock();
  4389. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4390. struct cnic_ulp_ops *ulp_ops;
  4391. void *ctx;
  4392. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4393. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4394. continue;
  4395. ctx = cp->ulp_handle[if_type];
  4396. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4397. }
  4398. rcu_read_unlock();
  4399. }
  4400. /**
  4401. * netdev event handler
  4402. */
  4403. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4404. void *ptr)
  4405. {
  4406. struct net_device *netdev = ptr;
  4407. struct cnic_dev *dev;
  4408. int new_dev = 0;
  4409. dev = cnic_from_netdev(netdev);
  4410. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4411. /* Check for the hot-plug device */
  4412. dev = is_cnic_dev(netdev);
  4413. if (dev) {
  4414. new_dev = 1;
  4415. cnic_hold(dev);
  4416. }
  4417. }
  4418. if (dev) {
  4419. struct cnic_local *cp = dev->cnic_priv;
  4420. if (new_dev)
  4421. cnic_ulp_init(dev);
  4422. else if (event == NETDEV_UNREGISTER)
  4423. cnic_ulp_exit(dev);
  4424. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4425. if (cnic_register_netdev(dev) != 0) {
  4426. cnic_put(dev);
  4427. goto done;
  4428. }
  4429. if (!cnic_start_hw(dev))
  4430. cnic_ulp_start(dev);
  4431. }
  4432. cnic_rcv_netevent(cp, event, 0);
  4433. if (event == NETDEV_GOING_DOWN) {
  4434. cnic_ulp_stop(dev);
  4435. cnic_stop_hw(dev);
  4436. cnic_unregister_netdev(dev);
  4437. } else if (event == NETDEV_UNREGISTER) {
  4438. write_lock(&cnic_dev_lock);
  4439. list_del_init(&dev->list);
  4440. write_unlock(&cnic_dev_lock);
  4441. cnic_put(dev);
  4442. cnic_free_dev(dev);
  4443. goto done;
  4444. }
  4445. cnic_put(dev);
  4446. } else {
  4447. struct net_device *realdev;
  4448. u16 vid;
  4449. vid = cnic_get_vlan(netdev, &realdev);
  4450. if (realdev) {
  4451. dev = cnic_from_netdev(realdev);
  4452. if (dev) {
  4453. vid |= VLAN_TAG_PRESENT;
  4454. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4455. cnic_put(dev);
  4456. }
  4457. }
  4458. }
  4459. done:
  4460. return NOTIFY_DONE;
  4461. }
  4462. static struct notifier_block cnic_netdev_notifier = {
  4463. .notifier_call = cnic_netdev_event
  4464. };
  4465. static void cnic_release(void)
  4466. {
  4467. struct cnic_dev *dev;
  4468. struct cnic_uio_dev *udev;
  4469. while (!list_empty(&cnic_dev_list)) {
  4470. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4471. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4472. cnic_ulp_stop(dev);
  4473. cnic_stop_hw(dev);
  4474. }
  4475. cnic_ulp_exit(dev);
  4476. cnic_unregister_netdev(dev);
  4477. list_del_init(&dev->list);
  4478. cnic_free_dev(dev);
  4479. }
  4480. while (!list_empty(&cnic_udev_list)) {
  4481. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4482. list);
  4483. cnic_free_uio(udev);
  4484. }
  4485. }
  4486. static int __init cnic_init(void)
  4487. {
  4488. int rc = 0;
  4489. pr_info("%s", version);
  4490. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4491. if (rc) {
  4492. cnic_release();
  4493. return rc;
  4494. }
  4495. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4496. if (!cnic_wq) {
  4497. cnic_release();
  4498. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4499. return -ENOMEM;
  4500. }
  4501. return 0;
  4502. }
  4503. static void __exit cnic_exit(void)
  4504. {
  4505. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4506. cnic_release();
  4507. destroy_workqueue(cnic_wq);
  4508. }
  4509. module_init(cnic_init);
  4510. module_exit(cnic_exit);