bnx2x_stats.c 50 KB

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  1. /* bnx2x_stats.c: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2011 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. * UDP CSUM errata workaround by Arik Gendelman
  13. * Slowpath and fastpath rework by Vladislav Zolotarov
  14. * Statistics and Link management by Yitchak Gertner
  15. *
  16. */
  17. #include "bnx2x_stats.h"
  18. #include "bnx2x_cmn.h"
  19. /* Statistics */
  20. /*
  21. * General service functions
  22. */
  23. static inline long bnx2x_hilo(u32 *hiref)
  24. {
  25. u32 lo = *(hiref + 1);
  26. #if (BITS_PER_LONG == 64)
  27. u32 hi = *hiref;
  28. return HILO_U64(hi, lo);
  29. #else
  30. return lo;
  31. #endif
  32. }
  33. /*
  34. * Init service functions
  35. */
  36. /* Post the next statistics ramrod. Protect it with the spin in
  37. * order to ensure the strict order between statistics ramrods
  38. * (each ramrod has a sequence number passed in a
  39. * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be
  40. * sent in order).
  41. */
  42. static void bnx2x_storm_stats_post(struct bnx2x *bp)
  43. {
  44. if (!bp->stats_pending) {
  45. int rc;
  46. spin_lock_bh(&bp->stats_lock);
  47. if (bp->stats_pending) {
  48. spin_unlock_bh(&bp->stats_lock);
  49. return;
  50. }
  51. bp->fw_stats_req->hdr.drv_stats_counter =
  52. cpu_to_le16(bp->stats_counter++);
  53. DP(NETIF_MSG_TIMER, "Sending statistics ramrod %d\n",
  54. bp->fw_stats_req->hdr.drv_stats_counter);
  55. /* send FW stats ramrod */
  56. rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
  57. U64_HI(bp->fw_stats_req_mapping),
  58. U64_LO(bp->fw_stats_req_mapping),
  59. NONE_CONNECTION_TYPE);
  60. if (rc == 0)
  61. bp->stats_pending = 1;
  62. spin_unlock_bh(&bp->stats_lock);
  63. }
  64. }
  65. static void bnx2x_hw_stats_post(struct bnx2x *bp)
  66. {
  67. struct dmae_command *dmae = &bp->stats_dmae;
  68. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  69. *stats_comp = DMAE_COMP_VAL;
  70. if (CHIP_REV_IS_SLOW(bp))
  71. return;
  72. /* loader */
  73. if (bp->executer_idx) {
  74. int loader_idx = PMF_DMAE_C(bp);
  75. u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  76. true, DMAE_COMP_GRC);
  77. opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
  78. memset(dmae, 0, sizeof(struct dmae_command));
  79. dmae->opcode = opcode;
  80. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
  81. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
  82. dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
  83. sizeof(struct dmae_command) *
  84. (loader_idx + 1)) >> 2;
  85. dmae->dst_addr_hi = 0;
  86. dmae->len = sizeof(struct dmae_command) >> 2;
  87. if (CHIP_IS_E1(bp))
  88. dmae->len--;
  89. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
  90. dmae->comp_addr_hi = 0;
  91. dmae->comp_val = 1;
  92. *stats_comp = 0;
  93. bnx2x_post_dmae(bp, dmae, loader_idx);
  94. } else if (bp->func_stx) {
  95. *stats_comp = 0;
  96. bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
  97. }
  98. }
  99. static int bnx2x_stats_comp(struct bnx2x *bp)
  100. {
  101. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  102. int cnt = 10;
  103. might_sleep();
  104. while (*stats_comp != DMAE_COMP_VAL) {
  105. if (!cnt) {
  106. BNX2X_ERR("timeout waiting for stats finished\n");
  107. break;
  108. }
  109. cnt--;
  110. usleep_range(1000, 1000);
  111. }
  112. return 1;
  113. }
  114. /*
  115. * Statistics service functions
  116. */
  117. static void bnx2x_stats_pmf_update(struct bnx2x *bp)
  118. {
  119. struct dmae_command *dmae;
  120. u32 opcode;
  121. int loader_idx = PMF_DMAE_C(bp);
  122. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  123. /* sanity */
  124. if (!IS_MF(bp) || !bp->port.pmf || !bp->port.port_stx) {
  125. BNX2X_ERR("BUG!\n");
  126. return;
  127. }
  128. bp->executer_idx = 0;
  129. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0);
  130. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  131. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
  132. dmae->src_addr_lo = bp->port.port_stx >> 2;
  133. dmae->src_addr_hi = 0;
  134. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  135. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  136. dmae->len = DMAE_LEN32_RD_MAX;
  137. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  138. dmae->comp_addr_hi = 0;
  139. dmae->comp_val = 1;
  140. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  141. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  142. dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
  143. dmae->src_addr_hi = 0;
  144. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
  145. DMAE_LEN32_RD_MAX * 4);
  146. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
  147. DMAE_LEN32_RD_MAX * 4);
  148. dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
  149. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  150. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  151. dmae->comp_val = DMAE_COMP_VAL;
  152. *stats_comp = 0;
  153. bnx2x_hw_stats_post(bp);
  154. bnx2x_stats_comp(bp);
  155. }
  156. static void bnx2x_port_stats_init(struct bnx2x *bp)
  157. {
  158. struct dmae_command *dmae;
  159. int port = BP_PORT(bp);
  160. u32 opcode;
  161. int loader_idx = PMF_DMAE_C(bp);
  162. u32 mac_addr;
  163. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  164. /* sanity */
  165. if (!bp->link_vars.link_up || !bp->port.pmf) {
  166. BNX2X_ERR("BUG!\n");
  167. return;
  168. }
  169. bp->executer_idx = 0;
  170. /* MCP */
  171. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  172. true, DMAE_COMP_GRC);
  173. if (bp->port.port_stx) {
  174. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  175. dmae->opcode = opcode;
  176. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  177. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  178. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  179. dmae->dst_addr_hi = 0;
  180. dmae->len = sizeof(struct host_port_stats) >> 2;
  181. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  182. dmae->comp_addr_hi = 0;
  183. dmae->comp_val = 1;
  184. }
  185. if (bp->func_stx) {
  186. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  187. dmae->opcode = opcode;
  188. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  189. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  190. dmae->dst_addr_lo = bp->func_stx >> 2;
  191. dmae->dst_addr_hi = 0;
  192. dmae->len = sizeof(struct host_func_stats) >> 2;
  193. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  194. dmae->comp_addr_hi = 0;
  195. dmae->comp_val = 1;
  196. }
  197. /* MAC */
  198. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  199. true, DMAE_COMP_GRC);
  200. /* EMAC is special */
  201. if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
  202. mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
  203. /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
  204. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  205. dmae->opcode = opcode;
  206. dmae->src_addr_lo = (mac_addr +
  207. EMAC_REG_EMAC_RX_STAT_AC) >> 2;
  208. dmae->src_addr_hi = 0;
  209. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  210. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  211. dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
  212. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  213. dmae->comp_addr_hi = 0;
  214. dmae->comp_val = 1;
  215. /* EMAC_REG_EMAC_RX_STAT_AC_28 */
  216. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  217. dmae->opcode = opcode;
  218. dmae->src_addr_lo = (mac_addr +
  219. EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
  220. dmae->src_addr_hi = 0;
  221. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  222. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  223. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  224. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  225. dmae->len = 1;
  226. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  227. dmae->comp_addr_hi = 0;
  228. dmae->comp_val = 1;
  229. /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
  230. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  231. dmae->opcode = opcode;
  232. dmae->src_addr_lo = (mac_addr +
  233. EMAC_REG_EMAC_TX_STAT_AC) >> 2;
  234. dmae->src_addr_hi = 0;
  235. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  236. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  237. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  238. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  239. dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
  240. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  241. dmae->comp_addr_hi = 0;
  242. dmae->comp_val = 1;
  243. } else {
  244. u32 tx_src_addr_lo, rx_src_addr_lo;
  245. u16 rx_len, tx_len;
  246. /* configure the params according to MAC type */
  247. switch (bp->link_vars.mac_type) {
  248. case MAC_TYPE_BMAC:
  249. mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
  250. NIG_REG_INGRESS_BMAC0_MEM);
  251. /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
  252. BIGMAC_REGISTER_TX_STAT_GTBYT */
  253. if (CHIP_IS_E1x(bp)) {
  254. tx_src_addr_lo = (mac_addr +
  255. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  256. tx_len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
  257. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  258. rx_src_addr_lo = (mac_addr +
  259. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  260. rx_len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
  261. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  262. } else {
  263. tx_src_addr_lo = (mac_addr +
  264. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  265. tx_len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
  266. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  267. rx_src_addr_lo = (mac_addr +
  268. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  269. rx_len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
  270. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  271. }
  272. break;
  273. case MAC_TYPE_UMAC: /* handled by MSTAT */
  274. case MAC_TYPE_XMAC: /* handled by MSTAT */
  275. default:
  276. mac_addr = port ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
  277. tx_src_addr_lo = (mac_addr +
  278. MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2;
  279. rx_src_addr_lo = (mac_addr +
  280. MSTAT_REG_RX_STAT_GR64_LO) >> 2;
  281. tx_len = sizeof(bp->slowpath->
  282. mac_stats.mstat_stats.stats_tx) >> 2;
  283. rx_len = sizeof(bp->slowpath->
  284. mac_stats.mstat_stats.stats_rx) >> 2;
  285. break;
  286. }
  287. /* TX stats */
  288. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  289. dmae->opcode = opcode;
  290. dmae->src_addr_lo = tx_src_addr_lo;
  291. dmae->src_addr_hi = 0;
  292. dmae->len = tx_len;
  293. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  294. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  295. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  296. dmae->comp_addr_hi = 0;
  297. dmae->comp_val = 1;
  298. /* RX stats */
  299. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  300. dmae->opcode = opcode;
  301. dmae->src_addr_hi = 0;
  302. dmae->src_addr_lo = rx_src_addr_lo;
  303. dmae->dst_addr_lo =
  304. U64_LO(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  305. dmae->dst_addr_hi =
  306. U64_HI(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  307. dmae->len = rx_len;
  308. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  309. dmae->comp_addr_hi = 0;
  310. dmae->comp_val = 1;
  311. }
  312. /* NIG */
  313. if (!CHIP_IS_E3(bp)) {
  314. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  315. dmae->opcode = opcode;
  316. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
  317. NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
  318. dmae->src_addr_hi = 0;
  319. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  320. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  321. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  322. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  323. dmae->len = (2*sizeof(u32)) >> 2;
  324. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  325. dmae->comp_addr_hi = 0;
  326. dmae->comp_val = 1;
  327. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  328. dmae->opcode = opcode;
  329. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
  330. NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
  331. dmae->src_addr_hi = 0;
  332. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  333. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  334. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  335. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  336. dmae->len = (2*sizeof(u32)) >> 2;
  337. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  338. dmae->comp_addr_hi = 0;
  339. dmae->comp_val = 1;
  340. }
  341. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  342. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  343. true, DMAE_COMP_PCI);
  344. dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
  345. NIG_REG_STAT0_BRB_DISCARD) >> 2;
  346. dmae->src_addr_hi = 0;
  347. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
  348. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
  349. dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
  350. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  351. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  352. dmae->comp_val = DMAE_COMP_VAL;
  353. *stats_comp = 0;
  354. }
  355. static void bnx2x_func_stats_init(struct bnx2x *bp)
  356. {
  357. struct dmae_command *dmae = &bp->stats_dmae;
  358. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  359. /* sanity */
  360. if (!bp->func_stx) {
  361. BNX2X_ERR("BUG!\n");
  362. return;
  363. }
  364. bp->executer_idx = 0;
  365. memset(dmae, 0, sizeof(struct dmae_command));
  366. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  367. true, DMAE_COMP_PCI);
  368. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  369. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  370. dmae->dst_addr_lo = bp->func_stx >> 2;
  371. dmae->dst_addr_hi = 0;
  372. dmae->len = sizeof(struct host_func_stats) >> 2;
  373. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  374. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  375. dmae->comp_val = DMAE_COMP_VAL;
  376. *stats_comp = 0;
  377. }
  378. static void bnx2x_stats_start(struct bnx2x *bp)
  379. {
  380. if (bp->port.pmf)
  381. bnx2x_port_stats_init(bp);
  382. else if (bp->func_stx)
  383. bnx2x_func_stats_init(bp);
  384. bnx2x_hw_stats_post(bp);
  385. bnx2x_storm_stats_post(bp);
  386. }
  387. static void bnx2x_stats_pmf_start(struct bnx2x *bp)
  388. {
  389. bnx2x_stats_comp(bp);
  390. bnx2x_stats_pmf_update(bp);
  391. bnx2x_stats_start(bp);
  392. }
  393. static void bnx2x_stats_restart(struct bnx2x *bp)
  394. {
  395. bnx2x_stats_comp(bp);
  396. bnx2x_stats_start(bp);
  397. }
  398. static void bnx2x_bmac_stats_update(struct bnx2x *bp)
  399. {
  400. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  401. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  402. struct {
  403. u32 lo;
  404. u32 hi;
  405. } diff;
  406. if (CHIP_IS_E1x(bp)) {
  407. struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
  408. /* the macros below will use "bmac1_stats" type */
  409. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  410. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  411. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  412. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  413. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  414. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  415. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  416. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  417. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  418. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  419. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  420. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  421. UPDATE_STAT64(tx_stat_gt127,
  422. tx_stat_etherstatspkts65octetsto127octets);
  423. UPDATE_STAT64(tx_stat_gt255,
  424. tx_stat_etherstatspkts128octetsto255octets);
  425. UPDATE_STAT64(tx_stat_gt511,
  426. tx_stat_etherstatspkts256octetsto511octets);
  427. UPDATE_STAT64(tx_stat_gt1023,
  428. tx_stat_etherstatspkts512octetsto1023octets);
  429. UPDATE_STAT64(tx_stat_gt1518,
  430. tx_stat_etherstatspkts1024octetsto1522octets);
  431. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  432. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  433. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  434. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  435. UPDATE_STAT64(tx_stat_gterr,
  436. tx_stat_dot3statsinternalmactransmiterrors);
  437. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  438. } else {
  439. struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats);
  440. /* the macros below will use "bmac2_stats" type */
  441. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  442. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  443. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  444. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  445. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  446. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  447. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  448. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  449. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  450. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  451. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  452. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  453. UPDATE_STAT64(tx_stat_gt127,
  454. tx_stat_etherstatspkts65octetsto127octets);
  455. UPDATE_STAT64(tx_stat_gt255,
  456. tx_stat_etherstatspkts128octetsto255octets);
  457. UPDATE_STAT64(tx_stat_gt511,
  458. tx_stat_etherstatspkts256octetsto511octets);
  459. UPDATE_STAT64(tx_stat_gt1023,
  460. tx_stat_etherstatspkts512octetsto1023octets);
  461. UPDATE_STAT64(tx_stat_gt1518,
  462. tx_stat_etherstatspkts1024octetsto1522octets);
  463. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  464. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  465. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  466. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  467. UPDATE_STAT64(tx_stat_gterr,
  468. tx_stat_dot3statsinternalmactransmiterrors);
  469. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  470. }
  471. estats->pause_frames_received_hi =
  472. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  473. estats->pause_frames_received_lo =
  474. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  475. estats->pause_frames_sent_hi =
  476. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  477. estats->pause_frames_sent_lo =
  478. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  479. }
  480. static void bnx2x_mstat_stats_update(struct bnx2x *bp)
  481. {
  482. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  483. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  484. struct mstat_stats *new = bnx2x_sp(bp, mac_stats.mstat_stats);
  485. ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
  486. ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
  487. ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
  488. ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
  489. ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
  490. ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
  491. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
  492. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
  493. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
  494. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
  495. ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
  496. ADD_STAT64(stats_tx.tx_gt127,
  497. tx_stat_etherstatspkts65octetsto127octets);
  498. ADD_STAT64(stats_tx.tx_gt255,
  499. tx_stat_etherstatspkts128octetsto255octets);
  500. ADD_STAT64(stats_tx.tx_gt511,
  501. tx_stat_etherstatspkts256octetsto511octets);
  502. ADD_STAT64(stats_tx.tx_gt1023,
  503. tx_stat_etherstatspkts512octetsto1023octets);
  504. ADD_STAT64(stats_tx.tx_gt1518,
  505. tx_stat_etherstatspkts1024octetsto1522octets);
  506. ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
  507. ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
  508. ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
  509. ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
  510. ADD_STAT64(stats_tx.tx_gterr,
  511. tx_stat_dot3statsinternalmactransmiterrors);
  512. ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
  513. ADD_64(estats->etherstatspkts1024octetsto1522octets_hi,
  514. new->stats_tx.tx_gt1518_hi,
  515. estats->etherstatspkts1024octetsto1522octets_lo,
  516. new->stats_tx.tx_gt1518_lo);
  517. ADD_64(estats->etherstatspktsover1522octets_hi,
  518. new->stats_tx.tx_gt2047_hi,
  519. estats->etherstatspktsover1522octets_lo,
  520. new->stats_tx.tx_gt2047_lo);
  521. ADD_64(estats->etherstatspktsover1522octets_hi,
  522. new->stats_tx.tx_gt4095_hi,
  523. estats->etherstatspktsover1522octets_lo,
  524. new->stats_tx.tx_gt4095_lo);
  525. ADD_64(estats->etherstatspktsover1522octets_hi,
  526. new->stats_tx.tx_gt9216_hi,
  527. estats->etherstatspktsover1522octets_lo,
  528. new->stats_tx.tx_gt9216_lo);
  529. ADD_64(estats->etherstatspktsover1522octets_hi,
  530. new->stats_tx.tx_gt16383_hi,
  531. estats->etherstatspktsover1522octets_lo,
  532. new->stats_tx.tx_gt16383_lo);
  533. estats->pause_frames_received_hi =
  534. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  535. estats->pause_frames_received_lo =
  536. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  537. estats->pause_frames_sent_hi =
  538. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  539. estats->pause_frames_sent_lo =
  540. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  541. }
  542. static void bnx2x_emac_stats_update(struct bnx2x *bp)
  543. {
  544. struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
  545. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  546. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  547. UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
  548. UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
  549. UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
  550. UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
  551. UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
  552. UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
  553. UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
  554. UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
  555. UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
  556. UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
  557. UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
  558. UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
  559. UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
  560. UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
  561. UPDATE_EXTEND_STAT(tx_stat_outxonsent);
  562. UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
  563. UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
  564. UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
  565. UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
  566. UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
  567. UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
  568. UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
  569. UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
  570. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
  571. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
  572. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
  573. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
  574. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
  575. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
  576. UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
  577. UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
  578. estats->pause_frames_received_hi =
  579. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
  580. estats->pause_frames_received_lo =
  581. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
  582. ADD_64(estats->pause_frames_received_hi,
  583. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
  584. estats->pause_frames_received_lo,
  585. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
  586. estats->pause_frames_sent_hi =
  587. pstats->mac_stx[1].tx_stat_outxonsent_hi;
  588. estats->pause_frames_sent_lo =
  589. pstats->mac_stx[1].tx_stat_outxonsent_lo;
  590. ADD_64(estats->pause_frames_sent_hi,
  591. pstats->mac_stx[1].tx_stat_outxoffsent_hi,
  592. estats->pause_frames_sent_lo,
  593. pstats->mac_stx[1].tx_stat_outxoffsent_lo);
  594. }
  595. static int bnx2x_hw_stats_update(struct bnx2x *bp)
  596. {
  597. struct nig_stats *new = bnx2x_sp(bp, nig_stats);
  598. struct nig_stats *old = &(bp->port.old_nig_stats);
  599. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  600. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  601. struct {
  602. u32 lo;
  603. u32 hi;
  604. } diff;
  605. switch (bp->link_vars.mac_type) {
  606. case MAC_TYPE_BMAC:
  607. bnx2x_bmac_stats_update(bp);
  608. break;
  609. case MAC_TYPE_EMAC:
  610. bnx2x_emac_stats_update(bp);
  611. break;
  612. case MAC_TYPE_UMAC:
  613. case MAC_TYPE_XMAC:
  614. bnx2x_mstat_stats_update(bp);
  615. break;
  616. case MAC_TYPE_NONE: /* unreached */
  617. BNX2X_ERR("stats updated by DMAE but no MAC active\n");
  618. return -1;
  619. default: /* unreached */
  620. BNX2X_ERR("Unknown MAC type\n");
  621. }
  622. ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
  623. new->brb_discard - old->brb_discard);
  624. ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
  625. new->brb_truncate - old->brb_truncate);
  626. if (!CHIP_IS_E3(bp)) {
  627. UPDATE_STAT64_NIG(egress_mac_pkt0,
  628. etherstatspkts1024octetsto1522octets);
  629. UPDATE_STAT64_NIG(egress_mac_pkt1,
  630. etherstatspktsover1522octets);
  631. }
  632. memcpy(old, new, sizeof(struct nig_stats));
  633. memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
  634. sizeof(struct mac_stx));
  635. estats->brb_drop_hi = pstats->brb_drop_hi;
  636. estats->brb_drop_lo = pstats->brb_drop_lo;
  637. pstats->host_port_stats_start = ++pstats->host_port_stats_end;
  638. if (!BP_NOMCP(bp)) {
  639. u32 nig_timer_max =
  640. SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
  641. if (nig_timer_max != estats->nig_timer_max) {
  642. estats->nig_timer_max = nig_timer_max;
  643. BNX2X_ERR("NIG timer max (%u)\n",
  644. estats->nig_timer_max);
  645. }
  646. }
  647. return 0;
  648. }
  649. static int bnx2x_storm_stats_update(struct bnx2x *bp)
  650. {
  651. struct tstorm_per_port_stats *tport =
  652. &bp->fw_stats_data->port.tstorm_port_statistics;
  653. struct tstorm_per_pf_stats *tfunc =
  654. &bp->fw_stats_data->pf.tstorm_pf_statistics;
  655. struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
  656. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  657. struct stats_counter *counters = &bp->fw_stats_data->storm_counters;
  658. int i;
  659. u16 cur_stats_counter;
  660. /* Make sure we use the value of the counter
  661. * used for sending the last stats ramrod.
  662. */
  663. spin_lock_bh(&bp->stats_lock);
  664. cur_stats_counter = bp->stats_counter - 1;
  665. spin_unlock_bh(&bp->stats_lock);
  666. /* are storm stats valid? */
  667. if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
  668. DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
  669. " xstorm counter (0x%x) != stats_counter (0x%x)\n",
  670. le16_to_cpu(counters->xstats_counter), bp->stats_counter);
  671. return -EAGAIN;
  672. }
  673. if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
  674. DP(BNX2X_MSG_STATS, "stats not updated by ustorm"
  675. " ustorm counter (0x%x) != stats_counter (0x%x)\n",
  676. le16_to_cpu(counters->ustats_counter), bp->stats_counter);
  677. return -EAGAIN;
  678. }
  679. if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
  680. DP(BNX2X_MSG_STATS, "stats not updated by cstorm"
  681. " cstorm counter (0x%x) != stats_counter (0x%x)\n",
  682. le16_to_cpu(counters->cstats_counter), bp->stats_counter);
  683. return -EAGAIN;
  684. }
  685. if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
  686. DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
  687. " tstorm counter (0x%x) != stats_counter (0x%x)\n",
  688. le16_to_cpu(counters->tstats_counter), bp->stats_counter);
  689. return -EAGAIN;
  690. }
  691. memcpy(&(fstats->total_bytes_received_hi),
  692. &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
  693. sizeof(struct host_func_stats) - 2*sizeof(u32));
  694. estats->error_bytes_received_hi = 0;
  695. estats->error_bytes_received_lo = 0;
  696. estats->etherstatsoverrsizepkts_hi = 0;
  697. estats->etherstatsoverrsizepkts_lo = 0;
  698. estats->no_buff_discard_hi = 0;
  699. estats->no_buff_discard_lo = 0;
  700. estats->total_tpa_aggregations_hi = 0;
  701. estats->total_tpa_aggregations_lo = 0;
  702. estats->total_tpa_aggregated_frames_hi = 0;
  703. estats->total_tpa_aggregated_frames_lo = 0;
  704. estats->total_tpa_bytes_hi = 0;
  705. estats->total_tpa_bytes_lo = 0;
  706. for_each_eth_queue(bp, i) {
  707. struct bnx2x_fastpath *fp = &bp->fp[i];
  708. struct tstorm_per_queue_stats *tclient =
  709. &bp->fw_stats_data->queue_stats[i].
  710. tstorm_queue_statistics;
  711. struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
  712. struct ustorm_per_queue_stats *uclient =
  713. &bp->fw_stats_data->queue_stats[i].
  714. ustorm_queue_statistics;
  715. struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
  716. struct xstorm_per_queue_stats *xclient =
  717. &bp->fw_stats_data->queue_stats[i].
  718. xstorm_queue_statistics;
  719. struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
  720. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  721. u32 diff;
  722. DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, "
  723. "bcast_sent 0x%x mcast_sent 0x%x\n",
  724. i, xclient->ucast_pkts_sent,
  725. xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
  726. DP(BNX2X_MSG_STATS, "---------------\n");
  727. qstats->total_broadcast_bytes_received_hi =
  728. le32_to_cpu(tclient->rcv_bcast_bytes.hi);
  729. qstats->total_broadcast_bytes_received_lo =
  730. le32_to_cpu(tclient->rcv_bcast_bytes.lo);
  731. qstats->total_multicast_bytes_received_hi =
  732. le32_to_cpu(tclient->rcv_mcast_bytes.hi);
  733. qstats->total_multicast_bytes_received_lo =
  734. le32_to_cpu(tclient->rcv_mcast_bytes.lo);
  735. qstats->total_unicast_bytes_received_hi =
  736. le32_to_cpu(tclient->rcv_ucast_bytes.hi);
  737. qstats->total_unicast_bytes_received_lo =
  738. le32_to_cpu(tclient->rcv_ucast_bytes.lo);
  739. /*
  740. * sum to total_bytes_received all
  741. * unicast/multicast/broadcast
  742. */
  743. qstats->total_bytes_received_hi =
  744. qstats->total_broadcast_bytes_received_hi;
  745. qstats->total_bytes_received_lo =
  746. qstats->total_broadcast_bytes_received_lo;
  747. ADD_64(qstats->total_bytes_received_hi,
  748. qstats->total_multicast_bytes_received_hi,
  749. qstats->total_bytes_received_lo,
  750. qstats->total_multicast_bytes_received_lo);
  751. ADD_64(qstats->total_bytes_received_hi,
  752. qstats->total_unicast_bytes_received_hi,
  753. qstats->total_bytes_received_lo,
  754. qstats->total_unicast_bytes_received_lo);
  755. qstats->valid_bytes_received_hi =
  756. qstats->total_bytes_received_hi;
  757. qstats->valid_bytes_received_lo =
  758. qstats->total_bytes_received_lo;
  759. UPDATE_EXTEND_TSTAT(rcv_ucast_pkts,
  760. total_unicast_packets_received);
  761. UPDATE_EXTEND_TSTAT(rcv_mcast_pkts,
  762. total_multicast_packets_received);
  763. UPDATE_EXTEND_TSTAT(rcv_bcast_pkts,
  764. total_broadcast_packets_received);
  765. UPDATE_EXTEND_TSTAT(pkts_too_big_discard,
  766. etherstatsoverrsizepkts);
  767. UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
  768. SUB_EXTEND_USTAT(ucast_no_buff_pkts,
  769. total_unicast_packets_received);
  770. SUB_EXTEND_USTAT(mcast_no_buff_pkts,
  771. total_multicast_packets_received);
  772. SUB_EXTEND_USTAT(bcast_no_buff_pkts,
  773. total_broadcast_packets_received);
  774. UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
  775. UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
  776. UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
  777. qstats->total_broadcast_bytes_transmitted_hi =
  778. le32_to_cpu(xclient->bcast_bytes_sent.hi);
  779. qstats->total_broadcast_bytes_transmitted_lo =
  780. le32_to_cpu(xclient->bcast_bytes_sent.lo);
  781. qstats->total_multicast_bytes_transmitted_hi =
  782. le32_to_cpu(xclient->mcast_bytes_sent.hi);
  783. qstats->total_multicast_bytes_transmitted_lo =
  784. le32_to_cpu(xclient->mcast_bytes_sent.lo);
  785. qstats->total_unicast_bytes_transmitted_hi =
  786. le32_to_cpu(xclient->ucast_bytes_sent.hi);
  787. qstats->total_unicast_bytes_transmitted_lo =
  788. le32_to_cpu(xclient->ucast_bytes_sent.lo);
  789. /*
  790. * sum to total_bytes_transmitted all
  791. * unicast/multicast/broadcast
  792. */
  793. qstats->total_bytes_transmitted_hi =
  794. qstats->total_unicast_bytes_transmitted_hi;
  795. qstats->total_bytes_transmitted_lo =
  796. qstats->total_unicast_bytes_transmitted_lo;
  797. ADD_64(qstats->total_bytes_transmitted_hi,
  798. qstats->total_broadcast_bytes_transmitted_hi,
  799. qstats->total_bytes_transmitted_lo,
  800. qstats->total_broadcast_bytes_transmitted_lo);
  801. ADD_64(qstats->total_bytes_transmitted_hi,
  802. qstats->total_multicast_bytes_transmitted_hi,
  803. qstats->total_bytes_transmitted_lo,
  804. qstats->total_multicast_bytes_transmitted_lo);
  805. UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
  806. total_unicast_packets_transmitted);
  807. UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
  808. total_multicast_packets_transmitted);
  809. UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
  810. total_broadcast_packets_transmitted);
  811. UPDATE_EXTEND_TSTAT(checksum_discard,
  812. total_packets_received_checksum_discarded);
  813. UPDATE_EXTEND_TSTAT(ttl0_discard,
  814. total_packets_received_ttl0_discarded);
  815. UPDATE_EXTEND_XSTAT(error_drop_pkts,
  816. total_transmitted_dropped_packets_error);
  817. /* TPA aggregations completed */
  818. UPDATE_EXTEND_USTAT(coalesced_events, total_tpa_aggregations);
  819. /* Number of network frames aggregated by TPA */
  820. UPDATE_EXTEND_USTAT(coalesced_pkts,
  821. total_tpa_aggregated_frames);
  822. /* Total number of bytes in completed TPA aggregations */
  823. qstats->total_tpa_bytes_lo =
  824. le32_to_cpu(uclient->coalesced_bytes.lo);
  825. qstats->total_tpa_bytes_hi =
  826. le32_to_cpu(uclient->coalesced_bytes.hi);
  827. /* TPA stats per-function */
  828. ADD_64(estats->total_tpa_aggregations_hi,
  829. qstats->total_tpa_aggregations_hi,
  830. estats->total_tpa_aggregations_lo,
  831. qstats->total_tpa_aggregations_lo);
  832. ADD_64(estats->total_tpa_aggregated_frames_hi,
  833. qstats->total_tpa_aggregated_frames_hi,
  834. estats->total_tpa_aggregated_frames_lo,
  835. qstats->total_tpa_aggregated_frames_lo);
  836. ADD_64(estats->total_tpa_bytes_hi,
  837. qstats->total_tpa_bytes_hi,
  838. estats->total_tpa_bytes_lo,
  839. qstats->total_tpa_bytes_lo);
  840. ADD_64(fstats->total_bytes_received_hi,
  841. qstats->total_bytes_received_hi,
  842. fstats->total_bytes_received_lo,
  843. qstats->total_bytes_received_lo);
  844. ADD_64(fstats->total_bytes_transmitted_hi,
  845. qstats->total_bytes_transmitted_hi,
  846. fstats->total_bytes_transmitted_lo,
  847. qstats->total_bytes_transmitted_lo);
  848. ADD_64(fstats->total_unicast_packets_received_hi,
  849. qstats->total_unicast_packets_received_hi,
  850. fstats->total_unicast_packets_received_lo,
  851. qstats->total_unicast_packets_received_lo);
  852. ADD_64(fstats->total_multicast_packets_received_hi,
  853. qstats->total_multicast_packets_received_hi,
  854. fstats->total_multicast_packets_received_lo,
  855. qstats->total_multicast_packets_received_lo);
  856. ADD_64(fstats->total_broadcast_packets_received_hi,
  857. qstats->total_broadcast_packets_received_hi,
  858. fstats->total_broadcast_packets_received_lo,
  859. qstats->total_broadcast_packets_received_lo);
  860. ADD_64(fstats->total_unicast_packets_transmitted_hi,
  861. qstats->total_unicast_packets_transmitted_hi,
  862. fstats->total_unicast_packets_transmitted_lo,
  863. qstats->total_unicast_packets_transmitted_lo);
  864. ADD_64(fstats->total_multicast_packets_transmitted_hi,
  865. qstats->total_multicast_packets_transmitted_hi,
  866. fstats->total_multicast_packets_transmitted_lo,
  867. qstats->total_multicast_packets_transmitted_lo);
  868. ADD_64(fstats->total_broadcast_packets_transmitted_hi,
  869. qstats->total_broadcast_packets_transmitted_hi,
  870. fstats->total_broadcast_packets_transmitted_lo,
  871. qstats->total_broadcast_packets_transmitted_lo);
  872. ADD_64(fstats->valid_bytes_received_hi,
  873. qstats->valid_bytes_received_hi,
  874. fstats->valid_bytes_received_lo,
  875. qstats->valid_bytes_received_lo);
  876. ADD_64(estats->etherstatsoverrsizepkts_hi,
  877. qstats->etherstatsoverrsizepkts_hi,
  878. estats->etherstatsoverrsizepkts_lo,
  879. qstats->etherstatsoverrsizepkts_lo);
  880. ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
  881. estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
  882. }
  883. ADD_64(fstats->total_bytes_received_hi,
  884. estats->rx_stat_ifhcinbadoctets_hi,
  885. fstats->total_bytes_received_lo,
  886. estats->rx_stat_ifhcinbadoctets_lo);
  887. ADD_64(fstats->total_bytes_received_hi,
  888. tfunc->rcv_error_bytes.hi,
  889. fstats->total_bytes_received_lo,
  890. tfunc->rcv_error_bytes.lo);
  891. memcpy(estats, &(fstats->total_bytes_received_hi),
  892. sizeof(struct host_func_stats) - 2*sizeof(u32));
  893. ADD_64(estats->error_bytes_received_hi,
  894. tfunc->rcv_error_bytes.hi,
  895. estats->error_bytes_received_lo,
  896. tfunc->rcv_error_bytes.lo);
  897. ADD_64(estats->etherstatsoverrsizepkts_hi,
  898. estats->rx_stat_dot3statsframestoolong_hi,
  899. estats->etherstatsoverrsizepkts_lo,
  900. estats->rx_stat_dot3statsframestoolong_lo);
  901. ADD_64(estats->error_bytes_received_hi,
  902. estats->rx_stat_ifhcinbadoctets_hi,
  903. estats->error_bytes_received_lo,
  904. estats->rx_stat_ifhcinbadoctets_lo);
  905. if (bp->port.pmf) {
  906. estats->mac_filter_discard =
  907. le32_to_cpu(tport->mac_filter_discard);
  908. estats->mf_tag_discard =
  909. le32_to_cpu(tport->mf_tag_discard);
  910. estats->brb_truncate_discard =
  911. le32_to_cpu(tport->brb_truncate_discard);
  912. estats->mac_discard = le32_to_cpu(tport->mac_discard);
  913. }
  914. fstats->host_func_stats_start = ++fstats->host_func_stats_end;
  915. bp->stats_pending = 0;
  916. return 0;
  917. }
  918. static void bnx2x_net_stats_update(struct bnx2x *bp)
  919. {
  920. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  921. struct net_device_stats *nstats = &bp->dev->stats;
  922. unsigned long tmp;
  923. int i;
  924. nstats->rx_packets =
  925. bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
  926. bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
  927. bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
  928. nstats->tx_packets =
  929. bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
  930. bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
  931. bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
  932. nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
  933. nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
  934. tmp = estats->mac_discard;
  935. for_each_rx_queue(bp, i)
  936. tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
  937. nstats->rx_dropped = tmp;
  938. nstats->tx_dropped = 0;
  939. nstats->multicast =
  940. bnx2x_hilo(&estats->total_multicast_packets_received_hi);
  941. nstats->collisions =
  942. bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
  943. nstats->rx_length_errors =
  944. bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
  945. bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
  946. nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
  947. bnx2x_hilo(&estats->brb_truncate_hi);
  948. nstats->rx_crc_errors =
  949. bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
  950. nstats->rx_frame_errors =
  951. bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
  952. nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
  953. nstats->rx_missed_errors = 0;
  954. nstats->rx_errors = nstats->rx_length_errors +
  955. nstats->rx_over_errors +
  956. nstats->rx_crc_errors +
  957. nstats->rx_frame_errors +
  958. nstats->rx_fifo_errors +
  959. nstats->rx_missed_errors;
  960. nstats->tx_aborted_errors =
  961. bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
  962. bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
  963. nstats->tx_carrier_errors =
  964. bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
  965. nstats->tx_fifo_errors = 0;
  966. nstats->tx_heartbeat_errors = 0;
  967. nstats->tx_window_errors = 0;
  968. nstats->tx_errors = nstats->tx_aborted_errors +
  969. nstats->tx_carrier_errors +
  970. bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
  971. }
  972. static void bnx2x_drv_stats_update(struct bnx2x *bp)
  973. {
  974. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  975. int i;
  976. estats->driver_xoff = 0;
  977. estats->rx_err_discard_pkt = 0;
  978. estats->rx_skb_alloc_failed = 0;
  979. estats->hw_csum_err = 0;
  980. for_each_queue(bp, i) {
  981. struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
  982. estats->driver_xoff += qstats->driver_xoff;
  983. estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
  984. estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
  985. estats->hw_csum_err += qstats->hw_csum_err;
  986. }
  987. }
  988. static bool bnx2x_edebug_stats_stopped(struct bnx2x *bp)
  989. {
  990. u32 val;
  991. if (SHMEM2_HAS(bp, edebug_driver_if[1])) {
  992. val = SHMEM2_RD(bp, edebug_driver_if[1]);
  993. if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT)
  994. return true;
  995. }
  996. return false;
  997. }
  998. static void bnx2x_stats_update(struct bnx2x *bp)
  999. {
  1000. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1001. if (bnx2x_edebug_stats_stopped(bp))
  1002. return;
  1003. if (*stats_comp != DMAE_COMP_VAL)
  1004. return;
  1005. if (bp->port.pmf)
  1006. bnx2x_hw_stats_update(bp);
  1007. if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
  1008. BNX2X_ERR("storm stats were not updated for 3 times\n");
  1009. bnx2x_panic();
  1010. return;
  1011. }
  1012. bnx2x_net_stats_update(bp);
  1013. bnx2x_drv_stats_update(bp);
  1014. if (netif_msg_timer(bp)) {
  1015. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  1016. int i, cos;
  1017. netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
  1018. estats->brb_drop_lo, estats->brb_truncate_lo);
  1019. for_each_eth_queue(bp, i) {
  1020. struct bnx2x_fastpath *fp = &bp->fp[i];
  1021. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  1022. printk(KERN_DEBUG "%s: rx usage(%4u) *rx_cons_sb(%u)"
  1023. " rx pkt(%lu) rx calls(%lu %lu)\n",
  1024. fp->name, (le16_to_cpu(*fp->rx_cons_sb) -
  1025. fp->rx_comp_cons),
  1026. le16_to_cpu(*fp->rx_cons_sb),
  1027. bnx2x_hilo(&qstats->
  1028. total_unicast_packets_received_hi),
  1029. fp->rx_calls, fp->rx_pkt);
  1030. }
  1031. for_each_eth_queue(bp, i) {
  1032. struct bnx2x_fastpath *fp = &bp->fp[i];
  1033. struct bnx2x_fp_txdata *txdata;
  1034. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  1035. struct netdev_queue *txq;
  1036. printk(KERN_DEBUG "%s: tx pkt(%lu) (Xoff events %u)",
  1037. fp->name, bnx2x_hilo(
  1038. &qstats->total_unicast_packets_transmitted_hi),
  1039. qstats->driver_xoff);
  1040. for_each_cos_in_tx_queue(fp, cos) {
  1041. txdata = &fp->txdata[cos];
  1042. txq = netdev_get_tx_queue(bp->dev,
  1043. FP_COS_TO_TXQ(fp, cos));
  1044. printk(KERN_DEBUG "%d: tx avail(%4u)"
  1045. " *tx_cons_sb(%u)"
  1046. " tx calls (%lu)"
  1047. " %s\n",
  1048. cos,
  1049. bnx2x_tx_avail(bp, txdata),
  1050. le16_to_cpu(*txdata->tx_cons_sb),
  1051. txdata->tx_pkt,
  1052. (netif_tx_queue_stopped(txq) ?
  1053. "Xoff" : "Xon")
  1054. );
  1055. }
  1056. }
  1057. }
  1058. bnx2x_hw_stats_post(bp);
  1059. bnx2x_storm_stats_post(bp);
  1060. }
  1061. static void bnx2x_port_stats_stop(struct bnx2x *bp)
  1062. {
  1063. struct dmae_command *dmae;
  1064. u32 opcode;
  1065. int loader_idx = PMF_DMAE_C(bp);
  1066. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1067. bp->executer_idx = 0;
  1068. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0);
  1069. if (bp->port.port_stx) {
  1070. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1071. if (bp->func_stx)
  1072. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  1073. opcode, DMAE_COMP_GRC);
  1074. else
  1075. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  1076. opcode, DMAE_COMP_PCI);
  1077. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  1078. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  1079. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  1080. dmae->dst_addr_hi = 0;
  1081. dmae->len = sizeof(struct host_port_stats) >> 2;
  1082. if (bp->func_stx) {
  1083. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  1084. dmae->comp_addr_hi = 0;
  1085. dmae->comp_val = 1;
  1086. } else {
  1087. dmae->comp_addr_lo =
  1088. U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1089. dmae->comp_addr_hi =
  1090. U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1091. dmae->comp_val = DMAE_COMP_VAL;
  1092. *stats_comp = 0;
  1093. }
  1094. }
  1095. if (bp->func_stx) {
  1096. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1097. dmae->opcode =
  1098. bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  1099. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  1100. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  1101. dmae->dst_addr_lo = bp->func_stx >> 2;
  1102. dmae->dst_addr_hi = 0;
  1103. dmae->len = sizeof(struct host_func_stats) >> 2;
  1104. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1105. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1106. dmae->comp_val = DMAE_COMP_VAL;
  1107. *stats_comp = 0;
  1108. }
  1109. }
  1110. static void bnx2x_stats_stop(struct bnx2x *bp)
  1111. {
  1112. int update = 0;
  1113. bnx2x_stats_comp(bp);
  1114. if (bp->port.pmf)
  1115. update = (bnx2x_hw_stats_update(bp) == 0);
  1116. update |= (bnx2x_storm_stats_update(bp) == 0);
  1117. if (update) {
  1118. bnx2x_net_stats_update(bp);
  1119. if (bp->port.pmf)
  1120. bnx2x_port_stats_stop(bp);
  1121. bnx2x_hw_stats_post(bp);
  1122. bnx2x_stats_comp(bp);
  1123. }
  1124. }
  1125. static void bnx2x_stats_do_nothing(struct bnx2x *bp)
  1126. {
  1127. }
  1128. static const struct {
  1129. void (*action)(struct bnx2x *bp);
  1130. enum bnx2x_stats_state next_state;
  1131. } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
  1132. /* state event */
  1133. {
  1134. /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
  1135. /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
  1136. /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
  1137. /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
  1138. },
  1139. {
  1140. /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
  1141. /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
  1142. /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
  1143. /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
  1144. }
  1145. };
  1146. void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
  1147. {
  1148. enum bnx2x_stats_state state;
  1149. if (unlikely(bp->panic))
  1150. return;
  1151. bnx2x_stats_stm[bp->stats_state][event].action(bp);
  1152. spin_lock_bh(&bp->stats_lock);
  1153. state = bp->stats_state;
  1154. bp->stats_state = bnx2x_stats_stm[state][event].next_state;
  1155. spin_unlock_bh(&bp->stats_lock);
  1156. if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
  1157. DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
  1158. state, event, bp->stats_state);
  1159. }
  1160. static void bnx2x_port_stats_base_init(struct bnx2x *bp)
  1161. {
  1162. struct dmae_command *dmae;
  1163. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1164. /* sanity */
  1165. if (!bp->port.pmf || !bp->port.port_stx) {
  1166. BNX2X_ERR("BUG!\n");
  1167. return;
  1168. }
  1169. bp->executer_idx = 0;
  1170. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1171. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  1172. true, DMAE_COMP_PCI);
  1173. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  1174. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  1175. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  1176. dmae->dst_addr_hi = 0;
  1177. dmae->len = sizeof(struct host_port_stats) >> 2;
  1178. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1179. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1180. dmae->comp_val = DMAE_COMP_VAL;
  1181. *stats_comp = 0;
  1182. bnx2x_hw_stats_post(bp);
  1183. bnx2x_stats_comp(bp);
  1184. }
  1185. static void bnx2x_func_stats_base_init(struct bnx2x *bp)
  1186. {
  1187. int vn, vn_max = IS_MF(bp) ? E1HVN_MAX : E1VN_MAX;
  1188. u32 func_stx;
  1189. /* sanity */
  1190. if (!bp->port.pmf || !bp->func_stx) {
  1191. BNX2X_ERR("BUG!\n");
  1192. return;
  1193. }
  1194. /* save our func_stx */
  1195. func_stx = bp->func_stx;
  1196. for (vn = VN_0; vn < vn_max; vn++) {
  1197. int mb_idx = CHIP_IS_E1x(bp) ? 2*vn + BP_PORT(bp) : vn;
  1198. bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
  1199. bnx2x_func_stats_init(bp);
  1200. bnx2x_hw_stats_post(bp);
  1201. bnx2x_stats_comp(bp);
  1202. }
  1203. /* restore our func_stx */
  1204. bp->func_stx = func_stx;
  1205. }
  1206. static void bnx2x_func_stats_base_update(struct bnx2x *bp)
  1207. {
  1208. struct dmae_command *dmae = &bp->stats_dmae;
  1209. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1210. /* sanity */
  1211. if (!bp->func_stx) {
  1212. BNX2X_ERR("BUG!\n");
  1213. return;
  1214. }
  1215. bp->executer_idx = 0;
  1216. memset(dmae, 0, sizeof(struct dmae_command));
  1217. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  1218. true, DMAE_COMP_PCI);
  1219. dmae->src_addr_lo = bp->func_stx >> 2;
  1220. dmae->src_addr_hi = 0;
  1221. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
  1222. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
  1223. dmae->len = sizeof(struct host_func_stats) >> 2;
  1224. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1225. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1226. dmae->comp_val = DMAE_COMP_VAL;
  1227. *stats_comp = 0;
  1228. bnx2x_hw_stats_post(bp);
  1229. bnx2x_stats_comp(bp);
  1230. }
  1231. /**
  1232. * This function will prepare the statistics ramrod data the way
  1233. * we will only have to increment the statistics counter and
  1234. * send the ramrod each time we have to.
  1235. *
  1236. * @param bp
  1237. */
  1238. static inline void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
  1239. {
  1240. int i;
  1241. struct stats_query_header *stats_hdr = &bp->fw_stats_req->hdr;
  1242. dma_addr_t cur_data_offset;
  1243. struct stats_query_entry *cur_query_entry;
  1244. stats_hdr->cmd_num = bp->fw_stats_num;
  1245. stats_hdr->drv_stats_counter = 0;
  1246. /* storm_counters struct contains the counters of completed
  1247. * statistics requests per storm which are incremented by FW
  1248. * each time it completes hadning a statistics ramrod. We will
  1249. * check these counters in the timer handler and discard a
  1250. * (statistics) ramrod completion.
  1251. */
  1252. cur_data_offset = bp->fw_stats_data_mapping +
  1253. offsetof(struct bnx2x_fw_stats_data, storm_counters);
  1254. stats_hdr->stats_counters_addrs.hi =
  1255. cpu_to_le32(U64_HI(cur_data_offset));
  1256. stats_hdr->stats_counters_addrs.lo =
  1257. cpu_to_le32(U64_LO(cur_data_offset));
  1258. /* prepare to the first stats ramrod (will be completed with
  1259. * the counters equal to zero) - init counters to somethig different.
  1260. */
  1261. memset(&bp->fw_stats_data->storm_counters, 0xff,
  1262. sizeof(struct stats_counter));
  1263. /**** Port FW statistics data ****/
  1264. cur_data_offset = bp->fw_stats_data_mapping +
  1265. offsetof(struct bnx2x_fw_stats_data, port);
  1266. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
  1267. cur_query_entry->kind = STATS_TYPE_PORT;
  1268. /* For port query index is a DONT CARE */
  1269. cur_query_entry->index = BP_PORT(bp);
  1270. /* For port query funcID is a DONT CARE */
  1271. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1272. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1273. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1274. /**** PF FW statistics data ****/
  1275. cur_data_offset = bp->fw_stats_data_mapping +
  1276. offsetof(struct bnx2x_fw_stats_data, pf);
  1277. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
  1278. cur_query_entry->kind = STATS_TYPE_PF;
  1279. /* For PF query index is a DONT CARE */
  1280. cur_query_entry->index = BP_PORT(bp);
  1281. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1282. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1283. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1284. /**** Clients' queries ****/
  1285. cur_data_offset = bp->fw_stats_data_mapping +
  1286. offsetof(struct bnx2x_fw_stats_data, queue_stats);
  1287. for_each_eth_queue(bp, i) {
  1288. cur_query_entry =
  1289. &bp->fw_stats_req->
  1290. query[BNX2X_FIRST_QUEUE_QUERY_IDX + i];
  1291. cur_query_entry->kind = STATS_TYPE_QUEUE;
  1292. cur_query_entry->index = bnx2x_stats_id(&bp->fp[i]);
  1293. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1294. cur_query_entry->address.hi =
  1295. cpu_to_le32(U64_HI(cur_data_offset));
  1296. cur_query_entry->address.lo =
  1297. cpu_to_le32(U64_LO(cur_data_offset));
  1298. cur_data_offset += sizeof(struct per_queue_stats);
  1299. }
  1300. }
  1301. void bnx2x_stats_init(struct bnx2x *bp)
  1302. {
  1303. int /*abs*/port = BP_PORT(bp);
  1304. int mb_idx = BP_FW_MB_IDX(bp);
  1305. int i;
  1306. bp->stats_pending = 0;
  1307. bp->executer_idx = 0;
  1308. bp->stats_counter = 0;
  1309. /* port and func stats for management */
  1310. if (!BP_NOMCP(bp)) {
  1311. bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
  1312. bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
  1313. } else {
  1314. bp->port.port_stx = 0;
  1315. bp->func_stx = 0;
  1316. }
  1317. DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
  1318. bp->port.port_stx, bp->func_stx);
  1319. port = BP_PORT(bp);
  1320. /* port stats */
  1321. memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
  1322. bp->port.old_nig_stats.brb_discard =
  1323. REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
  1324. bp->port.old_nig_stats.brb_truncate =
  1325. REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
  1326. if (!CHIP_IS_E3(bp)) {
  1327. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
  1328. &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
  1329. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
  1330. &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
  1331. }
  1332. /* function stats */
  1333. for_each_queue(bp, i) {
  1334. struct bnx2x_fastpath *fp = &bp->fp[i];
  1335. memset(&fp->old_tclient, 0, sizeof(fp->old_tclient));
  1336. memset(&fp->old_uclient, 0, sizeof(fp->old_uclient));
  1337. memset(&fp->old_xclient, 0, sizeof(fp->old_xclient));
  1338. memset(&fp->eth_q_stats, 0, sizeof(fp->eth_q_stats));
  1339. }
  1340. /* Prepare statistics ramrod data */
  1341. bnx2x_prep_fw_stats_req(bp);
  1342. memset(&bp->dev->stats, 0, sizeof(bp->dev->stats));
  1343. memset(&bp->eth_stats, 0, sizeof(bp->eth_stats));
  1344. bp->stats_state = STATS_STATE_DISABLED;
  1345. if (bp->port.pmf) {
  1346. if (bp->port.port_stx)
  1347. bnx2x_port_stats_base_init(bp);
  1348. if (bp->func_stx)
  1349. bnx2x_func_stats_base_init(bp);
  1350. } else if (bp->func_stx)
  1351. bnx2x_func_stats_base_update(bp);
  1352. }