bna_ctrl.c 74 KB

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  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include "bna.h"
  19. #include "bfa_cs.h"
  20. static void bna_device_cb_port_stopped(void *arg, enum bna_cb_status status);
  21. static void
  22. bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen,
  23. int status)
  24. {
  25. int i;
  26. u8 prio_map;
  27. port->llport.link_status = BNA_LINK_UP;
  28. if (aen->cee_linkup)
  29. port->llport.link_status = BNA_CEE_UP;
  30. /* Compute the priority */
  31. prio_map = aen->prio_map;
  32. if (prio_map) {
  33. for (i = 0; i < 8; i++) {
  34. if ((prio_map >> i) & 0x1)
  35. break;
  36. }
  37. port->priority = i;
  38. } else
  39. port->priority = 0;
  40. /* Dispatch events */
  41. bna_tx_mod_cee_link_status(&port->bna->tx_mod, aen->cee_linkup);
  42. bna_tx_mod_prio_changed(&port->bna->tx_mod, port->priority);
  43. port->link_cbfn(port->bna->bnad, port->llport.link_status);
  44. }
  45. static void
  46. bna_port_cb_link_down(struct bna_port *port, int status)
  47. {
  48. port->llport.link_status = BNA_LINK_DOWN;
  49. /* Dispatch events */
  50. bna_tx_mod_cee_link_status(&port->bna->tx_mod, BNA_LINK_DOWN);
  51. port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN);
  52. }
  53. static inline int
  54. llport_can_be_up(struct bna_llport *llport)
  55. {
  56. int ready = 0;
  57. if (llport->type == BNA_PORT_T_REGULAR)
  58. ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
  59. (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
  60. (llport->flags & BNA_LLPORT_F_PORT_ENABLED));
  61. else
  62. ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
  63. (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
  64. !(llport->flags & BNA_LLPORT_F_PORT_ENABLED));
  65. return ready;
  66. }
  67. #define llport_is_up llport_can_be_up
  68. enum bna_llport_event {
  69. LLPORT_E_START = 1,
  70. LLPORT_E_STOP = 2,
  71. LLPORT_E_FAIL = 3,
  72. LLPORT_E_UP = 4,
  73. LLPORT_E_DOWN = 5,
  74. LLPORT_E_FWRESP_UP_OK = 6,
  75. LLPORT_E_FWRESP_UP_FAIL = 7,
  76. LLPORT_E_FWRESP_DOWN = 8
  77. };
  78. static void
  79. bna_llport_cb_port_enabled(struct bna_llport *llport)
  80. {
  81. llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
  82. if (llport_can_be_up(llport))
  83. bfa_fsm_send_event(llport, LLPORT_E_UP);
  84. }
  85. static void
  86. bna_llport_cb_port_disabled(struct bna_llport *llport)
  87. {
  88. int llport_up = llport_is_up(llport);
  89. llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
  90. if (llport_up)
  91. bfa_fsm_send_event(llport, LLPORT_E_DOWN);
  92. }
  93. /**
  94. * MBOX
  95. */
  96. static int
  97. bna_is_aen(u8 msg_id)
  98. {
  99. switch (msg_id) {
  100. case BFI_LL_I2H_LINK_DOWN_AEN:
  101. case BFI_LL_I2H_LINK_UP_AEN:
  102. case BFI_LL_I2H_PORT_ENABLE_AEN:
  103. case BFI_LL_I2H_PORT_DISABLE_AEN:
  104. return 1;
  105. default:
  106. return 0;
  107. }
  108. }
  109. static void
  110. bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg)
  111. {
  112. struct bfi_ll_aen *aen = (struct bfi_ll_aen *)(msg);
  113. switch (aen->mh.msg_id) {
  114. case BFI_LL_I2H_LINK_UP_AEN:
  115. bna_port_cb_link_up(&bna->port, aen, aen->reason);
  116. break;
  117. case BFI_LL_I2H_LINK_DOWN_AEN:
  118. bna_port_cb_link_down(&bna->port, aen->reason);
  119. break;
  120. case BFI_LL_I2H_PORT_ENABLE_AEN:
  121. bna_llport_cb_port_enabled(&bna->port.llport);
  122. break;
  123. case BFI_LL_I2H_PORT_DISABLE_AEN:
  124. bna_llport_cb_port_disabled(&bna->port.llport);
  125. break;
  126. default:
  127. break;
  128. }
  129. }
  130. static void
  131. bna_ll_isr(void *llarg, struct bfi_mbmsg *msg)
  132. {
  133. struct bna *bna = (struct bna *)(llarg);
  134. struct bfi_ll_rsp *mb_rsp = (struct bfi_ll_rsp *)(msg);
  135. struct bfi_mhdr *cmd_h, *rsp_h;
  136. struct bna_mbox_qe *mb_qe = NULL;
  137. int to_post = 0;
  138. u8 aen = 0;
  139. char message[BNA_MESSAGE_SIZE];
  140. aen = bna_is_aen(mb_rsp->mh.msg_id);
  141. if (!aen) {
  142. mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
  143. cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
  144. rsp_h = (struct bfi_mhdr *)(&mb_rsp->mh);
  145. if ((BFA_I2HM(cmd_h->msg_id) == rsp_h->msg_id) &&
  146. (cmd_h->mtag.i2htok == rsp_h->mtag.i2htok)) {
  147. /* Remove the request from posted_q, update state */
  148. list_del(&mb_qe->qe);
  149. bna->mbox_mod.msg_pending--;
  150. if (list_empty(&bna->mbox_mod.posted_q))
  151. bna->mbox_mod.state = BNA_MBOX_FREE;
  152. else
  153. to_post = 1;
  154. /* Dispatch the cbfn */
  155. if (mb_qe->cbfn)
  156. mb_qe->cbfn(mb_qe->cbarg, mb_rsp->error);
  157. /* Post the next entry, if needed */
  158. if (to_post) {
  159. mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
  160. bfa_nw_ioc_mbox_queue(&bna->device.ioc,
  161. &mb_qe->cmd);
  162. }
  163. } else {
  164. snprintf(message, BNA_MESSAGE_SIZE,
  165. "No matching rsp for [%d:%d:%d]\n",
  166. mb_rsp->mh.msg_class, mb_rsp->mh.msg_id,
  167. mb_rsp->mh.mtag.i2htok);
  168. pr_info("%s", message);
  169. }
  170. } else
  171. bna_mbox_aen_callback(bna, msg);
  172. }
  173. static void
  174. bna_err_handler(struct bna *bna, u32 intr_status)
  175. {
  176. u32 init_halt;
  177. if (intr_status & __HALT_STATUS_BITS) {
  178. init_halt = readl(bna->device.ioc.ioc_regs.ll_halt);
  179. init_halt &= ~__FW_INIT_HALT_P;
  180. writel(init_halt, bna->device.ioc.ioc_regs.ll_halt);
  181. }
  182. bfa_nw_ioc_error_isr(&bna->device.ioc);
  183. }
  184. void
  185. bna_mbox_handler(struct bna *bna, u32 intr_status)
  186. {
  187. if (BNA_IS_ERR_INTR(intr_status)) {
  188. bna_err_handler(bna, intr_status);
  189. return;
  190. }
  191. if (BNA_IS_MBOX_INTR(intr_status))
  192. bfa_nw_ioc_mbox_isr(&bna->device.ioc);
  193. }
  194. void
  195. bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe)
  196. {
  197. struct bfi_mhdr *mh;
  198. mh = (struct bfi_mhdr *)(&mbox_qe->cmd.msg[0]);
  199. mh->mtag.i2htok = htons(bna->mbox_mod.msg_ctr);
  200. bna->mbox_mod.msg_ctr++;
  201. bna->mbox_mod.msg_pending++;
  202. if (bna->mbox_mod.state == BNA_MBOX_FREE) {
  203. list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
  204. bfa_nw_ioc_mbox_queue(&bna->device.ioc, &mbox_qe->cmd);
  205. bna->mbox_mod.state = BNA_MBOX_POSTED;
  206. } else {
  207. list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
  208. }
  209. }
  210. static void
  211. bna_mbox_flush_q(struct bna *bna, struct list_head *q)
  212. {
  213. struct bna_mbox_qe *mb_qe = NULL;
  214. struct list_head *mb_q;
  215. void (*cbfn)(void *arg, int status);
  216. void *cbarg;
  217. mb_q = &bna->mbox_mod.posted_q;
  218. while (!list_empty(mb_q)) {
  219. bfa_q_deq(mb_q, &mb_qe);
  220. cbfn = mb_qe->cbfn;
  221. cbarg = mb_qe->cbarg;
  222. bfa_q_qe_init(mb_qe);
  223. bna->mbox_mod.msg_pending--;
  224. if (cbfn)
  225. cbfn(cbarg, BNA_CB_NOT_EXEC);
  226. }
  227. bna->mbox_mod.state = BNA_MBOX_FREE;
  228. }
  229. static void
  230. bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod)
  231. {
  232. }
  233. static void
  234. bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod)
  235. {
  236. bna_mbox_flush_q(mbox_mod->bna, &mbox_mod->posted_q);
  237. }
  238. static void
  239. bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna)
  240. {
  241. bfa_nw_ioc_mbox_regisr(&bna->device.ioc, BFI_MC_LL, bna_ll_isr, bna);
  242. mbox_mod->state = BNA_MBOX_FREE;
  243. mbox_mod->msg_ctr = mbox_mod->msg_pending = 0;
  244. INIT_LIST_HEAD(&mbox_mod->posted_q);
  245. mbox_mod->bna = bna;
  246. }
  247. static void
  248. bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod)
  249. {
  250. mbox_mod->bna = NULL;
  251. }
  252. /**
  253. * LLPORT
  254. */
  255. #define call_llport_stop_cbfn(llport, status)\
  256. do {\
  257. if ((llport)->stop_cbfn)\
  258. (llport)->stop_cbfn(&(llport)->bna->port, status);\
  259. (llport)->stop_cbfn = NULL;\
  260. } while (0)
  261. static void bna_fw_llport_up(struct bna_llport *llport);
  262. static void bna_fw_cb_llport_up(void *arg, int status);
  263. static void bna_fw_llport_down(struct bna_llport *llport);
  264. static void bna_fw_cb_llport_down(void *arg, int status);
  265. static void bna_llport_start(struct bna_llport *llport);
  266. static void bna_llport_stop(struct bna_llport *llport);
  267. static void bna_llport_fail(struct bna_llport *llport);
  268. enum bna_llport_state {
  269. BNA_LLPORT_STOPPED = 1,
  270. BNA_LLPORT_DOWN = 2,
  271. BNA_LLPORT_UP_RESP_WAIT = 3,
  272. BNA_LLPORT_DOWN_RESP_WAIT = 4,
  273. BNA_LLPORT_UP = 5,
  274. BNA_LLPORT_LAST_RESP_WAIT = 6
  275. };
  276. bfa_fsm_state_decl(bna_llport, stopped, struct bna_llport,
  277. enum bna_llport_event);
  278. bfa_fsm_state_decl(bna_llport, down, struct bna_llport,
  279. enum bna_llport_event);
  280. bfa_fsm_state_decl(bna_llport, up_resp_wait, struct bna_llport,
  281. enum bna_llport_event);
  282. bfa_fsm_state_decl(bna_llport, down_resp_wait, struct bna_llport,
  283. enum bna_llport_event);
  284. bfa_fsm_state_decl(bna_llport, up, struct bna_llport,
  285. enum bna_llport_event);
  286. bfa_fsm_state_decl(bna_llport, last_resp_wait, struct bna_llport,
  287. enum bna_llport_event);
  288. static struct bfa_sm_table llport_sm_table[] = {
  289. {BFA_SM(bna_llport_sm_stopped), BNA_LLPORT_STOPPED},
  290. {BFA_SM(bna_llport_sm_down), BNA_LLPORT_DOWN},
  291. {BFA_SM(bna_llport_sm_up_resp_wait), BNA_LLPORT_UP_RESP_WAIT},
  292. {BFA_SM(bna_llport_sm_down_resp_wait), BNA_LLPORT_DOWN_RESP_WAIT},
  293. {BFA_SM(bna_llport_sm_up), BNA_LLPORT_UP},
  294. {BFA_SM(bna_llport_sm_last_resp_wait), BNA_LLPORT_LAST_RESP_WAIT}
  295. };
  296. static void
  297. bna_llport_sm_stopped_entry(struct bna_llport *llport)
  298. {
  299. llport->bna->port.link_cbfn((llport)->bna->bnad, BNA_LINK_DOWN);
  300. call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
  301. }
  302. static void
  303. bna_llport_sm_stopped(struct bna_llport *llport,
  304. enum bna_llport_event event)
  305. {
  306. switch (event) {
  307. case LLPORT_E_START:
  308. bfa_fsm_set_state(llport, bna_llport_sm_down);
  309. break;
  310. case LLPORT_E_STOP:
  311. call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
  312. break;
  313. case LLPORT_E_FAIL:
  314. break;
  315. case LLPORT_E_DOWN:
  316. /* This event is received due to Rx objects failing */
  317. /* No-op */
  318. break;
  319. case LLPORT_E_FWRESP_UP_OK:
  320. case LLPORT_E_FWRESP_DOWN:
  321. /**
  322. * These events are received due to flushing of mbox when
  323. * device fails
  324. */
  325. /* No-op */
  326. break;
  327. default:
  328. bfa_sm_fault(event);
  329. }
  330. }
  331. static void
  332. bna_llport_sm_down_entry(struct bna_llport *llport)
  333. {
  334. bnad_cb_port_link_status((llport)->bna->bnad, BNA_LINK_DOWN);
  335. }
  336. static void
  337. bna_llport_sm_down(struct bna_llport *llport,
  338. enum bna_llport_event event)
  339. {
  340. switch (event) {
  341. case LLPORT_E_STOP:
  342. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  343. break;
  344. case LLPORT_E_FAIL:
  345. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  346. break;
  347. case LLPORT_E_UP:
  348. bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
  349. bna_fw_llport_up(llport);
  350. break;
  351. default:
  352. bfa_sm_fault(event);
  353. }
  354. }
  355. static void
  356. bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport)
  357. {
  358. BUG_ON(!llport_can_be_up(llport));
  359. /**
  360. * NOTE: Do not call bna_fw_llport_up() here. That will over step
  361. * mbox due to down_resp_wait -> up_resp_wait transition on event
  362. * LLPORT_E_UP
  363. */
  364. }
  365. static void
  366. bna_llport_sm_up_resp_wait(struct bna_llport *llport,
  367. enum bna_llport_event event)
  368. {
  369. switch (event) {
  370. case LLPORT_E_STOP:
  371. bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
  372. break;
  373. case LLPORT_E_FAIL:
  374. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  375. break;
  376. case LLPORT_E_DOWN:
  377. bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
  378. break;
  379. case LLPORT_E_FWRESP_UP_OK:
  380. bfa_fsm_set_state(llport, bna_llport_sm_up);
  381. break;
  382. case LLPORT_E_FWRESP_UP_FAIL:
  383. bfa_fsm_set_state(llport, bna_llport_sm_down);
  384. break;
  385. case LLPORT_E_FWRESP_DOWN:
  386. /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */
  387. bna_fw_llport_up(llport);
  388. break;
  389. default:
  390. bfa_sm_fault(event);
  391. }
  392. }
  393. static void
  394. bna_llport_sm_down_resp_wait_entry(struct bna_llport *llport)
  395. {
  396. /**
  397. * NOTE: Do not call bna_fw_llport_down() here. That will over step
  398. * mbox due to up_resp_wait -> down_resp_wait transition on event
  399. * LLPORT_E_DOWN
  400. */
  401. }
  402. static void
  403. bna_llport_sm_down_resp_wait(struct bna_llport *llport,
  404. enum bna_llport_event event)
  405. {
  406. switch (event) {
  407. case LLPORT_E_STOP:
  408. bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
  409. break;
  410. case LLPORT_E_FAIL:
  411. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  412. break;
  413. case LLPORT_E_UP:
  414. bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
  415. break;
  416. case LLPORT_E_FWRESP_UP_OK:
  417. /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */
  418. bna_fw_llport_down(llport);
  419. break;
  420. case LLPORT_E_FWRESP_UP_FAIL:
  421. case LLPORT_E_FWRESP_DOWN:
  422. bfa_fsm_set_state(llport, bna_llport_sm_down);
  423. break;
  424. default:
  425. bfa_sm_fault(event);
  426. }
  427. }
  428. static void
  429. bna_llport_sm_up_entry(struct bna_llport *llport)
  430. {
  431. }
  432. static void
  433. bna_llport_sm_up(struct bna_llport *llport,
  434. enum bna_llport_event event)
  435. {
  436. switch (event) {
  437. case LLPORT_E_STOP:
  438. bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
  439. bna_fw_llport_down(llport);
  440. break;
  441. case LLPORT_E_FAIL:
  442. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  443. break;
  444. case LLPORT_E_DOWN:
  445. bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
  446. bna_fw_llport_down(llport);
  447. break;
  448. default:
  449. bfa_sm_fault(event);
  450. }
  451. }
  452. static void
  453. bna_llport_sm_last_resp_wait_entry(struct bna_llport *llport)
  454. {
  455. }
  456. static void
  457. bna_llport_sm_last_resp_wait(struct bna_llport *llport,
  458. enum bna_llport_event event)
  459. {
  460. switch (event) {
  461. case LLPORT_E_FAIL:
  462. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  463. break;
  464. case LLPORT_E_DOWN:
  465. /**
  466. * This event is received due to Rx objects stopping in
  467. * parallel to llport
  468. */
  469. /* No-op */
  470. break;
  471. case LLPORT_E_FWRESP_UP_OK:
  472. /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */
  473. bna_fw_llport_down(llport);
  474. break;
  475. case LLPORT_E_FWRESP_UP_FAIL:
  476. case LLPORT_E_FWRESP_DOWN:
  477. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  478. break;
  479. default:
  480. bfa_sm_fault(event);
  481. }
  482. }
  483. static void
  484. bna_fw_llport_admin_up(struct bna_llport *llport)
  485. {
  486. struct bfi_ll_port_admin_req ll_req;
  487. memset(&ll_req, 0, sizeof(ll_req));
  488. ll_req.mh.msg_class = BFI_MC_LL;
  489. ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
  490. ll_req.mh.mtag.h2i.lpu_id = 0;
  491. ll_req.up = BNA_STATUS_T_ENABLED;
  492. bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
  493. bna_fw_cb_llport_up, llport);
  494. bna_mbox_send(llport->bna, &llport->mbox_qe);
  495. }
  496. static void
  497. bna_fw_llport_up(struct bna_llport *llport)
  498. {
  499. if (llport->type == BNA_PORT_T_REGULAR)
  500. bna_fw_llport_admin_up(llport);
  501. }
  502. static void
  503. bna_fw_cb_llport_up(void *arg, int status)
  504. {
  505. struct bna_llport *llport = (struct bna_llport *)arg;
  506. bfa_q_qe_init(&llport->mbox_qe.qe);
  507. if (status == BFI_LL_CMD_FAIL) {
  508. if (llport->type == BNA_PORT_T_REGULAR)
  509. llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
  510. else
  511. llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
  512. bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_FAIL);
  513. } else
  514. bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_OK);
  515. }
  516. static void
  517. bna_fw_llport_admin_down(struct bna_llport *llport)
  518. {
  519. struct bfi_ll_port_admin_req ll_req;
  520. memset(&ll_req, 0, sizeof(ll_req));
  521. ll_req.mh.msg_class = BFI_MC_LL;
  522. ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
  523. ll_req.mh.mtag.h2i.lpu_id = 0;
  524. ll_req.up = BNA_STATUS_T_DISABLED;
  525. bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
  526. bna_fw_cb_llport_down, llport);
  527. bna_mbox_send(llport->bna, &llport->mbox_qe);
  528. }
  529. static void
  530. bna_fw_llport_down(struct bna_llport *llport)
  531. {
  532. if (llport->type == BNA_PORT_T_REGULAR)
  533. bna_fw_llport_admin_down(llport);
  534. }
  535. static void
  536. bna_fw_cb_llport_down(void *arg, int status)
  537. {
  538. struct bna_llport *llport = (struct bna_llport *)arg;
  539. bfa_q_qe_init(&llport->mbox_qe.qe);
  540. bfa_fsm_send_event(llport, LLPORT_E_FWRESP_DOWN);
  541. }
  542. static void
  543. bna_port_cb_llport_stopped(struct bna_port *port,
  544. enum bna_cb_status status)
  545. {
  546. bfa_wc_down(&port->chld_stop_wc);
  547. }
  548. static void
  549. bna_llport_init(struct bna_llport *llport, struct bna *bna)
  550. {
  551. llport->flags |= BNA_LLPORT_F_ADMIN_UP;
  552. llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
  553. llport->type = BNA_PORT_T_REGULAR;
  554. llport->bna = bna;
  555. llport->link_status = BNA_LINK_DOWN;
  556. llport->rx_started_count = 0;
  557. llport->stop_cbfn = NULL;
  558. bfa_q_qe_init(&llport->mbox_qe.qe);
  559. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  560. }
  561. static void
  562. bna_llport_uninit(struct bna_llport *llport)
  563. {
  564. llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
  565. llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
  566. llport->bna = NULL;
  567. }
  568. static void
  569. bna_llport_start(struct bna_llport *llport)
  570. {
  571. bfa_fsm_send_event(llport, LLPORT_E_START);
  572. }
  573. static void
  574. bna_llport_stop(struct bna_llport *llport)
  575. {
  576. llport->stop_cbfn = bna_port_cb_llport_stopped;
  577. bfa_fsm_send_event(llport, LLPORT_E_STOP);
  578. }
  579. static void
  580. bna_llport_fail(struct bna_llport *llport)
  581. {
  582. /* Reset the physical port status to enabled */
  583. llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
  584. bfa_fsm_send_event(llport, LLPORT_E_FAIL);
  585. }
  586. static int
  587. bna_llport_state_get(struct bna_llport *llport)
  588. {
  589. return bfa_sm_to_state(llport_sm_table, llport->fsm);
  590. }
  591. void
  592. bna_llport_rx_started(struct bna_llport *llport)
  593. {
  594. llport->rx_started_count++;
  595. if (llport->rx_started_count == 1) {
  596. llport->flags |= BNA_LLPORT_F_RX_STARTED;
  597. if (llport_can_be_up(llport))
  598. bfa_fsm_send_event(llport, LLPORT_E_UP);
  599. }
  600. }
  601. void
  602. bna_llport_rx_stopped(struct bna_llport *llport)
  603. {
  604. int llport_up = llport_is_up(llport);
  605. llport->rx_started_count--;
  606. if (llport->rx_started_count == 0) {
  607. llport->flags &= ~BNA_LLPORT_F_RX_STARTED;
  608. if (llport_up)
  609. bfa_fsm_send_event(llport, LLPORT_E_DOWN);
  610. }
  611. }
  612. /**
  613. * PORT
  614. */
  615. #define bna_port_chld_start(port)\
  616. do {\
  617. enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  618. BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
  619. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  620. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  621. bna_llport_start(&(port)->llport);\
  622. bna_tx_mod_start(&(port)->bna->tx_mod, tx_type);\
  623. bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
  624. } while (0)
  625. #define bna_port_chld_stop(port)\
  626. do {\
  627. enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  628. BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
  629. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  630. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  631. bfa_wc_up(&(port)->chld_stop_wc);\
  632. bfa_wc_up(&(port)->chld_stop_wc);\
  633. bfa_wc_up(&(port)->chld_stop_wc);\
  634. bna_llport_stop(&(port)->llport);\
  635. bna_tx_mod_stop(&(port)->bna->tx_mod, tx_type);\
  636. bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
  637. } while (0)
  638. #define bna_port_chld_fail(port)\
  639. do {\
  640. bna_llport_fail(&(port)->llport);\
  641. bna_tx_mod_fail(&(port)->bna->tx_mod);\
  642. bna_rx_mod_fail(&(port)->bna->rx_mod);\
  643. } while (0)
  644. #define bna_port_rx_start(port)\
  645. do {\
  646. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  647. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  648. bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
  649. } while (0)
  650. #define bna_port_rx_stop(port)\
  651. do {\
  652. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  653. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  654. bfa_wc_up(&(port)->chld_stop_wc);\
  655. bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
  656. } while (0)
  657. #define call_port_stop_cbfn(port, status)\
  658. do {\
  659. if ((port)->stop_cbfn)\
  660. (port)->stop_cbfn((port)->stop_cbarg, status);\
  661. (port)->stop_cbfn = NULL;\
  662. (port)->stop_cbarg = NULL;\
  663. } while (0)
  664. #define call_port_pause_cbfn(port, status)\
  665. do {\
  666. if ((port)->pause_cbfn)\
  667. (port)->pause_cbfn((port)->bna->bnad, status);\
  668. (port)->pause_cbfn = NULL;\
  669. } while (0)
  670. #define call_port_mtu_cbfn(port, status)\
  671. do {\
  672. if ((port)->mtu_cbfn)\
  673. (port)->mtu_cbfn((port)->bna->bnad, status);\
  674. (port)->mtu_cbfn = NULL;\
  675. } while (0)
  676. static void bna_fw_pause_set(struct bna_port *port);
  677. static void bna_fw_cb_pause_set(void *arg, int status);
  678. static void bna_fw_mtu_set(struct bna_port *port);
  679. static void bna_fw_cb_mtu_set(void *arg, int status);
  680. enum bna_port_event {
  681. PORT_E_START = 1,
  682. PORT_E_STOP = 2,
  683. PORT_E_FAIL = 3,
  684. PORT_E_PAUSE_CFG = 4,
  685. PORT_E_MTU_CFG = 5,
  686. PORT_E_CHLD_STOPPED = 6,
  687. PORT_E_FWRESP_PAUSE = 7,
  688. PORT_E_FWRESP_MTU = 8
  689. };
  690. enum bna_port_state {
  691. BNA_PORT_STOPPED = 1,
  692. BNA_PORT_MTU_INIT_WAIT = 2,
  693. BNA_PORT_PAUSE_INIT_WAIT = 3,
  694. BNA_PORT_LAST_RESP_WAIT = 4,
  695. BNA_PORT_STARTED = 5,
  696. BNA_PORT_PAUSE_CFG_WAIT = 6,
  697. BNA_PORT_RX_STOP_WAIT = 7,
  698. BNA_PORT_MTU_CFG_WAIT = 8,
  699. BNA_PORT_CHLD_STOP_WAIT = 9
  700. };
  701. bfa_fsm_state_decl(bna_port, stopped, struct bna_port,
  702. enum bna_port_event);
  703. bfa_fsm_state_decl(bna_port, mtu_init_wait, struct bna_port,
  704. enum bna_port_event);
  705. bfa_fsm_state_decl(bna_port, pause_init_wait, struct bna_port,
  706. enum bna_port_event);
  707. bfa_fsm_state_decl(bna_port, last_resp_wait, struct bna_port,
  708. enum bna_port_event);
  709. bfa_fsm_state_decl(bna_port, started, struct bna_port,
  710. enum bna_port_event);
  711. bfa_fsm_state_decl(bna_port, pause_cfg_wait, struct bna_port,
  712. enum bna_port_event);
  713. bfa_fsm_state_decl(bna_port, rx_stop_wait, struct bna_port,
  714. enum bna_port_event);
  715. bfa_fsm_state_decl(bna_port, mtu_cfg_wait, struct bna_port,
  716. enum bna_port_event);
  717. bfa_fsm_state_decl(bna_port, chld_stop_wait, struct bna_port,
  718. enum bna_port_event);
  719. static struct bfa_sm_table port_sm_table[] = {
  720. {BFA_SM(bna_port_sm_stopped), BNA_PORT_STOPPED},
  721. {BFA_SM(bna_port_sm_mtu_init_wait), BNA_PORT_MTU_INIT_WAIT},
  722. {BFA_SM(bna_port_sm_pause_init_wait), BNA_PORT_PAUSE_INIT_WAIT},
  723. {BFA_SM(bna_port_sm_last_resp_wait), BNA_PORT_LAST_RESP_WAIT},
  724. {BFA_SM(bna_port_sm_started), BNA_PORT_STARTED},
  725. {BFA_SM(bna_port_sm_pause_cfg_wait), BNA_PORT_PAUSE_CFG_WAIT},
  726. {BFA_SM(bna_port_sm_rx_stop_wait), BNA_PORT_RX_STOP_WAIT},
  727. {BFA_SM(bna_port_sm_mtu_cfg_wait), BNA_PORT_MTU_CFG_WAIT},
  728. {BFA_SM(bna_port_sm_chld_stop_wait), BNA_PORT_CHLD_STOP_WAIT}
  729. };
  730. static void
  731. bna_port_sm_stopped_entry(struct bna_port *port)
  732. {
  733. call_port_pause_cbfn(port, BNA_CB_SUCCESS);
  734. call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
  735. call_port_stop_cbfn(port, BNA_CB_SUCCESS);
  736. }
  737. static void
  738. bna_port_sm_stopped(struct bna_port *port, enum bna_port_event event)
  739. {
  740. switch (event) {
  741. case PORT_E_START:
  742. bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
  743. break;
  744. case PORT_E_STOP:
  745. call_port_stop_cbfn(port, BNA_CB_SUCCESS);
  746. break;
  747. case PORT_E_FAIL:
  748. /* No-op */
  749. break;
  750. case PORT_E_PAUSE_CFG:
  751. call_port_pause_cbfn(port, BNA_CB_SUCCESS);
  752. break;
  753. case PORT_E_MTU_CFG:
  754. call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
  755. break;
  756. case PORT_E_CHLD_STOPPED:
  757. /**
  758. * This event is received due to LLPort, Tx and Rx objects
  759. * failing
  760. */
  761. /* No-op */
  762. break;
  763. case PORT_E_FWRESP_PAUSE:
  764. case PORT_E_FWRESP_MTU:
  765. /**
  766. * These events are received due to flushing of mbox when
  767. * device fails
  768. */
  769. /* No-op */
  770. break;
  771. default:
  772. bfa_sm_fault(event);
  773. }
  774. }
  775. static void
  776. bna_port_sm_mtu_init_wait_entry(struct bna_port *port)
  777. {
  778. bna_fw_mtu_set(port);
  779. }
  780. static void
  781. bna_port_sm_mtu_init_wait(struct bna_port *port, enum bna_port_event event)
  782. {
  783. switch (event) {
  784. case PORT_E_STOP:
  785. bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
  786. break;
  787. case PORT_E_FAIL:
  788. bfa_fsm_set_state(port, bna_port_sm_stopped);
  789. break;
  790. case PORT_E_PAUSE_CFG:
  791. /* No-op */
  792. break;
  793. case PORT_E_MTU_CFG:
  794. port->flags |= BNA_PORT_F_MTU_CHANGED;
  795. break;
  796. case PORT_E_FWRESP_MTU:
  797. if (port->flags & BNA_PORT_F_MTU_CHANGED) {
  798. port->flags &= ~BNA_PORT_F_MTU_CHANGED;
  799. bna_fw_mtu_set(port);
  800. } else {
  801. bfa_fsm_set_state(port, bna_port_sm_pause_init_wait);
  802. }
  803. break;
  804. default:
  805. bfa_sm_fault(event);
  806. }
  807. }
  808. static void
  809. bna_port_sm_pause_init_wait_entry(struct bna_port *port)
  810. {
  811. bna_fw_pause_set(port);
  812. }
  813. static void
  814. bna_port_sm_pause_init_wait(struct bna_port *port,
  815. enum bna_port_event event)
  816. {
  817. switch (event) {
  818. case PORT_E_STOP:
  819. bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
  820. break;
  821. case PORT_E_FAIL:
  822. bfa_fsm_set_state(port, bna_port_sm_stopped);
  823. break;
  824. case PORT_E_PAUSE_CFG:
  825. port->flags |= BNA_PORT_F_PAUSE_CHANGED;
  826. break;
  827. case PORT_E_MTU_CFG:
  828. port->flags |= BNA_PORT_F_MTU_CHANGED;
  829. break;
  830. case PORT_E_FWRESP_PAUSE:
  831. if (port->flags & BNA_PORT_F_PAUSE_CHANGED) {
  832. port->flags &= ~BNA_PORT_F_PAUSE_CHANGED;
  833. bna_fw_pause_set(port);
  834. } else if (port->flags & BNA_PORT_F_MTU_CHANGED) {
  835. port->flags &= ~BNA_PORT_F_MTU_CHANGED;
  836. bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
  837. } else {
  838. bfa_fsm_set_state(port, bna_port_sm_started);
  839. bna_port_chld_start(port);
  840. }
  841. break;
  842. default:
  843. bfa_sm_fault(event);
  844. }
  845. }
  846. static void
  847. bna_port_sm_last_resp_wait_entry(struct bna_port *port)
  848. {
  849. }
  850. static void
  851. bna_port_sm_last_resp_wait(struct bna_port *port,
  852. enum bna_port_event event)
  853. {
  854. switch (event) {
  855. case PORT_E_FAIL:
  856. case PORT_E_FWRESP_PAUSE:
  857. case PORT_E_FWRESP_MTU:
  858. bfa_fsm_set_state(port, bna_port_sm_stopped);
  859. break;
  860. default:
  861. bfa_sm_fault(event);
  862. }
  863. }
  864. static void
  865. bna_port_sm_started_entry(struct bna_port *port)
  866. {
  867. /**
  868. * NOTE: Do not call bna_port_chld_start() here, since it will be
  869. * inadvertently called during pause_cfg_wait->started transition
  870. * as well
  871. */
  872. call_port_pause_cbfn(port, BNA_CB_SUCCESS);
  873. call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
  874. }
  875. static void
  876. bna_port_sm_started(struct bna_port *port,
  877. enum bna_port_event event)
  878. {
  879. switch (event) {
  880. case PORT_E_STOP:
  881. bfa_fsm_set_state(port, bna_port_sm_chld_stop_wait);
  882. break;
  883. case PORT_E_FAIL:
  884. bfa_fsm_set_state(port, bna_port_sm_stopped);
  885. bna_port_chld_fail(port);
  886. break;
  887. case PORT_E_PAUSE_CFG:
  888. bfa_fsm_set_state(port, bna_port_sm_pause_cfg_wait);
  889. break;
  890. case PORT_E_MTU_CFG:
  891. bfa_fsm_set_state(port, bna_port_sm_rx_stop_wait);
  892. break;
  893. default:
  894. bfa_sm_fault(event);
  895. }
  896. }
  897. static void
  898. bna_port_sm_pause_cfg_wait_entry(struct bna_port *port)
  899. {
  900. bna_fw_pause_set(port);
  901. }
  902. static void
  903. bna_port_sm_pause_cfg_wait(struct bna_port *port,
  904. enum bna_port_event event)
  905. {
  906. switch (event) {
  907. case PORT_E_FAIL:
  908. bfa_fsm_set_state(port, bna_port_sm_stopped);
  909. bna_port_chld_fail(port);
  910. break;
  911. case PORT_E_FWRESP_PAUSE:
  912. bfa_fsm_set_state(port, bna_port_sm_started);
  913. break;
  914. default:
  915. bfa_sm_fault(event);
  916. }
  917. }
  918. static void
  919. bna_port_sm_rx_stop_wait_entry(struct bna_port *port)
  920. {
  921. bna_port_rx_stop(port);
  922. }
  923. static void
  924. bna_port_sm_rx_stop_wait(struct bna_port *port,
  925. enum bna_port_event event)
  926. {
  927. switch (event) {
  928. case PORT_E_FAIL:
  929. bfa_fsm_set_state(port, bna_port_sm_stopped);
  930. bna_port_chld_fail(port);
  931. break;
  932. case PORT_E_CHLD_STOPPED:
  933. bfa_fsm_set_state(port, bna_port_sm_mtu_cfg_wait);
  934. break;
  935. default:
  936. bfa_sm_fault(event);
  937. }
  938. }
  939. static void
  940. bna_port_sm_mtu_cfg_wait_entry(struct bna_port *port)
  941. {
  942. bna_fw_mtu_set(port);
  943. }
  944. static void
  945. bna_port_sm_mtu_cfg_wait(struct bna_port *port, enum bna_port_event event)
  946. {
  947. switch (event) {
  948. case PORT_E_FAIL:
  949. bfa_fsm_set_state(port, bna_port_sm_stopped);
  950. bna_port_chld_fail(port);
  951. break;
  952. case PORT_E_FWRESP_MTU:
  953. bfa_fsm_set_state(port, bna_port_sm_started);
  954. bna_port_rx_start(port);
  955. break;
  956. default:
  957. bfa_sm_fault(event);
  958. }
  959. }
  960. static void
  961. bna_port_sm_chld_stop_wait_entry(struct bna_port *port)
  962. {
  963. bna_port_chld_stop(port);
  964. }
  965. static void
  966. bna_port_sm_chld_stop_wait(struct bna_port *port,
  967. enum bna_port_event event)
  968. {
  969. switch (event) {
  970. case PORT_E_FAIL:
  971. bfa_fsm_set_state(port, bna_port_sm_stopped);
  972. bna_port_chld_fail(port);
  973. break;
  974. case PORT_E_CHLD_STOPPED:
  975. bfa_fsm_set_state(port, bna_port_sm_stopped);
  976. break;
  977. default:
  978. bfa_sm_fault(event);
  979. }
  980. }
  981. static void
  982. bna_fw_pause_set(struct bna_port *port)
  983. {
  984. struct bfi_ll_set_pause_req ll_req;
  985. memset(&ll_req, 0, sizeof(ll_req));
  986. ll_req.mh.msg_class = BFI_MC_LL;
  987. ll_req.mh.msg_id = BFI_LL_H2I_SET_PAUSE_REQ;
  988. ll_req.mh.mtag.h2i.lpu_id = 0;
  989. ll_req.tx_pause = port->pause_config.tx_pause;
  990. ll_req.rx_pause = port->pause_config.rx_pause;
  991. bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
  992. bna_fw_cb_pause_set, port);
  993. bna_mbox_send(port->bna, &port->mbox_qe);
  994. }
  995. static void
  996. bna_fw_cb_pause_set(void *arg, int status)
  997. {
  998. struct bna_port *port = (struct bna_port *)arg;
  999. bfa_q_qe_init(&port->mbox_qe.qe);
  1000. bfa_fsm_send_event(port, PORT_E_FWRESP_PAUSE);
  1001. }
  1002. void
  1003. bna_fw_mtu_set(struct bna_port *port)
  1004. {
  1005. struct bfi_ll_mtu_info_req ll_req;
  1006. bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0);
  1007. ll_req.mtu = htons((u16)port->mtu);
  1008. bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
  1009. bna_fw_cb_mtu_set, port);
  1010. bna_mbox_send(port->bna, &port->mbox_qe);
  1011. }
  1012. void
  1013. bna_fw_cb_mtu_set(void *arg, int status)
  1014. {
  1015. struct bna_port *port = (struct bna_port *)arg;
  1016. bfa_q_qe_init(&port->mbox_qe.qe);
  1017. bfa_fsm_send_event(port, PORT_E_FWRESP_MTU);
  1018. }
  1019. static void
  1020. bna_port_cb_chld_stopped(void *arg)
  1021. {
  1022. struct bna_port *port = (struct bna_port *)arg;
  1023. bfa_fsm_send_event(port, PORT_E_CHLD_STOPPED);
  1024. }
  1025. static void
  1026. bna_port_init(struct bna_port *port, struct bna *bna)
  1027. {
  1028. port->bna = bna;
  1029. port->flags = 0;
  1030. port->mtu = 0;
  1031. port->type = BNA_PORT_T_REGULAR;
  1032. port->link_cbfn = bnad_cb_port_link_status;
  1033. port->chld_stop_wc.wc_resume = bna_port_cb_chld_stopped;
  1034. port->chld_stop_wc.wc_cbarg = port;
  1035. port->chld_stop_wc.wc_count = 0;
  1036. port->stop_cbfn = NULL;
  1037. port->stop_cbarg = NULL;
  1038. port->pause_cbfn = NULL;
  1039. port->mtu_cbfn = NULL;
  1040. bfa_q_qe_init(&port->mbox_qe.qe);
  1041. bfa_fsm_set_state(port, bna_port_sm_stopped);
  1042. bna_llport_init(&port->llport, bna);
  1043. }
  1044. static void
  1045. bna_port_uninit(struct bna_port *port)
  1046. {
  1047. bna_llport_uninit(&port->llport);
  1048. port->flags = 0;
  1049. port->bna = NULL;
  1050. }
  1051. static int
  1052. bna_port_state_get(struct bna_port *port)
  1053. {
  1054. return bfa_sm_to_state(port_sm_table, port->fsm);
  1055. }
  1056. static void
  1057. bna_port_start(struct bna_port *port)
  1058. {
  1059. port->flags |= BNA_PORT_F_DEVICE_READY;
  1060. if (port->flags & BNA_PORT_F_ENABLED)
  1061. bfa_fsm_send_event(port, PORT_E_START);
  1062. }
  1063. static void
  1064. bna_port_stop(struct bna_port *port)
  1065. {
  1066. port->stop_cbfn = bna_device_cb_port_stopped;
  1067. port->stop_cbarg = &port->bna->device;
  1068. port->flags &= ~BNA_PORT_F_DEVICE_READY;
  1069. bfa_fsm_send_event(port, PORT_E_STOP);
  1070. }
  1071. static void
  1072. bna_port_fail(struct bna_port *port)
  1073. {
  1074. port->flags &= ~BNA_PORT_F_DEVICE_READY;
  1075. bfa_fsm_send_event(port, PORT_E_FAIL);
  1076. }
  1077. void
  1078. bna_port_cb_tx_stopped(struct bna_port *port, enum bna_cb_status status)
  1079. {
  1080. bfa_wc_down(&port->chld_stop_wc);
  1081. }
  1082. void
  1083. bna_port_cb_rx_stopped(struct bna_port *port, enum bna_cb_status status)
  1084. {
  1085. bfa_wc_down(&port->chld_stop_wc);
  1086. }
  1087. int
  1088. bna_port_mtu_get(struct bna_port *port)
  1089. {
  1090. return port->mtu;
  1091. }
  1092. void
  1093. bna_port_enable(struct bna_port *port)
  1094. {
  1095. if (port->fsm != (bfa_sm_t)bna_port_sm_stopped)
  1096. return;
  1097. port->flags |= BNA_PORT_F_ENABLED;
  1098. if (port->flags & BNA_PORT_F_DEVICE_READY)
  1099. bfa_fsm_send_event(port, PORT_E_START);
  1100. }
  1101. void
  1102. bna_port_disable(struct bna_port *port, enum bna_cleanup_type type,
  1103. void (*cbfn)(void *, enum bna_cb_status))
  1104. {
  1105. if (type == BNA_SOFT_CLEANUP) {
  1106. (*cbfn)(port->bna->bnad, BNA_CB_SUCCESS);
  1107. return;
  1108. }
  1109. port->stop_cbfn = cbfn;
  1110. port->stop_cbarg = port->bna->bnad;
  1111. port->flags &= ~BNA_PORT_F_ENABLED;
  1112. bfa_fsm_send_event(port, PORT_E_STOP);
  1113. }
  1114. void
  1115. bna_port_pause_config(struct bna_port *port,
  1116. struct bna_pause_config *pause_config,
  1117. void (*cbfn)(struct bnad *, enum bna_cb_status))
  1118. {
  1119. port->pause_config = *pause_config;
  1120. port->pause_cbfn = cbfn;
  1121. bfa_fsm_send_event(port, PORT_E_PAUSE_CFG);
  1122. }
  1123. void
  1124. bna_port_mtu_set(struct bna_port *port, int mtu,
  1125. void (*cbfn)(struct bnad *, enum bna_cb_status))
  1126. {
  1127. port->mtu = mtu;
  1128. port->mtu_cbfn = cbfn;
  1129. bfa_fsm_send_event(port, PORT_E_MTU_CFG);
  1130. }
  1131. void
  1132. bna_port_mac_get(struct bna_port *port, mac_t *mac)
  1133. {
  1134. *mac = bfa_nw_ioc_get_mac(&port->bna->device.ioc);
  1135. }
  1136. /**
  1137. * DEVICE
  1138. */
  1139. #define enable_mbox_intr(_device)\
  1140. do {\
  1141. u32 intr_status;\
  1142. bna_intr_status_get((_device)->bna, intr_status);\
  1143. bnad_cb_device_enable_mbox_intr((_device)->bna->bnad);\
  1144. bna_mbox_intr_enable((_device)->bna);\
  1145. } while (0)
  1146. #define disable_mbox_intr(_device)\
  1147. do {\
  1148. bna_mbox_intr_disable((_device)->bna);\
  1149. bnad_cb_device_disable_mbox_intr((_device)->bna->bnad);\
  1150. } while (0)
  1151. static const struct bna_chip_regs_offset reg_offset[] =
  1152. {{HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS,
  1153. HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0},
  1154. {HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS,
  1155. HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1},
  1156. {HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS,
  1157. HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2},
  1158. {HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS,
  1159. HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3},
  1160. };
  1161. enum bna_device_event {
  1162. DEVICE_E_ENABLE = 1,
  1163. DEVICE_E_DISABLE = 2,
  1164. DEVICE_E_IOC_READY = 3,
  1165. DEVICE_E_IOC_FAILED = 4,
  1166. DEVICE_E_IOC_DISABLED = 5,
  1167. DEVICE_E_IOC_RESET = 6,
  1168. DEVICE_E_PORT_STOPPED = 7,
  1169. };
  1170. enum bna_device_state {
  1171. BNA_DEVICE_STOPPED = 1,
  1172. BNA_DEVICE_IOC_READY_WAIT = 2,
  1173. BNA_DEVICE_READY = 3,
  1174. BNA_DEVICE_PORT_STOP_WAIT = 4,
  1175. BNA_DEVICE_IOC_DISABLE_WAIT = 5,
  1176. BNA_DEVICE_FAILED = 6
  1177. };
  1178. bfa_fsm_state_decl(bna_device, stopped, struct bna_device,
  1179. enum bna_device_event);
  1180. bfa_fsm_state_decl(bna_device, ioc_ready_wait, struct bna_device,
  1181. enum bna_device_event);
  1182. bfa_fsm_state_decl(bna_device, ready, struct bna_device,
  1183. enum bna_device_event);
  1184. bfa_fsm_state_decl(bna_device, port_stop_wait, struct bna_device,
  1185. enum bna_device_event);
  1186. bfa_fsm_state_decl(bna_device, ioc_disable_wait, struct bna_device,
  1187. enum bna_device_event);
  1188. bfa_fsm_state_decl(bna_device, failed, struct bna_device,
  1189. enum bna_device_event);
  1190. static struct bfa_sm_table device_sm_table[] = {
  1191. {BFA_SM(bna_device_sm_stopped), BNA_DEVICE_STOPPED},
  1192. {BFA_SM(bna_device_sm_ioc_ready_wait), BNA_DEVICE_IOC_READY_WAIT},
  1193. {BFA_SM(bna_device_sm_ready), BNA_DEVICE_READY},
  1194. {BFA_SM(bna_device_sm_port_stop_wait), BNA_DEVICE_PORT_STOP_WAIT},
  1195. {BFA_SM(bna_device_sm_ioc_disable_wait), BNA_DEVICE_IOC_DISABLE_WAIT},
  1196. {BFA_SM(bna_device_sm_failed), BNA_DEVICE_FAILED},
  1197. };
  1198. static void
  1199. bna_device_sm_stopped_entry(struct bna_device *device)
  1200. {
  1201. if (device->stop_cbfn)
  1202. device->stop_cbfn(device->stop_cbarg, BNA_CB_SUCCESS);
  1203. device->stop_cbfn = NULL;
  1204. device->stop_cbarg = NULL;
  1205. }
  1206. static void
  1207. bna_device_sm_stopped(struct bna_device *device,
  1208. enum bna_device_event event)
  1209. {
  1210. switch (event) {
  1211. case DEVICE_E_ENABLE:
  1212. if (device->intr_type == BNA_INTR_T_MSIX)
  1213. bna_mbox_msix_idx_set(device);
  1214. bfa_nw_ioc_enable(&device->ioc);
  1215. bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
  1216. break;
  1217. case DEVICE_E_DISABLE:
  1218. bfa_fsm_set_state(device, bna_device_sm_stopped);
  1219. break;
  1220. case DEVICE_E_IOC_RESET:
  1221. enable_mbox_intr(device);
  1222. break;
  1223. case DEVICE_E_IOC_FAILED:
  1224. bfa_fsm_set_state(device, bna_device_sm_failed);
  1225. break;
  1226. default:
  1227. bfa_sm_fault(event);
  1228. }
  1229. }
  1230. static void
  1231. bna_device_sm_ioc_ready_wait_entry(struct bna_device *device)
  1232. {
  1233. /**
  1234. * Do not call bfa_ioc_enable() here. It must be called in the
  1235. * previous state due to failed -> ioc_ready_wait transition.
  1236. */
  1237. }
  1238. static void
  1239. bna_device_sm_ioc_ready_wait(struct bna_device *device,
  1240. enum bna_device_event event)
  1241. {
  1242. switch (event) {
  1243. case DEVICE_E_DISABLE:
  1244. if (device->ready_cbfn)
  1245. device->ready_cbfn(device->ready_cbarg,
  1246. BNA_CB_INTERRUPT);
  1247. device->ready_cbfn = NULL;
  1248. device->ready_cbarg = NULL;
  1249. bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
  1250. break;
  1251. case DEVICE_E_IOC_READY:
  1252. bfa_fsm_set_state(device, bna_device_sm_ready);
  1253. break;
  1254. case DEVICE_E_IOC_FAILED:
  1255. bfa_fsm_set_state(device, bna_device_sm_failed);
  1256. break;
  1257. case DEVICE_E_IOC_RESET:
  1258. enable_mbox_intr(device);
  1259. break;
  1260. default:
  1261. bfa_sm_fault(event);
  1262. }
  1263. }
  1264. static void
  1265. bna_device_sm_ready_entry(struct bna_device *device)
  1266. {
  1267. bna_mbox_mod_start(&device->bna->mbox_mod);
  1268. bna_port_start(&device->bna->port);
  1269. if (device->ready_cbfn)
  1270. device->ready_cbfn(device->ready_cbarg,
  1271. BNA_CB_SUCCESS);
  1272. device->ready_cbfn = NULL;
  1273. device->ready_cbarg = NULL;
  1274. }
  1275. static void
  1276. bna_device_sm_ready(struct bna_device *device, enum bna_device_event event)
  1277. {
  1278. switch (event) {
  1279. case DEVICE_E_DISABLE:
  1280. bfa_fsm_set_state(device, bna_device_sm_port_stop_wait);
  1281. break;
  1282. case DEVICE_E_IOC_FAILED:
  1283. bfa_fsm_set_state(device, bna_device_sm_failed);
  1284. break;
  1285. default:
  1286. bfa_sm_fault(event);
  1287. }
  1288. }
  1289. static void
  1290. bna_device_sm_port_stop_wait_entry(struct bna_device *device)
  1291. {
  1292. bna_port_stop(&device->bna->port);
  1293. }
  1294. static void
  1295. bna_device_sm_port_stop_wait(struct bna_device *device,
  1296. enum bna_device_event event)
  1297. {
  1298. switch (event) {
  1299. case DEVICE_E_PORT_STOPPED:
  1300. bna_mbox_mod_stop(&device->bna->mbox_mod);
  1301. bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
  1302. break;
  1303. case DEVICE_E_IOC_FAILED:
  1304. disable_mbox_intr(device);
  1305. bna_port_fail(&device->bna->port);
  1306. break;
  1307. default:
  1308. bfa_sm_fault(event);
  1309. }
  1310. }
  1311. static void
  1312. bna_device_sm_ioc_disable_wait_entry(struct bna_device *device)
  1313. {
  1314. bfa_nw_ioc_disable(&device->ioc);
  1315. }
  1316. static void
  1317. bna_device_sm_ioc_disable_wait(struct bna_device *device,
  1318. enum bna_device_event event)
  1319. {
  1320. switch (event) {
  1321. case DEVICE_E_IOC_DISABLED:
  1322. disable_mbox_intr(device);
  1323. bfa_fsm_set_state(device, bna_device_sm_stopped);
  1324. break;
  1325. default:
  1326. bfa_sm_fault(event);
  1327. }
  1328. }
  1329. static void
  1330. bna_device_sm_failed_entry(struct bna_device *device)
  1331. {
  1332. disable_mbox_intr(device);
  1333. bna_port_fail(&device->bna->port);
  1334. bna_mbox_mod_stop(&device->bna->mbox_mod);
  1335. if (device->ready_cbfn)
  1336. device->ready_cbfn(device->ready_cbarg,
  1337. BNA_CB_FAIL);
  1338. device->ready_cbfn = NULL;
  1339. device->ready_cbarg = NULL;
  1340. }
  1341. static void
  1342. bna_device_sm_failed(struct bna_device *device,
  1343. enum bna_device_event event)
  1344. {
  1345. switch (event) {
  1346. case DEVICE_E_DISABLE:
  1347. bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
  1348. break;
  1349. case DEVICE_E_IOC_RESET:
  1350. enable_mbox_intr(device);
  1351. bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
  1352. break;
  1353. default:
  1354. bfa_sm_fault(event);
  1355. }
  1356. }
  1357. /* IOC callback functions */
  1358. static void
  1359. bna_device_cb_iocll_ready(void *dev, enum bfa_status error)
  1360. {
  1361. struct bna_device *device = (struct bna_device *)dev;
  1362. if (error)
  1363. bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
  1364. else
  1365. bfa_fsm_send_event(device, DEVICE_E_IOC_READY);
  1366. }
  1367. static void
  1368. bna_device_cb_iocll_disabled(void *dev)
  1369. {
  1370. struct bna_device *device = (struct bna_device *)dev;
  1371. bfa_fsm_send_event(device, DEVICE_E_IOC_DISABLED);
  1372. }
  1373. static void
  1374. bna_device_cb_iocll_failed(void *dev)
  1375. {
  1376. struct bna_device *device = (struct bna_device *)dev;
  1377. bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
  1378. }
  1379. static void
  1380. bna_device_cb_iocll_reset(void *dev)
  1381. {
  1382. struct bna_device *device = (struct bna_device *)dev;
  1383. bfa_fsm_send_event(device, DEVICE_E_IOC_RESET);
  1384. }
  1385. static struct bfa_ioc_cbfn bfa_iocll_cbfn = {
  1386. bna_device_cb_iocll_ready,
  1387. bna_device_cb_iocll_disabled,
  1388. bna_device_cb_iocll_failed,
  1389. bna_device_cb_iocll_reset
  1390. };
  1391. /* device */
  1392. static void
  1393. bna_adv_device_init(struct bna_device *device, struct bna *bna,
  1394. struct bna_res_info *res_info)
  1395. {
  1396. u8 *kva;
  1397. u64 dma;
  1398. device->bna = bna;
  1399. kva = res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mdl[0].kva;
  1400. /**
  1401. * Attach common modules (Diag, SFP, CEE, Port) and claim respective
  1402. * DMA memory.
  1403. */
  1404. BNA_GET_DMA_ADDR(
  1405. &res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].dma, dma);
  1406. kva = res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].kva;
  1407. bfa_nw_cee_attach(&bna->cee, &device->ioc, bna);
  1408. bfa_nw_cee_mem_claim(&bna->cee, kva, dma);
  1409. kva += bfa_nw_cee_meminfo();
  1410. dma += bfa_nw_cee_meminfo();
  1411. }
  1412. static void
  1413. bna_device_init(struct bna_device *device, struct bna *bna,
  1414. struct bna_res_info *res_info)
  1415. {
  1416. u64 dma;
  1417. device->bna = bna;
  1418. /**
  1419. * Attach IOC and claim:
  1420. * 1. DMA memory for IOC attributes
  1421. * 2. Kernel memory for FW trace
  1422. */
  1423. bfa_nw_ioc_attach(&device->ioc, device, &bfa_iocll_cbfn);
  1424. bfa_nw_ioc_pci_init(&device->ioc, &bna->pcidev, BFI_MC_LL);
  1425. BNA_GET_DMA_ADDR(
  1426. &res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].dma, dma);
  1427. bfa_nw_ioc_mem_claim(&device->ioc,
  1428. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].kva,
  1429. dma);
  1430. bna_adv_device_init(device, bna, res_info);
  1431. /*
  1432. * Initialize mbox_mod only after IOC, so that mbox handler
  1433. * registration goes through
  1434. */
  1435. device->intr_type =
  1436. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type;
  1437. device->vector =
  1438. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.idl[0].vector;
  1439. bna_mbox_mod_init(&bna->mbox_mod, bna);
  1440. device->ready_cbfn = device->stop_cbfn = NULL;
  1441. device->ready_cbarg = device->stop_cbarg = NULL;
  1442. bfa_fsm_set_state(device, bna_device_sm_stopped);
  1443. }
  1444. static void
  1445. bna_device_uninit(struct bna_device *device)
  1446. {
  1447. bna_mbox_mod_uninit(&device->bna->mbox_mod);
  1448. bfa_nw_ioc_detach(&device->ioc);
  1449. device->bna = NULL;
  1450. }
  1451. static void
  1452. bna_device_cb_port_stopped(void *arg, enum bna_cb_status status)
  1453. {
  1454. struct bna_device *device = (struct bna_device *)arg;
  1455. bfa_fsm_send_event(device, DEVICE_E_PORT_STOPPED);
  1456. }
  1457. static int
  1458. bna_device_status_get(struct bna_device *device)
  1459. {
  1460. return device->fsm == (bfa_fsm_t)bna_device_sm_ready;
  1461. }
  1462. void
  1463. bna_device_enable(struct bna_device *device)
  1464. {
  1465. if (device->fsm != (bfa_fsm_t)bna_device_sm_stopped) {
  1466. bnad_cb_device_enabled(device->bna->bnad, BNA_CB_BUSY);
  1467. return;
  1468. }
  1469. device->ready_cbfn = bnad_cb_device_enabled;
  1470. device->ready_cbarg = device->bna->bnad;
  1471. bfa_fsm_send_event(device, DEVICE_E_ENABLE);
  1472. }
  1473. void
  1474. bna_device_disable(struct bna_device *device, enum bna_cleanup_type type)
  1475. {
  1476. if (type == BNA_SOFT_CLEANUP) {
  1477. bnad_cb_device_disabled(device->bna->bnad, BNA_CB_SUCCESS);
  1478. return;
  1479. }
  1480. device->stop_cbfn = bnad_cb_device_disabled;
  1481. device->stop_cbarg = device->bna->bnad;
  1482. bfa_fsm_send_event(device, DEVICE_E_DISABLE);
  1483. }
  1484. static int
  1485. bna_device_state_get(struct bna_device *device)
  1486. {
  1487. return bfa_sm_to_state(device_sm_table, device->fsm);
  1488. }
  1489. const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
  1490. {12, 12},
  1491. {6, 10},
  1492. {5, 10},
  1493. {4, 8},
  1494. {3, 6},
  1495. {3, 6},
  1496. {2, 4},
  1497. {1, 2},
  1498. };
  1499. /* utils */
  1500. static void
  1501. bna_adv_res_req(struct bna_res_info *res_info)
  1502. {
  1503. /* DMA memory for COMMON_MODULE */
  1504. res_info[BNA_RES_MEM_T_COM].res_type = BNA_RES_T_MEM;
  1505. res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  1506. res_info[BNA_RES_MEM_T_COM].res_u.mem_info.num = 1;
  1507. res_info[BNA_RES_MEM_T_COM].res_u.mem_info.len = ALIGN(
  1508. bfa_nw_cee_meminfo(), PAGE_SIZE);
  1509. /* Virtual memory for retreiving fw_trc */
  1510. res_info[BNA_RES_MEM_T_FWTRC].res_type = BNA_RES_T_MEM;
  1511. res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
  1512. res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.num = 0;
  1513. res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.len = 0;
  1514. /* DMA memory for retreiving stats */
  1515. res_info[BNA_RES_MEM_T_STATS].res_type = BNA_RES_T_MEM;
  1516. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  1517. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.num = 1;
  1518. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.len =
  1519. ALIGN(BFI_HW_STATS_SIZE, PAGE_SIZE);
  1520. /* Virtual memory for soft stats */
  1521. res_info[BNA_RES_MEM_T_SWSTATS].res_type = BNA_RES_T_MEM;
  1522. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
  1523. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.num = 1;
  1524. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.len =
  1525. sizeof(struct bna_sw_stats);
  1526. }
  1527. static void
  1528. bna_sw_stats_get(struct bna *bna, struct bna_sw_stats *sw_stats)
  1529. {
  1530. struct bna_tx *tx;
  1531. struct bna_txq *txq;
  1532. struct bna_rx *rx;
  1533. struct bna_rxp *rxp;
  1534. struct list_head *qe;
  1535. struct list_head *txq_qe;
  1536. struct list_head *rxp_qe;
  1537. struct list_head *mac_qe;
  1538. int i;
  1539. sw_stats->device_state = bna_device_state_get(&bna->device);
  1540. sw_stats->port_state = bna_port_state_get(&bna->port);
  1541. sw_stats->port_flags = bna->port.flags;
  1542. sw_stats->llport_state = bna_llport_state_get(&bna->port.llport);
  1543. sw_stats->priority = bna->port.priority;
  1544. i = 0;
  1545. list_for_each(qe, &bna->tx_mod.tx_active_q) {
  1546. tx = (struct bna_tx *)qe;
  1547. sw_stats->tx_stats[i].tx_state = bna_tx_state_get(tx);
  1548. sw_stats->tx_stats[i].tx_flags = tx->flags;
  1549. sw_stats->tx_stats[i].num_txqs = 0;
  1550. sw_stats->tx_stats[i].txq_bmap[0] = 0;
  1551. sw_stats->tx_stats[i].txq_bmap[1] = 0;
  1552. list_for_each(txq_qe, &tx->txq_q) {
  1553. txq = (struct bna_txq *)txq_qe;
  1554. if (txq->txq_id < 32)
  1555. sw_stats->tx_stats[i].txq_bmap[0] |=
  1556. ((u32)1 << txq->txq_id);
  1557. else
  1558. sw_stats->tx_stats[i].txq_bmap[1] |=
  1559. ((u32)
  1560. 1 << (txq->txq_id - 32));
  1561. sw_stats->tx_stats[i].num_txqs++;
  1562. }
  1563. sw_stats->tx_stats[i].txf_id = tx->txf.txf_id;
  1564. i++;
  1565. }
  1566. sw_stats->num_active_tx = i;
  1567. i = 0;
  1568. list_for_each(qe, &bna->rx_mod.rx_active_q) {
  1569. rx = (struct bna_rx *)qe;
  1570. sw_stats->rx_stats[i].rx_state = bna_rx_state_get(rx);
  1571. sw_stats->rx_stats[i].rx_flags = rx->rx_flags;
  1572. sw_stats->rx_stats[i].num_rxps = 0;
  1573. sw_stats->rx_stats[i].num_rxqs = 0;
  1574. sw_stats->rx_stats[i].rxq_bmap[0] = 0;
  1575. sw_stats->rx_stats[i].rxq_bmap[1] = 0;
  1576. sw_stats->rx_stats[i].cq_bmap[0] = 0;
  1577. sw_stats->rx_stats[i].cq_bmap[1] = 0;
  1578. list_for_each(rxp_qe, &rx->rxp_q) {
  1579. rxp = (struct bna_rxp *)rxp_qe;
  1580. sw_stats->rx_stats[i].num_rxqs += 1;
  1581. if (rxp->type == BNA_RXP_SINGLE) {
  1582. if (rxp->rxq.single.only->rxq_id < 32) {
  1583. sw_stats->rx_stats[i].rxq_bmap[0] |=
  1584. ((u32)1 <<
  1585. rxp->rxq.single.only->rxq_id);
  1586. } else {
  1587. sw_stats->rx_stats[i].rxq_bmap[1] |=
  1588. ((u32)1 <<
  1589. (rxp->rxq.single.only->rxq_id - 32));
  1590. }
  1591. } else {
  1592. if (rxp->rxq.slr.large->rxq_id < 32) {
  1593. sw_stats->rx_stats[i].rxq_bmap[0] |=
  1594. ((u32)1 <<
  1595. rxp->rxq.slr.large->rxq_id);
  1596. } else {
  1597. sw_stats->rx_stats[i].rxq_bmap[1] |=
  1598. ((u32)1 <<
  1599. (rxp->rxq.slr.large->rxq_id - 32));
  1600. }
  1601. if (rxp->rxq.slr.small->rxq_id < 32) {
  1602. sw_stats->rx_stats[i].rxq_bmap[0] |=
  1603. ((u32)1 <<
  1604. rxp->rxq.slr.small->rxq_id);
  1605. } else {
  1606. sw_stats->rx_stats[i].rxq_bmap[1] |=
  1607. ((u32)1 <<
  1608. (rxp->rxq.slr.small->rxq_id - 32));
  1609. }
  1610. sw_stats->rx_stats[i].num_rxqs += 1;
  1611. }
  1612. if (rxp->cq.cq_id < 32)
  1613. sw_stats->rx_stats[i].cq_bmap[0] |=
  1614. (1 << rxp->cq.cq_id);
  1615. else
  1616. sw_stats->rx_stats[i].cq_bmap[1] |=
  1617. (1 << (rxp->cq.cq_id - 32));
  1618. sw_stats->rx_stats[i].num_rxps++;
  1619. }
  1620. sw_stats->rx_stats[i].rxf_id = rx->rxf.rxf_id;
  1621. sw_stats->rx_stats[i].rxf_state = bna_rxf_state_get(&rx->rxf);
  1622. sw_stats->rx_stats[i].rxf_oper_state = rx->rxf.rxf_oper_state;
  1623. sw_stats->rx_stats[i].num_active_ucast = 0;
  1624. if (rx->rxf.ucast_active_mac)
  1625. sw_stats->rx_stats[i].num_active_ucast++;
  1626. list_for_each(mac_qe, &rx->rxf.ucast_active_q)
  1627. sw_stats->rx_stats[i].num_active_ucast++;
  1628. sw_stats->rx_stats[i].num_active_mcast = 0;
  1629. list_for_each(mac_qe, &rx->rxf.mcast_active_q)
  1630. sw_stats->rx_stats[i].num_active_mcast++;
  1631. sw_stats->rx_stats[i].rxmode_active = rx->rxf.rxmode_active;
  1632. sw_stats->rx_stats[i].vlan_filter_status =
  1633. rx->rxf.vlan_filter_status;
  1634. memcpy(sw_stats->rx_stats[i].vlan_filter_table,
  1635. rx->rxf.vlan_filter_table,
  1636. sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32));
  1637. sw_stats->rx_stats[i].rss_status = rx->rxf.rss_status;
  1638. sw_stats->rx_stats[i].hds_status = rx->rxf.hds_status;
  1639. i++;
  1640. }
  1641. sw_stats->num_active_rx = i;
  1642. }
  1643. static void
  1644. bna_fw_cb_stats_get(void *arg, int status)
  1645. {
  1646. struct bna *bna = (struct bna *)arg;
  1647. u64 *p_stats;
  1648. int i, count;
  1649. int rxf_count, txf_count;
  1650. u64 rxf_bmap, txf_bmap;
  1651. bfa_q_qe_init(&bna->mbox_qe.qe);
  1652. if (status == 0) {
  1653. p_stats = (u64 *)bna->stats.hw_stats;
  1654. count = sizeof(struct bfi_ll_stats) / sizeof(u64);
  1655. for (i = 0; i < count; i++)
  1656. p_stats[i] = cpu_to_be64(p_stats[i]);
  1657. rxf_count = 0;
  1658. rxf_bmap = (u64)bna->stats.rxf_bmap[0] |
  1659. ((u64)bna->stats.rxf_bmap[1] << 32);
  1660. for (i = 0; i < BFI_LL_RXF_ID_MAX; i++)
  1661. if (rxf_bmap & ((u64)1 << i))
  1662. rxf_count++;
  1663. txf_count = 0;
  1664. txf_bmap = (u64)bna->stats.txf_bmap[0] |
  1665. ((u64)bna->stats.txf_bmap[1] << 32);
  1666. for (i = 0; i < BFI_LL_TXF_ID_MAX; i++)
  1667. if (txf_bmap & ((u64)1 << i))
  1668. txf_count++;
  1669. p_stats = (u64 *)&bna->stats.hw_stats->rxf_stats[0] +
  1670. ((rxf_count * sizeof(struct bfi_ll_stats_rxf) +
  1671. txf_count * sizeof(struct bfi_ll_stats_txf))/
  1672. sizeof(u64));
  1673. /* Populate the TXF stats from the firmware DMAed copy */
  1674. for (i = (BFI_LL_TXF_ID_MAX - 1); i >= 0; i--)
  1675. if (txf_bmap & ((u64)1 << i)) {
  1676. p_stats -= sizeof(struct bfi_ll_stats_txf)/
  1677. sizeof(u64);
  1678. memcpy(&bna->stats.hw_stats->txf_stats[i],
  1679. p_stats,
  1680. sizeof(struct bfi_ll_stats_txf));
  1681. }
  1682. /* Populate the RXF stats from the firmware DMAed copy */
  1683. for (i = (BFI_LL_RXF_ID_MAX - 1); i >= 0; i--)
  1684. if (rxf_bmap & ((u64)1 << i)) {
  1685. p_stats -= sizeof(struct bfi_ll_stats_rxf)/
  1686. sizeof(u64);
  1687. memcpy(&bna->stats.hw_stats->rxf_stats[i],
  1688. p_stats,
  1689. sizeof(struct bfi_ll_stats_rxf));
  1690. }
  1691. bna_sw_stats_get(bna, bna->stats.sw_stats);
  1692. bnad_cb_stats_get(bna->bnad, BNA_CB_SUCCESS, &bna->stats);
  1693. } else
  1694. bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
  1695. }
  1696. static void
  1697. bna_fw_stats_get(struct bna *bna)
  1698. {
  1699. struct bfi_ll_stats_req ll_req;
  1700. bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0);
  1701. ll_req.stats_mask = htons(BFI_LL_STATS_ALL);
  1702. ll_req.rxf_id_mask[0] = htonl(bna->rx_mod.rxf_bmap[0]);
  1703. ll_req.rxf_id_mask[1] = htonl(bna->rx_mod.rxf_bmap[1]);
  1704. ll_req.txf_id_mask[0] = htonl(bna->tx_mod.txf_bmap[0]);
  1705. ll_req.txf_id_mask[1] = htonl(bna->tx_mod.txf_bmap[1]);
  1706. ll_req.host_buffer.a32.addr_hi = bna->hw_stats_dma.msb;
  1707. ll_req.host_buffer.a32.addr_lo = bna->hw_stats_dma.lsb;
  1708. bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req),
  1709. bna_fw_cb_stats_get, bna);
  1710. bna_mbox_send(bna, &bna->mbox_qe);
  1711. bna->stats.rxf_bmap[0] = bna->rx_mod.rxf_bmap[0];
  1712. bna->stats.rxf_bmap[1] = bna->rx_mod.rxf_bmap[1];
  1713. bna->stats.txf_bmap[0] = bna->tx_mod.txf_bmap[0];
  1714. bna->stats.txf_bmap[1] = bna->tx_mod.txf_bmap[1];
  1715. }
  1716. void
  1717. bna_stats_get(struct bna *bna)
  1718. {
  1719. if (bna_device_status_get(&bna->device))
  1720. bna_fw_stats_get(bna);
  1721. else
  1722. bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
  1723. }
  1724. /* IB */
  1725. static void
  1726. bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
  1727. {
  1728. ib->ib_config.coalescing_timeo = coalescing_timeo;
  1729. if (ib->start_count)
  1730. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  1731. (u32)ib->ib_config.coalescing_timeo, 0);
  1732. }
  1733. /* RxF */
  1734. void
  1735. bna_rxf_adv_init(struct bna_rxf *rxf,
  1736. struct bna_rx *rx,
  1737. struct bna_rx_config *q_config)
  1738. {
  1739. switch (q_config->rxp_type) {
  1740. case BNA_RXP_SINGLE:
  1741. /* No-op */
  1742. break;
  1743. case BNA_RXP_SLR:
  1744. rxf->ctrl_flags |= BNA_RXF_CF_SM_LG_RXQ;
  1745. break;
  1746. case BNA_RXP_HDS:
  1747. rxf->hds_cfg.hdr_type = q_config->hds_config.hdr_type;
  1748. rxf->hds_cfg.header_size =
  1749. q_config->hds_config.header_size;
  1750. rxf->forced_offset = 0;
  1751. break;
  1752. default:
  1753. break;
  1754. }
  1755. if (q_config->rss_status == BNA_STATUS_T_ENABLED) {
  1756. rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
  1757. rxf->rss_cfg.hash_type = q_config->rss_config.hash_type;
  1758. rxf->rss_cfg.hash_mask = q_config->rss_config.hash_mask;
  1759. memcpy(&rxf->rss_cfg.toeplitz_hash_key[0],
  1760. &q_config->rss_config.toeplitz_hash_key[0],
  1761. sizeof(rxf->rss_cfg.toeplitz_hash_key));
  1762. }
  1763. }
  1764. static void
  1765. rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status)
  1766. {
  1767. struct bfi_ll_rxf_req req;
  1768. bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
  1769. req.rxf_id = rxf->rxf_id;
  1770. req.enable = status;
  1771. bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
  1772. rxf_cb_cam_fltr_mbox_cmd, rxf);
  1773. bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
  1774. }
  1775. int
  1776. rxf_process_packet_filter_ucast(struct bna_rxf *rxf)
  1777. {
  1778. struct bna_mac *mac = NULL;
  1779. struct list_head *qe;
  1780. /* Add additional MAC entries */
  1781. if (!list_empty(&rxf->ucast_pending_add_q)) {
  1782. bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
  1783. bfa_q_qe_init(qe);
  1784. mac = (struct bna_mac *)qe;
  1785. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_ADD_REQ, mac);
  1786. list_add_tail(&mac->qe, &rxf->ucast_active_q);
  1787. return 1;
  1788. }
  1789. /* Delete MAC addresses previousely added */
  1790. if (!list_empty(&rxf->ucast_pending_del_q)) {
  1791. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  1792. bfa_q_qe_init(qe);
  1793. mac = (struct bna_mac *)qe;
  1794. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
  1795. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  1796. return 1;
  1797. }
  1798. return 0;
  1799. }
  1800. int
  1801. rxf_process_packet_filter_promisc(struct bna_rxf *rxf)
  1802. {
  1803. struct bna *bna = rxf->rx->bna;
  1804. /* Enable/disable promiscuous mode */
  1805. if (is_promisc_enable(rxf->rxmode_pending,
  1806. rxf->rxmode_pending_bitmask)) {
  1807. /* move promisc configuration from pending -> active */
  1808. promisc_inactive(rxf->rxmode_pending,
  1809. rxf->rxmode_pending_bitmask);
  1810. rxf->rxmode_active |= BNA_RXMODE_PROMISC;
  1811. /* Disable VLAN filter to allow all VLANs */
  1812. __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
  1813. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1814. BNA_STATUS_T_ENABLED);
  1815. return 1;
  1816. } else if (is_promisc_disable(rxf->rxmode_pending,
  1817. rxf->rxmode_pending_bitmask)) {
  1818. /* move promisc configuration from pending -> active */
  1819. promisc_inactive(rxf->rxmode_pending,
  1820. rxf->rxmode_pending_bitmask);
  1821. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1822. bna->rxf_promisc_id = BFI_MAX_RXF;
  1823. /* Revert VLAN filter */
  1824. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1825. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1826. BNA_STATUS_T_DISABLED);
  1827. return 1;
  1828. }
  1829. return 0;
  1830. }
  1831. int
  1832. rxf_process_packet_filter_allmulti(struct bna_rxf *rxf)
  1833. {
  1834. /* Enable/disable allmulti mode */
  1835. if (is_allmulti_enable(rxf->rxmode_pending,
  1836. rxf->rxmode_pending_bitmask)) {
  1837. /* move allmulti configuration from pending -> active */
  1838. allmulti_inactive(rxf->rxmode_pending,
  1839. rxf->rxmode_pending_bitmask);
  1840. rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
  1841. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1842. BNA_STATUS_T_ENABLED);
  1843. return 1;
  1844. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1845. rxf->rxmode_pending_bitmask)) {
  1846. /* move allmulti configuration from pending -> active */
  1847. allmulti_inactive(rxf->rxmode_pending,
  1848. rxf->rxmode_pending_bitmask);
  1849. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1850. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1851. BNA_STATUS_T_DISABLED);
  1852. return 1;
  1853. }
  1854. return 0;
  1855. }
  1856. int
  1857. rxf_clear_packet_filter_ucast(struct bna_rxf *rxf)
  1858. {
  1859. struct bna_mac *mac = NULL;
  1860. struct list_head *qe;
  1861. /* 1. delete pending ucast entries */
  1862. if (!list_empty(&rxf->ucast_pending_del_q)) {
  1863. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  1864. bfa_q_qe_init(qe);
  1865. mac = (struct bna_mac *)qe;
  1866. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
  1867. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  1868. return 1;
  1869. }
  1870. /* 2. clear active ucast entries; move them to pending_add_q */
  1871. if (!list_empty(&rxf->ucast_active_q)) {
  1872. bfa_q_deq(&rxf->ucast_active_q, &qe);
  1873. bfa_q_qe_init(qe);
  1874. mac = (struct bna_mac *)qe;
  1875. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
  1876. list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
  1877. return 1;
  1878. }
  1879. return 0;
  1880. }
  1881. int
  1882. rxf_clear_packet_filter_promisc(struct bna_rxf *rxf)
  1883. {
  1884. struct bna *bna = rxf->rx->bna;
  1885. /* 6. Execute pending promisc mode disable command */
  1886. if (is_promisc_disable(rxf->rxmode_pending,
  1887. rxf->rxmode_pending_bitmask)) {
  1888. /* move promisc configuration from pending -> active */
  1889. promisc_inactive(rxf->rxmode_pending,
  1890. rxf->rxmode_pending_bitmask);
  1891. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1892. bna->rxf_promisc_id = BFI_MAX_RXF;
  1893. /* Revert VLAN filter */
  1894. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1895. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1896. BNA_STATUS_T_DISABLED);
  1897. return 1;
  1898. }
  1899. /* 7. Clear active promisc mode; move it to pending enable */
  1900. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1901. /* move promisc configuration from active -> pending */
  1902. promisc_enable(rxf->rxmode_pending,
  1903. rxf->rxmode_pending_bitmask);
  1904. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1905. /* Revert VLAN filter */
  1906. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1907. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1908. BNA_STATUS_T_DISABLED);
  1909. return 1;
  1910. }
  1911. return 0;
  1912. }
  1913. int
  1914. rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf)
  1915. {
  1916. /* 10. Execute pending allmulti mode disable command */
  1917. if (is_allmulti_disable(rxf->rxmode_pending,
  1918. rxf->rxmode_pending_bitmask)) {
  1919. /* move allmulti configuration from pending -> active */
  1920. allmulti_inactive(rxf->rxmode_pending,
  1921. rxf->rxmode_pending_bitmask);
  1922. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1923. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1924. BNA_STATUS_T_DISABLED);
  1925. return 1;
  1926. }
  1927. /* 11. Clear active allmulti mode; move it to pending enable */
  1928. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1929. /* move allmulti configuration from active -> pending */
  1930. allmulti_enable(rxf->rxmode_pending,
  1931. rxf->rxmode_pending_bitmask);
  1932. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1933. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1934. BNA_STATUS_T_DISABLED);
  1935. return 1;
  1936. }
  1937. return 0;
  1938. }
  1939. void
  1940. rxf_reset_packet_filter_ucast(struct bna_rxf *rxf)
  1941. {
  1942. struct list_head *qe;
  1943. struct bna_mac *mac;
  1944. /* 1. Move active ucast entries to pending_add_q */
  1945. while (!list_empty(&rxf->ucast_active_q)) {
  1946. bfa_q_deq(&rxf->ucast_active_q, &qe);
  1947. bfa_q_qe_init(qe);
  1948. list_add_tail(qe, &rxf->ucast_pending_add_q);
  1949. }
  1950. /* 2. Throw away delete pending ucast entries */
  1951. while (!list_empty(&rxf->ucast_pending_del_q)) {
  1952. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  1953. bfa_q_qe_init(qe);
  1954. mac = (struct bna_mac *)qe;
  1955. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  1956. }
  1957. }
  1958. void
  1959. rxf_reset_packet_filter_promisc(struct bna_rxf *rxf)
  1960. {
  1961. struct bna *bna = rxf->rx->bna;
  1962. /* 6. Clear pending promisc mode disable */
  1963. if (is_promisc_disable(rxf->rxmode_pending,
  1964. rxf->rxmode_pending_bitmask)) {
  1965. promisc_inactive(rxf->rxmode_pending,
  1966. rxf->rxmode_pending_bitmask);
  1967. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1968. bna->rxf_promisc_id = BFI_MAX_RXF;
  1969. }
  1970. /* 7. Move promisc mode config from active -> pending */
  1971. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1972. promisc_enable(rxf->rxmode_pending,
  1973. rxf->rxmode_pending_bitmask);
  1974. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1975. }
  1976. }
  1977. void
  1978. rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf)
  1979. {
  1980. /* 10. Clear pending allmulti mode disable */
  1981. if (is_allmulti_disable(rxf->rxmode_pending,
  1982. rxf->rxmode_pending_bitmask)) {
  1983. allmulti_inactive(rxf->rxmode_pending,
  1984. rxf->rxmode_pending_bitmask);
  1985. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1986. }
  1987. /* 11. Move allmulti mode config from active -> pending */
  1988. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1989. allmulti_enable(rxf->rxmode_pending,
  1990. rxf->rxmode_pending_bitmask);
  1991. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1992. }
  1993. }
  1994. /**
  1995. * Should only be called by bna_rxf_mode_set.
  1996. * Helps deciding if h/w configuration is needed or not.
  1997. * Returns:
  1998. * 0 = no h/w change
  1999. * 1 = need h/w change
  2000. */
  2001. static int
  2002. rxf_promisc_enable(struct bna_rxf *rxf)
  2003. {
  2004. struct bna *bna = rxf->rx->bna;
  2005. int ret = 0;
  2006. /* There can not be any pending disable command */
  2007. /* Do nothing if pending enable or already enabled */
  2008. if (is_promisc_enable(rxf->rxmode_pending,
  2009. rxf->rxmode_pending_bitmask) ||
  2010. (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
  2011. /* Schedule enable */
  2012. } else {
  2013. /* Promisc mode should not be active in the system */
  2014. promisc_enable(rxf->rxmode_pending,
  2015. rxf->rxmode_pending_bitmask);
  2016. bna->rxf_promisc_id = rxf->rxf_id;
  2017. ret = 1;
  2018. }
  2019. return ret;
  2020. }
  2021. /**
  2022. * Should only be called by bna_rxf_mode_set.
  2023. * Helps deciding if h/w configuration is needed or not.
  2024. * Returns:
  2025. * 0 = no h/w change
  2026. * 1 = need h/w change
  2027. */
  2028. static int
  2029. rxf_promisc_disable(struct bna_rxf *rxf)
  2030. {
  2031. struct bna *bna = rxf->rx->bna;
  2032. int ret = 0;
  2033. /* There can not be any pending disable */
  2034. /* Turn off pending enable command , if any */
  2035. if (is_promisc_enable(rxf->rxmode_pending,
  2036. rxf->rxmode_pending_bitmask)) {
  2037. /* Promisc mode should not be active */
  2038. /* system promisc state should be pending */
  2039. promisc_inactive(rxf->rxmode_pending,
  2040. rxf->rxmode_pending_bitmask);
  2041. /* Remove the promisc state from the system */
  2042. bna->rxf_promisc_id = BFI_MAX_RXF;
  2043. /* Schedule disable */
  2044. } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  2045. /* Promisc mode should be active in the system */
  2046. promisc_disable(rxf->rxmode_pending,
  2047. rxf->rxmode_pending_bitmask);
  2048. ret = 1;
  2049. /* Do nothing if already disabled */
  2050. } else {
  2051. }
  2052. return ret;
  2053. }
  2054. /**
  2055. * Should only be called by bna_rxf_mode_set.
  2056. * Helps deciding if h/w configuration is needed or not.
  2057. * Returns:
  2058. * 0 = no h/w change
  2059. * 1 = need h/w change
  2060. */
  2061. static int
  2062. rxf_allmulti_enable(struct bna_rxf *rxf)
  2063. {
  2064. int ret = 0;
  2065. /* There can not be any pending disable command */
  2066. /* Do nothing if pending enable or already enabled */
  2067. if (is_allmulti_enable(rxf->rxmode_pending,
  2068. rxf->rxmode_pending_bitmask) ||
  2069. (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
  2070. /* Schedule enable */
  2071. } else {
  2072. allmulti_enable(rxf->rxmode_pending,
  2073. rxf->rxmode_pending_bitmask);
  2074. ret = 1;
  2075. }
  2076. return ret;
  2077. }
  2078. /**
  2079. * Should only be called by bna_rxf_mode_set.
  2080. * Helps deciding if h/w configuration is needed or not.
  2081. * Returns:
  2082. * 0 = no h/w change
  2083. * 1 = need h/w change
  2084. */
  2085. static int
  2086. rxf_allmulti_disable(struct bna_rxf *rxf)
  2087. {
  2088. int ret = 0;
  2089. /* There can not be any pending disable */
  2090. /* Turn off pending enable command , if any */
  2091. if (is_allmulti_enable(rxf->rxmode_pending,
  2092. rxf->rxmode_pending_bitmask)) {
  2093. /* Allmulti mode should not be active */
  2094. allmulti_inactive(rxf->rxmode_pending,
  2095. rxf->rxmode_pending_bitmask);
  2096. /* Schedule disable */
  2097. } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  2098. allmulti_disable(rxf->rxmode_pending,
  2099. rxf->rxmode_pending_bitmask);
  2100. ret = 1;
  2101. }
  2102. return ret;
  2103. }
  2104. /* RxF <- bnad */
  2105. enum bna_cb_status
  2106. bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
  2107. enum bna_rxmode bitmask,
  2108. void (*cbfn)(struct bnad *, struct bna_rx *,
  2109. enum bna_cb_status))
  2110. {
  2111. struct bna_rxf *rxf = &rx->rxf;
  2112. int need_hw_config = 0;
  2113. /* Process the commands */
  2114. if (is_promisc_enable(new_mode, bitmask)) {
  2115. /* If promisc mode is already enabled elsewhere in the system */
  2116. if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) &&
  2117. (rx->bna->rxf_promisc_id != rxf->rxf_id))
  2118. goto err_return;
  2119. if (rxf_promisc_enable(rxf))
  2120. need_hw_config = 1;
  2121. } else if (is_promisc_disable(new_mode, bitmask)) {
  2122. if (rxf_promisc_disable(rxf))
  2123. need_hw_config = 1;
  2124. }
  2125. if (is_allmulti_enable(new_mode, bitmask)) {
  2126. if (rxf_allmulti_enable(rxf))
  2127. need_hw_config = 1;
  2128. } else if (is_allmulti_disable(new_mode, bitmask)) {
  2129. if (rxf_allmulti_disable(rxf))
  2130. need_hw_config = 1;
  2131. }
  2132. /* Trigger h/w if needed */
  2133. if (need_hw_config) {
  2134. rxf->cam_fltr_cbfn = cbfn;
  2135. rxf->cam_fltr_cbarg = rx->bna->bnad;
  2136. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  2137. } else if (cbfn)
  2138. (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
  2139. return BNA_CB_SUCCESS;
  2140. err_return:
  2141. return BNA_CB_FAIL;
  2142. }
  2143. void
  2144. /* RxF <- bnad */
  2145. bna_rx_vlanfilter_enable(struct bna_rx *rx)
  2146. {
  2147. struct bna_rxf *rxf = &rx->rxf;
  2148. if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
  2149. rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
  2150. rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
  2151. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  2152. }
  2153. }
  2154. /* Rx */
  2155. /* Rx <- bnad */
  2156. void
  2157. bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
  2158. {
  2159. struct bna_rxp *rxp;
  2160. struct list_head *qe;
  2161. list_for_each(qe, &rx->rxp_q) {
  2162. rxp = (struct bna_rxp *)qe;
  2163. rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
  2164. bna_ib_coalescing_timeo_set(rxp->cq.ib, coalescing_timeo);
  2165. }
  2166. }
  2167. /* Rx <- bnad */
  2168. void
  2169. bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
  2170. {
  2171. int i, j;
  2172. for (i = 0; i < BNA_LOAD_T_MAX; i++)
  2173. for (j = 0; j < BNA_BIAS_T_MAX; j++)
  2174. bna->rx_mod.dim_vector[i][j] = vector[i][j];
  2175. }
  2176. /* Rx <- bnad */
  2177. void
  2178. bna_rx_dim_update(struct bna_ccb *ccb)
  2179. {
  2180. struct bna *bna = ccb->cq->rx->bna;
  2181. u32 load, bias;
  2182. u32 pkt_rt, small_rt, large_rt;
  2183. u8 coalescing_timeo;
  2184. if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
  2185. (ccb->pkt_rate.large_pkt_cnt == 0))
  2186. return;
  2187. /* Arrive at preconfigured coalescing timeo value based on pkt rate */
  2188. small_rt = ccb->pkt_rate.small_pkt_cnt;
  2189. large_rt = ccb->pkt_rate.large_pkt_cnt;
  2190. pkt_rt = small_rt + large_rt;
  2191. if (pkt_rt < BNA_PKT_RATE_10K)
  2192. load = BNA_LOAD_T_LOW_4;
  2193. else if (pkt_rt < BNA_PKT_RATE_20K)
  2194. load = BNA_LOAD_T_LOW_3;
  2195. else if (pkt_rt < BNA_PKT_RATE_30K)
  2196. load = BNA_LOAD_T_LOW_2;
  2197. else if (pkt_rt < BNA_PKT_RATE_40K)
  2198. load = BNA_LOAD_T_LOW_1;
  2199. else if (pkt_rt < BNA_PKT_RATE_50K)
  2200. load = BNA_LOAD_T_HIGH_1;
  2201. else if (pkt_rt < BNA_PKT_RATE_60K)
  2202. load = BNA_LOAD_T_HIGH_2;
  2203. else if (pkt_rt < BNA_PKT_RATE_80K)
  2204. load = BNA_LOAD_T_HIGH_3;
  2205. else
  2206. load = BNA_LOAD_T_HIGH_4;
  2207. if (small_rt > (large_rt << 1))
  2208. bias = 0;
  2209. else
  2210. bias = 1;
  2211. ccb->pkt_rate.small_pkt_cnt = 0;
  2212. ccb->pkt_rate.large_pkt_cnt = 0;
  2213. coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
  2214. ccb->rx_coalescing_timeo = coalescing_timeo;
  2215. /* Set it to IB */
  2216. bna_ib_coalescing_timeo_set(ccb->cq->ib, coalescing_timeo);
  2217. }
  2218. /* Tx */
  2219. /* TX <- bnad */
  2220. void
  2221. bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
  2222. {
  2223. struct bna_txq *txq;
  2224. struct list_head *qe;
  2225. list_for_each(qe, &tx->txq_q) {
  2226. txq = (struct bna_txq *)qe;
  2227. bna_ib_coalescing_timeo_set(txq->ib, coalescing_timeo);
  2228. }
  2229. }
  2230. /*
  2231. * Private data
  2232. */
  2233. struct bna_ritseg_pool_cfg {
  2234. u32 pool_size;
  2235. u32 pool_entry_size;
  2236. };
  2237. init_ritseg_pool(ritseg_pool_cfg);
  2238. /*
  2239. * Private functions
  2240. */
  2241. static void
  2242. bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
  2243. struct bna_res_info *res_info)
  2244. {
  2245. int i;
  2246. ucam_mod->ucmac = (struct bna_mac *)
  2247. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
  2248. INIT_LIST_HEAD(&ucam_mod->free_q);
  2249. for (i = 0; i < BFI_MAX_UCMAC; i++) {
  2250. bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
  2251. list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q);
  2252. }
  2253. ucam_mod->bna = bna;
  2254. }
  2255. static void
  2256. bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod)
  2257. {
  2258. struct list_head *qe;
  2259. int i = 0;
  2260. list_for_each(qe, &ucam_mod->free_q)
  2261. i++;
  2262. ucam_mod->bna = NULL;
  2263. }
  2264. static void
  2265. bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
  2266. struct bna_res_info *res_info)
  2267. {
  2268. int i;
  2269. mcam_mod->mcmac = (struct bna_mac *)
  2270. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
  2271. INIT_LIST_HEAD(&mcam_mod->free_q);
  2272. for (i = 0; i < BFI_MAX_MCMAC; i++) {
  2273. bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
  2274. list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q);
  2275. }
  2276. mcam_mod->bna = bna;
  2277. }
  2278. static void
  2279. bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod)
  2280. {
  2281. struct list_head *qe;
  2282. int i = 0;
  2283. list_for_each(qe, &mcam_mod->free_q)
  2284. i++;
  2285. mcam_mod->bna = NULL;
  2286. }
  2287. static void
  2288. bna_rit_mod_init(struct bna_rit_mod *rit_mod,
  2289. struct bna_res_info *res_info)
  2290. {
  2291. int i;
  2292. int j;
  2293. int count;
  2294. int offset;
  2295. rit_mod->rit = (struct bna_rit_entry *)
  2296. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mdl[0].kva;
  2297. rit_mod->rit_segment = (struct bna_rit_segment *)
  2298. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mdl[0].kva;
  2299. count = 0;
  2300. offset = 0;
  2301. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2302. INIT_LIST_HEAD(&rit_mod->rit_seg_pool[i]);
  2303. for (j = 0; j < ritseg_pool_cfg[i].pool_size; j++) {
  2304. bfa_q_qe_init(&rit_mod->rit_segment[count].qe);
  2305. rit_mod->rit_segment[count].max_rit_size =
  2306. ritseg_pool_cfg[i].pool_entry_size;
  2307. rit_mod->rit_segment[count].rit_offset = offset;
  2308. rit_mod->rit_segment[count].rit =
  2309. &rit_mod->rit[offset];
  2310. list_add_tail(&rit_mod->rit_segment[count].qe,
  2311. &rit_mod->rit_seg_pool[i]);
  2312. count++;
  2313. offset += ritseg_pool_cfg[i].pool_entry_size;
  2314. }
  2315. }
  2316. }
  2317. /*
  2318. * Public functions
  2319. */
  2320. /* Called during probe(), before calling bna_init() */
  2321. void
  2322. bna_res_req(struct bna_res_info *res_info)
  2323. {
  2324. bna_adv_res_req(res_info);
  2325. /* DMA memory for retrieving IOC attributes */
  2326. res_info[BNA_RES_MEM_T_ATTR].res_type = BNA_RES_T_MEM;
  2327. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  2328. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.num = 1;
  2329. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.len =
  2330. ALIGN(bfa_nw_ioc_meminfo(), PAGE_SIZE);
  2331. /* DMA memory for index segment of an IB */
  2332. res_info[BNA_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  2333. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  2334. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.len =
  2335. BFI_IBIDX_SIZE * BFI_IBIDX_MAX_SEGSIZE;
  2336. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.num = BFI_MAX_IB;
  2337. /* Virtual memory for IB objects - stored by IB module */
  2338. res_info[BNA_RES_MEM_T_IB_ARRAY].res_type = BNA_RES_T_MEM;
  2339. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mem_type =
  2340. BNA_MEM_T_KVA;
  2341. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.num = 1;
  2342. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.len =
  2343. BFI_MAX_IB * sizeof(struct bna_ib);
  2344. /* Virtual memory for intr objects - stored by IB module */
  2345. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_type = BNA_RES_T_MEM;
  2346. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mem_type =
  2347. BNA_MEM_T_KVA;
  2348. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.num = 1;
  2349. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.len =
  2350. BFI_MAX_IB * sizeof(struct bna_intr);
  2351. /* Virtual memory for idx_seg objects - stored by IB module */
  2352. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_type = BNA_RES_T_MEM;
  2353. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mem_type =
  2354. BNA_MEM_T_KVA;
  2355. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.num = 1;
  2356. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.len =
  2357. BFI_IBIDX_TOTAL_SEGS * sizeof(struct bna_ibidx_seg);
  2358. /* Virtual memory for Tx objects - stored by Tx module */
  2359. res_info[BNA_RES_MEM_T_TX_ARRAY].res_type = BNA_RES_T_MEM;
  2360. res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mem_type =
  2361. BNA_MEM_T_KVA;
  2362. res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.num = 1;
  2363. res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.len =
  2364. BFI_MAX_TXQ * sizeof(struct bna_tx);
  2365. /* Virtual memory for TxQ - stored by Tx module */
  2366. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_type = BNA_RES_T_MEM;
  2367. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mem_type =
  2368. BNA_MEM_T_KVA;
  2369. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.num = 1;
  2370. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.len =
  2371. BFI_MAX_TXQ * sizeof(struct bna_txq);
  2372. /* Virtual memory for Rx objects - stored by Rx module */
  2373. res_info[BNA_RES_MEM_T_RX_ARRAY].res_type = BNA_RES_T_MEM;
  2374. res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mem_type =
  2375. BNA_MEM_T_KVA;
  2376. res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.num = 1;
  2377. res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.len =
  2378. BFI_MAX_RXQ * sizeof(struct bna_rx);
  2379. /* Virtual memory for RxPath - stored by Rx module */
  2380. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_type = BNA_RES_T_MEM;
  2381. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mem_type =
  2382. BNA_MEM_T_KVA;
  2383. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.num = 1;
  2384. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.len =
  2385. BFI_MAX_RXQ * sizeof(struct bna_rxp);
  2386. /* Virtual memory for RxQ - stored by Rx module */
  2387. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_type = BNA_RES_T_MEM;
  2388. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mem_type =
  2389. BNA_MEM_T_KVA;
  2390. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.num = 1;
  2391. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.len =
  2392. BFI_MAX_RXQ * sizeof(struct bna_rxq);
  2393. /* Virtual memory for Unicast MAC address - stored by ucam module */
  2394. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_type = BNA_RES_T_MEM;
  2395. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mem_type =
  2396. BNA_MEM_T_KVA;
  2397. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.num = 1;
  2398. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.len =
  2399. BFI_MAX_UCMAC * sizeof(struct bna_mac);
  2400. /* Virtual memory for Multicast MAC address - stored by mcam module */
  2401. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_type = BNA_RES_T_MEM;
  2402. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mem_type =
  2403. BNA_MEM_T_KVA;
  2404. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.num = 1;
  2405. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.len =
  2406. BFI_MAX_MCMAC * sizeof(struct bna_mac);
  2407. /* Virtual memory for RIT entries */
  2408. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_type = BNA_RES_T_MEM;
  2409. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mem_type =
  2410. BNA_MEM_T_KVA;
  2411. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.num = 1;
  2412. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.len =
  2413. BFI_MAX_RIT_SIZE * sizeof(struct bna_rit_entry);
  2414. /* Virtual memory for RIT segment table */
  2415. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_type = BNA_RES_T_MEM;
  2416. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mem_type =
  2417. BNA_MEM_T_KVA;
  2418. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.num = 1;
  2419. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.len =
  2420. BFI_RIT_TOTAL_SEGS * sizeof(struct bna_rit_segment);
  2421. /* Interrupt resource for mailbox interrupt */
  2422. res_info[BNA_RES_INTR_T_MBOX].res_type = BNA_RES_T_INTR;
  2423. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type =
  2424. BNA_INTR_T_MSIX;
  2425. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.num = 1;
  2426. }
  2427. /* Called during probe() */
  2428. void
  2429. bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev,
  2430. struct bna_res_info *res_info)
  2431. {
  2432. bna->bnad = bnad;
  2433. bna->pcidev = *pcidev;
  2434. bna->stats.hw_stats = (struct bfi_ll_stats *)
  2435. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].kva;
  2436. bna->hw_stats_dma.msb =
  2437. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.msb;
  2438. bna->hw_stats_dma.lsb =
  2439. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.lsb;
  2440. bna->stats.sw_stats = (struct bna_sw_stats *)
  2441. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mdl[0].kva;
  2442. bna->regs.page_addr = bna->pcidev.pci_bar_kva +
  2443. reg_offset[bna->pcidev.pci_func].page_addr;
  2444. bna->regs.fn_int_status = bna->pcidev.pci_bar_kva +
  2445. reg_offset[bna->pcidev.pci_func].fn_int_status;
  2446. bna->regs.fn_int_mask = bna->pcidev.pci_bar_kva +
  2447. reg_offset[bna->pcidev.pci_func].fn_int_mask;
  2448. if (bna->pcidev.pci_func < 3)
  2449. bna->port_num = 0;
  2450. else
  2451. bna->port_num = 1;
  2452. /* Also initializes diag, cee, sfp, phy_port and mbox_mod */
  2453. bna_device_init(&bna->device, bna, res_info);
  2454. bna_port_init(&bna->port, bna);
  2455. bna_tx_mod_init(&bna->tx_mod, bna, res_info);
  2456. bna_rx_mod_init(&bna->rx_mod, bna, res_info);
  2457. bna_ib_mod_init(&bna->ib_mod, bna, res_info);
  2458. bna_rit_mod_init(&bna->rit_mod, res_info);
  2459. bna_ucam_mod_init(&bna->ucam_mod, bna, res_info);
  2460. bna_mcam_mod_init(&bna->mcam_mod, bna, res_info);
  2461. bna->rxf_promisc_id = BFI_MAX_RXF;
  2462. /* Mbox q element for posting stat request to f/w */
  2463. bfa_q_qe_init(&bna->mbox_qe.qe);
  2464. }
  2465. void
  2466. bna_uninit(struct bna *bna)
  2467. {
  2468. bna_mcam_mod_uninit(&bna->mcam_mod);
  2469. bna_ucam_mod_uninit(&bna->ucam_mod);
  2470. bna_ib_mod_uninit(&bna->ib_mod);
  2471. bna_rx_mod_uninit(&bna->rx_mod);
  2472. bna_tx_mod_uninit(&bna->tx_mod);
  2473. bna_port_uninit(&bna->port);
  2474. bna_device_uninit(&bna->device);
  2475. bna->bnad = NULL;
  2476. }
  2477. struct bna_mac *
  2478. bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod)
  2479. {
  2480. struct list_head *qe;
  2481. if (list_empty(&ucam_mod->free_q))
  2482. return NULL;
  2483. bfa_q_deq(&ucam_mod->free_q, &qe);
  2484. return (struct bna_mac *)qe;
  2485. }
  2486. void
  2487. bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod, struct bna_mac *mac)
  2488. {
  2489. list_add_tail(&mac->qe, &ucam_mod->free_q);
  2490. }
  2491. struct bna_mac *
  2492. bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod)
  2493. {
  2494. struct list_head *qe;
  2495. if (list_empty(&mcam_mod->free_q))
  2496. return NULL;
  2497. bfa_q_deq(&mcam_mod->free_q, &qe);
  2498. return (struct bna_mac *)qe;
  2499. }
  2500. void
  2501. bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod, struct bna_mac *mac)
  2502. {
  2503. list_add_tail(&mac->qe, &mcam_mod->free_q);
  2504. }
  2505. /**
  2506. * Note: This should be called in the same locking context as the call to
  2507. * bna_rit_mod_seg_get()
  2508. */
  2509. int
  2510. bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size)
  2511. {
  2512. int i;
  2513. /* Select the pool for seg_size */
  2514. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2515. if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
  2516. break;
  2517. }
  2518. if (i == BFI_RIT_SEG_TOTAL_POOLS)
  2519. return 0;
  2520. if (list_empty(&rit_mod->rit_seg_pool[i]))
  2521. return 0;
  2522. return 1;
  2523. }
  2524. struct bna_rit_segment *
  2525. bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size)
  2526. {
  2527. struct bna_rit_segment *seg;
  2528. struct list_head *qe;
  2529. int i;
  2530. /* Select the pool for seg_size */
  2531. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2532. if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
  2533. break;
  2534. }
  2535. if (i == BFI_RIT_SEG_TOTAL_POOLS)
  2536. return NULL;
  2537. if (list_empty(&rit_mod->rit_seg_pool[i]))
  2538. return NULL;
  2539. bfa_q_deq(&rit_mod->rit_seg_pool[i], &qe);
  2540. seg = (struct bna_rit_segment *)qe;
  2541. bfa_q_qe_init(&seg->qe);
  2542. seg->rit_size = seg_size;
  2543. return seg;
  2544. }
  2545. void
  2546. bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod,
  2547. struct bna_rit_segment *seg)
  2548. {
  2549. int i;
  2550. /* Select the pool for seg->max_rit_size */
  2551. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2552. if (seg->max_rit_size == ritseg_pool_cfg[i].pool_entry_size)
  2553. break;
  2554. }
  2555. seg->rit_size = 0;
  2556. list_add_tail(&seg->qe, &rit_mod->rit_seg_pool[i]);
  2557. }