au1000_eth.c 33 KB

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  1. /*
  2. *
  3. * Alchemy Au1x00 ethernet driver
  4. *
  5. * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6. * Copyright 2002 TimeSys Corp.
  7. * Added ethtool/mii-tool support,
  8. * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9. * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
  10. * or riemer@riemer-nt.de: fixed the link beat detection with
  11. * ioctls (SIOCGMIIPHY)
  12. * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
  13. * converted to use linux-2.6.x's PHY framework
  14. *
  15. * Author: MontaVista Software, Inc.
  16. * ppopov@mvista.com or source@mvista.com
  17. *
  18. * ########################################################################
  19. *
  20. * This program is free software; you can distribute it and/or modify it
  21. * under the terms of the GNU General Public License (Version 2) as
  22. * published by the Free Software Foundation.
  23. *
  24. * This program is distributed in the hope it will be useful, but WITHOUT
  25. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  27. * for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License along
  30. * with this program; if not, write to the Free Software Foundation, Inc.,
  31. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  32. *
  33. * ########################################################################
  34. *
  35. *
  36. */
  37. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  38. #include <linux/capability.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/module.h>
  41. #include <linux/kernel.h>
  42. #include <linux/string.h>
  43. #include <linux/timer.h>
  44. #include <linux/errno.h>
  45. #include <linux/in.h>
  46. #include <linux/ioport.h>
  47. #include <linux/bitops.h>
  48. #include <linux/slab.h>
  49. #include <linux/interrupt.h>
  50. #include <linux/init.h>
  51. #include <linux/netdevice.h>
  52. #include <linux/etherdevice.h>
  53. #include <linux/ethtool.h>
  54. #include <linux/mii.h>
  55. #include <linux/skbuff.h>
  56. #include <linux/delay.h>
  57. #include <linux/crc32.h>
  58. #include <linux/phy.h>
  59. #include <linux/platform_device.h>
  60. #include <linux/cpu.h>
  61. #include <linux/io.h>
  62. #include <asm/mipsregs.h>
  63. #include <asm/irq.h>
  64. #include <asm/processor.h>
  65. #include <au1000.h>
  66. #include <au1xxx_eth.h>
  67. #include <prom.h>
  68. #include "au1000_eth.h"
  69. #ifdef AU1000_ETH_DEBUG
  70. static int au1000_debug = 5;
  71. #else
  72. static int au1000_debug = 3;
  73. #endif
  74. #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
  75. NETIF_MSG_PROBE | \
  76. NETIF_MSG_LINK)
  77. #define DRV_NAME "au1000_eth"
  78. #define DRV_VERSION "1.7"
  79. #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
  80. #define DRV_DESC "Au1xxx on-chip Ethernet driver"
  81. MODULE_AUTHOR(DRV_AUTHOR);
  82. MODULE_DESCRIPTION(DRV_DESC);
  83. MODULE_LICENSE("GPL");
  84. MODULE_VERSION(DRV_VERSION);
  85. /*
  86. * Theory of operation
  87. *
  88. * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
  89. * There are four receive and four transmit descriptors. These
  90. * descriptors are not in memory; rather, they are just a set of
  91. * hardware registers.
  92. *
  93. * Since the Au1000 has a coherent data cache, the receive and
  94. * transmit buffers are allocated from the KSEG0 segment. The
  95. * hardware registers, however, are still mapped at KSEG1 to
  96. * make sure there's no out-of-order writes, and that all writes
  97. * complete immediately.
  98. */
  99. /*
  100. * board-specific configurations
  101. *
  102. * PHY detection algorithm
  103. *
  104. * If phy_static_config is undefined, the PHY setup is
  105. * autodetected:
  106. *
  107. * mii_probe() first searches the current MAC's MII bus for a PHY,
  108. * selecting the first (or last, if phy_search_highest_addr is
  109. * defined) PHY address not already claimed by another netdev.
  110. *
  111. * If nothing was found that way when searching for the 2nd ethernet
  112. * controller's PHY and phy1_search_mac0 is defined, then
  113. * the first MII bus is searched as well for an unclaimed PHY; this is
  114. * needed in case of a dual-PHY accessible only through the MAC0's MII
  115. * bus.
  116. *
  117. * Finally, if no PHY is found, then the corresponding ethernet
  118. * controller is not registered to the network subsystem.
  119. */
  120. /* autodetection defaults: phy1_search_mac0 */
  121. /* static PHY setup
  122. *
  123. * most boards PHY setup should be detectable properly with the
  124. * autodetection algorithm in mii_probe(), but in some cases (e.g. if
  125. * you have a switch attached, or want to use the PHY's interrupt
  126. * notification capabilities) you can provide a static PHY
  127. * configuration here
  128. *
  129. * IRQs may only be set, if a PHY address was configured
  130. * If a PHY address is given, also a bus id is required to be set
  131. *
  132. * ps: make sure the used irqs are configured properly in the board
  133. * specific irq-map
  134. */
  135. static void au1000_enable_mac(struct net_device *dev, int force_reset)
  136. {
  137. unsigned long flags;
  138. struct au1000_private *aup = netdev_priv(dev);
  139. spin_lock_irqsave(&aup->lock, flags);
  140. if (force_reset || (!aup->mac_enabled)) {
  141. writel(MAC_EN_CLOCK_ENABLE, aup->enable);
  142. au_sync_delay(2);
  143. writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
  144. | MAC_EN_CLOCK_ENABLE), aup->enable);
  145. au_sync_delay(2);
  146. aup->mac_enabled = 1;
  147. }
  148. spin_unlock_irqrestore(&aup->lock, flags);
  149. }
  150. /*
  151. * MII operations
  152. */
  153. static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
  154. {
  155. struct au1000_private *aup = netdev_priv(dev);
  156. u32 *const mii_control_reg = &aup->mac->mii_control;
  157. u32 *const mii_data_reg = &aup->mac->mii_data;
  158. u32 timedout = 20;
  159. u32 mii_control;
  160. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  161. mdelay(1);
  162. if (--timedout == 0) {
  163. netdev_err(dev, "read_MII busy timeout!!\n");
  164. return -1;
  165. }
  166. }
  167. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  168. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
  169. writel(mii_control, mii_control_reg);
  170. timedout = 20;
  171. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  172. mdelay(1);
  173. if (--timedout == 0) {
  174. netdev_err(dev, "mdio_read busy timeout!!\n");
  175. return -1;
  176. }
  177. }
  178. return readl(mii_data_reg);
  179. }
  180. static void au1000_mdio_write(struct net_device *dev, int phy_addr,
  181. int reg, u16 value)
  182. {
  183. struct au1000_private *aup = netdev_priv(dev);
  184. u32 *const mii_control_reg = &aup->mac->mii_control;
  185. u32 *const mii_data_reg = &aup->mac->mii_data;
  186. u32 timedout = 20;
  187. u32 mii_control;
  188. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  189. mdelay(1);
  190. if (--timedout == 0) {
  191. netdev_err(dev, "mdio_write busy timeout!!\n");
  192. return;
  193. }
  194. }
  195. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  196. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
  197. writel(value, mii_data_reg);
  198. writel(mii_control, mii_control_reg);
  199. }
  200. static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
  201. {
  202. /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
  203. * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus)
  204. */
  205. struct net_device *const dev = bus->priv;
  206. /* make sure the MAC associated with this
  207. * mii_bus is enabled
  208. */
  209. au1000_enable_mac(dev, 0);
  210. return au1000_mdio_read(dev, phy_addr, regnum);
  211. }
  212. static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
  213. u16 value)
  214. {
  215. struct net_device *const dev = bus->priv;
  216. /* make sure the MAC associated with this
  217. * mii_bus is enabled
  218. */
  219. au1000_enable_mac(dev, 0);
  220. au1000_mdio_write(dev, phy_addr, regnum, value);
  221. return 0;
  222. }
  223. static int au1000_mdiobus_reset(struct mii_bus *bus)
  224. {
  225. struct net_device *const dev = bus->priv;
  226. /* make sure the MAC associated with this
  227. * mii_bus is enabled
  228. */
  229. au1000_enable_mac(dev, 0);
  230. return 0;
  231. }
  232. static void au1000_hard_stop(struct net_device *dev)
  233. {
  234. struct au1000_private *aup = netdev_priv(dev);
  235. u32 reg;
  236. netif_dbg(aup, drv, dev, "hard stop\n");
  237. reg = readl(&aup->mac->control);
  238. reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
  239. writel(reg, &aup->mac->control);
  240. au_sync_delay(10);
  241. }
  242. static void au1000_enable_rx_tx(struct net_device *dev)
  243. {
  244. struct au1000_private *aup = netdev_priv(dev);
  245. u32 reg;
  246. netif_dbg(aup, hw, dev, "enable_rx_tx\n");
  247. reg = readl(&aup->mac->control);
  248. reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
  249. writel(reg, &aup->mac->control);
  250. au_sync_delay(10);
  251. }
  252. static void
  253. au1000_adjust_link(struct net_device *dev)
  254. {
  255. struct au1000_private *aup = netdev_priv(dev);
  256. struct phy_device *phydev = aup->phy_dev;
  257. unsigned long flags;
  258. u32 reg;
  259. int status_change = 0;
  260. BUG_ON(!aup->phy_dev);
  261. spin_lock_irqsave(&aup->lock, flags);
  262. if (phydev->link && (aup->old_speed != phydev->speed)) {
  263. /* speed changed */
  264. switch (phydev->speed) {
  265. case SPEED_10:
  266. case SPEED_100:
  267. break;
  268. default:
  269. netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
  270. phydev->speed);
  271. break;
  272. }
  273. aup->old_speed = phydev->speed;
  274. status_change = 1;
  275. }
  276. if (phydev->link && (aup->old_duplex != phydev->duplex)) {
  277. /* duplex mode changed */
  278. /* switching duplex mode requires to disable rx and tx! */
  279. au1000_hard_stop(dev);
  280. reg = readl(&aup->mac->control);
  281. if (DUPLEX_FULL == phydev->duplex) {
  282. reg |= MAC_FULL_DUPLEX;
  283. reg &= ~MAC_DISABLE_RX_OWN;
  284. } else {
  285. reg &= ~MAC_FULL_DUPLEX;
  286. reg |= MAC_DISABLE_RX_OWN;
  287. }
  288. writel(reg, &aup->mac->control);
  289. au_sync_delay(1);
  290. au1000_enable_rx_tx(dev);
  291. aup->old_duplex = phydev->duplex;
  292. status_change = 1;
  293. }
  294. if (phydev->link != aup->old_link) {
  295. /* link state changed */
  296. if (!phydev->link) {
  297. /* link went down */
  298. aup->old_speed = 0;
  299. aup->old_duplex = -1;
  300. }
  301. aup->old_link = phydev->link;
  302. status_change = 1;
  303. }
  304. spin_unlock_irqrestore(&aup->lock, flags);
  305. if (status_change) {
  306. if (phydev->link)
  307. netdev_info(dev, "link up (%d/%s)\n",
  308. phydev->speed,
  309. DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
  310. else
  311. netdev_info(dev, "link down\n");
  312. }
  313. }
  314. static int au1000_mii_probe(struct net_device *dev)
  315. {
  316. struct au1000_private *const aup = netdev_priv(dev);
  317. struct phy_device *phydev = NULL;
  318. int phy_addr;
  319. if (aup->phy_static_config) {
  320. BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
  321. if (aup->phy_addr)
  322. phydev = aup->mii_bus->phy_map[aup->phy_addr];
  323. else
  324. netdev_info(dev, "using PHY-less setup\n");
  325. return 0;
  326. }
  327. /* find the first (lowest address) PHY
  328. * on the current MAC's MII bus
  329. */
  330. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
  331. if (aup->mii_bus->phy_map[phy_addr]) {
  332. phydev = aup->mii_bus->phy_map[phy_addr];
  333. if (!aup->phy_search_highest_addr)
  334. /* break out with first one found */
  335. break;
  336. }
  337. if (aup->phy1_search_mac0) {
  338. /* try harder to find a PHY */
  339. if (!phydev && (aup->mac_id == 1)) {
  340. /* no PHY found, maybe we have a dual PHY? */
  341. dev_info(&dev->dev, ": no PHY found on MAC1, "
  342. "let's see if it's attached to MAC0...\n");
  343. /* find the first (lowest address) non-attached
  344. * PHY on the MAC0 MII bus
  345. */
  346. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  347. struct phy_device *const tmp_phydev =
  348. aup->mii_bus->phy_map[phy_addr];
  349. if (aup->mac_id == 1)
  350. break;
  351. /* no PHY here... */
  352. if (!tmp_phydev)
  353. continue;
  354. /* already claimed by MAC0 */
  355. if (tmp_phydev->attached_dev)
  356. continue;
  357. phydev = tmp_phydev;
  358. break; /* found it */
  359. }
  360. }
  361. }
  362. if (!phydev) {
  363. netdev_err(dev, "no PHY found\n");
  364. return -1;
  365. }
  366. /* now we are supposed to have a proper phydev, to attach to... */
  367. BUG_ON(phydev->attached_dev);
  368. phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
  369. 0, PHY_INTERFACE_MODE_MII);
  370. if (IS_ERR(phydev)) {
  371. netdev_err(dev, "Could not attach to PHY\n");
  372. return PTR_ERR(phydev);
  373. }
  374. /* mask with MAC supported features */
  375. phydev->supported &= (SUPPORTED_10baseT_Half
  376. | SUPPORTED_10baseT_Full
  377. | SUPPORTED_100baseT_Half
  378. | SUPPORTED_100baseT_Full
  379. | SUPPORTED_Autoneg
  380. /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
  381. | SUPPORTED_MII
  382. | SUPPORTED_TP);
  383. phydev->advertising = phydev->supported;
  384. aup->old_link = 0;
  385. aup->old_speed = 0;
  386. aup->old_duplex = -1;
  387. aup->phy_dev = phydev;
  388. netdev_info(dev, "attached PHY driver [%s] "
  389. "(mii_bus:phy_addr=%s, irq=%d)\n",
  390. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  391. return 0;
  392. }
  393. /*
  394. * Buffer allocation/deallocation routines. The buffer descriptor returned
  395. * has the virtual and dma address of a buffer suitable for
  396. * both, receive and transmit operations.
  397. */
  398. static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
  399. {
  400. struct db_dest *pDB;
  401. pDB = aup->pDBfree;
  402. if (pDB)
  403. aup->pDBfree = pDB->pnext;
  404. return pDB;
  405. }
  406. void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
  407. {
  408. struct db_dest *pDBfree = aup->pDBfree;
  409. if (pDBfree)
  410. pDBfree->pnext = pDB;
  411. aup->pDBfree = pDB;
  412. }
  413. static void au1000_reset_mac_unlocked(struct net_device *dev)
  414. {
  415. struct au1000_private *const aup = netdev_priv(dev);
  416. int i;
  417. au1000_hard_stop(dev);
  418. writel(MAC_EN_CLOCK_ENABLE, aup->enable);
  419. au_sync_delay(2);
  420. writel(0, aup->enable);
  421. au_sync_delay(2);
  422. aup->tx_full = 0;
  423. for (i = 0; i < NUM_RX_DMA; i++) {
  424. /* reset control bits */
  425. aup->rx_dma_ring[i]->buff_stat &= ~0xf;
  426. }
  427. for (i = 0; i < NUM_TX_DMA; i++) {
  428. /* reset control bits */
  429. aup->tx_dma_ring[i]->buff_stat &= ~0xf;
  430. }
  431. aup->mac_enabled = 0;
  432. }
  433. static void au1000_reset_mac(struct net_device *dev)
  434. {
  435. struct au1000_private *const aup = netdev_priv(dev);
  436. unsigned long flags;
  437. netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
  438. (unsigned)aup);
  439. spin_lock_irqsave(&aup->lock, flags);
  440. au1000_reset_mac_unlocked(dev);
  441. spin_unlock_irqrestore(&aup->lock, flags);
  442. }
  443. /*
  444. * Setup the receive and transmit "rings". These pointers are the addresses
  445. * of the rx and tx MAC DMA registers so they are fixed by the hardware --
  446. * these are not descriptors sitting in memory.
  447. */
  448. static void
  449. au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
  450. {
  451. int i;
  452. for (i = 0; i < NUM_RX_DMA; i++) {
  453. aup->rx_dma_ring[i] =
  454. (struct rx_dma *)
  455. (rx_base + sizeof(struct rx_dma)*i);
  456. }
  457. for (i = 0; i < NUM_TX_DMA; i++) {
  458. aup->tx_dma_ring[i] =
  459. (struct tx_dma *)
  460. (tx_base + sizeof(struct tx_dma)*i);
  461. }
  462. }
  463. /*
  464. * ethtool operations
  465. */
  466. static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  467. {
  468. struct au1000_private *aup = netdev_priv(dev);
  469. if (aup->phy_dev)
  470. return phy_ethtool_gset(aup->phy_dev, cmd);
  471. return -EINVAL;
  472. }
  473. static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  474. {
  475. struct au1000_private *aup = netdev_priv(dev);
  476. if (!capable(CAP_NET_ADMIN))
  477. return -EPERM;
  478. if (aup->phy_dev)
  479. return phy_ethtool_sset(aup->phy_dev, cmd);
  480. return -EINVAL;
  481. }
  482. static void
  483. au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  484. {
  485. struct au1000_private *aup = netdev_priv(dev);
  486. strcpy(info->driver, DRV_NAME);
  487. strcpy(info->version, DRV_VERSION);
  488. info->fw_version[0] = '\0';
  489. sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
  490. info->regdump_len = 0;
  491. }
  492. static void au1000_set_msglevel(struct net_device *dev, u32 value)
  493. {
  494. struct au1000_private *aup = netdev_priv(dev);
  495. aup->msg_enable = value;
  496. }
  497. static u32 au1000_get_msglevel(struct net_device *dev)
  498. {
  499. struct au1000_private *aup = netdev_priv(dev);
  500. return aup->msg_enable;
  501. }
  502. static const struct ethtool_ops au1000_ethtool_ops = {
  503. .get_settings = au1000_get_settings,
  504. .set_settings = au1000_set_settings,
  505. .get_drvinfo = au1000_get_drvinfo,
  506. .get_link = ethtool_op_get_link,
  507. .get_msglevel = au1000_get_msglevel,
  508. .set_msglevel = au1000_set_msglevel,
  509. };
  510. /*
  511. * Initialize the interface.
  512. *
  513. * When the device powers up, the clocks are disabled and the
  514. * mac is in reset state. When the interface is closed, we
  515. * do the same -- reset the device and disable the clocks to
  516. * conserve power. Thus, whenever au1000_init() is called,
  517. * the device should already be in reset state.
  518. */
  519. static int au1000_init(struct net_device *dev)
  520. {
  521. struct au1000_private *aup = netdev_priv(dev);
  522. unsigned long flags;
  523. int i;
  524. u32 control;
  525. netif_dbg(aup, hw, dev, "au1000_init\n");
  526. /* bring the device out of reset */
  527. au1000_enable_mac(dev, 1);
  528. spin_lock_irqsave(&aup->lock, flags);
  529. writel(0, &aup->mac->control);
  530. aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
  531. aup->tx_tail = aup->tx_head;
  532. aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
  533. writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
  534. &aup->mac->mac_addr_high);
  535. writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
  536. dev->dev_addr[1]<<8 | dev->dev_addr[0],
  537. &aup->mac->mac_addr_low);
  538. for (i = 0; i < NUM_RX_DMA; i++)
  539. aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
  540. au_sync();
  541. control = MAC_RX_ENABLE | MAC_TX_ENABLE;
  542. #ifndef CONFIG_CPU_LITTLE_ENDIAN
  543. control |= MAC_BIG_ENDIAN;
  544. #endif
  545. if (aup->phy_dev) {
  546. if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
  547. control |= MAC_FULL_DUPLEX;
  548. else
  549. control |= MAC_DISABLE_RX_OWN;
  550. } else { /* PHY-less op, assume full-duplex */
  551. control |= MAC_FULL_DUPLEX;
  552. }
  553. writel(control, &aup->mac->control);
  554. writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
  555. au_sync();
  556. spin_unlock_irqrestore(&aup->lock, flags);
  557. return 0;
  558. }
  559. static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
  560. {
  561. struct net_device_stats *ps = &dev->stats;
  562. ps->rx_packets++;
  563. if (status & RX_MCAST_FRAME)
  564. ps->multicast++;
  565. if (status & RX_ERROR) {
  566. ps->rx_errors++;
  567. if (status & RX_MISSED_FRAME)
  568. ps->rx_missed_errors++;
  569. if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
  570. ps->rx_length_errors++;
  571. if (status & RX_CRC_ERROR)
  572. ps->rx_crc_errors++;
  573. if (status & RX_COLL)
  574. ps->collisions++;
  575. } else
  576. ps->rx_bytes += status & RX_FRAME_LEN_MASK;
  577. }
  578. /*
  579. * Au1000 receive routine.
  580. */
  581. static int au1000_rx(struct net_device *dev)
  582. {
  583. struct au1000_private *aup = netdev_priv(dev);
  584. struct sk_buff *skb;
  585. struct rx_dma *prxd;
  586. u32 buff_stat, status;
  587. struct db_dest *pDB;
  588. u32 frmlen;
  589. netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
  590. prxd = aup->rx_dma_ring[aup->rx_head];
  591. buff_stat = prxd->buff_stat;
  592. while (buff_stat & RX_T_DONE) {
  593. status = prxd->status;
  594. pDB = aup->rx_db_inuse[aup->rx_head];
  595. au1000_update_rx_stats(dev, status);
  596. if (!(status & RX_ERROR)) {
  597. /* good frame */
  598. frmlen = (status & RX_FRAME_LEN_MASK);
  599. frmlen -= 4; /* Remove FCS */
  600. skb = dev_alloc_skb(frmlen + 2);
  601. if (skb == NULL) {
  602. netdev_err(dev, "Memory squeeze, dropping packet.\n");
  603. dev->stats.rx_dropped++;
  604. continue;
  605. }
  606. skb_reserve(skb, 2); /* 16 byte IP header align */
  607. skb_copy_to_linear_data(skb,
  608. (unsigned char *)pDB->vaddr, frmlen);
  609. skb_put(skb, frmlen);
  610. skb->protocol = eth_type_trans(skb, dev);
  611. netif_rx(skb); /* pass the packet to upper layers */
  612. } else {
  613. if (au1000_debug > 4) {
  614. pr_err("rx_error(s):");
  615. if (status & RX_MISSED_FRAME)
  616. pr_cont(" miss");
  617. if (status & RX_WDOG_TIMER)
  618. pr_cont(" wdog");
  619. if (status & RX_RUNT)
  620. pr_cont(" runt");
  621. if (status & RX_OVERLEN)
  622. pr_cont(" overlen");
  623. if (status & RX_COLL)
  624. pr_cont(" coll");
  625. if (status & RX_MII_ERROR)
  626. pr_cont(" mii error");
  627. if (status & RX_CRC_ERROR)
  628. pr_cont(" crc error");
  629. if (status & RX_LEN_ERROR)
  630. pr_cont(" len error");
  631. if (status & RX_U_CNTRL_FRAME)
  632. pr_cont(" u control frame");
  633. pr_cont("\n");
  634. }
  635. }
  636. prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
  637. aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
  638. au_sync();
  639. /* next descriptor */
  640. prxd = aup->rx_dma_ring[aup->rx_head];
  641. buff_stat = prxd->buff_stat;
  642. }
  643. return 0;
  644. }
  645. static void au1000_update_tx_stats(struct net_device *dev, u32 status)
  646. {
  647. struct au1000_private *aup = netdev_priv(dev);
  648. struct net_device_stats *ps = &dev->stats;
  649. if (status & TX_FRAME_ABORTED) {
  650. if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
  651. if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
  652. /* any other tx errors are only valid
  653. * in half duplex mode
  654. */
  655. ps->tx_errors++;
  656. ps->tx_aborted_errors++;
  657. }
  658. } else {
  659. ps->tx_errors++;
  660. ps->tx_aborted_errors++;
  661. if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
  662. ps->tx_carrier_errors++;
  663. }
  664. }
  665. }
  666. /*
  667. * Called from the interrupt service routine to acknowledge
  668. * the TX DONE bits. This is a must if the irq is setup as
  669. * edge triggered.
  670. */
  671. static void au1000_tx_ack(struct net_device *dev)
  672. {
  673. struct au1000_private *aup = netdev_priv(dev);
  674. struct tx_dma *ptxd;
  675. ptxd = aup->tx_dma_ring[aup->tx_tail];
  676. while (ptxd->buff_stat & TX_T_DONE) {
  677. au1000_update_tx_stats(dev, ptxd->status);
  678. ptxd->buff_stat &= ~TX_T_DONE;
  679. ptxd->len = 0;
  680. au_sync();
  681. aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
  682. ptxd = aup->tx_dma_ring[aup->tx_tail];
  683. if (aup->tx_full) {
  684. aup->tx_full = 0;
  685. netif_wake_queue(dev);
  686. }
  687. }
  688. }
  689. /*
  690. * Au1000 interrupt service routine.
  691. */
  692. static irqreturn_t au1000_interrupt(int irq, void *dev_id)
  693. {
  694. struct net_device *dev = dev_id;
  695. /* Handle RX interrupts first to minimize chance of overrun */
  696. au1000_rx(dev);
  697. au1000_tx_ack(dev);
  698. return IRQ_RETVAL(1);
  699. }
  700. static int au1000_open(struct net_device *dev)
  701. {
  702. int retval;
  703. struct au1000_private *aup = netdev_priv(dev);
  704. netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
  705. retval = request_irq(dev->irq, au1000_interrupt, 0,
  706. dev->name, dev);
  707. if (retval) {
  708. netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
  709. return retval;
  710. }
  711. retval = au1000_init(dev);
  712. if (retval) {
  713. netdev_err(dev, "error in au1000_init\n");
  714. free_irq(dev->irq, dev);
  715. return retval;
  716. }
  717. if (aup->phy_dev) {
  718. /* cause the PHY state machine to schedule a link state check */
  719. aup->phy_dev->state = PHY_CHANGELINK;
  720. phy_start(aup->phy_dev);
  721. }
  722. netif_start_queue(dev);
  723. netif_dbg(aup, drv, dev, "open: Initialization done.\n");
  724. return 0;
  725. }
  726. static int au1000_close(struct net_device *dev)
  727. {
  728. unsigned long flags;
  729. struct au1000_private *const aup = netdev_priv(dev);
  730. netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
  731. if (aup->phy_dev)
  732. phy_stop(aup->phy_dev);
  733. spin_lock_irqsave(&aup->lock, flags);
  734. au1000_reset_mac_unlocked(dev);
  735. /* stop the device */
  736. netif_stop_queue(dev);
  737. /* disable the interrupt */
  738. free_irq(dev->irq, dev);
  739. spin_unlock_irqrestore(&aup->lock, flags);
  740. return 0;
  741. }
  742. /*
  743. * Au1000 transmit routine.
  744. */
  745. static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
  746. {
  747. struct au1000_private *aup = netdev_priv(dev);
  748. struct net_device_stats *ps = &dev->stats;
  749. struct tx_dma *ptxd;
  750. u32 buff_stat;
  751. struct db_dest *pDB;
  752. int i;
  753. netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
  754. (unsigned)aup, skb->len,
  755. skb->data, aup->tx_head);
  756. ptxd = aup->tx_dma_ring[aup->tx_head];
  757. buff_stat = ptxd->buff_stat;
  758. if (buff_stat & TX_DMA_ENABLE) {
  759. /* We've wrapped around and the transmitter is still busy */
  760. netif_stop_queue(dev);
  761. aup->tx_full = 1;
  762. return NETDEV_TX_BUSY;
  763. } else if (buff_stat & TX_T_DONE) {
  764. au1000_update_tx_stats(dev, ptxd->status);
  765. ptxd->len = 0;
  766. }
  767. if (aup->tx_full) {
  768. aup->tx_full = 0;
  769. netif_wake_queue(dev);
  770. }
  771. pDB = aup->tx_db_inuse[aup->tx_head];
  772. skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
  773. if (skb->len < ETH_ZLEN) {
  774. for (i = skb->len; i < ETH_ZLEN; i++)
  775. ((char *)pDB->vaddr)[i] = 0;
  776. ptxd->len = ETH_ZLEN;
  777. } else
  778. ptxd->len = skb->len;
  779. ps->tx_packets++;
  780. ps->tx_bytes += ptxd->len;
  781. ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
  782. au_sync();
  783. dev_kfree_skb(skb);
  784. aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
  785. return NETDEV_TX_OK;
  786. }
  787. /*
  788. * The Tx ring has been full longer than the watchdog timeout
  789. * value. The transmitter must be hung?
  790. */
  791. static void au1000_tx_timeout(struct net_device *dev)
  792. {
  793. netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
  794. au1000_reset_mac(dev);
  795. au1000_init(dev);
  796. dev->trans_start = jiffies; /* prevent tx timeout */
  797. netif_wake_queue(dev);
  798. }
  799. static void au1000_multicast_list(struct net_device *dev)
  800. {
  801. struct au1000_private *aup = netdev_priv(dev);
  802. u32 reg;
  803. netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
  804. reg = readl(&aup->mac->control);
  805. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  806. reg |= MAC_PROMISCUOUS;
  807. } else if ((dev->flags & IFF_ALLMULTI) ||
  808. netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
  809. reg |= MAC_PASS_ALL_MULTI;
  810. reg &= ~MAC_PROMISCUOUS;
  811. netdev_info(dev, "Pass all multicast\n");
  812. } else {
  813. struct netdev_hw_addr *ha;
  814. u32 mc_filter[2]; /* Multicast hash filter */
  815. mc_filter[1] = mc_filter[0] = 0;
  816. netdev_for_each_mc_addr(ha, dev)
  817. set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
  818. (long *)mc_filter);
  819. writel(mc_filter[1], &aup->mac->multi_hash_high);
  820. writel(mc_filter[0], &aup->mac->multi_hash_low);
  821. reg &= ~MAC_PROMISCUOUS;
  822. reg |= MAC_HASH_MODE;
  823. }
  824. writel(reg, &aup->mac->control);
  825. }
  826. static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  827. {
  828. struct au1000_private *aup = netdev_priv(dev);
  829. if (!netif_running(dev))
  830. return -EINVAL;
  831. if (!aup->phy_dev)
  832. return -EINVAL; /* PHY not controllable */
  833. return phy_mii_ioctl(aup->phy_dev, rq, cmd);
  834. }
  835. static const struct net_device_ops au1000_netdev_ops = {
  836. .ndo_open = au1000_open,
  837. .ndo_stop = au1000_close,
  838. .ndo_start_xmit = au1000_tx,
  839. .ndo_set_multicast_list = au1000_multicast_list,
  840. .ndo_do_ioctl = au1000_ioctl,
  841. .ndo_tx_timeout = au1000_tx_timeout,
  842. .ndo_set_mac_address = eth_mac_addr,
  843. .ndo_validate_addr = eth_validate_addr,
  844. .ndo_change_mtu = eth_change_mtu,
  845. };
  846. static int __devinit au1000_probe(struct platform_device *pdev)
  847. {
  848. static unsigned version_printed;
  849. struct au1000_private *aup = NULL;
  850. struct au1000_eth_platform_data *pd;
  851. struct net_device *dev = NULL;
  852. struct db_dest *pDB, *pDBfree;
  853. int irq, i, err = 0;
  854. struct resource *base, *macen;
  855. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  856. if (!base) {
  857. dev_err(&pdev->dev, "failed to retrieve base register\n");
  858. err = -ENODEV;
  859. goto out;
  860. }
  861. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  862. if (!macen) {
  863. dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
  864. err = -ENODEV;
  865. goto out;
  866. }
  867. irq = platform_get_irq(pdev, 0);
  868. if (irq < 0) {
  869. dev_err(&pdev->dev, "failed to retrieve IRQ\n");
  870. err = -ENODEV;
  871. goto out;
  872. }
  873. if (!request_mem_region(base->start, resource_size(base),
  874. pdev->name)) {
  875. dev_err(&pdev->dev, "failed to request memory region for base registers\n");
  876. err = -ENXIO;
  877. goto out;
  878. }
  879. if (!request_mem_region(macen->start, resource_size(macen),
  880. pdev->name)) {
  881. dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
  882. err = -ENXIO;
  883. goto err_request;
  884. }
  885. dev = alloc_etherdev(sizeof(struct au1000_private));
  886. if (!dev) {
  887. dev_err(&pdev->dev, "alloc_etherdev failed\n");
  888. err = -ENOMEM;
  889. goto err_alloc;
  890. }
  891. SET_NETDEV_DEV(dev, &pdev->dev);
  892. platform_set_drvdata(pdev, dev);
  893. aup = netdev_priv(dev);
  894. spin_lock_init(&aup->lock);
  895. aup->msg_enable = (au1000_debug < 4 ?
  896. AU1000_DEF_MSG_ENABLE : au1000_debug);
  897. /* Allocate the data buffers
  898. * Snooping works fine with eth on all au1xxx
  899. */
  900. aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
  901. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  902. &aup->dma_addr, 0);
  903. if (!aup->vaddr) {
  904. dev_err(&pdev->dev, "failed to allocate data buffers\n");
  905. err = -ENOMEM;
  906. goto err_vaddr;
  907. }
  908. /* aup->mac is the base address of the MAC's registers */
  909. aup->mac = (struct mac_reg *)
  910. ioremap_nocache(base->start, resource_size(base));
  911. if (!aup->mac) {
  912. dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
  913. err = -ENXIO;
  914. goto err_remap1;
  915. }
  916. /* Setup some variables for quick register address access */
  917. aup->enable = (u32 *)ioremap_nocache(macen->start,
  918. resource_size(macen));
  919. if (!aup->enable) {
  920. dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
  921. err = -ENXIO;
  922. goto err_remap2;
  923. }
  924. aup->mac_id = pdev->id;
  925. if (pdev->id == 0)
  926. au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
  927. else if (pdev->id == 1)
  928. au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
  929. /* set a random MAC now in case platform_data doesn't provide one */
  930. random_ether_addr(dev->dev_addr);
  931. writel(0, aup->enable);
  932. aup->mac_enabled = 0;
  933. pd = pdev->dev.platform_data;
  934. if (!pd) {
  935. dev_info(&pdev->dev, "no platform_data passed,"
  936. " PHY search on MAC0\n");
  937. aup->phy1_search_mac0 = 1;
  938. } else {
  939. if (is_valid_ether_addr(pd->mac))
  940. memcpy(dev->dev_addr, pd->mac, 6);
  941. aup->phy_static_config = pd->phy_static_config;
  942. aup->phy_search_highest_addr = pd->phy_search_highest_addr;
  943. aup->phy1_search_mac0 = pd->phy1_search_mac0;
  944. aup->phy_addr = pd->phy_addr;
  945. aup->phy_busid = pd->phy_busid;
  946. aup->phy_irq = pd->phy_irq;
  947. }
  948. if (aup->phy_busid && aup->phy_busid > 0) {
  949. dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
  950. err = -ENODEV;
  951. goto err_mdiobus_alloc;
  952. }
  953. aup->mii_bus = mdiobus_alloc();
  954. if (aup->mii_bus == NULL) {
  955. dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
  956. err = -ENOMEM;
  957. goto err_mdiobus_alloc;
  958. }
  959. aup->mii_bus->priv = dev;
  960. aup->mii_bus->read = au1000_mdiobus_read;
  961. aup->mii_bus->write = au1000_mdiobus_write;
  962. aup->mii_bus->reset = au1000_mdiobus_reset;
  963. aup->mii_bus->name = "au1000_eth_mii";
  964. snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
  965. aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  966. if (aup->mii_bus->irq == NULL)
  967. goto err_out;
  968. for (i = 0; i < PHY_MAX_ADDR; ++i)
  969. aup->mii_bus->irq[i] = PHY_POLL;
  970. /* if known, set corresponding PHY IRQs */
  971. if (aup->phy_static_config)
  972. if (aup->phy_irq && aup->phy_busid == aup->mac_id)
  973. aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
  974. err = mdiobus_register(aup->mii_bus);
  975. if (err) {
  976. dev_err(&pdev->dev, "failed to register MDIO bus\n");
  977. goto err_mdiobus_reg;
  978. }
  979. if (au1000_mii_probe(dev) != 0)
  980. goto err_out;
  981. pDBfree = NULL;
  982. /* setup the data buffer descriptors and attach a buffer to each one */
  983. pDB = aup->db;
  984. for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
  985. pDB->pnext = pDBfree;
  986. pDBfree = pDB;
  987. pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
  988. pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
  989. pDB++;
  990. }
  991. aup->pDBfree = pDBfree;
  992. for (i = 0; i < NUM_RX_DMA; i++) {
  993. pDB = au1000_GetFreeDB(aup);
  994. if (!pDB)
  995. goto err_out;
  996. aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  997. aup->rx_db_inuse[i] = pDB;
  998. }
  999. for (i = 0; i < NUM_TX_DMA; i++) {
  1000. pDB = au1000_GetFreeDB(aup);
  1001. if (!pDB)
  1002. goto err_out;
  1003. aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  1004. aup->tx_dma_ring[i]->len = 0;
  1005. aup->tx_db_inuse[i] = pDB;
  1006. }
  1007. dev->base_addr = base->start;
  1008. dev->irq = irq;
  1009. dev->netdev_ops = &au1000_netdev_ops;
  1010. SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
  1011. dev->watchdog_timeo = ETH_TX_TIMEOUT;
  1012. /*
  1013. * The boot code uses the ethernet controller, so reset it to start
  1014. * fresh. au1000_init() expects that the device is in reset state.
  1015. */
  1016. au1000_reset_mac(dev);
  1017. err = register_netdev(dev);
  1018. if (err) {
  1019. netdev_err(dev, "Cannot register net device, aborting.\n");
  1020. goto err_out;
  1021. }
  1022. netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
  1023. (unsigned long)base->start, irq);
  1024. if (version_printed++ == 0)
  1025. pr_info("%s version %s %s\n",
  1026. DRV_NAME, DRV_VERSION, DRV_AUTHOR);
  1027. return 0;
  1028. err_out:
  1029. if (aup->mii_bus != NULL)
  1030. mdiobus_unregister(aup->mii_bus);
  1031. /* here we should have a valid dev plus aup-> register addresses
  1032. * so we can reset the mac properly.
  1033. */
  1034. au1000_reset_mac(dev);
  1035. for (i = 0; i < NUM_RX_DMA; i++) {
  1036. if (aup->rx_db_inuse[i])
  1037. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1038. }
  1039. for (i = 0; i < NUM_TX_DMA; i++) {
  1040. if (aup->tx_db_inuse[i])
  1041. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1042. }
  1043. err_mdiobus_reg:
  1044. mdiobus_free(aup->mii_bus);
  1045. err_mdiobus_alloc:
  1046. iounmap(aup->enable);
  1047. err_remap2:
  1048. iounmap(aup->mac);
  1049. err_remap1:
  1050. dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1051. (void *)aup->vaddr, aup->dma_addr);
  1052. err_vaddr:
  1053. free_netdev(dev);
  1054. err_alloc:
  1055. release_mem_region(macen->start, resource_size(macen));
  1056. err_request:
  1057. release_mem_region(base->start, resource_size(base));
  1058. out:
  1059. return err;
  1060. }
  1061. static int __devexit au1000_remove(struct platform_device *pdev)
  1062. {
  1063. struct net_device *dev = platform_get_drvdata(pdev);
  1064. struct au1000_private *aup = netdev_priv(dev);
  1065. int i;
  1066. struct resource *base, *macen;
  1067. platform_set_drvdata(pdev, NULL);
  1068. unregister_netdev(dev);
  1069. mdiobus_unregister(aup->mii_bus);
  1070. mdiobus_free(aup->mii_bus);
  1071. for (i = 0; i < NUM_RX_DMA; i++)
  1072. if (aup->rx_db_inuse[i])
  1073. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1074. for (i = 0; i < NUM_TX_DMA; i++)
  1075. if (aup->tx_db_inuse[i])
  1076. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1077. dma_free_noncoherent(NULL, MAX_BUF_SIZE *
  1078. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1079. (void *)aup->vaddr, aup->dma_addr);
  1080. iounmap(aup->mac);
  1081. iounmap(aup->enable);
  1082. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1083. release_mem_region(base->start, resource_size(base));
  1084. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1085. release_mem_region(macen->start, resource_size(macen));
  1086. free_netdev(dev);
  1087. return 0;
  1088. }
  1089. static struct platform_driver au1000_eth_driver = {
  1090. .probe = au1000_probe,
  1091. .remove = __devexit_p(au1000_remove),
  1092. .driver = {
  1093. .name = "au1000-eth",
  1094. .owner = THIS_MODULE,
  1095. },
  1096. };
  1097. MODULE_ALIAS("platform:au1000-eth");
  1098. static int __init au1000_init_module(void)
  1099. {
  1100. return platform_driver_register(&au1000_eth_driver);
  1101. }
  1102. static void __exit au1000_exit_module(void)
  1103. {
  1104. platform_driver_unregister(&au1000_eth_driver);
  1105. }
  1106. module_init(au1000_init_module);
  1107. module_exit(au1000_exit_module);