ab3550-core.c 30 KB

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  1. /*
  2. * Copyright (C) 2007-2010 ST-Ericsson
  3. * License terms: GNU General Public License (GPL) version 2
  4. * Low-level core for exclusive access to the AB3550 IC on the I2C bus
  5. * and some basic chip-configuration.
  6. * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
  7. * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
  8. * Author: Mattias Wallin <mattias.wallin@stericsson.com>
  9. * Author: Rickard Andersson <rickard.andersson@stericsson.com>
  10. */
  11. #include <linux/i2c.h>
  12. #include <linux/mutex.h>
  13. #include <linux/err.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <linux/device.h>
  17. #include <linux/irq.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/random.h>
  20. #include <linux/workqueue.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/uaccess.h>
  24. #include <linux/mfd/abx500.h>
  25. #include <linux/list.h>
  26. #include <linux/bitops.h>
  27. #include <linux/spinlock.h>
  28. #include <linux/mfd/core.h>
  29. #define AB3550_NAME_STRING "ab3550"
  30. #define AB3550_ID_FORMAT_STRING "AB3550 %s"
  31. #define AB3550_NUM_BANKS 2
  32. #define AB3550_NUM_EVENT_REG 5
  33. /* These are the only registers inside AB3550 used in this main file */
  34. /* Chip ID register */
  35. #define AB3550_CID_REG 0x20
  36. /* Interrupt event registers */
  37. #define AB3550_EVENT_BANK 0
  38. #define AB3550_EVENT_REG 0x22
  39. /* Read/write operation values. */
  40. #define AB3550_PERM_RD (0x01)
  41. #define AB3550_PERM_WR (0x02)
  42. /* Read/write permissions. */
  43. #define AB3550_PERM_RO (AB3550_PERM_RD)
  44. #define AB3550_PERM_RW (AB3550_PERM_RD | AB3550_PERM_WR)
  45. /**
  46. * struct ab3550
  47. * @access_mutex: lock out concurrent accesses to the AB registers
  48. * @i2c_client: I2C client for this chip
  49. * @chip_name: name of this chip variant
  50. * @chip_id: 8 bit chip ID for this chip variant
  51. * @mask_work: a worker for writing to mask registers
  52. * @event_lock: a lock to protect the event_mask
  53. * @event_mask: a local copy of the mask event registers
  54. * @startup_events: a copy of the first reading of the event registers
  55. * @startup_events_read: whether the first events have been read
  56. */
  57. struct ab3550 {
  58. struct mutex access_mutex;
  59. struct i2c_client *i2c_client[AB3550_NUM_BANKS];
  60. char chip_name[32];
  61. u8 chip_id;
  62. struct work_struct mask_work;
  63. spinlock_t event_lock;
  64. u8 event_mask[AB3550_NUM_EVENT_REG];
  65. u8 startup_events[AB3550_NUM_EVENT_REG];
  66. bool startup_events_read;
  67. #ifdef CONFIG_DEBUG_FS
  68. unsigned int debug_bank;
  69. unsigned int debug_address;
  70. #endif
  71. };
  72. /**
  73. * struct ab3550_reg_range
  74. * @first: the first address of the range
  75. * @last: the last address of the range
  76. * @perm: access permissions for the range
  77. */
  78. struct ab3550_reg_range {
  79. u8 first;
  80. u8 last;
  81. u8 perm;
  82. };
  83. /**
  84. * struct ab3550_reg_ranges
  85. * @count: the number of ranges in the list
  86. * @range: the list of register ranges
  87. */
  88. struct ab3550_reg_ranges {
  89. u8 count;
  90. const struct ab3550_reg_range *range;
  91. };
  92. /*
  93. * Permissible register ranges for reading and writing per device and bank.
  94. *
  95. * The ranges must be listed in increasing address order, and no overlaps are
  96. * allowed. It is assumed that write permission implies read permission
  97. * (i.e. only RO and RW permissions should be used). Ranges with write
  98. * permission must not be split up.
  99. */
  100. #define NO_RANGE {.count = 0, .range = NULL,}
  101. static struct
  102. ab3550_reg_ranges ab3550_reg_ranges[AB3550_NUM_DEVICES][AB3550_NUM_BANKS] = {
  103. [AB3550_DEVID_DAC] = {
  104. NO_RANGE,
  105. {
  106. .count = 2,
  107. .range = (struct ab3550_reg_range[]) {
  108. {
  109. .first = 0xb0,
  110. .last = 0xba,
  111. .perm = AB3550_PERM_RW,
  112. },
  113. {
  114. .first = 0xbc,
  115. .last = 0xc3,
  116. .perm = AB3550_PERM_RW,
  117. },
  118. },
  119. },
  120. },
  121. [AB3550_DEVID_LEDS] = {
  122. NO_RANGE,
  123. {
  124. .count = 2,
  125. .range = (struct ab3550_reg_range[]) {
  126. {
  127. .first = 0x5a,
  128. .last = 0x88,
  129. .perm = AB3550_PERM_RW,
  130. },
  131. {
  132. .first = 0x8a,
  133. .last = 0xad,
  134. .perm = AB3550_PERM_RW,
  135. },
  136. }
  137. },
  138. },
  139. [AB3550_DEVID_POWER] = {
  140. {
  141. .count = 1,
  142. .range = (struct ab3550_reg_range[]) {
  143. {
  144. .first = 0x21,
  145. .last = 0x21,
  146. .perm = AB3550_PERM_RO,
  147. },
  148. }
  149. },
  150. NO_RANGE,
  151. },
  152. [AB3550_DEVID_REGULATORS] = {
  153. {
  154. .count = 1,
  155. .range = (struct ab3550_reg_range[]) {
  156. {
  157. .first = 0x69,
  158. .last = 0xa3,
  159. .perm = AB3550_PERM_RW,
  160. },
  161. }
  162. },
  163. {
  164. .count = 1,
  165. .range = (struct ab3550_reg_range[]) {
  166. {
  167. .first = 0x14,
  168. .last = 0x16,
  169. .perm = AB3550_PERM_RW,
  170. },
  171. }
  172. },
  173. },
  174. [AB3550_DEVID_SIM] = {
  175. {
  176. .count = 1,
  177. .range = (struct ab3550_reg_range[]) {
  178. {
  179. .first = 0x21,
  180. .last = 0x21,
  181. .perm = AB3550_PERM_RO,
  182. },
  183. }
  184. },
  185. {
  186. .count = 1,
  187. .range = (struct ab3550_reg_range[]) {
  188. {
  189. .first = 0x14,
  190. .last = 0x17,
  191. .perm = AB3550_PERM_RW,
  192. },
  193. }
  194. },
  195. },
  196. [AB3550_DEVID_UART] = {
  197. NO_RANGE,
  198. NO_RANGE,
  199. },
  200. [AB3550_DEVID_RTC] = {
  201. {
  202. .count = 1,
  203. .range = (struct ab3550_reg_range[]) {
  204. {
  205. .first = 0x00,
  206. .last = 0x0c,
  207. .perm = AB3550_PERM_RW,
  208. },
  209. }
  210. },
  211. NO_RANGE,
  212. },
  213. [AB3550_DEVID_CHARGER] = {
  214. {
  215. .count = 2,
  216. .range = (struct ab3550_reg_range[]) {
  217. {
  218. .first = 0x10,
  219. .last = 0x1a,
  220. .perm = AB3550_PERM_RW,
  221. },
  222. {
  223. .first = 0x21,
  224. .last = 0x21,
  225. .perm = AB3550_PERM_RO,
  226. },
  227. }
  228. },
  229. NO_RANGE,
  230. },
  231. [AB3550_DEVID_ADC] = {
  232. NO_RANGE,
  233. {
  234. .count = 1,
  235. .range = (struct ab3550_reg_range[]) {
  236. {
  237. .first = 0x20,
  238. .last = 0x56,
  239. .perm = AB3550_PERM_RW,
  240. },
  241. }
  242. },
  243. },
  244. [AB3550_DEVID_FUELGAUGE] = {
  245. {
  246. .count = 1,
  247. .range = (struct ab3550_reg_range[]) {
  248. {
  249. .first = 0x21,
  250. .last = 0x21,
  251. .perm = AB3550_PERM_RO,
  252. },
  253. }
  254. },
  255. {
  256. .count = 1,
  257. .range = (struct ab3550_reg_range[]) {
  258. {
  259. .first = 0x00,
  260. .last = 0x0e,
  261. .perm = AB3550_PERM_RW,
  262. },
  263. }
  264. },
  265. },
  266. [AB3550_DEVID_VIBRATOR] = {
  267. NO_RANGE,
  268. {
  269. .count = 1,
  270. .range = (struct ab3550_reg_range[]) {
  271. {
  272. .first = 0x10,
  273. .last = 0x13,
  274. .perm = AB3550_PERM_RW,
  275. },
  276. }
  277. },
  278. },
  279. [AB3550_DEVID_CODEC] = {
  280. {
  281. .count = 2,
  282. .range = (struct ab3550_reg_range[]) {
  283. {
  284. .first = 0x31,
  285. .last = 0x63,
  286. .perm = AB3550_PERM_RW,
  287. },
  288. {
  289. .first = 0x65,
  290. .last = 0x68,
  291. .perm = AB3550_PERM_RW,
  292. },
  293. }
  294. },
  295. NO_RANGE,
  296. },
  297. };
  298. static struct mfd_cell ab3550_devs[AB3550_NUM_DEVICES] = {
  299. [AB3550_DEVID_DAC] = {
  300. .name = "ab3550-dac",
  301. .id = AB3550_DEVID_DAC,
  302. .num_resources = 0,
  303. },
  304. [AB3550_DEVID_LEDS] = {
  305. .name = "ab3550-leds",
  306. .id = AB3550_DEVID_LEDS,
  307. },
  308. [AB3550_DEVID_POWER] = {
  309. .name = "ab3550-power",
  310. .id = AB3550_DEVID_POWER,
  311. },
  312. [AB3550_DEVID_REGULATORS] = {
  313. .name = "ab3550-regulators",
  314. .id = AB3550_DEVID_REGULATORS,
  315. },
  316. [AB3550_DEVID_SIM] = {
  317. .name = "ab3550-sim",
  318. .id = AB3550_DEVID_SIM,
  319. },
  320. [AB3550_DEVID_UART] = {
  321. .name = "ab3550-uart",
  322. .id = AB3550_DEVID_UART,
  323. },
  324. [AB3550_DEVID_RTC] = {
  325. .name = "ab3550-rtc",
  326. .id = AB3550_DEVID_RTC,
  327. },
  328. [AB3550_DEVID_CHARGER] = {
  329. .name = "ab3550-charger",
  330. .id = AB3550_DEVID_CHARGER,
  331. },
  332. [AB3550_DEVID_ADC] = {
  333. .name = "ab3550-adc",
  334. .id = AB3550_DEVID_ADC,
  335. .num_resources = 10,
  336. .resources = (struct resource[]) {
  337. {
  338. .name = "TRIGGER-0",
  339. .flags = IORESOURCE_IRQ,
  340. .start = 16,
  341. .end = 16,
  342. },
  343. {
  344. .name = "TRIGGER-1",
  345. .flags = IORESOURCE_IRQ,
  346. .start = 17,
  347. .end = 17,
  348. },
  349. {
  350. .name = "TRIGGER-2",
  351. .flags = IORESOURCE_IRQ,
  352. .start = 18,
  353. .end = 18,
  354. },
  355. {
  356. .name = "TRIGGER-3",
  357. .flags = IORESOURCE_IRQ,
  358. .start = 19,
  359. .end = 19,
  360. },
  361. {
  362. .name = "TRIGGER-4",
  363. .flags = IORESOURCE_IRQ,
  364. .start = 20,
  365. .end = 20,
  366. },
  367. {
  368. .name = "TRIGGER-5",
  369. .flags = IORESOURCE_IRQ,
  370. .start = 21,
  371. .end = 21,
  372. },
  373. {
  374. .name = "TRIGGER-6",
  375. .flags = IORESOURCE_IRQ,
  376. .start = 22,
  377. .end = 22,
  378. },
  379. {
  380. .name = "TRIGGER-7",
  381. .flags = IORESOURCE_IRQ,
  382. .start = 23,
  383. .end = 23,
  384. },
  385. {
  386. .name = "TRIGGER-VBAT-TXON",
  387. .flags = IORESOURCE_IRQ,
  388. .start = 13,
  389. .end = 13,
  390. },
  391. {
  392. .name = "TRIGGER-VBAT",
  393. .flags = IORESOURCE_IRQ,
  394. .start = 12,
  395. .end = 12,
  396. },
  397. },
  398. },
  399. [AB3550_DEVID_FUELGAUGE] = {
  400. .name = "ab3550-fuelgauge",
  401. .id = AB3550_DEVID_FUELGAUGE,
  402. },
  403. [AB3550_DEVID_VIBRATOR] = {
  404. .name = "ab3550-vibrator",
  405. .id = AB3550_DEVID_VIBRATOR,
  406. },
  407. [AB3550_DEVID_CODEC] = {
  408. .name = "ab3550-codec",
  409. .id = AB3550_DEVID_CODEC,
  410. },
  411. };
  412. /*
  413. * I2C transactions with error messages.
  414. */
  415. static int ab3550_i2c_master_send(struct ab3550 *ab, u8 bank, u8 *data,
  416. u8 count)
  417. {
  418. int err;
  419. err = i2c_master_send(ab->i2c_client[bank], data, count);
  420. if (err < 0) {
  421. dev_err(&ab->i2c_client[0]->dev, "send error: %d\n", err);
  422. return err;
  423. }
  424. return 0;
  425. }
  426. static int ab3550_i2c_master_recv(struct ab3550 *ab, u8 bank, u8 *data,
  427. u8 count)
  428. {
  429. int err;
  430. err = i2c_master_recv(ab->i2c_client[bank], data, count);
  431. if (err < 0) {
  432. dev_err(&ab->i2c_client[0]->dev, "receive error: %d\n", err);
  433. return err;
  434. }
  435. return 0;
  436. }
  437. /*
  438. * Functionality for getting/setting register values.
  439. */
  440. static int get_register_interruptible(struct ab3550 *ab, u8 bank, u8 reg,
  441. u8 *value)
  442. {
  443. int err;
  444. err = mutex_lock_interruptible(&ab->access_mutex);
  445. if (err)
  446. return err;
  447. err = ab3550_i2c_master_send(ab, bank, &reg, 1);
  448. if (!err)
  449. err = ab3550_i2c_master_recv(ab, bank, value, 1);
  450. mutex_unlock(&ab->access_mutex);
  451. return err;
  452. }
  453. static int get_register_page_interruptible(struct ab3550 *ab, u8 bank,
  454. u8 first_reg, u8 *regvals, u8 numregs)
  455. {
  456. int err;
  457. err = mutex_lock_interruptible(&ab->access_mutex);
  458. if (err)
  459. return err;
  460. err = ab3550_i2c_master_send(ab, bank, &first_reg, 1);
  461. if (!err)
  462. err = ab3550_i2c_master_recv(ab, bank, regvals, numregs);
  463. mutex_unlock(&ab->access_mutex);
  464. return err;
  465. }
  466. static int mask_and_set_register_interruptible(struct ab3550 *ab, u8 bank,
  467. u8 reg, u8 bitmask, u8 bitvalues)
  468. {
  469. int err = 0;
  470. if (likely(bitmask)) {
  471. u8 reg_bits[2] = {reg, 0};
  472. err = mutex_lock_interruptible(&ab->access_mutex);
  473. if (err)
  474. return err;
  475. if (bitmask == 0xFF) /* No need to read in this case. */
  476. reg_bits[1] = bitvalues;
  477. else { /* Read and modify the register value. */
  478. u8 bits;
  479. err = ab3550_i2c_master_send(ab, bank, &reg, 1);
  480. if (err)
  481. goto unlock_and_return;
  482. err = ab3550_i2c_master_recv(ab, bank, &bits, 1);
  483. if (err)
  484. goto unlock_and_return;
  485. reg_bits[1] = ((~bitmask & bits) |
  486. (bitmask & bitvalues));
  487. }
  488. /* Write the new value. */
  489. err = ab3550_i2c_master_send(ab, bank, reg_bits, 2);
  490. unlock_and_return:
  491. mutex_unlock(&ab->access_mutex);
  492. }
  493. return err;
  494. }
  495. /*
  496. * Read/write permission checking functions.
  497. */
  498. static bool page_write_allowed(const struct ab3550_reg_ranges *ranges,
  499. u8 first_reg, u8 last_reg)
  500. {
  501. u8 i;
  502. if (last_reg < first_reg)
  503. return false;
  504. for (i = 0; i < ranges->count; i++) {
  505. if (first_reg < ranges->range[i].first)
  506. break;
  507. if ((last_reg <= ranges->range[i].last) &&
  508. (ranges->range[i].perm & AB3550_PERM_WR))
  509. return true;
  510. }
  511. return false;
  512. }
  513. static bool reg_write_allowed(const struct ab3550_reg_ranges *ranges, u8 reg)
  514. {
  515. return page_write_allowed(ranges, reg, reg);
  516. }
  517. static bool page_read_allowed(const struct ab3550_reg_ranges *ranges,
  518. u8 first_reg, u8 last_reg)
  519. {
  520. u8 i;
  521. if (last_reg < first_reg)
  522. return false;
  523. /* Find the range (if it exists in the list) that includes first_reg. */
  524. for (i = 0; i < ranges->count; i++) {
  525. if (first_reg < ranges->range[i].first)
  526. return false;
  527. if (first_reg <= ranges->range[i].last)
  528. break;
  529. }
  530. /* Make sure that the entire range up to and including last_reg is
  531. * readable. This may span several of the ranges in the list.
  532. */
  533. while ((i < ranges->count) &&
  534. (ranges->range[i].perm & AB3550_PERM_RD)) {
  535. if (last_reg <= ranges->range[i].last)
  536. return true;
  537. if ((++i >= ranges->count) ||
  538. (ranges->range[i].first !=
  539. (ranges->range[i - 1].last + 1))) {
  540. break;
  541. }
  542. }
  543. return false;
  544. }
  545. static bool reg_read_allowed(const struct ab3550_reg_ranges *ranges, u8 reg)
  546. {
  547. return page_read_allowed(ranges, reg, reg);
  548. }
  549. /*
  550. * The register access functionality.
  551. */
  552. static int ab3550_get_chip_id(struct device *dev)
  553. {
  554. struct ab3550 *ab = dev_get_drvdata(dev->parent);
  555. return (int)ab->chip_id;
  556. }
  557. static int ab3550_mask_and_set_register_interruptible(struct device *dev,
  558. u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
  559. {
  560. struct ab3550 *ab;
  561. struct platform_device *pdev = to_platform_device(dev);
  562. if ((AB3550_NUM_BANKS <= bank) ||
  563. !reg_write_allowed(&ab3550_reg_ranges[pdev->id][bank], reg))
  564. return -EINVAL;
  565. ab = dev_get_drvdata(dev->parent);
  566. return mask_and_set_register_interruptible(ab, bank, reg,
  567. bitmask, bitvalues);
  568. }
  569. static int ab3550_set_register_interruptible(struct device *dev, u8 bank,
  570. u8 reg, u8 value)
  571. {
  572. return ab3550_mask_and_set_register_interruptible(dev, bank, reg, 0xFF,
  573. value);
  574. }
  575. static int ab3550_get_register_interruptible(struct device *dev, u8 bank,
  576. u8 reg, u8 *value)
  577. {
  578. struct ab3550 *ab;
  579. struct platform_device *pdev = to_platform_device(dev);
  580. if ((AB3550_NUM_BANKS <= bank) ||
  581. !reg_read_allowed(&ab3550_reg_ranges[pdev->id][bank], reg))
  582. return -EINVAL;
  583. ab = dev_get_drvdata(dev->parent);
  584. return get_register_interruptible(ab, bank, reg, value);
  585. }
  586. static int ab3550_get_register_page_interruptible(struct device *dev, u8 bank,
  587. u8 first_reg, u8 *regvals, u8 numregs)
  588. {
  589. struct ab3550 *ab;
  590. struct platform_device *pdev = to_platform_device(dev);
  591. if ((AB3550_NUM_BANKS <= bank) ||
  592. !page_read_allowed(&ab3550_reg_ranges[pdev->id][bank],
  593. first_reg, (first_reg + numregs - 1)))
  594. return -EINVAL;
  595. ab = dev_get_drvdata(dev->parent);
  596. return get_register_page_interruptible(ab, bank, first_reg, regvals,
  597. numregs);
  598. }
  599. static int ab3550_event_registers_startup_state_get(struct device *dev,
  600. u8 *event)
  601. {
  602. struct ab3550 *ab;
  603. ab = dev_get_drvdata(dev->parent);
  604. if (!ab->startup_events_read)
  605. return -EAGAIN; /* Try again later */
  606. memcpy(event, ab->startup_events, AB3550_NUM_EVENT_REG);
  607. return 0;
  608. }
  609. static int ab3550_startup_irq_enabled(struct device *dev, unsigned int irq)
  610. {
  611. struct ab3550 *ab;
  612. struct ab3550_platform_data *plf_data;
  613. bool val;
  614. ab = irq_get_chip_data(irq);
  615. plf_data = ab->i2c_client[0]->dev.platform_data;
  616. irq -= plf_data->irq.base;
  617. val = ((ab->startup_events[irq / 8] & BIT(irq % 8)) != 0);
  618. return val;
  619. }
  620. static struct abx500_ops ab3550_ops = {
  621. .get_chip_id = ab3550_get_chip_id,
  622. .get_register = ab3550_get_register_interruptible,
  623. .set_register = ab3550_set_register_interruptible,
  624. .get_register_page = ab3550_get_register_page_interruptible,
  625. .set_register_page = NULL,
  626. .mask_and_set_register = ab3550_mask_and_set_register_interruptible,
  627. .event_registers_startup_state_get =
  628. ab3550_event_registers_startup_state_get,
  629. .startup_irq_enabled = ab3550_startup_irq_enabled,
  630. };
  631. static irqreturn_t ab3550_irq_handler(int irq, void *data)
  632. {
  633. struct ab3550 *ab = data;
  634. int err;
  635. unsigned int i;
  636. u8 e[AB3550_NUM_EVENT_REG];
  637. u8 *events;
  638. unsigned long flags;
  639. events = (ab->startup_events_read ? e : ab->startup_events);
  640. err = get_register_page_interruptible(ab, AB3550_EVENT_BANK,
  641. AB3550_EVENT_REG, events, AB3550_NUM_EVENT_REG);
  642. if (err)
  643. goto err_event_rd;
  644. if (!ab->startup_events_read) {
  645. dev_info(&ab->i2c_client[0]->dev,
  646. "startup events 0x%x,0x%x,0x%x,0x%x,0x%x\n",
  647. ab->startup_events[0], ab->startup_events[1],
  648. ab->startup_events[2], ab->startup_events[3],
  649. ab->startup_events[4]);
  650. ab->startup_events_read = true;
  651. goto out;
  652. }
  653. /* The two highest bits in event[4] are not used. */
  654. events[4] &= 0x3f;
  655. spin_lock_irqsave(&ab->event_lock, flags);
  656. for (i = 0; i < AB3550_NUM_EVENT_REG; i++)
  657. events[i] &= ~ab->event_mask[i];
  658. spin_unlock_irqrestore(&ab->event_lock, flags);
  659. for (i = 0; i < AB3550_NUM_EVENT_REG; i++) {
  660. u8 bit;
  661. u8 event_reg;
  662. dev_dbg(&ab->i2c_client[0]->dev, "IRQ Event[%d]: 0x%2x\n",
  663. i, events[i]);
  664. event_reg = events[i];
  665. for (bit = 0; event_reg; bit++, event_reg /= 2) {
  666. if (event_reg % 2) {
  667. unsigned int irq;
  668. struct ab3550_platform_data *plf_data;
  669. plf_data = ab->i2c_client[0]->dev.platform_data;
  670. irq = plf_data->irq.base + (i * 8) + bit;
  671. handle_nested_irq(irq);
  672. }
  673. }
  674. }
  675. out:
  676. return IRQ_HANDLED;
  677. err_event_rd:
  678. dev_dbg(&ab->i2c_client[0]->dev, "error reading event registers\n");
  679. return IRQ_HANDLED;
  680. }
  681. #ifdef CONFIG_DEBUG_FS
  682. static struct ab3550_reg_ranges debug_ranges[AB3550_NUM_BANKS] = {
  683. {
  684. .count = 6,
  685. .range = (struct ab3550_reg_range[]) {
  686. {
  687. .first = 0x00,
  688. .last = 0x0e,
  689. },
  690. {
  691. .first = 0x10,
  692. .last = 0x1a,
  693. },
  694. {
  695. .first = 0x1e,
  696. .last = 0x4f,
  697. },
  698. {
  699. .first = 0x51,
  700. .last = 0x63,
  701. },
  702. {
  703. .first = 0x65,
  704. .last = 0xa3,
  705. },
  706. {
  707. .first = 0xa5,
  708. .last = 0xa8,
  709. },
  710. }
  711. },
  712. {
  713. .count = 8,
  714. .range = (struct ab3550_reg_range[]) {
  715. {
  716. .first = 0x00,
  717. .last = 0x0e,
  718. },
  719. {
  720. .first = 0x10,
  721. .last = 0x17,
  722. },
  723. {
  724. .first = 0x1a,
  725. .last = 0x1c,
  726. },
  727. {
  728. .first = 0x20,
  729. .last = 0x56,
  730. },
  731. {
  732. .first = 0x5a,
  733. .last = 0x88,
  734. },
  735. {
  736. .first = 0x8a,
  737. .last = 0xad,
  738. },
  739. {
  740. .first = 0xb0,
  741. .last = 0xba,
  742. },
  743. {
  744. .first = 0xbc,
  745. .last = 0xc3,
  746. },
  747. }
  748. },
  749. };
  750. static int ab3550_registers_print(struct seq_file *s, void *p)
  751. {
  752. struct ab3550 *ab = s->private;
  753. int bank;
  754. seq_printf(s, AB3550_NAME_STRING " register values:\n");
  755. for (bank = 0; bank < AB3550_NUM_BANKS; bank++) {
  756. unsigned int i;
  757. seq_printf(s, " bank %d:\n", bank);
  758. for (i = 0; i < debug_ranges[bank].count; i++) {
  759. u8 reg;
  760. for (reg = debug_ranges[bank].range[i].first;
  761. reg <= debug_ranges[bank].range[i].last;
  762. reg++) {
  763. u8 value;
  764. get_register_interruptible(ab, bank, reg,
  765. &value);
  766. seq_printf(s, " [%d/0x%02X]: 0x%02X\n", bank,
  767. reg, value);
  768. }
  769. }
  770. }
  771. return 0;
  772. }
  773. static int ab3550_registers_open(struct inode *inode, struct file *file)
  774. {
  775. return single_open(file, ab3550_registers_print, inode->i_private);
  776. }
  777. static const struct file_operations ab3550_registers_fops = {
  778. .open = ab3550_registers_open,
  779. .read = seq_read,
  780. .llseek = seq_lseek,
  781. .release = single_release,
  782. .owner = THIS_MODULE,
  783. };
  784. static int ab3550_bank_print(struct seq_file *s, void *p)
  785. {
  786. struct ab3550 *ab = s->private;
  787. seq_printf(s, "%d\n", ab->debug_bank);
  788. return 0;
  789. }
  790. static int ab3550_bank_open(struct inode *inode, struct file *file)
  791. {
  792. return single_open(file, ab3550_bank_print, inode->i_private);
  793. }
  794. static ssize_t ab3550_bank_write(struct file *file,
  795. const char __user *user_buf,
  796. size_t count, loff_t *ppos)
  797. {
  798. struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private;
  799. unsigned long user_bank;
  800. int err;
  801. /* Get userspace string and assure termination */
  802. err = kstrtoul_from_user(user_buf, count, 0, &user_bank);
  803. if (err)
  804. return err;
  805. if (user_bank >= AB3550_NUM_BANKS) {
  806. dev_err(&ab->i2c_client[0]->dev,
  807. "debugfs error input > number of banks\n");
  808. return -EINVAL;
  809. }
  810. ab->debug_bank = user_bank;
  811. return count;
  812. }
  813. static int ab3550_address_print(struct seq_file *s, void *p)
  814. {
  815. struct ab3550 *ab = s->private;
  816. seq_printf(s, "0x%02X\n", ab->debug_address);
  817. return 0;
  818. }
  819. static int ab3550_address_open(struct inode *inode, struct file *file)
  820. {
  821. return single_open(file, ab3550_address_print, inode->i_private);
  822. }
  823. static ssize_t ab3550_address_write(struct file *file,
  824. const char __user *user_buf,
  825. size_t count, loff_t *ppos)
  826. {
  827. struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private;
  828. unsigned long user_address;
  829. int err;
  830. /* Get userspace string and assure termination */
  831. err = kstrtoul_from_user(user_buf, count, 0, &user_address);
  832. if (err)
  833. return err;
  834. if (user_address > 0xff) {
  835. dev_err(&ab->i2c_client[0]->dev,
  836. "debugfs error input > 0xff\n");
  837. return -EINVAL;
  838. }
  839. ab->debug_address = user_address;
  840. return count;
  841. }
  842. static int ab3550_val_print(struct seq_file *s, void *p)
  843. {
  844. struct ab3550 *ab = s->private;
  845. int err;
  846. u8 regvalue;
  847. err = get_register_interruptible(ab, (u8)ab->debug_bank,
  848. (u8)ab->debug_address, &regvalue);
  849. if (err)
  850. return -EINVAL;
  851. seq_printf(s, "0x%02X\n", regvalue);
  852. return 0;
  853. }
  854. static int ab3550_val_open(struct inode *inode, struct file *file)
  855. {
  856. return single_open(file, ab3550_val_print, inode->i_private);
  857. }
  858. static ssize_t ab3550_val_write(struct file *file,
  859. const char __user *user_buf,
  860. size_t count, loff_t *ppos)
  861. {
  862. struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private;
  863. unsigned long user_val;
  864. int err;
  865. u8 regvalue;
  866. /* Get userspace string and assure termination */
  867. err = kstrtoul_from_user(user_buf, count, 0, &user_val);
  868. if (err)
  869. return err;
  870. if (user_val > 0xff) {
  871. dev_err(&ab->i2c_client[0]->dev,
  872. "debugfs error input > 0xff\n");
  873. return -EINVAL;
  874. }
  875. err = mask_and_set_register_interruptible(
  876. ab, (u8)ab->debug_bank,
  877. (u8)ab->debug_address, 0xFF, (u8)user_val);
  878. if (err)
  879. return -EINVAL;
  880. get_register_interruptible(ab, (u8)ab->debug_bank,
  881. (u8)ab->debug_address, &regvalue);
  882. if (err)
  883. return -EINVAL;
  884. return count;
  885. }
  886. static const struct file_operations ab3550_bank_fops = {
  887. .open = ab3550_bank_open,
  888. .write = ab3550_bank_write,
  889. .read = seq_read,
  890. .llseek = seq_lseek,
  891. .release = single_release,
  892. .owner = THIS_MODULE,
  893. };
  894. static const struct file_operations ab3550_address_fops = {
  895. .open = ab3550_address_open,
  896. .write = ab3550_address_write,
  897. .read = seq_read,
  898. .llseek = seq_lseek,
  899. .release = single_release,
  900. .owner = THIS_MODULE,
  901. };
  902. static const struct file_operations ab3550_val_fops = {
  903. .open = ab3550_val_open,
  904. .write = ab3550_val_write,
  905. .read = seq_read,
  906. .llseek = seq_lseek,
  907. .release = single_release,
  908. .owner = THIS_MODULE,
  909. };
  910. static struct dentry *ab3550_dir;
  911. static struct dentry *ab3550_reg_file;
  912. static struct dentry *ab3550_bank_file;
  913. static struct dentry *ab3550_address_file;
  914. static struct dentry *ab3550_val_file;
  915. static inline void ab3550_setup_debugfs(struct ab3550 *ab)
  916. {
  917. ab->debug_bank = 0;
  918. ab->debug_address = 0x00;
  919. ab3550_dir = debugfs_create_dir(AB3550_NAME_STRING, NULL);
  920. if (!ab3550_dir)
  921. goto exit_no_debugfs;
  922. ab3550_reg_file = debugfs_create_file("all-registers",
  923. S_IRUGO, ab3550_dir, ab, &ab3550_registers_fops);
  924. if (!ab3550_reg_file)
  925. goto exit_destroy_dir;
  926. ab3550_bank_file = debugfs_create_file("register-bank",
  927. (S_IRUGO | S_IWUSR), ab3550_dir, ab, &ab3550_bank_fops);
  928. if (!ab3550_bank_file)
  929. goto exit_destroy_reg;
  930. ab3550_address_file = debugfs_create_file("register-address",
  931. (S_IRUGO | S_IWUSR), ab3550_dir, ab, &ab3550_address_fops);
  932. if (!ab3550_address_file)
  933. goto exit_destroy_bank;
  934. ab3550_val_file = debugfs_create_file("register-value",
  935. (S_IRUGO | S_IWUSR), ab3550_dir, ab, &ab3550_val_fops);
  936. if (!ab3550_val_file)
  937. goto exit_destroy_address;
  938. return;
  939. exit_destroy_address:
  940. debugfs_remove(ab3550_address_file);
  941. exit_destroy_bank:
  942. debugfs_remove(ab3550_bank_file);
  943. exit_destroy_reg:
  944. debugfs_remove(ab3550_reg_file);
  945. exit_destroy_dir:
  946. debugfs_remove(ab3550_dir);
  947. exit_no_debugfs:
  948. dev_err(&ab->i2c_client[0]->dev, "failed to create debugfs entries.\n");
  949. return;
  950. }
  951. static inline void ab3550_remove_debugfs(void)
  952. {
  953. debugfs_remove(ab3550_val_file);
  954. debugfs_remove(ab3550_address_file);
  955. debugfs_remove(ab3550_bank_file);
  956. debugfs_remove(ab3550_reg_file);
  957. debugfs_remove(ab3550_dir);
  958. }
  959. #else /* !CONFIG_DEBUG_FS */
  960. static inline void ab3550_setup_debugfs(struct ab3550 *ab)
  961. {
  962. }
  963. static inline void ab3550_remove_debugfs(void)
  964. {
  965. }
  966. #endif
  967. /*
  968. * Basic set-up, datastructure creation/destruction and I2C interface.
  969. * This sets up a default config in the AB3550 chip so that it
  970. * will work as expected.
  971. */
  972. static int __init ab3550_setup(struct ab3550 *ab)
  973. {
  974. int err = 0;
  975. int i;
  976. struct ab3550_platform_data *plf_data;
  977. struct abx500_init_settings *settings;
  978. plf_data = ab->i2c_client[0]->dev.platform_data;
  979. settings = plf_data->init_settings;
  980. for (i = 0; i < plf_data->init_settings_sz; i++) {
  981. err = mask_and_set_register_interruptible(ab,
  982. settings[i].bank,
  983. settings[i].reg,
  984. 0xFF, settings[i].setting);
  985. if (err)
  986. goto exit_no_setup;
  987. /* If event mask register update the event mask in ab3550 */
  988. if ((settings[i].bank == 0) &&
  989. (AB3550_IMR1 <= settings[i].reg) &&
  990. (settings[i].reg <= AB3550_IMR5)) {
  991. ab->event_mask[settings[i].reg - AB3550_IMR1] =
  992. settings[i].setting;
  993. }
  994. }
  995. exit_no_setup:
  996. return err;
  997. }
  998. static void ab3550_mask_work(struct work_struct *work)
  999. {
  1000. struct ab3550 *ab = container_of(work, struct ab3550, mask_work);
  1001. int i;
  1002. unsigned long flags;
  1003. u8 mask[AB3550_NUM_EVENT_REG];
  1004. spin_lock_irqsave(&ab->event_lock, flags);
  1005. for (i = 0; i < AB3550_NUM_EVENT_REG; i++)
  1006. mask[i] = ab->event_mask[i];
  1007. spin_unlock_irqrestore(&ab->event_lock, flags);
  1008. for (i = 0; i < AB3550_NUM_EVENT_REG; i++) {
  1009. int err;
  1010. err = mask_and_set_register_interruptible(ab, 0,
  1011. (AB3550_IMR1 + i), ~0, mask[i]);
  1012. if (err)
  1013. dev_err(&ab->i2c_client[0]->dev,
  1014. "ab3550_mask_work failed 0x%x,0x%x\n",
  1015. (AB3550_IMR1 + i), mask[i]);
  1016. }
  1017. }
  1018. static void ab3550_mask(struct irq_data *data)
  1019. {
  1020. unsigned long flags;
  1021. struct ab3550 *ab;
  1022. struct ab3550_platform_data *plf_data;
  1023. int irq;
  1024. ab = irq_data_get_irq_chip_data(data);
  1025. plf_data = ab->i2c_client[0]->dev.platform_data;
  1026. irq = data->irq - plf_data->irq.base;
  1027. spin_lock_irqsave(&ab->event_lock, flags);
  1028. ab->event_mask[irq / 8] |= BIT(irq % 8);
  1029. spin_unlock_irqrestore(&ab->event_lock, flags);
  1030. schedule_work(&ab->mask_work);
  1031. }
  1032. static void ab3550_unmask(struct irq_data *data)
  1033. {
  1034. unsigned long flags;
  1035. struct ab3550 *ab;
  1036. struct ab3550_platform_data *plf_data;
  1037. int irq;
  1038. ab = irq_data_get_irq_chip_data(data);
  1039. plf_data = ab->i2c_client[0]->dev.platform_data;
  1040. irq = data->irq - plf_data->irq.base;
  1041. spin_lock_irqsave(&ab->event_lock, flags);
  1042. ab->event_mask[irq / 8] &= ~BIT(irq % 8);
  1043. spin_unlock_irqrestore(&ab->event_lock, flags);
  1044. schedule_work(&ab->mask_work);
  1045. }
  1046. static void noop(struct irq_data *data)
  1047. {
  1048. }
  1049. static struct irq_chip ab3550_irq_chip = {
  1050. .name = "ab3550-core", /* Keep the same name as the request */
  1051. .irq_disable = ab3550_mask, /* No default to mask in chip.c */
  1052. .irq_ack = noop,
  1053. .irq_mask = ab3550_mask,
  1054. .irq_unmask = ab3550_unmask,
  1055. };
  1056. struct ab_family_id {
  1057. u8 id;
  1058. char *name;
  1059. };
  1060. static const struct ab_family_id ids[] __initdata = {
  1061. /* AB3550 */
  1062. {
  1063. .id = AB3550_P1A,
  1064. .name = "P1A"
  1065. },
  1066. /* Terminator */
  1067. {
  1068. .id = 0x00,
  1069. }
  1070. };
  1071. static int __init ab3550_probe(struct i2c_client *client,
  1072. const struct i2c_device_id *id)
  1073. {
  1074. struct ab3550 *ab;
  1075. struct ab3550_platform_data *ab3550_plf_data =
  1076. client->dev.platform_data;
  1077. int err;
  1078. int i;
  1079. int num_i2c_clients = 0;
  1080. ab = kzalloc(sizeof(struct ab3550), GFP_KERNEL);
  1081. if (!ab) {
  1082. dev_err(&client->dev,
  1083. "could not allocate " AB3550_NAME_STRING " device\n");
  1084. return -ENOMEM;
  1085. }
  1086. /* Initialize data structure */
  1087. mutex_init(&ab->access_mutex);
  1088. spin_lock_init(&ab->event_lock);
  1089. ab->i2c_client[0] = client;
  1090. i2c_set_clientdata(client, ab);
  1091. /* Read chip ID register */
  1092. err = get_register_interruptible(ab, 0, AB3550_CID_REG, &ab->chip_id);
  1093. if (err) {
  1094. dev_err(&client->dev, "could not communicate with the analog "
  1095. "baseband chip\n");
  1096. goto exit_no_detect;
  1097. }
  1098. for (i = 0; ids[i].id != 0x0; i++) {
  1099. if (ids[i].id == ab->chip_id) {
  1100. snprintf(&ab->chip_name[0], sizeof(ab->chip_name) - 1,
  1101. AB3550_ID_FORMAT_STRING, ids[i].name);
  1102. break;
  1103. }
  1104. }
  1105. if (ids[i].id == 0x0) {
  1106. dev_err(&client->dev, "unknown analog baseband chip id: 0x%x\n",
  1107. ab->chip_id);
  1108. dev_err(&client->dev, "driver not started!\n");
  1109. goto exit_no_detect;
  1110. }
  1111. dev_info(&client->dev, "detected AB chip: %s\n", &ab->chip_name[0]);
  1112. /* Attach other dummy I2C clients. */
  1113. while (++num_i2c_clients < AB3550_NUM_BANKS) {
  1114. ab->i2c_client[num_i2c_clients] =
  1115. i2c_new_dummy(client->adapter,
  1116. (client->addr + num_i2c_clients));
  1117. if (!ab->i2c_client[num_i2c_clients]) {
  1118. err = -ENOMEM;
  1119. goto exit_no_dummy_client;
  1120. }
  1121. strlcpy(ab->i2c_client[num_i2c_clients]->name, id->name,
  1122. sizeof(ab->i2c_client[num_i2c_clients]->name));
  1123. }
  1124. err = ab3550_setup(ab);
  1125. if (err)
  1126. goto exit_no_setup;
  1127. INIT_WORK(&ab->mask_work, ab3550_mask_work);
  1128. for (i = 0; i < ab3550_plf_data->irq.count; i++) {
  1129. unsigned int irq;
  1130. irq = ab3550_plf_data->irq.base + i;
  1131. irq_set_chip_data(irq, ab);
  1132. irq_set_chip_and_handler(irq, &ab3550_irq_chip,
  1133. handle_simple_irq);
  1134. irq_set_nested_thread(irq, 1);
  1135. #ifdef CONFIG_ARM
  1136. set_irq_flags(irq, IRQF_VALID);
  1137. #else
  1138. irq_set_noprobe(irq);
  1139. #endif
  1140. }
  1141. err = request_threaded_irq(client->irq, NULL, ab3550_irq_handler,
  1142. IRQF_ONESHOT, "ab3550-core", ab);
  1143. /* This real unpredictable IRQ is of course sampled for entropy */
  1144. rand_initialize_irq(client->irq);
  1145. if (err)
  1146. goto exit_no_irq;
  1147. err = abx500_register_ops(&client->dev, &ab3550_ops);
  1148. if (err)
  1149. goto exit_no_ops;
  1150. /* Set up and register the platform devices. */
  1151. for (i = 0; i < AB3550_NUM_DEVICES; i++) {
  1152. ab3550_devs[i].platform_data = ab3550_plf_data->dev_data[i];
  1153. ab3550_devs[i].pdata_size = ab3550_plf_data->dev_data_sz[i];
  1154. }
  1155. err = mfd_add_devices(&client->dev, 0, ab3550_devs,
  1156. ARRAY_SIZE(ab3550_devs), NULL,
  1157. ab3550_plf_data->irq.base);
  1158. ab3550_setup_debugfs(ab);
  1159. return 0;
  1160. exit_no_ops:
  1161. exit_no_irq:
  1162. exit_no_setup:
  1163. exit_no_dummy_client:
  1164. /* Unregister the dummy i2c clients. */
  1165. while (--num_i2c_clients)
  1166. i2c_unregister_device(ab->i2c_client[num_i2c_clients]);
  1167. exit_no_detect:
  1168. kfree(ab);
  1169. return err;
  1170. }
  1171. static int __exit ab3550_remove(struct i2c_client *client)
  1172. {
  1173. struct ab3550 *ab = i2c_get_clientdata(client);
  1174. int num_i2c_clients = AB3550_NUM_BANKS;
  1175. mfd_remove_devices(&client->dev);
  1176. ab3550_remove_debugfs();
  1177. while (--num_i2c_clients)
  1178. i2c_unregister_device(ab->i2c_client[num_i2c_clients]);
  1179. /*
  1180. * At this point, all subscribers should have unregistered
  1181. * their notifiers so deactivate IRQ
  1182. */
  1183. free_irq(client->irq, ab);
  1184. kfree(ab);
  1185. return 0;
  1186. }
  1187. static const struct i2c_device_id ab3550_id[] = {
  1188. {AB3550_NAME_STRING, 0},
  1189. {}
  1190. };
  1191. MODULE_DEVICE_TABLE(i2c, ab3550_id);
  1192. static struct i2c_driver ab3550_driver = {
  1193. .driver = {
  1194. .name = AB3550_NAME_STRING,
  1195. .owner = THIS_MODULE,
  1196. },
  1197. .id_table = ab3550_id,
  1198. .probe = ab3550_probe,
  1199. .remove = __exit_p(ab3550_remove),
  1200. };
  1201. static int __init ab3550_i2c_init(void)
  1202. {
  1203. return i2c_add_driver(&ab3550_driver);
  1204. }
  1205. static void __exit ab3550_i2c_exit(void)
  1206. {
  1207. i2c_del_driver(&ab3550_driver);
  1208. }
  1209. subsys_initcall(ab3550_i2c_init);
  1210. module_exit(ab3550_i2c_exit);
  1211. MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>");
  1212. MODULE_DESCRIPTION("AB3550 core driver");
  1213. MODULE_LICENSE("GPL");