tegra-kbc.c 19 KB

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  1. /*
  2. * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
  3. * keyboard controller
  4. *
  5. * Copyright (c) 2009-2011, NVIDIA Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/input.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/delay.h>
  26. #include <linux/io.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/clk.h>
  29. #include <linux/slab.h>
  30. #include <mach/clk.h>
  31. #include <mach/kbc.h>
  32. #define KBC_MAX_DEBOUNCE_CNT 0x3ffu
  33. /* KBC row scan time and delay for beginning the row scan. */
  34. #define KBC_ROW_SCAN_TIME 16
  35. #define KBC_ROW_SCAN_DLY 5
  36. /* KBC uses a 32KHz clock so a cycle = 1/32Khz */
  37. #define KBC_CYCLE_MS 32
  38. /* KBC Registers */
  39. /* KBC Control Register */
  40. #define KBC_CONTROL_0 0x0
  41. #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
  42. #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
  43. #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
  44. #define KBC_CONTROL_KBC_EN (1 << 0)
  45. /* KBC Interrupt Register */
  46. #define KBC_INT_0 0x4
  47. #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
  48. #define KBC_ROW_CFG0_0 0x8
  49. #define KBC_COL_CFG0_0 0x18
  50. #define KBC_INIT_DLY_0 0x28
  51. #define KBC_RPT_DLY_0 0x2c
  52. #define KBC_KP_ENT0_0 0x30
  53. #define KBC_KP_ENT1_0 0x34
  54. #define KBC_ROW0_MASK_0 0x38
  55. #define KBC_ROW_SHIFT 3
  56. struct tegra_kbc {
  57. void __iomem *mmio;
  58. struct input_dev *idev;
  59. unsigned int irq;
  60. spinlock_t lock;
  61. unsigned int repoll_dly;
  62. unsigned long cp_dly_jiffies;
  63. bool use_fn_map;
  64. bool use_ghost_filter;
  65. const struct tegra_kbc_platform_data *pdata;
  66. unsigned short keycode[KBC_MAX_KEY * 2];
  67. unsigned short current_keys[KBC_MAX_KPENT];
  68. unsigned int num_pressed_keys;
  69. struct timer_list timer;
  70. struct clk *clk;
  71. };
  72. static const u32 tegra_kbc_default_keymap[] = {
  73. KEY(0, 2, KEY_W),
  74. KEY(0, 3, KEY_S),
  75. KEY(0, 4, KEY_A),
  76. KEY(0, 5, KEY_Z),
  77. KEY(0, 7, KEY_FN),
  78. KEY(1, 7, KEY_LEFTMETA),
  79. KEY(2, 6, KEY_RIGHTALT),
  80. KEY(2, 7, KEY_LEFTALT),
  81. KEY(3, 0, KEY_5),
  82. KEY(3, 1, KEY_4),
  83. KEY(3, 2, KEY_R),
  84. KEY(3, 3, KEY_E),
  85. KEY(3, 4, KEY_F),
  86. KEY(3, 5, KEY_D),
  87. KEY(3, 6, KEY_X),
  88. KEY(4, 0, KEY_7),
  89. KEY(4, 1, KEY_6),
  90. KEY(4, 2, KEY_T),
  91. KEY(4, 3, KEY_H),
  92. KEY(4, 4, KEY_G),
  93. KEY(4, 5, KEY_V),
  94. KEY(4, 6, KEY_C),
  95. KEY(4, 7, KEY_SPACE),
  96. KEY(5, 0, KEY_9),
  97. KEY(5, 1, KEY_8),
  98. KEY(5, 2, KEY_U),
  99. KEY(5, 3, KEY_Y),
  100. KEY(5, 4, KEY_J),
  101. KEY(5, 5, KEY_N),
  102. KEY(5, 6, KEY_B),
  103. KEY(5, 7, KEY_BACKSLASH),
  104. KEY(6, 0, KEY_MINUS),
  105. KEY(6, 1, KEY_0),
  106. KEY(6, 2, KEY_O),
  107. KEY(6, 3, KEY_I),
  108. KEY(6, 4, KEY_L),
  109. KEY(6, 5, KEY_K),
  110. KEY(6, 6, KEY_COMMA),
  111. KEY(6, 7, KEY_M),
  112. KEY(7, 1, KEY_EQUAL),
  113. KEY(7, 2, KEY_RIGHTBRACE),
  114. KEY(7, 3, KEY_ENTER),
  115. KEY(7, 7, KEY_MENU),
  116. KEY(8, 4, KEY_RIGHTSHIFT),
  117. KEY(8, 5, KEY_LEFTSHIFT),
  118. KEY(9, 5, KEY_RIGHTCTRL),
  119. KEY(9, 7, KEY_LEFTCTRL),
  120. KEY(11, 0, KEY_LEFTBRACE),
  121. KEY(11, 1, KEY_P),
  122. KEY(11, 2, KEY_APOSTROPHE),
  123. KEY(11, 3, KEY_SEMICOLON),
  124. KEY(11, 4, KEY_SLASH),
  125. KEY(11, 5, KEY_DOT),
  126. KEY(12, 0, KEY_F10),
  127. KEY(12, 1, KEY_F9),
  128. KEY(12, 2, KEY_BACKSPACE),
  129. KEY(12, 3, KEY_3),
  130. KEY(12, 4, KEY_2),
  131. KEY(12, 5, KEY_UP),
  132. KEY(12, 6, KEY_PRINT),
  133. KEY(12, 7, KEY_PAUSE),
  134. KEY(13, 0, KEY_INSERT),
  135. KEY(13, 1, KEY_DELETE),
  136. KEY(13, 3, KEY_PAGEUP),
  137. KEY(13, 4, KEY_PAGEDOWN),
  138. KEY(13, 5, KEY_RIGHT),
  139. KEY(13, 6, KEY_DOWN),
  140. KEY(13, 7, KEY_LEFT),
  141. KEY(14, 0, KEY_F11),
  142. KEY(14, 1, KEY_F12),
  143. KEY(14, 2, KEY_F8),
  144. KEY(14, 3, KEY_Q),
  145. KEY(14, 4, KEY_F4),
  146. KEY(14, 5, KEY_F3),
  147. KEY(14, 6, KEY_1),
  148. KEY(14, 7, KEY_F7),
  149. KEY(15, 0, KEY_ESC),
  150. KEY(15, 1, KEY_GRAVE),
  151. KEY(15, 2, KEY_F5),
  152. KEY(15, 3, KEY_TAB),
  153. KEY(15, 4, KEY_F1),
  154. KEY(15, 5, KEY_F2),
  155. KEY(15, 6, KEY_CAPSLOCK),
  156. KEY(15, 7, KEY_F6),
  157. /* Software Handled Function Keys */
  158. KEY(20, 0, KEY_KP7),
  159. KEY(21, 0, KEY_KP9),
  160. KEY(21, 1, KEY_KP8),
  161. KEY(21, 2, KEY_KP4),
  162. KEY(21, 4, KEY_KP1),
  163. KEY(22, 1, KEY_KPSLASH),
  164. KEY(22, 2, KEY_KP6),
  165. KEY(22, 3, KEY_KP5),
  166. KEY(22, 4, KEY_KP3),
  167. KEY(22, 5, KEY_KP2),
  168. KEY(22, 7, KEY_KP0),
  169. KEY(27, 1, KEY_KPASTERISK),
  170. KEY(27, 3, KEY_KPMINUS),
  171. KEY(27, 4, KEY_KPPLUS),
  172. KEY(27, 5, KEY_KPDOT),
  173. KEY(28, 5, KEY_VOLUMEUP),
  174. KEY(29, 3, KEY_HOME),
  175. KEY(29, 4, KEY_END),
  176. KEY(29, 5, KEY_BRIGHTNESSDOWN),
  177. KEY(29, 6, KEY_VOLUMEDOWN),
  178. KEY(29, 7, KEY_BRIGHTNESSUP),
  179. KEY(30, 0, KEY_NUMLOCK),
  180. KEY(30, 1, KEY_SCROLLLOCK),
  181. KEY(30, 2, KEY_MUTE),
  182. KEY(31, 4, KEY_HELP),
  183. };
  184. static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
  185. .keymap = tegra_kbc_default_keymap,
  186. .keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap),
  187. };
  188. static void tegra_kbc_report_released_keys(struct input_dev *input,
  189. unsigned short old_keycodes[],
  190. unsigned int old_num_keys,
  191. unsigned short new_keycodes[],
  192. unsigned int new_num_keys)
  193. {
  194. unsigned int i, j;
  195. for (i = 0; i < old_num_keys; i++) {
  196. for (j = 0; j < new_num_keys; j++)
  197. if (old_keycodes[i] == new_keycodes[j])
  198. break;
  199. if (j == new_num_keys)
  200. input_report_key(input, old_keycodes[i], 0);
  201. }
  202. }
  203. static void tegra_kbc_report_pressed_keys(struct input_dev *input,
  204. unsigned char scancodes[],
  205. unsigned short keycodes[],
  206. unsigned int num_pressed_keys)
  207. {
  208. unsigned int i;
  209. for (i = 0; i < num_pressed_keys; i++) {
  210. input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
  211. input_report_key(input, keycodes[i], 1);
  212. }
  213. }
  214. static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
  215. {
  216. unsigned char scancodes[KBC_MAX_KPENT];
  217. unsigned short keycodes[KBC_MAX_KPENT];
  218. u32 val = 0;
  219. unsigned int i;
  220. unsigned int num_down = 0;
  221. unsigned long flags;
  222. bool fn_keypress = false;
  223. bool key_in_same_row = false;
  224. bool key_in_same_col = false;
  225. spin_lock_irqsave(&kbc->lock, flags);
  226. for (i = 0; i < KBC_MAX_KPENT; i++) {
  227. if ((i % 4) == 0)
  228. val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
  229. if (val & 0x80) {
  230. unsigned int col = val & 0x07;
  231. unsigned int row = (val >> 3) & 0x0f;
  232. unsigned char scancode =
  233. MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
  234. scancodes[num_down] = scancode;
  235. keycodes[num_down] = kbc->keycode[scancode];
  236. /* If driver uses Fn map, do not report the Fn key. */
  237. if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
  238. fn_keypress = true;
  239. else
  240. num_down++;
  241. }
  242. val >>= 8;
  243. }
  244. /*
  245. * Matrix keyboard designs are prone to keyboard ghosting.
  246. * Ghosting occurs if there are 3 keys such that -
  247. * any 2 of the 3 keys share a row, and any 2 of them share a column.
  248. * If so ignore the key presses for this iteration.
  249. */
  250. if ((kbc->use_ghost_filter) && (num_down >= 3)) {
  251. for (i = 0; i < num_down; i++) {
  252. unsigned int j;
  253. u8 curr_col = scancodes[i] & 0x07;
  254. u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
  255. /*
  256. * Find 2 keys such that one key is in the same row
  257. * and the other is in the same column as the i-th key.
  258. */
  259. for (j = i + 1; j < num_down; j++) {
  260. u8 col = scancodes[j] & 0x07;
  261. u8 row = scancodes[j] >> KBC_ROW_SHIFT;
  262. if (col == curr_col)
  263. key_in_same_col = true;
  264. if (row == curr_row)
  265. key_in_same_row = true;
  266. }
  267. }
  268. }
  269. /*
  270. * If the platform uses Fn keymaps, translate keys on a Fn keypress.
  271. * Function keycodes are KBC_MAX_KEY apart from the plain keycodes.
  272. */
  273. if (fn_keypress) {
  274. for (i = 0; i < num_down; i++) {
  275. scancodes[i] += KBC_MAX_KEY;
  276. keycodes[i] = kbc->keycode[scancodes[i]];
  277. }
  278. }
  279. spin_unlock_irqrestore(&kbc->lock, flags);
  280. /* Ignore the key presses for this iteration? */
  281. if (key_in_same_col && key_in_same_row)
  282. return;
  283. tegra_kbc_report_released_keys(kbc->idev,
  284. kbc->current_keys, kbc->num_pressed_keys,
  285. keycodes, num_down);
  286. tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
  287. input_sync(kbc->idev);
  288. memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
  289. kbc->num_pressed_keys = num_down;
  290. }
  291. static void tegra_kbc_keypress_timer(unsigned long data)
  292. {
  293. struct tegra_kbc *kbc = (struct tegra_kbc *)data;
  294. unsigned long flags;
  295. u32 val;
  296. unsigned int i;
  297. val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
  298. if (val) {
  299. unsigned long dly;
  300. tegra_kbc_report_keys(kbc);
  301. /*
  302. * If more than one keys are pressed we need not wait
  303. * for the repoll delay.
  304. */
  305. dly = (val == 1) ? kbc->repoll_dly : 1;
  306. mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
  307. } else {
  308. /* Release any pressed keys and exit the polling loop */
  309. for (i = 0; i < kbc->num_pressed_keys; i++)
  310. input_report_key(kbc->idev, kbc->current_keys[i], 0);
  311. input_sync(kbc->idev);
  312. kbc->num_pressed_keys = 0;
  313. /* All keys are released so enable the keypress interrupt */
  314. spin_lock_irqsave(&kbc->lock, flags);
  315. val = readl(kbc->mmio + KBC_CONTROL_0);
  316. val |= KBC_CONTROL_FIFO_CNT_INT_EN;
  317. writel(val, kbc->mmio + KBC_CONTROL_0);
  318. spin_unlock_irqrestore(&kbc->lock, flags);
  319. }
  320. }
  321. static irqreturn_t tegra_kbc_isr(int irq, void *args)
  322. {
  323. struct tegra_kbc *kbc = args;
  324. u32 val, ctl;
  325. /*
  326. * Until all keys are released, defer further processing to
  327. * the polling loop in tegra_kbc_keypress_timer
  328. */
  329. ctl = readl(kbc->mmio + KBC_CONTROL_0);
  330. ctl &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
  331. writel(ctl, kbc->mmio + KBC_CONTROL_0);
  332. /*
  333. * Quickly bail out & reenable interrupts if the fifo threshold
  334. * count interrupt wasn't the interrupt source
  335. */
  336. val = readl(kbc->mmio + KBC_INT_0);
  337. writel(val, kbc->mmio + KBC_INT_0);
  338. if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
  339. /*
  340. * Schedule timer to run when hardware is in continuous
  341. * polling mode.
  342. */
  343. mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
  344. } else {
  345. ctl |= KBC_CONTROL_FIFO_CNT_INT_EN;
  346. writel(ctl, kbc->mmio + KBC_CONTROL_0);
  347. }
  348. return IRQ_HANDLED;
  349. }
  350. static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
  351. {
  352. const struct tegra_kbc_platform_data *pdata = kbc->pdata;
  353. int i;
  354. unsigned int rst_val;
  355. /* Either mask all keys or none. */
  356. rst_val = (filter && !pdata->wakeup) ? ~0 : 0;
  357. for (i = 0; i < KBC_MAX_ROW; i++)
  358. writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
  359. }
  360. static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
  361. {
  362. const struct tegra_kbc_platform_data *pdata = kbc->pdata;
  363. int i;
  364. for (i = 0; i < KBC_MAX_GPIO; i++) {
  365. u32 r_shft = 5 * (i % 6);
  366. u32 c_shft = 4 * (i % 8);
  367. u32 r_mask = 0x1f << r_shft;
  368. u32 c_mask = 0x0f << c_shft;
  369. u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
  370. u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
  371. u32 row_cfg = readl(kbc->mmio + r_offs);
  372. u32 col_cfg = readl(kbc->mmio + c_offs);
  373. row_cfg &= ~r_mask;
  374. col_cfg &= ~c_mask;
  375. if (pdata->pin_cfg[i].is_row)
  376. row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft;
  377. else
  378. col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft;
  379. writel(row_cfg, kbc->mmio + r_offs);
  380. writel(col_cfg, kbc->mmio + c_offs);
  381. }
  382. }
  383. static int tegra_kbc_start(struct tegra_kbc *kbc)
  384. {
  385. const struct tegra_kbc_platform_data *pdata = kbc->pdata;
  386. unsigned long flags;
  387. unsigned int debounce_cnt;
  388. u32 val = 0;
  389. clk_enable(kbc->clk);
  390. /* Reset the KBC controller to clear all previous status.*/
  391. tegra_periph_reset_assert(kbc->clk);
  392. udelay(100);
  393. tegra_periph_reset_deassert(kbc->clk);
  394. udelay(100);
  395. tegra_kbc_config_pins(kbc);
  396. tegra_kbc_setup_wakekeys(kbc, false);
  397. writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
  398. /* Keyboard debounce count is maximum of 12 bits. */
  399. debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
  400. val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
  401. val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
  402. val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
  403. val |= KBC_CONTROL_KBC_EN; /* enable */
  404. writel(val, kbc->mmio + KBC_CONTROL_0);
  405. /*
  406. * Compute the delay(ns) from interrupt mode to continuous polling
  407. * mode so the timer routine is scheduled appropriately.
  408. */
  409. val = readl(kbc->mmio + KBC_INIT_DLY_0);
  410. kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
  411. kbc->num_pressed_keys = 0;
  412. /*
  413. * Atomically clear out any remaining entries in the key FIFO
  414. * and enable keyboard interrupts.
  415. */
  416. spin_lock_irqsave(&kbc->lock, flags);
  417. while (1) {
  418. val = readl(kbc->mmio + KBC_INT_0);
  419. val >>= 4;
  420. if (!val)
  421. break;
  422. val = readl(kbc->mmio + KBC_KP_ENT0_0);
  423. val = readl(kbc->mmio + KBC_KP_ENT1_0);
  424. }
  425. writel(0x7, kbc->mmio + KBC_INT_0);
  426. spin_unlock_irqrestore(&kbc->lock, flags);
  427. enable_irq(kbc->irq);
  428. return 0;
  429. }
  430. static void tegra_kbc_stop(struct tegra_kbc *kbc)
  431. {
  432. unsigned long flags;
  433. u32 val;
  434. spin_lock_irqsave(&kbc->lock, flags);
  435. val = readl(kbc->mmio + KBC_CONTROL_0);
  436. val &= ~1;
  437. writel(val, kbc->mmio + KBC_CONTROL_0);
  438. spin_unlock_irqrestore(&kbc->lock, flags);
  439. disable_irq(kbc->irq);
  440. del_timer_sync(&kbc->timer);
  441. clk_disable(kbc->clk);
  442. }
  443. static int tegra_kbc_open(struct input_dev *dev)
  444. {
  445. struct tegra_kbc *kbc = input_get_drvdata(dev);
  446. return tegra_kbc_start(kbc);
  447. }
  448. static void tegra_kbc_close(struct input_dev *dev)
  449. {
  450. struct tegra_kbc *kbc = input_get_drvdata(dev);
  451. return tegra_kbc_stop(kbc);
  452. }
  453. static bool __devinit
  454. tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
  455. struct device *dev, unsigned int *num_rows)
  456. {
  457. int i;
  458. *num_rows = 0;
  459. for (i = 0; i < KBC_MAX_GPIO; i++) {
  460. const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];
  461. if (pin_cfg->is_row) {
  462. if (pin_cfg->num >= KBC_MAX_ROW) {
  463. dev_err(dev,
  464. "pin_cfg[%d]: invalid row number %d\n",
  465. i, pin_cfg->num);
  466. return false;
  467. }
  468. (*num_rows)++;
  469. } else {
  470. if (pin_cfg->num >= KBC_MAX_COL) {
  471. dev_err(dev,
  472. "pin_cfg[%d]: invalid column number %d\n",
  473. i, pin_cfg->num);
  474. return false;
  475. }
  476. }
  477. }
  478. return true;
  479. }
  480. static int __devinit tegra_kbc_probe(struct platform_device *pdev)
  481. {
  482. const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
  483. const struct matrix_keymap_data *keymap_data;
  484. struct tegra_kbc *kbc;
  485. struct input_dev *input_dev;
  486. struct resource *res;
  487. int irq;
  488. int err;
  489. int num_rows = 0;
  490. unsigned int debounce_cnt;
  491. unsigned int scan_time_rows;
  492. if (!pdata)
  493. return -EINVAL;
  494. if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows))
  495. return -EINVAL;
  496. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  497. if (!res) {
  498. dev_err(&pdev->dev, "failed to get I/O memory\n");
  499. return -ENXIO;
  500. }
  501. irq = platform_get_irq(pdev, 0);
  502. if (irq < 0) {
  503. dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
  504. return -ENXIO;
  505. }
  506. kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
  507. input_dev = input_allocate_device();
  508. if (!kbc || !input_dev) {
  509. err = -ENOMEM;
  510. goto err_free_mem;
  511. }
  512. kbc->pdata = pdata;
  513. kbc->idev = input_dev;
  514. kbc->irq = irq;
  515. spin_lock_init(&kbc->lock);
  516. setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
  517. res = request_mem_region(res->start, resource_size(res), pdev->name);
  518. if (!res) {
  519. dev_err(&pdev->dev, "failed to request I/O memory\n");
  520. err = -EBUSY;
  521. goto err_free_mem;
  522. }
  523. kbc->mmio = ioremap(res->start, resource_size(res));
  524. if (!kbc->mmio) {
  525. dev_err(&pdev->dev, "failed to remap I/O memory\n");
  526. err = -ENXIO;
  527. goto err_free_mem_region;
  528. }
  529. kbc->clk = clk_get(&pdev->dev, NULL);
  530. if (IS_ERR(kbc->clk)) {
  531. dev_err(&pdev->dev, "failed to get keyboard clock\n");
  532. err = PTR_ERR(kbc->clk);
  533. goto err_iounmap;
  534. }
  535. /*
  536. * The time delay between two consecutive reads of the FIFO is
  537. * the sum of the repeat time and the time taken for scanning
  538. * the rows. There is an additional delay before the row scanning
  539. * starts. The repoll delay is computed in milliseconds.
  540. */
  541. debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
  542. scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
  543. kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
  544. kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS);
  545. input_dev->name = pdev->name;
  546. input_dev->id.bustype = BUS_HOST;
  547. input_dev->dev.parent = &pdev->dev;
  548. input_dev->open = tegra_kbc_open;
  549. input_dev->close = tegra_kbc_close;
  550. input_set_drvdata(input_dev, kbc);
  551. input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP);
  552. input_set_capability(input_dev, EV_MSC, MSC_SCAN);
  553. input_dev->keycode = kbc->keycode;
  554. input_dev->keycodesize = sizeof(kbc->keycode[0]);
  555. input_dev->keycodemax = KBC_MAX_KEY;
  556. if (pdata->use_fn_map)
  557. input_dev->keycodemax *= 2;
  558. kbc->use_fn_map = pdata->use_fn_map;
  559. kbc->use_ghost_filter = pdata->use_ghost_filter;
  560. keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
  561. matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
  562. input_dev->keycode, input_dev->keybit);
  563. err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH,
  564. pdev->name, kbc);
  565. if (err) {
  566. dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
  567. goto err_put_clk;
  568. }
  569. disable_irq(kbc->irq);
  570. err = input_register_device(kbc->idev);
  571. if (err) {
  572. dev_err(&pdev->dev, "failed to register input device\n");
  573. goto err_free_irq;
  574. }
  575. platform_set_drvdata(pdev, kbc);
  576. device_init_wakeup(&pdev->dev, pdata->wakeup);
  577. return 0;
  578. err_free_irq:
  579. free_irq(kbc->irq, pdev);
  580. err_put_clk:
  581. clk_put(kbc->clk);
  582. err_iounmap:
  583. iounmap(kbc->mmio);
  584. err_free_mem_region:
  585. release_mem_region(res->start, resource_size(res));
  586. err_free_mem:
  587. input_free_device(kbc->idev);
  588. kfree(kbc);
  589. return err;
  590. }
  591. static int __devexit tegra_kbc_remove(struct platform_device *pdev)
  592. {
  593. struct tegra_kbc *kbc = platform_get_drvdata(pdev);
  594. struct resource *res;
  595. free_irq(kbc->irq, pdev);
  596. clk_put(kbc->clk);
  597. input_unregister_device(kbc->idev);
  598. iounmap(kbc->mmio);
  599. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  600. release_mem_region(res->start, resource_size(res));
  601. kfree(kbc);
  602. platform_set_drvdata(pdev, NULL);
  603. return 0;
  604. }
  605. #ifdef CONFIG_PM_SLEEP
  606. static int tegra_kbc_suspend(struct device *dev)
  607. {
  608. struct platform_device *pdev = to_platform_device(dev);
  609. struct tegra_kbc *kbc = platform_get_drvdata(pdev);
  610. if (device_may_wakeup(&pdev->dev)) {
  611. tegra_kbc_setup_wakekeys(kbc, true);
  612. enable_irq_wake(kbc->irq);
  613. /* Forcefully clear the interrupt status */
  614. writel(0x7, kbc->mmio + KBC_INT_0);
  615. msleep(30);
  616. } else {
  617. mutex_lock(&kbc->idev->mutex);
  618. if (kbc->idev->users)
  619. tegra_kbc_stop(kbc);
  620. mutex_unlock(&kbc->idev->mutex);
  621. }
  622. return 0;
  623. }
  624. static int tegra_kbc_resume(struct device *dev)
  625. {
  626. struct platform_device *pdev = to_platform_device(dev);
  627. struct tegra_kbc *kbc = platform_get_drvdata(pdev);
  628. int err = 0;
  629. if (device_may_wakeup(&pdev->dev)) {
  630. disable_irq_wake(kbc->irq);
  631. tegra_kbc_setup_wakekeys(kbc, false);
  632. } else {
  633. mutex_lock(&kbc->idev->mutex);
  634. if (kbc->idev->users)
  635. err = tegra_kbc_start(kbc);
  636. mutex_unlock(&kbc->idev->mutex);
  637. }
  638. return err;
  639. }
  640. #endif
  641. static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
  642. static struct platform_driver tegra_kbc_driver = {
  643. .probe = tegra_kbc_probe,
  644. .remove = __devexit_p(tegra_kbc_remove),
  645. .driver = {
  646. .name = "tegra-kbc",
  647. .owner = THIS_MODULE,
  648. .pm = &tegra_kbc_pm_ops,
  649. },
  650. };
  651. static void __exit tegra_kbc_exit(void)
  652. {
  653. platform_driver_unregister(&tegra_kbc_driver);
  654. }
  655. module_exit(tegra_kbc_exit);
  656. static int __init tegra_kbc_init(void)
  657. {
  658. return platform_driver_register(&tegra_kbc_driver);
  659. }
  660. module_init(tegra_kbc_init);
  661. MODULE_LICENSE("GPL");
  662. MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
  663. MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
  664. MODULE_ALIAS("platform:tegra-kbc");