radeon_ttm.c 22 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <ttm/ttm_bo_api.h>
  33. #include <ttm/ttm_bo_driver.h>
  34. #include <ttm/ttm_placement.h>
  35. #include <ttm/ttm_module.h>
  36. #include <ttm/ttm_page_alloc.h>
  37. #include <drm/drmP.h>
  38. #include <drm/radeon_drm.h>
  39. #include <linux/seq_file.h>
  40. #include <linux/slab.h>
  41. #include "radeon_reg.h"
  42. #include "radeon.h"
  43. #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  44. static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  45. static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  46. {
  47. struct radeon_mman *mman;
  48. struct radeon_device *rdev;
  49. mman = container_of(bdev, struct radeon_mman, bdev);
  50. rdev = container_of(mman, struct radeon_device, mman);
  51. return rdev;
  52. }
  53. /*
  54. * Global memory.
  55. */
  56. static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  57. {
  58. return ttm_mem_global_init(ref->object);
  59. }
  60. static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  61. {
  62. ttm_mem_global_release(ref->object);
  63. }
  64. static int radeon_ttm_global_init(struct radeon_device *rdev)
  65. {
  66. struct drm_global_reference *global_ref;
  67. int r;
  68. rdev->mman.mem_global_referenced = false;
  69. global_ref = &rdev->mman.mem_global_ref;
  70. global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  71. global_ref->size = sizeof(struct ttm_mem_global);
  72. global_ref->init = &radeon_ttm_mem_global_init;
  73. global_ref->release = &radeon_ttm_mem_global_release;
  74. r = drm_global_item_ref(global_ref);
  75. if (r != 0) {
  76. DRM_ERROR("Failed setting up TTM memory accounting "
  77. "subsystem.\n");
  78. return r;
  79. }
  80. rdev->mman.bo_global_ref.mem_glob =
  81. rdev->mman.mem_global_ref.object;
  82. global_ref = &rdev->mman.bo_global_ref.ref;
  83. global_ref->global_type = DRM_GLOBAL_TTM_BO;
  84. global_ref->size = sizeof(struct ttm_bo_global);
  85. global_ref->init = &ttm_bo_global_init;
  86. global_ref->release = &ttm_bo_global_release;
  87. r = drm_global_item_ref(global_ref);
  88. if (r != 0) {
  89. DRM_ERROR("Failed setting up TTM BO subsystem.\n");
  90. drm_global_item_unref(&rdev->mman.mem_global_ref);
  91. return r;
  92. }
  93. rdev->mman.mem_global_referenced = true;
  94. return 0;
  95. }
  96. static void radeon_ttm_global_fini(struct radeon_device *rdev)
  97. {
  98. if (rdev->mman.mem_global_referenced) {
  99. drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
  100. drm_global_item_unref(&rdev->mman.mem_global_ref);
  101. rdev->mman.mem_global_referenced = false;
  102. }
  103. }
  104. struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev);
  105. static struct ttm_backend*
  106. radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev)
  107. {
  108. struct radeon_device *rdev;
  109. rdev = radeon_get_rdev(bdev);
  110. #if __OS_HAS_AGP
  111. if (rdev->flags & RADEON_IS_AGP) {
  112. return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge);
  113. } else
  114. #endif
  115. {
  116. return radeon_ttm_backend_create(rdev);
  117. }
  118. }
  119. static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  120. {
  121. return 0;
  122. }
  123. static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  124. struct ttm_mem_type_manager *man)
  125. {
  126. struct radeon_device *rdev;
  127. rdev = radeon_get_rdev(bdev);
  128. switch (type) {
  129. case TTM_PL_SYSTEM:
  130. /* System memory */
  131. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  132. man->available_caching = TTM_PL_MASK_CACHING;
  133. man->default_caching = TTM_PL_FLAG_CACHED;
  134. break;
  135. case TTM_PL_TT:
  136. man->func = &ttm_bo_manager_func;
  137. man->gpu_offset = rdev->mc.gtt_start;
  138. man->available_caching = TTM_PL_MASK_CACHING;
  139. man->default_caching = TTM_PL_FLAG_CACHED;
  140. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
  141. #if __OS_HAS_AGP
  142. if (rdev->flags & RADEON_IS_AGP) {
  143. if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
  144. DRM_ERROR("AGP is not enabled for memory type %u\n",
  145. (unsigned)type);
  146. return -EINVAL;
  147. }
  148. if (!rdev->ddev->agp->cant_use_aperture)
  149. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  150. man->available_caching = TTM_PL_FLAG_UNCACHED |
  151. TTM_PL_FLAG_WC;
  152. man->default_caching = TTM_PL_FLAG_WC;
  153. }
  154. #endif
  155. break;
  156. case TTM_PL_VRAM:
  157. /* "On-card" video ram */
  158. man->func = &ttm_bo_manager_func;
  159. man->gpu_offset = rdev->mc.vram_start;
  160. man->flags = TTM_MEMTYPE_FLAG_FIXED |
  161. TTM_MEMTYPE_FLAG_MAPPABLE;
  162. man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
  163. man->default_caching = TTM_PL_FLAG_WC;
  164. break;
  165. default:
  166. DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
  167. return -EINVAL;
  168. }
  169. return 0;
  170. }
  171. static void radeon_evict_flags(struct ttm_buffer_object *bo,
  172. struct ttm_placement *placement)
  173. {
  174. struct radeon_bo *rbo;
  175. static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  176. if (!radeon_ttm_bo_is_radeon_bo(bo)) {
  177. placement->fpfn = 0;
  178. placement->lpfn = 0;
  179. placement->placement = &placements;
  180. placement->busy_placement = &placements;
  181. placement->num_placement = 1;
  182. placement->num_busy_placement = 1;
  183. return;
  184. }
  185. rbo = container_of(bo, struct radeon_bo, tbo);
  186. switch (bo->mem.mem_type) {
  187. case TTM_PL_VRAM:
  188. if (rbo->rdev->cp.ready == false)
  189. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
  190. else
  191. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
  192. break;
  193. case TTM_PL_TT:
  194. default:
  195. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
  196. }
  197. *placement = rbo->placement;
  198. }
  199. static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  200. {
  201. return 0;
  202. }
  203. static void radeon_move_null(struct ttm_buffer_object *bo,
  204. struct ttm_mem_reg *new_mem)
  205. {
  206. struct ttm_mem_reg *old_mem = &bo->mem;
  207. BUG_ON(old_mem->mm_node != NULL);
  208. *old_mem = *new_mem;
  209. new_mem->mm_node = NULL;
  210. }
  211. static int radeon_move_blit(struct ttm_buffer_object *bo,
  212. bool evict, int no_wait_reserve, bool no_wait_gpu,
  213. struct ttm_mem_reg *new_mem,
  214. struct ttm_mem_reg *old_mem)
  215. {
  216. struct radeon_device *rdev;
  217. uint64_t old_start, new_start;
  218. struct radeon_fence *fence;
  219. int r;
  220. rdev = radeon_get_rdev(bo->bdev);
  221. r = radeon_fence_create(rdev, &fence);
  222. if (unlikely(r)) {
  223. return r;
  224. }
  225. old_start = old_mem->start << PAGE_SHIFT;
  226. new_start = new_mem->start << PAGE_SHIFT;
  227. switch (old_mem->mem_type) {
  228. case TTM_PL_VRAM:
  229. old_start += rdev->mc.vram_start;
  230. break;
  231. case TTM_PL_TT:
  232. old_start += rdev->mc.gtt_start;
  233. break;
  234. default:
  235. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  236. return -EINVAL;
  237. }
  238. switch (new_mem->mem_type) {
  239. case TTM_PL_VRAM:
  240. new_start += rdev->mc.vram_start;
  241. break;
  242. case TTM_PL_TT:
  243. new_start += rdev->mc.gtt_start;
  244. break;
  245. default:
  246. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  247. return -EINVAL;
  248. }
  249. if (!rdev->cp.ready) {
  250. DRM_ERROR("Trying to move memory with CP turned off.\n");
  251. return -EINVAL;
  252. }
  253. r = radeon_copy(rdev, old_start, new_start, new_mem->num_pages, fence);
  254. /* FIXME: handle copy error */
  255. r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
  256. evict, no_wait_reserve, no_wait_gpu, new_mem);
  257. radeon_fence_unref(&fence);
  258. return r;
  259. }
  260. static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
  261. bool evict, bool interruptible,
  262. bool no_wait_reserve, bool no_wait_gpu,
  263. struct ttm_mem_reg *new_mem)
  264. {
  265. struct radeon_device *rdev;
  266. struct ttm_mem_reg *old_mem = &bo->mem;
  267. struct ttm_mem_reg tmp_mem;
  268. u32 placements;
  269. struct ttm_placement placement;
  270. int r;
  271. rdev = radeon_get_rdev(bo->bdev);
  272. tmp_mem = *new_mem;
  273. tmp_mem.mm_node = NULL;
  274. placement.fpfn = 0;
  275. placement.lpfn = 0;
  276. placement.num_placement = 1;
  277. placement.placement = &placements;
  278. placement.num_busy_placement = 1;
  279. placement.busy_placement = &placements;
  280. placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  281. r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
  282. interruptible, no_wait_reserve, no_wait_gpu);
  283. if (unlikely(r)) {
  284. return r;
  285. }
  286. r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
  287. if (unlikely(r)) {
  288. goto out_cleanup;
  289. }
  290. r = ttm_tt_bind(bo->ttm, &tmp_mem);
  291. if (unlikely(r)) {
  292. goto out_cleanup;
  293. }
  294. r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem);
  295. if (unlikely(r)) {
  296. goto out_cleanup;
  297. }
  298. r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
  299. out_cleanup:
  300. ttm_bo_mem_put(bo, &tmp_mem);
  301. return r;
  302. }
  303. static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
  304. bool evict, bool interruptible,
  305. bool no_wait_reserve, bool no_wait_gpu,
  306. struct ttm_mem_reg *new_mem)
  307. {
  308. struct radeon_device *rdev;
  309. struct ttm_mem_reg *old_mem = &bo->mem;
  310. struct ttm_mem_reg tmp_mem;
  311. struct ttm_placement placement;
  312. u32 placements;
  313. int r;
  314. rdev = radeon_get_rdev(bo->bdev);
  315. tmp_mem = *new_mem;
  316. tmp_mem.mm_node = NULL;
  317. placement.fpfn = 0;
  318. placement.lpfn = 0;
  319. placement.num_placement = 1;
  320. placement.placement = &placements;
  321. placement.num_busy_placement = 1;
  322. placement.busy_placement = &placements;
  323. placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  324. r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu);
  325. if (unlikely(r)) {
  326. return r;
  327. }
  328. r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
  329. if (unlikely(r)) {
  330. goto out_cleanup;
  331. }
  332. r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
  333. if (unlikely(r)) {
  334. goto out_cleanup;
  335. }
  336. out_cleanup:
  337. ttm_bo_mem_put(bo, &tmp_mem);
  338. return r;
  339. }
  340. static int radeon_bo_move(struct ttm_buffer_object *bo,
  341. bool evict, bool interruptible,
  342. bool no_wait_reserve, bool no_wait_gpu,
  343. struct ttm_mem_reg *new_mem)
  344. {
  345. struct radeon_device *rdev;
  346. struct ttm_mem_reg *old_mem = &bo->mem;
  347. int r;
  348. rdev = radeon_get_rdev(bo->bdev);
  349. if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
  350. radeon_move_null(bo, new_mem);
  351. return 0;
  352. }
  353. if ((old_mem->mem_type == TTM_PL_TT &&
  354. new_mem->mem_type == TTM_PL_SYSTEM) ||
  355. (old_mem->mem_type == TTM_PL_SYSTEM &&
  356. new_mem->mem_type == TTM_PL_TT)) {
  357. /* bind is enough */
  358. radeon_move_null(bo, new_mem);
  359. return 0;
  360. }
  361. if (!rdev->cp.ready || rdev->asic->copy == NULL) {
  362. /* use memcpy */
  363. goto memcpy;
  364. }
  365. if (old_mem->mem_type == TTM_PL_VRAM &&
  366. new_mem->mem_type == TTM_PL_SYSTEM) {
  367. r = radeon_move_vram_ram(bo, evict, interruptible,
  368. no_wait_reserve, no_wait_gpu, new_mem);
  369. } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
  370. new_mem->mem_type == TTM_PL_VRAM) {
  371. r = radeon_move_ram_vram(bo, evict, interruptible,
  372. no_wait_reserve, no_wait_gpu, new_mem);
  373. } else {
  374. r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
  375. }
  376. if (r) {
  377. memcpy:
  378. r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
  379. }
  380. return r;
  381. }
  382. static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  383. {
  384. struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
  385. struct radeon_device *rdev = radeon_get_rdev(bdev);
  386. mem->bus.addr = NULL;
  387. mem->bus.offset = 0;
  388. mem->bus.size = mem->num_pages << PAGE_SHIFT;
  389. mem->bus.base = 0;
  390. mem->bus.is_iomem = false;
  391. if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
  392. return -EINVAL;
  393. switch (mem->mem_type) {
  394. case TTM_PL_SYSTEM:
  395. /* system memory */
  396. return 0;
  397. case TTM_PL_TT:
  398. #if __OS_HAS_AGP
  399. if (rdev->flags & RADEON_IS_AGP) {
  400. /* RADEON_IS_AGP is set only if AGP is active */
  401. mem->bus.offset = mem->start << PAGE_SHIFT;
  402. mem->bus.base = rdev->mc.agp_base;
  403. mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
  404. }
  405. #endif
  406. break;
  407. case TTM_PL_VRAM:
  408. mem->bus.offset = mem->start << PAGE_SHIFT;
  409. /* check if it's visible */
  410. if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
  411. return -EINVAL;
  412. mem->bus.base = rdev->mc.aper_base;
  413. mem->bus.is_iomem = true;
  414. break;
  415. default:
  416. return -EINVAL;
  417. }
  418. return 0;
  419. }
  420. static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  421. {
  422. }
  423. static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
  424. bool lazy, bool interruptible)
  425. {
  426. return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
  427. }
  428. static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
  429. {
  430. return 0;
  431. }
  432. static void radeon_sync_obj_unref(void **sync_obj)
  433. {
  434. radeon_fence_unref((struct radeon_fence **)sync_obj);
  435. }
  436. static void *radeon_sync_obj_ref(void *sync_obj)
  437. {
  438. return radeon_fence_ref((struct radeon_fence *)sync_obj);
  439. }
  440. static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
  441. {
  442. return radeon_fence_signaled((struct radeon_fence *)sync_obj);
  443. }
  444. static struct ttm_bo_driver radeon_bo_driver = {
  445. .create_ttm_backend_entry = &radeon_create_ttm_backend_entry,
  446. .invalidate_caches = &radeon_invalidate_caches,
  447. .init_mem_type = &radeon_init_mem_type,
  448. .evict_flags = &radeon_evict_flags,
  449. .move = &radeon_bo_move,
  450. .verify_access = &radeon_verify_access,
  451. .sync_obj_signaled = &radeon_sync_obj_signaled,
  452. .sync_obj_wait = &radeon_sync_obj_wait,
  453. .sync_obj_flush = &radeon_sync_obj_flush,
  454. .sync_obj_unref = &radeon_sync_obj_unref,
  455. .sync_obj_ref = &radeon_sync_obj_ref,
  456. .move_notify = &radeon_bo_move_notify,
  457. .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
  458. .io_mem_reserve = &radeon_ttm_io_mem_reserve,
  459. .io_mem_free = &radeon_ttm_io_mem_free,
  460. };
  461. int radeon_ttm_init(struct radeon_device *rdev)
  462. {
  463. int r;
  464. r = radeon_ttm_global_init(rdev);
  465. if (r) {
  466. return r;
  467. }
  468. /* No others user of address space so set it to 0 */
  469. r = ttm_bo_device_init(&rdev->mman.bdev,
  470. rdev->mman.bo_global_ref.ref.object,
  471. &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
  472. rdev->need_dma32);
  473. if (r) {
  474. DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
  475. return r;
  476. }
  477. rdev->mman.initialized = true;
  478. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
  479. rdev->mc.real_vram_size >> PAGE_SHIFT);
  480. if (r) {
  481. DRM_ERROR("Failed initializing VRAM heap.\n");
  482. return r;
  483. }
  484. r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
  485. RADEON_GEM_DOMAIN_VRAM,
  486. &rdev->stollen_vga_memory);
  487. if (r) {
  488. return r;
  489. }
  490. r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
  491. if (r)
  492. return r;
  493. r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
  494. radeon_bo_unreserve(rdev->stollen_vga_memory);
  495. if (r) {
  496. radeon_bo_unref(&rdev->stollen_vga_memory);
  497. return r;
  498. }
  499. DRM_INFO("radeon: %uM of VRAM memory ready\n",
  500. (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
  501. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
  502. rdev->mc.gtt_size >> PAGE_SHIFT);
  503. if (r) {
  504. DRM_ERROR("Failed initializing GTT heap.\n");
  505. return r;
  506. }
  507. DRM_INFO("radeon: %uM of GTT memory ready.\n",
  508. (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
  509. if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  510. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  511. }
  512. r = radeon_ttm_debugfs_init(rdev);
  513. if (r) {
  514. DRM_ERROR("Failed to init debugfs\n");
  515. return r;
  516. }
  517. return 0;
  518. }
  519. void radeon_ttm_fini(struct radeon_device *rdev)
  520. {
  521. int r;
  522. if (!rdev->mman.initialized)
  523. return;
  524. if (rdev->stollen_vga_memory) {
  525. r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
  526. if (r == 0) {
  527. radeon_bo_unpin(rdev->stollen_vga_memory);
  528. radeon_bo_unreserve(rdev->stollen_vga_memory);
  529. }
  530. radeon_bo_unref(&rdev->stollen_vga_memory);
  531. }
  532. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  533. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
  534. ttm_bo_device_release(&rdev->mman.bdev);
  535. radeon_gart_fini(rdev);
  536. radeon_ttm_global_fini(rdev);
  537. rdev->mman.initialized = false;
  538. DRM_INFO("radeon: ttm finalized\n");
  539. }
  540. /* this should only be called at bootup or when userspace
  541. * isn't running */
  542. void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
  543. {
  544. struct ttm_mem_type_manager *man;
  545. if (!rdev->mman.initialized)
  546. return;
  547. man = &rdev->mman.bdev.man[TTM_PL_VRAM];
  548. /* this just adjusts TTM size idea, which sets lpfn to the correct value */
  549. man->size = size >> PAGE_SHIFT;
  550. }
  551. static struct vm_operations_struct radeon_ttm_vm_ops;
  552. static const struct vm_operations_struct *ttm_vm_ops = NULL;
  553. static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
  554. {
  555. struct ttm_buffer_object *bo;
  556. struct radeon_device *rdev;
  557. int r;
  558. bo = (struct ttm_buffer_object *)vma->vm_private_data;
  559. if (bo == NULL) {
  560. return VM_FAULT_NOPAGE;
  561. }
  562. rdev = radeon_get_rdev(bo->bdev);
  563. mutex_lock(&rdev->vram_mutex);
  564. r = ttm_vm_ops->fault(vma, vmf);
  565. mutex_unlock(&rdev->vram_mutex);
  566. return r;
  567. }
  568. int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
  569. {
  570. struct drm_file *file_priv;
  571. struct radeon_device *rdev;
  572. int r;
  573. if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
  574. return drm_mmap(filp, vma);
  575. }
  576. file_priv = filp->private_data;
  577. rdev = file_priv->minor->dev->dev_private;
  578. if (rdev == NULL) {
  579. return -EINVAL;
  580. }
  581. r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
  582. if (unlikely(r != 0)) {
  583. return r;
  584. }
  585. if (unlikely(ttm_vm_ops == NULL)) {
  586. ttm_vm_ops = vma->vm_ops;
  587. radeon_ttm_vm_ops = *ttm_vm_ops;
  588. radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
  589. }
  590. vma->vm_ops = &radeon_ttm_vm_ops;
  591. return 0;
  592. }
  593. /*
  594. * TTM backend functions.
  595. */
  596. struct radeon_ttm_backend {
  597. struct ttm_backend backend;
  598. struct radeon_device *rdev;
  599. unsigned long num_pages;
  600. struct page **pages;
  601. struct page *dummy_read_page;
  602. dma_addr_t *dma_addrs;
  603. bool populated;
  604. bool bound;
  605. unsigned offset;
  606. };
  607. static int radeon_ttm_backend_populate(struct ttm_backend *backend,
  608. unsigned long num_pages,
  609. struct page **pages,
  610. struct page *dummy_read_page,
  611. dma_addr_t *dma_addrs)
  612. {
  613. struct radeon_ttm_backend *gtt;
  614. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  615. gtt->pages = pages;
  616. gtt->dma_addrs = dma_addrs;
  617. gtt->num_pages = num_pages;
  618. gtt->dummy_read_page = dummy_read_page;
  619. gtt->populated = true;
  620. return 0;
  621. }
  622. static void radeon_ttm_backend_clear(struct ttm_backend *backend)
  623. {
  624. struct radeon_ttm_backend *gtt;
  625. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  626. gtt->pages = NULL;
  627. gtt->dma_addrs = NULL;
  628. gtt->num_pages = 0;
  629. gtt->dummy_read_page = NULL;
  630. gtt->populated = false;
  631. gtt->bound = false;
  632. }
  633. static int radeon_ttm_backend_bind(struct ttm_backend *backend,
  634. struct ttm_mem_reg *bo_mem)
  635. {
  636. struct radeon_ttm_backend *gtt;
  637. int r;
  638. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  639. gtt->offset = bo_mem->start << PAGE_SHIFT;
  640. if (!gtt->num_pages) {
  641. WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
  642. gtt->num_pages, bo_mem, backend);
  643. }
  644. r = radeon_gart_bind(gtt->rdev, gtt->offset,
  645. gtt->num_pages, gtt->pages, gtt->dma_addrs);
  646. if (r) {
  647. DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
  648. gtt->num_pages, gtt->offset);
  649. return r;
  650. }
  651. gtt->bound = true;
  652. return 0;
  653. }
  654. static int radeon_ttm_backend_unbind(struct ttm_backend *backend)
  655. {
  656. struct radeon_ttm_backend *gtt;
  657. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  658. radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages);
  659. gtt->bound = false;
  660. return 0;
  661. }
  662. static void radeon_ttm_backend_destroy(struct ttm_backend *backend)
  663. {
  664. struct radeon_ttm_backend *gtt;
  665. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  666. if (gtt->bound) {
  667. radeon_ttm_backend_unbind(backend);
  668. }
  669. kfree(gtt);
  670. }
  671. static struct ttm_backend_func radeon_backend_func = {
  672. .populate = &radeon_ttm_backend_populate,
  673. .clear = &radeon_ttm_backend_clear,
  674. .bind = &radeon_ttm_backend_bind,
  675. .unbind = &radeon_ttm_backend_unbind,
  676. .destroy = &radeon_ttm_backend_destroy,
  677. };
  678. struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
  679. {
  680. struct radeon_ttm_backend *gtt;
  681. gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL);
  682. if (gtt == NULL) {
  683. return NULL;
  684. }
  685. gtt->backend.bdev = &rdev->mman.bdev;
  686. gtt->backend.flags = 0;
  687. gtt->backend.func = &radeon_backend_func;
  688. gtt->rdev = rdev;
  689. gtt->pages = NULL;
  690. gtt->num_pages = 0;
  691. gtt->dummy_read_page = NULL;
  692. gtt->populated = false;
  693. gtt->bound = false;
  694. return &gtt->backend;
  695. }
  696. #define RADEON_DEBUGFS_MEM_TYPES 2
  697. #if defined(CONFIG_DEBUG_FS)
  698. static int radeon_mm_dump_table(struct seq_file *m, void *data)
  699. {
  700. struct drm_info_node *node = (struct drm_info_node *)m->private;
  701. struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
  702. struct drm_device *dev = node->minor->dev;
  703. struct radeon_device *rdev = dev->dev_private;
  704. int ret;
  705. struct ttm_bo_global *glob = rdev->mman.bdev.glob;
  706. spin_lock(&glob->lru_lock);
  707. ret = drm_mm_dump_table(m, mm);
  708. spin_unlock(&glob->lru_lock);
  709. return ret;
  710. }
  711. #endif
  712. static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
  713. {
  714. #if defined(CONFIG_DEBUG_FS)
  715. static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+1];
  716. static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+1][32];
  717. unsigned i;
  718. for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
  719. if (i == 0)
  720. sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
  721. else
  722. sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
  723. radeon_mem_types_list[i].name = radeon_mem_types_names[i];
  724. radeon_mem_types_list[i].show = &radeon_mm_dump_table;
  725. radeon_mem_types_list[i].driver_features = 0;
  726. if (i == 0)
  727. radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
  728. else
  729. radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
  730. }
  731. /* Add ttm page pool to debugfs */
  732. sprintf(radeon_mem_types_names[i], "ttm_page_pool");
  733. radeon_mem_types_list[i].name = radeon_mem_types_names[i];
  734. radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs;
  735. radeon_mem_types_list[i].driver_features = 0;
  736. radeon_mem_types_list[i].data = NULL;
  737. return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES+1);
  738. #endif
  739. return 0;
  740. }