radeon_fence.c 12 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <linux/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. #include "radeon_trace.h"
  42. static void radeon_fence_write(struct radeon_device *rdev, u32 seq)
  43. {
  44. if (rdev->wb.enabled) {
  45. u32 scratch_index;
  46. if (rdev->wb.use_event)
  47. scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  48. else
  49. scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  50. rdev->wb.wb[scratch_index/4] = cpu_to_le32(seq);;
  51. } else
  52. WREG32(rdev->fence_drv.scratch_reg, seq);
  53. }
  54. static u32 radeon_fence_read(struct radeon_device *rdev)
  55. {
  56. u32 seq;
  57. if (rdev->wb.enabled) {
  58. u32 scratch_index;
  59. if (rdev->wb.use_event)
  60. scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  61. else
  62. scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  63. seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
  64. } else
  65. seq = RREG32(rdev->fence_drv.scratch_reg);
  66. return seq;
  67. }
  68. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  69. {
  70. unsigned long irq_flags;
  71. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  72. if (fence->emited) {
  73. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  74. return 0;
  75. }
  76. fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
  77. if (!rdev->cp.ready)
  78. /* FIXME: cp is not running assume everythings is done right
  79. * away
  80. */
  81. radeon_fence_write(rdev, fence->seq);
  82. else
  83. radeon_fence_ring_emit(rdev, fence);
  84. trace_radeon_fence_emit(rdev->ddev, fence->seq);
  85. fence->emited = true;
  86. list_move_tail(&fence->list, &rdev->fence_drv.emited);
  87. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  88. return 0;
  89. }
  90. static bool radeon_fence_poll_locked(struct radeon_device *rdev)
  91. {
  92. struct radeon_fence *fence;
  93. struct list_head *i, *n;
  94. uint32_t seq;
  95. bool wake = false;
  96. unsigned long cjiffies;
  97. seq = radeon_fence_read(rdev);
  98. if (seq != rdev->fence_drv.last_seq) {
  99. rdev->fence_drv.last_seq = seq;
  100. rdev->fence_drv.last_jiffies = jiffies;
  101. rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  102. } else {
  103. cjiffies = jiffies;
  104. if (time_after(cjiffies, rdev->fence_drv.last_jiffies)) {
  105. cjiffies -= rdev->fence_drv.last_jiffies;
  106. if (time_after(rdev->fence_drv.last_timeout, cjiffies)) {
  107. /* update the timeout */
  108. rdev->fence_drv.last_timeout -= cjiffies;
  109. } else {
  110. /* the 500ms timeout is elapsed we should test
  111. * for GPU lockup
  112. */
  113. rdev->fence_drv.last_timeout = 1;
  114. }
  115. } else {
  116. /* wrap around update last jiffies, we will just wait
  117. * a little longer
  118. */
  119. rdev->fence_drv.last_jiffies = cjiffies;
  120. }
  121. return false;
  122. }
  123. n = NULL;
  124. list_for_each(i, &rdev->fence_drv.emited) {
  125. fence = list_entry(i, struct radeon_fence, list);
  126. if (fence->seq == seq) {
  127. n = i;
  128. break;
  129. }
  130. }
  131. /* all fence previous to this one are considered as signaled */
  132. if (n) {
  133. i = n;
  134. do {
  135. n = i->prev;
  136. list_move_tail(i, &rdev->fence_drv.signaled);
  137. fence = list_entry(i, struct radeon_fence, list);
  138. fence->signaled = true;
  139. i = n;
  140. } while (i != &rdev->fence_drv.emited);
  141. wake = true;
  142. }
  143. return wake;
  144. }
  145. static void radeon_fence_destroy(struct kref *kref)
  146. {
  147. unsigned long irq_flags;
  148. struct radeon_fence *fence;
  149. fence = container_of(kref, struct radeon_fence, kref);
  150. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  151. list_del(&fence->list);
  152. fence->emited = false;
  153. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  154. kfree(fence);
  155. }
  156. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
  157. {
  158. unsigned long irq_flags;
  159. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  160. if ((*fence) == NULL) {
  161. return -ENOMEM;
  162. }
  163. kref_init(&((*fence)->kref));
  164. (*fence)->rdev = rdev;
  165. (*fence)->emited = false;
  166. (*fence)->signaled = false;
  167. (*fence)->seq = 0;
  168. INIT_LIST_HEAD(&(*fence)->list);
  169. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  170. list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
  171. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  172. return 0;
  173. }
  174. bool radeon_fence_signaled(struct radeon_fence *fence)
  175. {
  176. unsigned long irq_flags;
  177. bool signaled = false;
  178. if (!fence)
  179. return true;
  180. if (fence->rdev->gpu_lockup)
  181. return true;
  182. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  183. signaled = fence->signaled;
  184. /* if we are shuting down report all fence as signaled */
  185. if (fence->rdev->shutdown) {
  186. signaled = true;
  187. }
  188. if (!fence->emited) {
  189. WARN(1, "Querying an unemited fence : %p !\n", fence);
  190. signaled = true;
  191. }
  192. if (!signaled) {
  193. radeon_fence_poll_locked(fence->rdev);
  194. signaled = fence->signaled;
  195. }
  196. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  197. return signaled;
  198. }
  199. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  200. {
  201. struct radeon_device *rdev;
  202. unsigned long irq_flags, timeout;
  203. u32 seq;
  204. int r;
  205. if (fence == NULL) {
  206. WARN(1, "Querying an invalid fence : %p !\n", fence);
  207. return 0;
  208. }
  209. rdev = fence->rdev;
  210. if (radeon_fence_signaled(fence)) {
  211. return 0;
  212. }
  213. timeout = rdev->fence_drv.last_timeout;
  214. retry:
  215. /* save current sequence used to check for GPU lockup */
  216. seq = rdev->fence_drv.last_seq;
  217. trace_radeon_fence_wait_begin(rdev->ddev, seq);
  218. if (intr) {
  219. radeon_irq_kms_sw_irq_get(rdev);
  220. r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
  221. radeon_fence_signaled(fence), timeout);
  222. radeon_irq_kms_sw_irq_put(rdev);
  223. if (unlikely(r < 0)) {
  224. return r;
  225. }
  226. } else {
  227. radeon_irq_kms_sw_irq_get(rdev);
  228. r = wait_event_timeout(rdev->fence_drv.queue,
  229. radeon_fence_signaled(fence), timeout);
  230. radeon_irq_kms_sw_irq_put(rdev);
  231. }
  232. trace_radeon_fence_wait_end(rdev->ddev, seq);
  233. if (unlikely(!radeon_fence_signaled(fence))) {
  234. /* we were interrupted for some reason and fence isn't
  235. * isn't signaled yet, resume wait
  236. */
  237. if (r) {
  238. timeout = r;
  239. goto retry;
  240. }
  241. /* don't protect read access to rdev->fence_drv.last_seq
  242. * if we experiencing a lockup the value doesn't change
  243. */
  244. if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) {
  245. /* good news we believe it's a lockup */
  246. WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
  247. fence->seq, seq);
  248. /* FIXME: what should we do ? marking everyone
  249. * as signaled for now
  250. */
  251. rdev->gpu_lockup = true;
  252. r = radeon_gpu_reset(rdev);
  253. if (r)
  254. return r;
  255. radeon_fence_write(rdev, fence->seq);
  256. rdev->gpu_lockup = false;
  257. }
  258. timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  259. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  260. rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  261. rdev->fence_drv.last_jiffies = jiffies;
  262. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  263. goto retry;
  264. }
  265. return 0;
  266. }
  267. int radeon_fence_wait_next(struct radeon_device *rdev)
  268. {
  269. unsigned long irq_flags;
  270. struct radeon_fence *fence;
  271. int r;
  272. if (rdev->gpu_lockup) {
  273. return 0;
  274. }
  275. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  276. if (list_empty(&rdev->fence_drv.emited)) {
  277. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  278. return 0;
  279. }
  280. fence = list_entry(rdev->fence_drv.emited.next,
  281. struct radeon_fence, list);
  282. radeon_fence_ref(fence);
  283. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  284. r = radeon_fence_wait(fence, false);
  285. radeon_fence_unref(&fence);
  286. return r;
  287. }
  288. int radeon_fence_wait_last(struct radeon_device *rdev)
  289. {
  290. unsigned long irq_flags;
  291. struct radeon_fence *fence;
  292. int r;
  293. if (rdev->gpu_lockup) {
  294. return 0;
  295. }
  296. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  297. if (list_empty(&rdev->fence_drv.emited)) {
  298. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  299. return 0;
  300. }
  301. fence = list_entry(rdev->fence_drv.emited.prev,
  302. struct radeon_fence, list);
  303. radeon_fence_ref(fence);
  304. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  305. r = radeon_fence_wait(fence, false);
  306. radeon_fence_unref(&fence);
  307. return r;
  308. }
  309. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  310. {
  311. kref_get(&fence->kref);
  312. return fence;
  313. }
  314. void radeon_fence_unref(struct radeon_fence **fence)
  315. {
  316. struct radeon_fence *tmp = *fence;
  317. *fence = NULL;
  318. if (tmp) {
  319. kref_put(&tmp->kref, radeon_fence_destroy);
  320. }
  321. }
  322. void radeon_fence_process(struct radeon_device *rdev)
  323. {
  324. unsigned long irq_flags;
  325. bool wake;
  326. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  327. wake = radeon_fence_poll_locked(rdev);
  328. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  329. if (wake) {
  330. wake_up_all(&rdev->fence_drv.queue);
  331. }
  332. }
  333. int radeon_fence_driver_init(struct radeon_device *rdev)
  334. {
  335. unsigned long irq_flags;
  336. int r;
  337. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  338. r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
  339. if (r) {
  340. dev_err(rdev->dev, "fence failed to get scratch register\n");
  341. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  342. return r;
  343. }
  344. radeon_fence_write(rdev, 0);
  345. atomic_set(&rdev->fence_drv.seq, 0);
  346. INIT_LIST_HEAD(&rdev->fence_drv.created);
  347. INIT_LIST_HEAD(&rdev->fence_drv.emited);
  348. INIT_LIST_HEAD(&rdev->fence_drv.signaled);
  349. init_waitqueue_head(&rdev->fence_drv.queue);
  350. rdev->fence_drv.initialized = true;
  351. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  352. if (radeon_debugfs_fence_init(rdev)) {
  353. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  354. }
  355. return 0;
  356. }
  357. void radeon_fence_driver_fini(struct radeon_device *rdev)
  358. {
  359. unsigned long irq_flags;
  360. if (!rdev->fence_drv.initialized)
  361. return;
  362. wake_up_all(&rdev->fence_drv.queue);
  363. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  364. radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
  365. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  366. rdev->fence_drv.initialized = false;
  367. }
  368. /*
  369. * Fence debugfs
  370. */
  371. #if defined(CONFIG_DEBUG_FS)
  372. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  373. {
  374. struct drm_info_node *node = (struct drm_info_node *)m->private;
  375. struct drm_device *dev = node->minor->dev;
  376. struct radeon_device *rdev = dev->dev_private;
  377. struct radeon_fence *fence;
  378. seq_printf(m, "Last signaled fence 0x%08X\n",
  379. radeon_fence_read(rdev));
  380. if (!list_empty(&rdev->fence_drv.emited)) {
  381. fence = list_entry(rdev->fence_drv.emited.prev,
  382. struct radeon_fence, list);
  383. seq_printf(m, "Last emited fence %p with 0x%08X\n",
  384. fence, fence->seq);
  385. }
  386. return 0;
  387. }
  388. static struct drm_info_list radeon_debugfs_fence_list[] = {
  389. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  390. };
  391. #endif
  392. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  393. {
  394. #if defined(CONFIG_DEBUG_FS)
  395. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  396. #else
  397. return 0;
  398. #endif
  399. }