nouveau_ramht.c 8.1 KB

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  1. /*
  2. * Copyright 2010 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "drmP.h"
  25. #include "nouveau_drv.h"
  26. #include "nouveau_ramht.h"
  27. static u32
  28. nouveau_ramht_hash_handle(struct nouveau_channel *chan, u32 handle)
  29. {
  30. struct drm_device *dev = chan->dev;
  31. struct drm_nouveau_private *dev_priv = dev->dev_private;
  32. struct nouveau_ramht *ramht = chan->ramht;
  33. u32 hash = 0;
  34. int i;
  35. NV_DEBUG(dev, "ch%d handle=0x%08x\n", chan->id, handle);
  36. for (i = 32; i > 0; i -= ramht->bits) {
  37. hash ^= (handle & ((1 << ramht->bits) - 1));
  38. handle >>= ramht->bits;
  39. }
  40. if (dev_priv->card_type < NV_50)
  41. hash ^= chan->id << (ramht->bits - 4);
  42. hash <<= 3;
  43. NV_DEBUG(dev, "hash=0x%08x\n", hash);
  44. return hash;
  45. }
  46. static int
  47. nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht,
  48. u32 offset)
  49. {
  50. struct drm_nouveau_private *dev_priv = dev->dev_private;
  51. u32 ctx = nv_ro32(ramht, offset + 4);
  52. if (dev_priv->card_type < NV_40)
  53. return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
  54. return (ctx != 0);
  55. }
  56. static int
  57. nouveau_ramht_entry_same_channel(struct nouveau_channel *chan,
  58. struct nouveau_gpuobj *ramht, u32 offset)
  59. {
  60. struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  61. u32 ctx = nv_ro32(ramht, offset + 4);
  62. if (dev_priv->card_type >= NV_50)
  63. return true;
  64. else if (dev_priv->card_type >= NV_40)
  65. return chan->id ==
  66. ((ctx >> NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) & 0x1f);
  67. else
  68. return chan->id ==
  69. ((ctx >> NV_RAMHT_CONTEXT_CHANNEL_SHIFT) & 0x1f);
  70. }
  71. int
  72. nouveau_ramht_insert(struct nouveau_channel *chan, u32 handle,
  73. struct nouveau_gpuobj *gpuobj)
  74. {
  75. struct drm_device *dev = chan->dev;
  76. struct drm_nouveau_private *dev_priv = dev->dev_private;
  77. struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
  78. struct nouveau_ramht_entry *entry;
  79. struct nouveau_gpuobj *ramht = chan->ramht->gpuobj;
  80. unsigned long flags;
  81. u32 ctx, co, ho;
  82. if (nouveau_ramht_find(chan, handle))
  83. return -EEXIST;
  84. entry = kmalloc(sizeof(*entry), GFP_KERNEL);
  85. if (!entry)
  86. return -ENOMEM;
  87. entry->channel = chan;
  88. entry->gpuobj = NULL;
  89. entry->handle = handle;
  90. nouveau_gpuobj_ref(gpuobj, &entry->gpuobj);
  91. if (dev_priv->card_type < NV_40) {
  92. ctx = NV_RAMHT_CONTEXT_VALID | (gpuobj->pinst >> 4) |
  93. (chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
  94. (gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
  95. } else
  96. if (dev_priv->card_type < NV_50) {
  97. ctx = (gpuobj->pinst >> 4) |
  98. (chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
  99. (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
  100. } else {
  101. if (gpuobj->engine == NVOBJ_ENGINE_DISPLAY) {
  102. ctx = (gpuobj->cinst << 10) |
  103. (chan->id << 28) |
  104. chan->id; /* HASH_TAG */
  105. } else {
  106. ctx = (gpuobj->cinst >> 4) |
  107. ((gpuobj->engine <<
  108. NV40_RAMHT_CONTEXT_ENGINE_SHIFT));
  109. }
  110. }
  111. spin_lock_irqsave(&chan->ramht->lock, flags);
  112. list_add(&entry->head, &chan->ramht->entries);
  113. co = ho = nouveau_ramht_hash_handle(chan, handle);
  114. do {
  115. if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
  116. NV_DEBUG(dev,
  117. "insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
  118. chan->id, co, handle, ctx);
  119. nv_wo32(ramht, co + 0, handle);
  120. nv_wo32(ramht, co + 4, ctx);
  121. spin_unlock_irqrestore(&chan->ramht->lock, flags);
  122. instmem->flush(dev);
  123. return 0;
  124. }
  125. NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
  126. chan->id, co, nv_ro32(ramht, co));
  127. co += 8;
  128. if (co >= ramht->size)
  129. co = 0;
  130. } while (co != ho);
  131. NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id);
  132. list_del(&entry->head);
  133. spin_unlock_irqrestore(&chan->ramht->lock, flags);
  134. kfree(entry);
  135. return -ENOMEM;
  136. }
  137. static struct nouveau_ramht_entry *
  138. nouveau_ramht_remove_entry(struct nouveau_channel *chan, u32 handle)
  139. {
  140. struct nouveau_ramht *ramht = chan ? chan->ramht : NULL;
  141. struct nouveau_ramht_entry *entry;
  142. unsigned long flags;
  143. if (!ramht)
  144. return NULL;
  145. spin_lock_irqsave(&ramht->lock, flags);
  146. list_for_each_entry(entry, &ramht->entries, head) {
  147. if (entry->channel == chan &&
  148. (!handle || entry->handle == handle)) {
  149. list_del(&entry->head);
  150. spin_unlock_irqrestore(&ramht->lock, flags);
  151. return entry;
  152. }
  153. }
  154. spin_unlock_irqrestore(&ramht->lock, flags);
  155. return NULL;
  156. }
  157. static void
  158. nouveau_ramht_remove_hash(struct nouveau_channel *chan, u32 handle)
  159. {
  160. struct drm_device *dev = chan->dev;
  161. struct drm_nouveau_private *dev_priv = dev->dev_private;
  162. struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
  163. struct nouveau_gpuobj *ramht = chan->ramht->gpuobj;
  164. unsigned long flags;
  165. u32 co, ho;
  166. spin_lock_irqsave(&chan->ramht->lock, flags);
  167. co = ho = nouveau_ramht_hash_handle(chan, handle);
  168. do {
  169. if (nouveau_ramht_entry_valid(dev, ramht, co) &&
  170. nouveau_ramht_entry_same_channel(chan, ramht, co) &&
  171. (handle == nv_ro32(ramht, co))) {
  172. NV_DEBUG(dev,
  173. "remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
  174. chan->id, co, handle, nv_ro32(ramht, co + 4));
  175. nv_wo32(ramht, co + 0, 0x00000000);
  176. nv_wo32(ramht, co + 4, 0x00000000);
  177. instmem->flush(dev);
  178. goto out;
  179. }
  180. co += 8;
  181. if (co >= ramht->size)
  182. co = 0;
  183. } while (co != ho);
  184. NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n",
  185. chan->id, handle);
  186. out:
  187. spin_unlock_irqrestore(&chan->ramht->lock, flags);
  188. }
  189. int
  190. nouveau_ramht_remove(struct nouveau_channel *chan, u32 handle)
  191. {
  192. struct nouveau_ramht_entry *entry;
  193. entry = nouveau_ramht_remove_entry(chan, handle);
  194. if (!entry)
  195. return -ENOENT;
  196. nouveau_ramht_remove_hash(chan, entry->handle);
  197. nouveau_gpuobj_ref(NULL, &entry->gpuobj);
  198. kfree(entry);
  199. return 0;
  200. }
  201. struct nouveau_gpuobj *
  202. nouveau_ramht_find(struct nouveau_channel *chan, u32 handle)
  203. {
  204. struct nouveau_ramht *ramht = chan->ramht;
  205. struct nouveau_ramht_entry *entry;
  206. struct nouveau_gpuobj *gpuobj = NULL;
  207. unsigned long flags;
  208. if (unlikely(!chan->ramht))
  209. return NULL;
  210. spin_lock_irqsave(&ramht->lock, flags);
  211. list_for_each_entry(entry, &chan->ramht->entries, head) {
  212. if (entry->channel == chan && entry->handle == handle) {
  213. gpuobj = entry->gpuobj;
  214. break;
  215. }
  216. }
  217. spin_unlock_irqrestore(&ramht->lock, flags);
  218. return gpuobj;
  219. }
  220. int
  221. nouveau_ramht_new(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
  222. struct nouveau_ramht **pramht)
  223. {
  224. struct nouveau_ramht *ramht;
  225. ramht = kzalloc(sizeof(*ramht), GFP_KERNEL);
  226. if (!ramht)
  227. return -ENOMEM;
  228. ramht->dev = dev;
  229. kref_init(&ramht->refcount);
  230. ramht->bits = drm_order(gpuobj->size / 8);
  231. INIT_LIST_HEAD(&ramht->entries);
  232. spin_lock_init(&ramht->lock);
  233. nouveau_gpuobj_ref(gpuobj, &ramht->gpuobj);
  234. *pramht = ramht;
  235. return 0;
  236. }
  237. static void
  238. nouveau_ramht_del(struct kref *ref)
  239. {
  240. struct nouveau_ramht *ramht =
  241. container_of(ref, struct nouveau_ramht, refcount);
  242. nouveau_gpuobj_ref(NULL, &ramht->gpuobj);
  243. kfree(ramht);
  244. }
  245. void
  246. nouveau_ramht_ref(struct nouveau_ramht *ref, struct nouveau_ramht **ptr,
  247. struct nouveau_channel *chan)
  248. {
  249. struct nouveau_ramht_entry *entry;
  250. struct nouveau_ramht *ramht;
  251. if (ref)
  252. kref_get(&ref->refcount);
  253. ramht = *ptr;
  254. if (ramht) {
  255. while ((entry = nouveau_ramht_remove_entry(chan, 0))) {
  256. nouveau_ramht_remove_hash(chan, entry->handle);
  257. nouveau_gpuobj_ref(NULL, &entry->gpuobj);
  258. kfree(entry);
  259. }
  260. kref_put(&ramht->refcount, nouveau_ramht_del);
  261. }
  262. *ptr = ref;
  263. }