nouveau_fence.c 14 KB

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  1. /*
  2. * Copyright (C) 2007 Ben Skeggs.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #include "drmP.h"
  27. #include "drm.h"
  28. #include <linux/ktime.h>
  29. #include <linux/hrtimer.h>
  30. #include "nouveau_drv.h"
  31. #include "nouveau_ramht.h"
  32. #include "nouveau_dma.h"
  33. #define USE_REFCNT(dev) (nouveau_private(dev)->chipset >= 0x10)
  34. #define USE_SEMA(dev) (nouveau_private(dev)->chipset >= 0x17)
  35. struct nouveau_fence {
  36. struct nouveau_channel *channel;
  37. struct kref refcount;
  38. struct list_head entry;
  39. uint32_t sequence;
  40. bool signalled;
  41. void (*work)(void *priv, bool signalled);
  42. void *priv;
  43. };
  44. struct nouveau_semaphore {
  45. struct kref ref;
  46. struct drm_device *dev;
  47. struct drm_mm_node *mem;
  48. };
  49. static inline struct nouveau_fence *
  50. nouveau_fence(void *sync_obj)
  51. {
  52. return (struct nouveau_fence *)sync_obj;
  53. }
  54. static void
  55. nouveau_fence_del(struct kref *ref)
  56. {
  57. struct nouveau_fence *fence =
  58. container_of(ref, struct nouveau_fence, refcount);
  59. nouveau_channel_ref(NULL, &fence->channel);
  60. kfree(fence);
  61. }
  62. void
  63. nouveau_fence_update(struct nouveau_channel *chan)
  64. {
  65. struct drm_device *dev = chan->dev;
  66. struct nouveau_fence *tmp, *fence;
  67. uint32_t sequence;
  68. spin_lock(&chan->fence.lock);
  69. /* Fetch the last sequence if the channel is still up and running */
  70. if (likely(!list_empty(&chan->fence.pending))) {
  71. if (USE_REFCNT(dev))
  72. sequence = nvchan_rd32(chan, 0x48);
  73. else
  74. sequence = atomic_read(&chan->fence.last_sequence_irq);
  75. if (chan->fence.sequence_ack == sequence)
  76. goto out;
  77. chan->fence.sequence_ack = sequence;
  78. }
  79. list_for_each_entry_safe(fence, tmp, &chan->fence.pending, entry) {
  80. sequence = fence->sequence;
  81. fence->signalled = true;
  82. list_del(&fence->entry);
  83. if (unlikely(fence->work))
  84. fence->work(fence->priv, true);
  85. kref_put(&fence->refcount, nouveau_fence_del);
  86. if (sequence == chan->fence.sequence_ack)
  87. break;
  88. }
  89. out:
  90. spin_unlock(&chan->fence.lock);
  91. }
  92. int
  93. nouveau_fence_new(struct nouveau_channel *chan, struct nouveau_fence **pfence,
  94. bool emit)
  95. {
  96. struct nouveau_fence *fence;
  97. int ret = 0;
  98. fence = kzalloc(sizeof(*fence), GFP_KERNEL);
  99. if (!fence)
  100. return -ENOMEM;
  101. kref_init(&fence->refcount);
  102. nouveau_channel_ref(chan, &fence->channel);
  103. if (emit)
  104. ret = nouveau_fence_emit(fence);
  105. if (ret)
  106. nouveau_fence_unref(&fence);
  107. *pfence = fence;
  108. return ret;
  109. }
  110. struct nouveau_channel *
  111. nouveau_fence_channel(struct nouveau_fence *fence)
  112. {
  113. return fence ? nouveau_channel_get_unlocked(fence->channel) : NULL;
  114. }
  115. int
  116. nouveau_fence_emit(struct nouveau_fence *fence)
  117. {
  118. struct nouveau_channel *chan = fence->channel;
  119. struct drm_device *dev = chan->dev;
  120. struct drm_nouveau_private *dev_priv = dev->dev_private;
  121. int ret;
  122. ret = RING_SPACE(chan, 2);
  123. if (ret)
  124. return ret;
  125. if (unlikely(chan->fence.sequence == chan->fence.sequence_ack - 1)) {
  126. nouveau_fence_update(chan);
  127. BUG_ON(chan->fence.sequence ==
  128. chan->fence.sequence_ack - 1);
  129. }
  130. fence->sequence = ++chan->fence.sequence;
  131. kref_get(&fence->refcount);
  132. spin_lock(&chan->fence.lock);
  133. list_add_tail(&fence->entry, &chan->fence.pending);
  134. spin_unlock(&chan->fence.lock);
  135. if (USE_REFCNT(dev)) {
  136. if (dev_priv->card_type < NV_C0)
  137. BEGIN_RING(chan, NvSubSw, 0x0050, 1);
  138. else
  139. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0050, 1);
  140. } else {
  141. BEGIN_RING(chan, NvSubSw, 0x0150, 1);
  142. }
  143. OUT_RING (chan, fence->sequence);
  144. FIRE_RING(chan);
  145. return 0;
  146. }
  147. void
  148. nouveau_fence_work(struct nouveau_fence *fence,
  149. void (*work)(void *priv, bool signalled),
  150. void *priv)
  151. {
  152. BUG_ON(fence->work);
  153. spin_lock(&fence->channel->fence.lock);
  154. if (fence->signalled) {
  155. work(priv, true);
  156. } else {
  157. fence->work = work;
  158. fence->priv = priv;
  159. }
  160. spin_unlock(&fence->channel->fence.lock);
  161. }
  162. void
  163. __nouveau_fence_unref(void **sync_obj)
  164. {
  165. struct nouveau_fence *fence = nouveau_fence(*sync_obj);
  166. if (fence)
  167. kref_put(&fence->refcount, nouveau_fence_del);
  168. *sync_obj = NULL;
  169. }
  170. void *
  171. __nouveau_fence_ref(void *sync_obj)
  172. {
  173. struct nouveau_fence *fence = nouveau_fence(sync_obj);
  174. kref_get(&fence->refcount);
  175. return sync_obj;
  176. }
  177. bool
  178. __nouveau_fence_signalled(void *sync_obj, void *sync_arg)
  179. {
  180. struct nouveau_fence *fence = nouveau_fence(sync_obj);
  181. struct nouveau_channel *chan = fence->channel;
  182. if (fence->signalled)
  183. return true;
  184. nouveau_fence_update(chan);
  185. return fence->signalled;
  186. }
  187. int
  188. __nouveau_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
  189. {
  190. unsigned long timeout = jiffies + (3 * DRM_HZ);
  191. unsigned long sleep_time = NSEC_PER_MSEC / 1000;
  192. ktime_t t;
  193. int ret = 0;
  194. while (1) {
  195. if (__nouveau_fence_signalled(sync_obj, sync_arg))
  196. break;
  197. if (time_after_eq(jiffies, timeout)) {
  198. ret = -EBUSY;
  199. break;
  200. }
  201. __set_current_state(intr ? TASK_INTERRUPTIBLE
  202. : TASK_UNINTERRUPTIBLE);
  203. if (lazy) {
  204. t = ktime_set(0, sleep_time);
  205. schedule_hrtimeout(&t, HRTIMER_MODE_REL);
  206. sleep_time *= 2;
  207. if (sleep_time > NSEC_PER_MSEC)
  208. sleep_time = NSEC_PER_MSEC;
  209. }
  210. if (intr && signal_pending(current)) {
  211. ret = -ERESTARTSYS;
  212. break;
  213. }
  214. }
  215. __set_current_state(TASK_RUNNING);
  216. return ret;
  217. }
  218. static struct nouveau_semaphore *
  219. semaphore_alloc(struct drm_device *dev)
  220. {
  221. struct drm_nouveau_private *dev_priv = dev->dev_private;
  222. struct nouveau_semaphore *sema;
  223. int size = (dev_priv->chipset < 0x84) ? 4 : 16;
  224. int ret, i;
  225. if (!USE_SEMA(dev))
  226. return NULL;
  227. sema = kmalloc(sizeof(*sema), GFP_KERNEL);
  228. if (!sema)
  229. goto fail;
  230. ret = drm_mm_pre_get(&dev_priv->fence.heap);
  231. if (ret)
  232. goto fail;
  233. spin_lock(&dev_priv->fence.lock);
  234. sema->mem = drm_mm_search_free(&dev_priv->fence.heap, size, 0, 0);
  235. if (sema->mem)
  236. sema->mem = drm_mm_get_block_atomic(sema->mem, size, 0);
  237. spin_unlock(&dev_priv->fence.lock);
  238. if (!sema->mem)
  239. goto fail;
  240. kref_init(&sema->ref);
  241. sema->dev = dev;
  242. for (i = sema->mem->start; i < sema->mem->start + size; i += 4)
  243. nouveau_bo_wr32(dev_priv->fence.bo, i / 4, 0);
  244. return sema;
  245. fail:
  246. kfree(sema);
  247. return NULL;
  248. }
  249. static void
  250. semaphore_free(struct kref *ref)
  251. {
  252. struct nouveau_semaphore *sema =
  253. container_of(ref, struct nouveau_semaphore, ref);
  254. struct drm_nouveau_private *dev_priv = sema->dev->dev_private;
  255. spin_lock(&dev_priv->fence.lock);
  256. drm_mm_put_block(sema->mem);
  257. spin_unlock(&dev_priv->fence.lock);
  258. kfree(sema);
  259. }
  260. static void
  261. semaphore_work(void *priv, bool signalled)
  262. {
  263. struct nouveau_semaphore *sema = priv;
  264. struct drm_nouveau_private *dev_priv = sema->dev->dev_private;
  265. if (unlikely(!signalled))
  266. nouveau_bo_wr32(dev_priv->fence.bo, sema->mem->start / 4, 1);
  267. kref_put(&sema->ref, semaphore_free);
  268. }
  269. static int
  270. semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
  271. {
  272. struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  273. struct nouveau_fence *fence = NULL;
  274. u64 offset = chan->fence.vma.offset + sema->mem->start;
  275. int ret;
  276. if (dev_priv->chipset < 0x84) {
  277. ret = RING_SPACE(chan, 4);
  278. if (ret)
  279. return ret;
  280. BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 3);
  281. OUT_RING (chan, NvSema);
  282. OUT_RING (chan, offset);
  283. OUT_RING (chan, 1);
  284. } else
  285. if (dev_priv->chipset < 0xc0) {
  286. ret = RING_SPACE(chan, 7);
  287. if (ret)
  288. return ret;
  289. BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
  290. OUT_RING (chan, chan->vram_handle);
  291. BEGIN_RING(chan, NvSubSw, 0x0010, 4);
  292. OUT_RING (chan, upper_32_bits(offset));
  293. OUT_RING (chan, lower_32_bits(offset));
  294. OUT_RING (chan, 1);
  295. OUT_RING (chan, 1); /* ACQUIRE_EQ */
  296. } else {
  297. ret = RING_SPACE(chan, 5);
  298. if (ret)
  299. return ret;
  300. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
  301. OUT_RING (chan, upper_32_bits(offset));
  302. OUT_RING (chan, lower_32_bits(offset));
  303. OUT_RING (chan, 1);
  304. OUT_RING (chan, 0x1001); /* ACQUIRE_EQ */
  305. }
  306. /* Delay semaphore destruction until its work is done */
  307. ret = nouveau_fence_new(chan, &fence, true);
  308. if (ret)
  309. return ret;
  310. kref_get(&sema->ref);
  311. nouveau_fence_work(fence, semaphore_work, sema);
  312. nouveau_fence_unref(&fence);
  313. return 0;
  314. }
  315. static int
  316. semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
  317. {
  318. struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  319. struct nouveau_fence *fence = NULL;
  320. u64 offset = chan->fence.vma.offset + sema->mem->start;
  321. int ret;
  322. if (dev_priv->chipset < 0x84) {
  323. ret = RING_SPACE(chan, 5);
  324. if (ret)
  325. return ret;
  326. BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 2);
  327. OUT_RING (chan, NvSema);
  328. OUT_RING (chan, offset);
  329. BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_RELEASE, 1);
  330. OUT_RING (chan, 1);
  331. } else
  332. if (dev_priv->chipset < 0xc0) {
  333. ret = RING_SPACE(chan, 7);
  334. if (ret)
  335. return ret;
  336. BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
  337. OUT_RING (chan, chan->vram_handle);
  338. BEGIN_RING(chan, NvSubSw, 0x0010, 4);
  339. OUT_RING (chan, upper_32_bits(offset));
  340. OUT_RING (chan, lower_32_bits(offset));
  341. OUT_RING (chan, 1);
  342. OUT_RING (chan, 2); /* RELEASE */
  343. } else {
  344. ret = RING_SPACE(chan, 5);
  345. if (ret)
  346. return ret;
  347. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
  348. OUT_RING (chan, upper_32_bits(offset));
  349. OUT_RING (chan, lower_32_bits(offset));
  350. OUT_RING (chan, 1);
  351. OUT_RING (chan, 0x1002); /* RELEASE */
  352. }
  353. /* Delay semaphore destruction until its work is done */
  354. ret = nouveau_fence_new(chan, &fence, true);
  355. if (ret)
  356. return ret;
  357. kref_get(&sema->ref);
  358. nouveau_fence_work(fence, semaphore_work, sema);
  359. nouveau_fence_unref(&fence);
  360. return 0;
  361. }
  362. int
  363. nouveau_fence_sync(struct nouveau_fence *fence,
  364. struct nouveau_channel *wchan)
  365. {
  366. struct nouveau_channel *chan = nouveau_fence_channel(fence);
  367. struct drm_device *dev = wchan->dev;
  368. struct nouveau_semaphore *sema;
  369. int ret = 0;
  370. if (likely(!chan || chan == wchan ||
  371. nouveau_fence_signalled(fence)))
  372. goto out;
  373. sema = semaphore_alloc(dev);
  374. if (!sema) {
  375. /* Early card or broken userspace, fall back to
  376. * software sync. */
  377. ret = nouveau_fence_wait(fence, true, false);
  378. goto out;
  379. }
  380. /* try to take chan's mutex, if we can't take it right away
  381. * we have to fallback to software sync to prevent locking
  382. * order issues
  383. */
  384. if (!mutex_trylock(&chan->mutex)) {
  385. ret = nouveau_fence_wait(fence, true, false);
  386. goto out_unref;
  387. }
  388. /* Make wchan wait until it gets signalled */
  389. ret = semaphore_acquire(wchan, sema);
  390. if (ret)
  391. goto out_unlock;
  392. /* Signal the semaphore from chan */
  393. ret = semaphore_release(chan, sema);
  394. out_unlock:
  395. mutex_unlock(&chan->mutex);
  396. out_unref:
  397. kref_put(&sema->ref, semaphore_free);
  398. out:
  399. if (chan)
  400. nouveau_channel_put_unlocked(&chan);
  401. return ret;
  402. }
  403. int
  404. __nouveau_fence_flush(void *sync_obj, void *sync_arg)
  405. {
  406. return 0;
  407. }
  408. int
  409. nouveau_fence_channel_init(struct nouveau_channel *chan)
  410. {
  411. struct drm_device *dev = chan->dev;
  412. struct drm_nouveau_private *dev_priv = dev->dev_private;
  413. struct nouveau_gpuobj *obj = NULL;
  414. int ret;
  415. if (dev_priv->card_type < NV_C0) {
  416. /* Create an NV_SW object for various sync purposes */
  417. ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW);
  418. if (ret)
  419. return ret;
  420. ret = RING_SPACE(chan, 2);
  421. if (ret)
  422. return ret;
  423. BEGIN_RING(chan, NvSubSw, 0, 1);
  424. OUT_RING (chan, NvSw);
  425. FIRE_RING (chan);
  426. }
  427. /* Setup area of memory shared between all channels for x-chan sync */
  428. if (USE_SEMA(dev) && dev_priv->chipset < 0x84) {
  429. struct ttm_mem_reg *mem = &dev_priv->fence.bo->bo.mem;
  430. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  431. mem->start << PAGE_SHIFT,
  432. mem->size, NV_MEM_ACCESS_RW,
  433. NV_MEM_TARGET_VRAM, &obj);
  434. if (ret)
  435. return ret;
  436. ret = nouveau_ramht_insert(chan, NvSema, obj);
  437. nouveau_gpuobj_ref(NULL, &obj);
  438. if (ret)
  439. return ret;
  440. } else {
  441. /* map fence bo into channel's vm */
  442. ret = nouveau_bo_vma_add(dev_priv->fence.bo, chan->vm,
  443. &chan->fence.vma);
  444. if (ret)
  445. return ret;
  446. }
  447. INIT_LIST_HEAD(&chan->fence.pending);
  448. spin_lock_init(&chan->fence.lock);
  449. atomic_set(&chan->fence.last_sequence_irq, 0);
  450. return 0;
  451. }
  452. void
  453. nouveau_fence_channel_fini(struct nouveau_channel *chan)
  454. {
  455. struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  456. struct nouveau_fence *tmp, *fence;
  457. spin_lock(&chan->fence.lock);
  458. list_for_each_entry_safe(fence, tmp, &chan->fence.pending, entry) {
  459. fence->signalled = true;
  460. list_del(&fence->entry);
  461. if (unlikely(fence->work))
  462. fence->work(fence->priv, false);
  463. kref_put(&fence->refcount, nouveau_fence_del);
  464. }
  465. spin_unlock(&chan->fence.lock);
  466. nouveau_bo_vma_del(dev_priv->fence.bo, &chan->fence.vma);
  467. }
  468. int
  469. nouveau_fence_init(struct drm_device *dev)
  470. {
  471. struct drm_nouveau_private *dev_priv = dev->dev_private;
  472. int size = (dev_priv->chipset < 0x84) ? 4096 : 16384;
  473. int ret;
  474. /* Create a shared VRAM heap for cross-channel sync. */
  475. if (USE_SEMA(dev)) {
  476. ret = nouveau_bo_new(dev, size, 0, TTM_PL_FLAG_VRAM,
  477. 0, 0, &dev_priv->fence.bo);
  478. if (ret)
  479. return ret;
  480. ret = nouveau_bo_pin(dev_priv->fence.bo, TTM_PL_FLAG_VRAM);
  481. if (ret)
  482. goto fail;
  483. ret = nouveau_bo_map(dev_priv->fence.bo);
  484. if (ret)
  485. goto fail;
  486. ret = drm_mm_init(&dev_priv->fence.heap, 0,
  487. dev_priv->fence.bo->bo.mem.size);
  488. if (ret)
  489. goto fail;
  490. spin_lock_init(&dev_priv->fence.lock);
  491. }
  492. return 0;
  493. fail:
  494. nouveau_bo_unmap(dev_priv->fence.bo);
  495. nouveau_bo_ref(NULL, &dev_priv->fence.bo);
  496. return ret;
  497. }
  498. void
  499. nouveau_fence_fini(struct drm_device *dev)
  500. {
  501. struct drm_nouveau_private *dev_priv = dev->dev_private;
  502. if (USE_SEMA(dev)) {
  503. drm_mm_takedown(&dev_priv->fence.heap);
  504. nouveau_bo_unmap(dev_priv->fence.bo);
  505. nouveau_bo_unpin(dev_priv->fence.bo);
  506. nouveau_bo_ref(NULL, &dev_priv->fence.bo);
  507. }
  508. }