nouveau_channel.c 13 KB

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  1. /*
  2. * Copyright 2005-2006 Stephane Marchesin
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. */
  24. #include "drmP.h"
  25. #include "drm.h"
  26. #include "nouveau_drv.h"
  27. #include "nouveau_drm.h"
  28. #include "nouveau_dma.h"
  29. #include "nouveau_ramht.h"
  30. static int
  31. nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
  32. {
  33. u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
  34. struct drm_device *dev = chan->dev;
  35. struct drm_nouveau_private *dev_priv = dev->dev_private;
  36. int ret;
  37. /* allocate buffer object */
  38. ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, &chan->pushbuf_bo);
  39. if (ret)
  40. goto out;
  41. ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
  42. if (ret)
  43. goto out;
  44. ret = nouveau_bo_map(chan->pushbuf_bo);
  45. if (ret)
  46. goto out;
  47. /* create DMA object covering the entire memtype where the push
  48. * buffer resides, userspace can submit its own push buffers from
  49. * anywhere within the same memtype.
  50. */
  51. chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
  52. if (dev_priv->card_type >= NV_50) {
  53. ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
  54. &chan->pushbuf_vma);
  55. if (ret)
  56. goto out;
  57. if (dev_priv->card_type < NV_C0) {
  58. ret = nouveau_gpuobj_dma_new(chan,
  59. NV_CLASS_DMA_IN_MEMORY, 0,
  60. (1ULL << 40),
  61. NV_MEM_ACCESS_RO,
  62. NV_MEM_TARGET_VM,
  63. &chan->pushbuf);
  64. }
  65. chan->pushbuf_base = chan->pushbuf_vma.offset;
  66. } else
  67. if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
  68. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
  69. dev_priv->gart_info.aper_size,
  70. NV_MEM_ACCESS_RO,
  71. NV_MEM_TARGET_GART,
  72. &chan->pushbuf);
  73. } else
  74. if (dev_priv->card_type != NV_04) {
  75. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
  76. dev_priv->fb_available_size,
  77. NV_MEM_ACCESS_RO,
  78. NV_MEM_TARGET_VRAM,
  79. &chan->pushbuf);
  80. } else {
  81. /* NV04 cmdbuf hack, from original ddx.. not sure of it's
  82. * exact reason for existing :) PCI access to cmdbuf in
  83. * VRAM.
  84. */
  85. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  86. pci_resource_start(dev->pdev, 1),
  87. dev_priv->fb_available_size,
  88. NV_MEM_ACCESS_RO,
  89. NV_MEM_TARGET_PCI,
  90. &chan->pushbuf);
  91. }
  92. out:
  93. if (ret) {
  94. NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
  95. nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
  96. nouveau_gpuobj_ref(NULL, &chan->pushbuf);
  97. if (chan->pushbuf_bo) {
  98. nouveau_bo_unmap(chan->pushbuf_bo);
  99. nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  100. }
  101. }
  102. return 0;
  103. }
  104. /* allocates and initializes a fifo for user space consumption */
  105. int
  106. nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
  107. struct drm_file *file_priv,
  108. uint32_t vram_handle, uint32_t gart_handle)
  109. {
  110. struct drm_nouveau_private *dev_priv = dev->dev_private;
  111. struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  112. struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
  113. struct nouveau_channel *chan;
  114. unsigned long flags;
  115. int ret;
  116. /* allocate and lock channel structure */
  117. chan = kzalloc(sizeof(*chan), GFP_KERNEL);
  118. if (!chan)
  119. return -ENOMEM;
  120. chan->dev = dev;
  121. chan->file_priv = file_priv;
  122. chan->vram_handle = vram_handle;
  123. chan->gart_handle = gart_handle;
  124. kref_init(&chan->ref);
  125. atomic_set(&chan->users, 1);
  126. mutex_init(&chan->mutex);
  127. mutex_lock(&chan->mutex);
  128. /* allocate hw channel id */
  129. spin_lock_irqsave(&dev_priv->channels.lock, flags);
  130. for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
  131. if (!dev_priv->channels.ptr[chan->id]) {
  132. nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
  133. break;
  134. }
  135. }
  136. spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
  137. if (chan->id == pfifo->channels) {
  138. mutex_unlock(&chan->mutex);
  139. kfree(chan);
  140. return -ENODEV;
  141. }
  142. NV_DEBUG(dev, "initialising channel %d\n", chan->id);
  143. INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
  144. INIT_LIST_HEAD(&chan->nvsw.flip);
  145. INIT_LIST_HEAD(&chan->fence.pending);
  146. /* setup channel's memory and vm */
  147. ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
  148. if (ret) {
  149. NV_ERROR(dev, "gpuobj %d\n", ret);
  150. nouveau_channel_put(&chan);
  151. return ret;
  152. }
  153. /* Allocate space for per-channel fixed notifier memory */
  154. ret = nouveau_notifier_init_channel(chan);
  155. if (ret) {
  156. NV_ERROR(dev, "ntfy %d\n", ret);
  157. nouveau_channel_put(&chan);
  158. return ret;
  159. }
  160. /* Allocate DMA push buffer */
  161. ret = nouveau_channel_pushbuf_init(chan);
  162. if (ret) {
  163. NV_ERROR(dev, "pushbuf %d\n", ret);
  164. nouveau_channel_put(&chan);
  165. return ret;
  166. }
  167. nouveau_dma_pre_init(chan);
  168. chan->user_put = 0x40;
  169. chan->user_get = 0x44;
  170. /* disable the fifo caches */
  171. pfifo->reassign(dev, false);
  172. /* Construct initial RAMFC for new channel */
  173. ret = pfifo->create_context(chan);
  174. if (ret) {
  175. nouveau_channel_put(&chan);
  176. return ret;
  177. }
  178. pfifo->reassign(dev, true);
  179. ret = nouveau_dma_init(chan);
  180. if (!ret)
  181. ret = nouveau_fence_channel_init(chan);
  182. if (ret) {
  183. nouveau_channel_put(&chan);
  184. return ret;
  185. }
  186. nouveau_debugfs_channel_init(chan);
  187. NV_DEBUG(dev, "channel %d initialised\n", chan->id);
  188. if (fpriv) {
  189. spin_lock(&fpriv->lock);
  190. list_add(&chan->list, &fpriv->channels);
  191. spin_unlock(&fpriv->lock);
  192. }
  193. *chan_ret = chan;
  194. return 0;
  195. }
  196. struct nouveau_channel *
  197. nouveau_channel_get_unlocked(struct nouveau_channel *ref)
  198. {
  199. struct nouveau_channel *chan = NULL;
  200. if (likely(ref && atomic_inc_not_zero(&ref->users)))
  201. nouveau_channel_ref(ref, &chan);
  202. return chan;
  203. }
  204. struct nouveau_channel *
  205. nouveau_channel_get(struct drm_file *file_priv, int id)
  206. {
  207. struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
  208. struct nouveau_channel *chan;
  209. spin_lock(&fpriv->lock);
  210. list_for_each_entry(chan, &fpriv->channels, list) {
  211. if (chan->id == id) {
  212. chan = nouveau_channel_get_unlocked(chan);
  213. spin_unlock(&fpriv->lock);
  214. mutex_lock(&chan->mutex);
  215. return chan;
  216. }
  217. }
  218. spin_unlock(&fpriv->lock);
  219. return ERR_PTR(-EINVAL);
  220. }
  221. void
  222. nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
  223. {
  224. struct nouveau_channel *chan = *pchan;
  225. struct drm_device *dev = chan->dev;
  226. struct drm_nouveau_private *dev_priv = dev->dev_private;
  227. struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  228. unsigned long flags;
  229. int i;
  230. /* decrement the refcount, and we're done if there's still refs */
  231. if (likely(!atomic_dec_and_test(&chan->users))) {
  232. nouveau_channel_ref(NULL, pchan);
  233. return;
  234. }
  235. /* no one wants the channel anymore */
  236. NV_DEBUG(dev, "freeing channel %d\n", chan->id);
  237. nouveau_debugfs_channel_fini(chan);
  238. /* give it chance to idle */
  239. nouveau_channel_idle(chan);
  240. /* ensure all outstanding fences are signaled. they should be if the
  241. * above attempts at idling were OK, but if we failed this'll tell TTM
  242. * we're done with the buffers.
  243. */
  244. nouveau_fence_channel_fini(chan);
  245. /* boot it off the hardware */
  246. pfifo->reassign(dev, false);
  247. /* destroy the engine specific contexts */
  248. pfifo->destroy_context(chan);
  249. for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
  250. if (chan->engctx[i])
  251. dev_priv->eng[i]->context_del(chan, i);
  252. }
  253. pfifo->reassign(dev, true);
  254. /* aside from its resources, the channel should now be dead,
  255. * remove it from the channel list
  256. */
  257. spin_lock_irqsave(&dev_priv->channels.lock, flags);
  258. nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
  259. spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
  260. /* destroy any resources the channel owned */
  261. nouveau_gpuobj_ref(NULL, &chan->pushbuf);
  262. if (chan->pushbuf_bo) {
  263. nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
  264. nouveau_bo_unmap(chan->pushbuf_bo);
  265. nouveau_bo_unpin(chan->pushbuf_bo);
  266. nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  267. }
  268. nouveau_ramht_ref(NULL, &chan->ramht, chan);
  269. nouveau_notifier_takedown_channel(chan);
  270. nouveau_gpuobj_channel_takedown(chan);
  271. nouveau_channel_ref(NULL, pchan);
  272. }
  273. void
  274. nouveau_channel_put(struct nouveau_channel **pchan)
  275. {
  276. mutex_unlock(&(*pchan)->mutex);
  277. nouveau_channel_put_unlocked(pchan);
  278. }
  279. static void
  280. nouveau_channel_del(struct kref *ref)
  281. {
  282. struct nouveau_channel *chan =
  283. container_of(ref, struct nouveau_channel, ref);
  284. kfree(chan);
  285. }
  286. void
  287. nouveau_channel_ref(struct nouveau_channel *chan,
  288. struct nouveau_channel **pchan)
  289. {
  290. if (chan)
  291. kref_get(&chan->ref);
  292. if (*pchan)
  293. kref_put(&(*pchan)->ref, nouveau_channel_del);
  294. *pchan = chan;
  295. }
  296. void
  297. nouveau_channel_idle(struct nouveau_channel *chan)
  298. {
  299. struct drm_device *dev = chan->dev;
  300. struct nouveau_fence *fence = NULL;
  301. int ret;
  302. nouveau_fence_update(chan);
  303. if (chan->fence.sequence != chan->fence.sequence_ack) {
  304. ret = nouveau_fence_new(chan, &fence, true);
  305. if (!ret) {
  306. ret = nouveau_fence_wait(fence, false, false);
  307. nouveau_fence_unref(&fence);
  308. }
  309. if (ret)
  310. NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
  311. }
  312. }
  313. /* cleans up all the fifos from file_priv */
  314. void
  315. nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
  316. {
  317. struct drm_nouveau_private *dev_priv = dev->dev_private;
  318. struct nouveau_engine *engine = &dev_priv->engine;
  319. struct nouveau_channel *chan;
  320. int i;
  321. NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
  322. for (i = 0; i < engine->fifo.channels; i++) {
  323. chan = nouveau_channel_get(file_priv, i);
  324. if (IS_ERR(chan))
  325. continue;
  326. list_del(&chan->list);
  327. atomic_dec(&chan->users);
  328. nouveau_channel_put(&chan);
  329. }
  330. }
  331. /***********************************
  332. * ioctls wrapping the functions
  333. ***********************************/
  334. static int
  335. nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
  336. struct drm_file *file_priv)
  337. {
  338. struct drm_nouveau_private *dev_priv = dev->dev_private;
  339. struct drm_nouveau_channel_alloc *init = data;
  340. struct nouveau_channel *chan;
  341. int ret;
  342. if (!dev_priv->eng[NVOBJ_ENGINE_GR])
  343. return -ENODEV;
  344. if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
  345. return -EINVAL;
  346. ret = nouveau_channel_alloc(dev, &chan, file_priv,
  347. init->fb_ctxdma_handle,
  348. init->tt_ctxdma_handle);
  349. if (ret)
  350. return ret;
  351. init->channel = chan->id;
  352. if (chan->dma.ib_max)
  353. init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
  354. NOUVEAU_GEM_DOMAIN_GART;
  355. else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
  356. init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
  357. else
  358. init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
  359. if (dev_priv->card_type < NV_C0) {
  360. init->subchan[0].handle = NvM2MF;
  361. if (dev_priv->card_type < NV_50)
  362. init->subchan[0].grclass = 0x0039;
  363. else
  364. init->subchan[0].grclass = 0x5039;
  365. init->subchan[1].handle = NvSw;
  366. init->subchan[1].grclass = NV_SW;
  367. init->nr_subchan = 2;
  368. } else {
  369. init->subchan[0].handle = 0x9039;
  370. init->subchan[0].grclass = 0x9039;
  371. init->nr_subchan = 1;
  372. }
  373. /* Named memory object area */
  374. ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
  375. &init->notifier_handle);
  376. if (ret == 0)
  377. atomic_inc(&chan->users); /* userspace reference */
  378. nouveau_channel_put(&chan);
  379. return ret;
  380. }
  381. static int
  382. nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
  383. struct drm_file *file_priv)
  384. {
  385. struct drm_nouveau_channel_free *req = data;
  386. struct nouveau_channel *chan;
  387. chan = nouveau_channel_get(file_priv, req->channel);
  388. if (IS_ERR(chan))
  389. return PTR_ERR(chan);
  390. list_del(&chan->list);
  391. atomic_dec(&chan->users);
  392. nouveau_channel_put(&chan);
  393. return 0;
  394. }
  395. /***********************************
  396. * finally, the ioctl table
  397. ***********************************/
  398. struct drm_ioctl_desc nouveau_ioctls[] = {
  399. DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
  400. DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  401. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
  402. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
  403. DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
  404. DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
  405. DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
  406. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
  407. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
  408. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
  409. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
  410. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
  411. };
  412. int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);