nouveau_bo.c 28 KB

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  1. /*
  2. * Copyright 2007 Dave Airlied
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. /*
  25. * Authors: Dave Airlied <airlied@linux.ie>
  26. * Ben Skeggs <darktama@iinet.net.au>
  27. * Jeremy Kolb <jkolb@brandeis.edu>
  28. */
  29. #include "drmP.h"
  30. #include "nouveau_drm.h"
  31. #include "nouveau_drv.h"
  32. #include "nouveau_dma.h"
  33. #include "nouveau_mm.h"
  34. #include "nouveau_vm.h"
  35. #include <linux/log2.h>
  36. #include <linux/slab.h>
  37. static void
  38. nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
  39. {
  40. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  41. struct drm_device *dev = dev_priv->dev;
  42. struct nouveau_bo *nvbo = nouveau_bo(bo);
  43. if (unlikely(nvbo->gem))
  44. DRM_ERROR("bo %p still attached to GEM object\n", bo);
  45. nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
  46. kfree(nvbo);
  47. }
  48. static void
  49. nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
  50. int *align, int *size)
  51. {
  52. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  53. if (dev_priv->card_type < NV_50) {
  54. if (nvbo->tile_mode) {
  55. if (dev_priv->chipset >= 0x40) {
  56. *align = 65536;
  57. *size = roundup(*size, 64 * nvbo->tile_mode);
  58. } else if (dev_priv->chipset >= 0x30) {
  59. *align = 32768;
  60. *size = roundup(*size, 64 * nvbo->tile_mode);
  61. } else if (dev_priv->chipset >= 0x20) {
  62. *align = 16384;
  63. *size = roundup(*size, 64 * nvbo->tile_mode);
  64. } else if (dev_priv->chipset >= 0x10) {
  65. *align = 16384;
  66. *size = roundup(*size, 32 * nvbo->tile_mode);
  67. }
  68. }
  69. } else {
  70. *size = roundup(*size, (1 << nvbo->page_shift));
  71. *align = max((1 << nvbo->page_shift), *align);
  72. }
  73. *size = roundup(*size, PAGE_SIZE);
  74. }
  75. int
  76. nouveau_bo_new(struct drm_device *dev, int size, int align,
  77. uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
  78. struct nouveau_bo **pnvbo)
  79. {
  80. struct drm_nouveau_private *dev_priv = dev->dev_private;
  81. struct nouveau_bo *nvbo;
  82. int ret;
  83. nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
  84. if (!nvbo)
  85. return -ENOMEM;
  86. INIT_LIST_HEAD(&nvbo->head);
  87. INIT_LIST_HEAD(&nvbo->entry);
  88. INIT_LIST_HEAD(&nvbo->vma_list);
  89. nvbo->tile_mode = tile_mode;
  90. nvbo->tile_flags = tile_flags;
  91. nvbo->bo.bdev = &dev_priv->ttm.bdev;
  92. nvbo->page_shift = 12;
  93. if (dev_priv->bar1_vm) {
  94. if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
  95. nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
  96. }
  97. nouveau_bo_fixup_align(nvbo, flags, &align, &size);
  98. nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
  99. nouveau_bo_placement_set(nvbo, flags, 0);
  100. ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
  101. ttm_bo_type_device, &nvbo->placement,
  102. align >> PAGE_SHIFT, 0, false, NULL, size,
  103. nouveau_bo_del_ttm);
  104. if (ret) {
  105. /* ttm will call nouveau_bo_del_ttm if it fails.. */
  106. return ret;
  107. }
  108. *pnvbo = nvbo;
  109. return 0;
  110. }
  111. static void
  112. set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
  113. {
  114. *n = 0;
  115. if (type & TTM_PL_FLAG_VRAM)
  116. pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
  117. if (type & TTM_PL_FLAG_TT)
  118. pl[(*n)++] = TTM_PL_FLAG_TT | flags;
  119. if (type & TTM_PL_FLAG_SYSTEM)
  120. pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
  121. }
  122. static void
  123. set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
  124. {
  125. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  126. int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
  127. if (dev_priv->card_type == NV_10 &&
  128. nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
  129. nvbo->bo.mem.num_pages < vram_pages / 2) {
  130. /*
  131. * Make sure that the color and depth buffers are handled
  132. * by independent memory controller units. Up to a 9x
  133. * speed up when alpha-blending and depth-test are enabled
  134. * at the same time.
  135. */
  136. if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
  137. nvbo->placement.fpfn = vram_pages / 2;
  138. nvbo->placement.lpfn = ~0;
  139. } else {
  140. nvbo->placement.fpfn = 0;
  141. nvbo->placement.lpfn = vram_pages / 2;
  142. }
  143. }
  144. }
  145. void
  146. nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
  147. {
  148. struct ttm_placement *pl = &nvbo->placement;
  149. uint32_t flags = TTM_PL_MASK_CACHING |
  150. (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
  151. pl->placement = nvbo->placements;
  152. set_placement_list(nvbo->placements, &pl->num_placement,
  153. type, flags);
  154. pl->busy_placement = nvbo->busy_placements;
  155. set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
  156. type | busy, flags);
  157. set_placement_range(nvbo, type);
  158. }
  159. int
  160. nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
  161. {
  162. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  163. struct ttm_buffer_object *bo = &nvbo->bo;
  164. int ret;
  165. if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
  166. NV_ERROR(nouveau_bdev(bo->bdev)->dev,
  167. "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
  168. 1 << bo->mem.mem_type, memtype);
  169. return -EINVAL;
  170. }
  171. if (nvbo->pin_refcnt++)
  172. return 0;
  173. ret = ttm_bo_reserve(bo, false, false, false, 0);
  174. if (ret)
  175. goto out;
  176. nouveau_bo_placement_set(nvbo, memtype, 0);
  177. ret = nouveau_bo_validate(nvbo, false, false, false);
  178. if (ret == 0) {
  179. switch (bo->mem.mem_type) {
  180. case TTM_PL_VRAM:
  181. dev_priv->fb_aper_free -= bo->mem.size;
  182. break;
  183. case TTM_PL_TT:
  184. dev_priv->gart_info.aper_free -= bo->mem.size;
  185. break;
  186. default:
  187. break;
  188. }
  189. }
  190. ttm_bo_unreserve(bo);
  191. out:
  192. if (unlikely(ret))
  193. nvbo->pin_refcnt--;
  194. return ret;
  195. }
  196. int
  197. nouveau_bo_unpin(struct nouveau_bo *nvbo)
  198. {
  199. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  200. struct ttm_buffer_object *bo = &nvbo->bo;
  201. int ret;
  202. if (--nvbo->pin_refcnt)
  203. return 0;
  204. ret = ttm_bo_reserve(bo, false, false, false, 0);
  205. if (ret)
  206. return ret;
  207. nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
  208. ret = nouveau_bo_validate(nvbo, false, false, false);
  209. if (ret == 0) {
  210. switch (bo->mem.mem_type) {
  211. case TTM_PL_VRAM:
  212. dev_priv->fb_aper_free += bo->mem.size;
  213. break;
  214. case TTM_PL_TT:
  215. dev_priv->gart_info.aper_free += bo->mem.size;
  216. break;
  217. default:
  218. break;
  219. }
  220. }
  221. ttm_bo_unreserve(bo);
  222. return ret;
  223. }
  224. int
  225. nouveau_bo_map(struct nouveau_bo *nvbo)
  226. {
  227. int ret;
  228. ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
  229. if (ret)
  230. return ret;
  231. ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
  232. ttm_bo_unreserve(&nvbo->bo);
  233. return ret;
  234. }
  235. void
  236. nouveau_bo_unmap(struct nouveau_bo *nvbo)
  237. {
  238. if (nvbo)
  239. ttm_bo_kunmap(&nvbo->kmap);
  240. }
  241. int
  242. nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
  243. bool no_wait_reserve, bool no_wait_gpu)
  244. {
  245. int ret;
  246. ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
  247. no_wait_reserve, no_wait_gpu);
  248. if (ret)
  249. return ret;
  250. return 0;
  251. }
  252. u16
  253. nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
  254. {
  255. bool is_iomem;
  256. u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  257. mem = &mem[index];
  258. if (is_iomem)
  259. return ioread16_native((void __force __iomem *)mem);
  260. else
  261. return *mem;
  262. }
  263. void
  264. nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
  265. {
  266. bool is_iomem;
  267. u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  268. mem = &mem[index];
  269. if (is_iomem)
  270. iowrite16_native(val, (void __force __iomem *)mem);
  271. else
  272. *mem = val;
  273. }
  274. u32
  275. nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
  276. {
  277. bool is_iomem;
  278. u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  279. mem = &mem[index];
  280. if (is_iomem)
  281. return ioread32_native((void __force __iomem *)mem);
  282. else
  283. return *mem;
  284. }
  285. void
  286. nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
  287. {
  288. bool is_iomem;
  289. u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  290. mem = &mem[index];
  291. if (is_iomem)
  292. iowrite32_native(val, (void __force __iomem *)mem);
  293. else
  294. *mem = val;
  295. }
  296. static struct ttm_backend *
  297. nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
  298. {
  299. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  300. struct drm_device *dev = dev_priv->dev;
  301. switch (dev_priv->gart_info.type) {
  302. #if __OS_HAS_AGP
  303. case NOUVEAU_GART_AGP:
  304. return ttm_agp_backend_init(bdev, dev->agp->bridge);
  305. #endif
  306. case NOUVEAU_GART_PDMA:
  307. case NOUVEAU_GART_HW:
  308. return nouveau_sgdma_init_ttm(dev);
  309. default:
  310. NV_ERROR(dev, "Unknown GART type %d\n",
  311. dev_priv->gart_info.type);
  312. break;
  313. }
  314. return NULL;
  315. }
  316. static int
  317. nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  318. {
  319. /* We'll do this from user space. */
  320. return 0;
  321. }
  322. static int
  323. nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  324. struct ttm_mem_type_manager *man)
  325. {
  326. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  327. struct drm_device *dev = dev_priv->dev;
  328. switch (type) {
  329. case TTM_PL_SYSTEM:
  330. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  331. man->available_caching = TTM_PL_MASK_CACHING;
  332. man->default_caching = TTM_PL_FLAG_CACHED;
  333. break;
  334. case TTM_PL_VRAM:
  335. if (dev_priv->card_type >= NV_50) {
  336. man->func = &nouveau_vram_manager;
  337. man->io_reserve_fastpath = false;
  338. man->use_io_reserve_lru = true;
  339. } else {
  340. man->func = &ttm_bo_manager_func;
  341. }
  342. man->flags = TTM_MEMTYPE_FLAG_FIXED |
  343. TTM_MEMTYPE_FLAG_MAPPABLE;
  344. man->available_caching = TTM_PL_FLAG_UNCACHED |
  345. TTM_PL_FLAG_WC;
  346. man->default_caching = TTM_PL_FLAG_WC;
  347. break;
  348. case TTM_PL_TT:
  349. if (dev_priv->card_type >= NV_50)
  350. man->func = &nouveau_gart_manager;
  351. else
  352. man->func = &ttm_bo_manager_func;
  353. switch (dev_priv->gart_info.type) {
  354. case NOUVEAU_GART_AGP:
  355. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  356. man->available_caching = TTM_PL_FLAG_UNCACHED |
  357. TTM_PL_FLAG_WC;
  358. man->default_caching = TTM_PL_FLAG_WC;
  359. break;
  360. case NOUVEAU_GART_PDMA:
  361. case NOUVEAU_GART_HW:
  362. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
  363. TTM_MEMTYPE_FLAG_CMA;
  364. man->available_caching = TTM_PL_MASK_CACHING;
  365. man->default_caching = TTM_PL_FLAG_CACHED;
  366. break;
  367. default:
  368. NV_ERROR(dev, "Unknown GART type: %d\n",
  369. dev_priv->gart_info.type);
  370. return -EINVAL;
  371. }
  372. break;
  373. default:
  374. NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
  375. return -EINVAL;
  376. }
  377. return 0;
  378. }
  379. static void
  380. nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
  381. {
  382. struct nouveau_bo *nvbo = nouveau_bo(bo);
  383. switch (bo->mem.mem_type) {
  384. case TTM_PL_VRAM:
  385. nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
  386. TTM_PL_FLAG_SYSTEM);
  387. break;
  388. default:
  389. nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
  390. break;
  391. }
  392. *pl = nvbo->placement;
  393. }
  394. /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
  395. * TTM_PL_{VRAM,TT} directly.
  396. */
  397. static int
  398. nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
  399. struct nouveau_bo *nvbo, bool evict,
  400. bool no_wait_reserve, bool no_wait_gpu,
  401. struct ttm_mem_reg *new_mem)
  402. {
  403. struct nouveau_fence *fence = NULL;
  404. int ret;
  405. ret = nouveau_fence_new(chan, &fence, true);
  406. if (ret)
  407. return ret;
  408. ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
  409. no_wait_reserve, no_wait_gpu, new_mem);
  410. nouveau_fence_unref(&fence);
  411. return ret;
  412. }
  413. static int
  414. nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
  415. struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
  416. {
  417. struct nouveau_mem *node = old_mem->mm_node;
  418. u64 src_offset = node->vma[0].offset;
  419. u64 dst_offset = node->vma[1].offset;
  420. u32 page_count = new_mem->num_pages;
  421. int ret;
  422. page_count = new_mem->num_pages;
  423. while (page_count) {
  424. int line_count = (page_count > 2047) ? 2047 : page_count;
  425. ret = RING_SPACE(chan, 12);
  426. if (ret)
  427. return ret;
  428. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2);
  429. OUT_RING (chan, upper_32_bits(dst_offset));
  430. OUT_RING (chan, lower_32_bits(dst_offset));
  431. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6);
  432. OUT_RING (chan, upper_32_bits(src_offset));
  433. OUT_RING (chan, lower_32_bits(src_offset));
  434. OUT_RING (chan, PAGE_SIZE); /* src_pitch */
  435. OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
  436. OUT_RING (chan, PAGE_SIZE); /* line_length */
  437. OUT_RING (chan, line_count);
  438. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1);
  439. OUT_RING (chan, 0x00100110);
  440. page_count -= line_count;
  441. src_offset += (PAGE_SIZE * line_count);
  442. dst_offset += (PAGE_SIZE * line_count);
  443. }
  444. return 0;
  445. }
  446. static int
  447. nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
  448. struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
  449. {
  450. struct nouveau_mem *node = old_mem->mm_node;
  451. struct nouveau_bo *nvbo = nouveau_bo(bo);
  452. u64 length = (new_mem->num_pages << PAGE_SHIFT);
  453. u64 src_offset = node->vma[0].offset;
  454. u64 dst_offset = node->vma[1].offset;
  455. int ret;
  456. while (length) {
  457. u32 amount, stride, height;
  458. amount = min(length, (u64)(4 * 1024 * 1024));
  459. stride = 16 * 4;
  460. height = amount / stride;
  461. if (new_mem->mem_type == TTM_PL_VRAM &&
  462. nouveau_bo_tile_layout(nvbo)) {
  463. ret = RING_SPACE(chan, 8);
  464. if (ret)
  465. return ret;
  466. BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
  467. OUT_RING (chan, 0);
  468. OUT_RING (chan, 0);
  469. OUT_RING (chan, stride);
  470. OUT_RING (chan, height);
  471. OUT_RING (chan, 1);
  472. OUT_RING (chan, 0);
  473. OUT_RING (chan, 0);
  474. } else {
  475. ret = RING_SPACE(chan, 2);
  476. if (ret)
  477. return ret;
  478. BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
  479. OUT_RING (chan, 1);
  480. }
  481. if (old_mem->mem_type == TTM_PL_VRAM &&
  482. nouveau_bo_tile_layout(nvbo)) {
  483. ret = RING_SPACE(chan, 8);
  484. if (ret)
  485. return ret;
  486. BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
  487. OUT_RING (chan, 0);
  488. OUT_RING (chan, 0);
  489. OUT_RING (chan, stride);
  490. OUT_RING (chan, height);
  491. OUT_RING (chan, 1);
  492. OUT_RING (chan, 0);
  493. OUT_RING (chan, 0);
  494. } else {
  495. ret = RING_SPACE(chan, 2);
  496. if (ret)
  497. return ret;
  498. BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
  499. OUT_RING (chan, 1);
  500. }
  501. ret = RING_SPACE(chan, 14);
  502. if (ret)
  503. return ret;
  504. BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
  505. OUT_RING (chan, upper_32_bits(src_offset));
  506. OUT_RING (chan, upper_32_bits(dst_offset));
  507. BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
  508. OUT_RING (chan, lower_32_bits(src_offset));
  509. OUT_RING (chan, lower_32_bits(dst_offset));
  510. OUT_RING (chan, stride);
  511. OUT_RING (chan, stride);
  512. OUT_RING (chan, stride);
  513. OUT_RING (chan, height);
  514. OUT_RING (chan, 0x00000101);
  515. OUT_RING (chan, 0x00000000);
  516. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
  517. OUT_RING (chan, 0);
  518. length -= amount;
  519. src_offset += amount;
  520. dst_offset += amount;
  521. }
  522. return 0;
  523. }
  524. static inline uint32_t
  525. nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
  526. struct nouveau_channel *chan, struct ttm_mem_reg *mem)
  527. {
  528. if (mem->mem_type == TTM_PL_TT)
  529. return chan->gart_handle;
  530. return chan->vram_handle;
  531. }
  532. static int
  533. nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
  534. struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
  535. {
  536. u32 src_offset = old_mem->start << PAGE_SHIFT;
  537. u32 dst_offset = new_mem->start << PAGE_SHIFT;
  538. u32 page_count = new_mem->num_pages;
  539. int ret;
  540. ret = RING_SPACE(chan, 3);
  541. if (ret)
  542. return ret;
  543. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
  544. OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
  545. OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
  546. page_count = new_mem->num_pages;
  547. while (page_count) {
  548. int line_count = (page_count > 2047) ? 2047 : page_count;
  549. ret = RING_SPACE(chan, 11);
  550. if (ret)
  551. return ret;
  552. BEGIN_RING(chan, NvSubM2MF,
  553. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  554. OUT_RING (chan, src_offset);
  555. OUT_RING (chan, dst_offset);
  556. OUT_RING (chan, PAGE_SIZE); /* src_pitch */
  557. OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
  558. OUT_RING (chan, PAGE_SIZE); /* line_length */
  559. OUT_RING (chan, line_count);
  560. OUT_RING (chan, 0x00000101);
  561. OUT_RING (chan, 0x00000000);
  562. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
  563. OUT_RING (chan, 0);
  564. page_count -= line_count;
  565. src_offset += (PAGE_SIZE * line_count);
  566. dst_offset += (PAGE_SIZE * line_count);
  567. }
  568. return 0;
  569. }
  570. static int
  571. nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
  572. struct ttm_mem_reg *mem, struct nouveau_vma *vma)
  573. {
  574. struct nouveau_mem *node = mem->mm_node;
  575. int ret;
  576. ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
  577. node->page_shift, NV_MEM_ACCESS_RO, vma);
  578. if (ret)
  579. return ret;
  580. if (mem->mem_type == TTM_PL_VRAM)
  581. nouveau_vm_map(vma, node);
  582. else
  583. nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT,
  584. node, node->pages);
  585. return 0;
  586. }
  587. static int
  588. nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
  589. bool no_wait_reserve, bool no_wait_gpu,
  590. struct ttm_mem_reg *new_mem)
  591. {
  592. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  593. struct nouveau_bo *nvbo = nouveau_bo(bo);
  594. struct ttm_mem_reg *old_mem = &bo->mem;
  595. struct nouveau_channel *chan;
  596. int ret;
  597. chan = nvbo->channel;
  598. if (!chan) {
  599. chan = dev_priv->channel;
  600. mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
  601. }
  602. /* create temporary vmas for the transfer and attach them to the
  603. * old nouveau_mem node, these will get cleaned up after ttm has
  604. * destroyed the ttm_mem_reg
  605. */
  606. if (dev_priv->card_type >= NV_50) {
  607. struct nouveau_mem *node = old_mem->mm_node;
  608. ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
  609. if (ret)
  610. goto out;
  611. ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
  612. if (ret)
  613. goto out;
  614. }
  615. if (dev_priv->card_type < NV_50)
  616. ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
  617. else
  618. if (dev_priv->card_type < NV_C0)
  619. ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
  620. else
  621. ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
  622. if (ret == 0) {
  623. ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
  624. no_wait_reserve,
  625. no_wait_gpu, new_mem);
  626. }
  627. out:
  628. if (chan == dev_priv->channel)
  629. mutex_unlock(&chan->mutex);
  630. return ret;
  631. }
  632. static int
  633. nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
  634. bool no_wait_reserve, bool no_wait_gpu,
  635. struct ttm_mem_reg *new_mem)
  636. {
  637. u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  638. struct ttm_placement placement;
  639. struct ttm_mem_reg tmp_mem;
  640. int ret;
  641. placement.fpfn = placement.lpfn = 0;
  642. placement.num_placement = placement.num_busy_placement = 1;
  643. placement.placement = placement.busy_placement = &placement_memtype;
  644. tmp_mem = *new_mem;
  645. tmp_mem.mm_node = NULL;
  646. ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
  647. if (ret)
  648. return ret;
  649. ret = ttm_tt_bind(bo->ttm, &tmp_mem);
  650. if (ret)
  651. goto out;
  652. ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
  653. if (ret)
  654. goto out;
  655. ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
  656. out:
  657. ttm_bo_mem_put(bo, &tmp_mem);
  658. return ret;
  659. }
  660. static int
  661. nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
  662. bool no_wait_reserve, bool no_wait_gpu,
  663. struct ttm_mem_reg *new_mem)
  664. {
  665. u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  666. struct ttm_placement placement;
  667. struct ttm_mem_reg tmp_mem;
  668. int ret;
  669. placement.fpfn = placement.lpfn = 0;
  670. placement.num_placement = placement.num_busy_placement = 1;
  671. placement.placement = placement.busy_placement = &placement_memtype;
  672. tmp_mem = *new_mem;
  673. tmp_mem.mm_node = NULL;
  674. ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
  675. if (ret)
  676. return ret;
  677. ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
  678. if (ret)
  679. goto out;
  680. ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
  681. if (ret)
  682. goto out;
  683. out:
  684. ttm_bo_mem_put(bo, &tmp_mem);
  685. return ret;
  686. }
  687. static void
  688. nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
  689. {
  690. struct nouveau_mem *node = new_mem->mm_node;
  691. struct nouveau_bo *nvbo = nouveau_bo(bo);
  692. struct nouveau_vma *vma;
  693. list_for_each_entry(vma, &nvbo->vma_list, head) {
  694. if (new_mem->mem_type == TTM_PL_VRAM) {
  695. nouveau_vm_map(vma, new_mem->mm_node);
  696. } else
  697. if (new_mem->mem_type == TTM_PL_TT &&
  698. nvbo->page_shift == vma->vm->spg_shift) {
  699. nouveau_vm_map_sg(vma, 0, new_mem->
  700. num_pages << PAGE_SHIFT,
  701. node, node->pages);
  702. } else {
  703. nouveau_vm_unmap(vma);
  704. }
  705. }
  706. }
  707. static int
  708. nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
  709. struct nouveau_tile_reg **new_tile)
  710. {
  711. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  712. struct drm_device *dev = dev_priv->dev;
  713. struct nouveau_bo *nvbo = nouveau_bo(bo);
  714. u64 offset = new_mem->start << PAGE_SHIFT;
  715. *new_tile = NULL;
  716. if (new_mem->mem_type != TTM_PL_VRAM)
  717. return 0;
  718. if (dev_priv->card_type >= NV_10) {
  719. *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
  720. nvbo->tile_mode,
  721. nvbo->tile_flags);
  722. }
  723. return 0;
  724. }
  725. static void
  726. nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
  727. struct nouveau_tile_reg *new_tile,
  728. struct nouveau_tile_reg **old_tile)
  729. {
  730. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  731. struct drm_device *dev = dev_priv->dev;
  732. nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
  733. *old_tile = new_tile;
  734. }
  735. static int
  736. nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
  737. bool no_wait_reserve, bool no_wait_gpu,
  738. struct ttm_mem_reg *new_mem)
  739. {
  740. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  741. struct nouveau_bo *nvbo = nouveau_bo(bo);
  742. struct ttm_mem_reg *old_mem = &bo->mem;
  743. struct nouveau_tile_reg *new_tile = NULL;
  744. int ret = 0;
  745. if (dev_priv->card_type < NV_50) {
  746. ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
  747. if (ret)
  748. return ret;
  749. }
  750. /* Fake bo copy. */
  751. if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
  752. BUG_ON(bo->mem.mm_node != NULL);
  753. bo->mem = *new_mem;
  754. new_mem->mm_node = NULL;
  755. goto out;
  756. }
  757. /* Software copy if the card isn't up and running yet. */
  758. if (!dev_priv->channel) {
  759. ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
  760. goto out;
  761. }
  762. /* Hardware assisted copy. */
  763. if (new_mem->mem_type == TTM_PL_SYSTEM)
  764. ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  765. else if (old_mem->mem_type == TTM_PL_SYSTEM)
  766. ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  767. else
  768. ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  769. if (!ret)
  770. goto out;
  771. /* Fallback to software copy. */
  772. ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
  773. out:
  774. if (dev_priv->card_type < NV_50) {
  775. if (ret)
  776. nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
  777. else
  778. nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
  779. }
  780. return ret;
  781. }
  782. static int
  783. nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  784. {
  785. return 0;
  786. }
  787. static int
  788. nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  789. {
  790. struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
  791. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  792. struct drm_device *dev = dev_priv->dev;
  793. int ret;
  794. mem->bus.addr = NULL;
  795. mem->bus.offset = 0;
  796. mem->bus.size = mem->num_pages << PAGE_SHIFT;
  797. mem->bus.base = 0;
  798. mem->bus.is_iomem = false;
  799. if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
  800. return -EINVAL;
  801. switch (mem->mem_type) {
  802. case TTM_PL_SYSTEM:
  803. /* System memory */
  804. return 0;
  805. case TTM_PL_TT:
  806. #if __OS_HAS_AGP
  807. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  808. mem->bus.offset = mem->start << PAGE_SHIFT;
  809. mem->bus.base = dev_priv->gart_info.aper_base;
  810. mem->bus.is_iomem = true;
  811. }
  812. #endif
  813. break;
  814. case TTM_PL_VRAM:
  815. {
  816. struct nouveau_mem *node = mem->mm_node;
  817. u8 page_shift;
  818. if (!dev_priv->bar1_vm) {
  819. mem->bus.offset = mem->start << PAGE_SHIFT;
  820. mem->bus.base = pci_resource_start(dev->pdev, 1);
  821. mem->bus.is_iomem = true;
  822. break;
  823. }
  824. if (dev_priv->card_type == NV_C0)
  825. page_shift = node->page_shift;
  826. else
  827. page_shift = 12;
  828. ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
  829. page_shift, NV_MEM_ACCESS_RW,
  830. &node->bar_vma);
  831. if (ret)
  832. return ret;
  833. nouveau_vm_map(&node->bar_vma, node);
  834. if (ret) {
  835. nouveau_vm_put(&node->bar_vma);
  836. return ret;
  837. }
  838. mem->bus.offset = node->bar_vma.offset;
  839. if (dev_priv->card_type == NV_50) /*XXX*/
  840. mem->bus.offset -= 0x0020000000ULL;
  841. mem->bus.base = pci_resource_start(dev->pdev, 1);
  842. mem->bus.is_iomem = true;
  843. }
  844. break;
  845. default:
  846. return -EINVAL;
  847. }
  848. return 0;
  849. }
  850. static void
  851. nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  852. {
  853. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  854. struct nouveau_mem *node = mem->mm_node;
  855. if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
  856. return;
  857. if (!node->bar_vma.node)
  858. return;
  859. nouveau_vm_unmap(&node->bar_vma);
  860. nouveau_vm_put(&node->bar_vma);
  861. }
  862. static int
  863. nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
  864. {
  865. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  866. struct nouveau_bo *nvbo = nouveau_bo(bo);
  867. /* as long as the bo isn't in vram, and isn't tiled, we've got
  868. * nothing to do here.
  869. */
  870. if (bo->mem.mem_type != TTM_PL_VRAM) {
  871. if (dev_priv->card_type < NV_50 ||
  872. !nouveau_bo_tile_layout(nvbo))
  873. return 0;
  874. }
  875. /* make sure bo is in mappable vram */
  876. if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
  877. return 0;
  878. nvbo->placement.fpfn = 0;
  879. nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
  880. nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
  881. return nouveau_bo_validate(nvbo, false, true, false);
  882. }
  883. void
  884. nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
  885. {
  886. struct nouveau_fence *old_fence;
  887. if (likely(fence))
  888. nouveau_fence_ref(fence);
  889. spin_lock(&nvbo->bo.bdev->fence_lock);
  890. old_fence = nvbo->bo.sync_obj;
  891. nvbo->bo.sync_obj = fence;
  892. spin_unlock(&nvbo->bo.bdev->fence_lock);
  893. nouveau_fence_unref(&old_fence);
  894. }
  895. struct ttm_bo_driver nouveau_bo_driver = {
  896. .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
  897. .invalidate_caches = nouveau_bo_invalidate_caches,
  898. .init_mem_type = nouveau_bo_init_mem_type,
  899. .evict_flags = nouveau_bo_evict_flags,
  900. .move_notify = nouveau_bo_move_ntfy,
  901. .move = nouveau_bo_move,
  902. .verify_access = nouveau_bo_verify_access,
  903. .sync_obj_signaled = __nouveau_fence_signalled,
  904. .sync_obj_wait = __nouveau_fence_wait,
  905. .sync_obj_flush = __nouveau_fence_flush,
  906. .sync_obj_unref = __nouveau_fence_unref,
  907. .sync_obj_ref = __nouveau_fence_ref,
  908. .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
  909. .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
  910. .io_mem_free = &nouveau_ttm_io_mem_free,
  911. };
  912. struct nouveau_vma *
  913. nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
  914. {
  915. struct nouveau_vma *vma;
  916. list_for_each_entry(vma, &nvbo->vma_list, head) {
  917. if (vma->vm == vm)
  918. return vma;
  919. }
  920. return NULL;
  921. }
  922. int
  923. nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
  924. struct nouveau_vma *vma)
  925. {
  926. const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
  927. struct nouveau_mem *node = nvbo->bo.mem.mm_node;
  928. int ret;
  929. ret = nouveau_vm_get(vm, size, nvbo->page_shift,
  930. NV_MEM_ACCESS_RW, vma);
  931. if (ret)
  932. return ret;
  933. if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
  934. nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
  935. else
  936. if (nvbo->bo.mem.mem_type == TTM_PL_TT)
  937. nouveau_vm_map_sg(vma, 0, size, node, node->pages);
  938. list_add_tail(&vma->head, &nvbo->vma_list);
  939. vma->refcount = 1;
  940. return 0;
  941. }
  942. void
  943. nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
  944. {
  945. if (vma->node) {
  946. if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
  947. spin_lock(&nvbo->bo.bdev->fence_lock);
  948. ttm_bo_wait(&nvbo->bo, false, false, false);
  949. spin_unlock(&nvbo->bo.bdev->fence_lock);
  950. nouveau_vm_unmap(vma);
  951. }
  952. nouveau_vm_put(vma);
  953. list_del(&vma->head);
  954. }
  955. }