i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/slab.h>
  39. #include <linux/pagemap.h>
  40. #define I810_BUF_FREE 2
  41. #define I810_BUF_CLIENT 1
  42. #define I810_BUF_HARDWARE 0
  43. #define I810_BUF_UNMAPPED 0
  44. #define I810_BUF_MAPPED 1
  45. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  46. {
  47. struct drm_device_dma *dma = dev->dma;
  48. int i;
  49. int used;
  50. /* Linear search might not be the best solution */
  51. for (i = 0; i < dma->buf_count; i++) {
  52. struct drm_buf *buf = dma->buflist[i];
  53. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  54. /* In use is already a pointer */
  55. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  56. I810_BUF_CLIENT);
  57. if (used == I810_BUF_FREE)
  58. return buf;
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(struct drm_device *dev, struct drm_buf *buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. struct drm_file *priv = filp->private_data;
  80. struct drm_device *dev;
  81. drm_i810_private_t *dev_priv;
  82. struct drm_buf *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. dev = priv->minor->dev;
  85. dev_priv = dev->dev_private;
  86. buf = dev_priv->mmap_buffer;
  87. buf_priv = buf->dev_private;
  88. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  89. vma->vm_file = filp;
  90. buf_priv->currently_mapped = I810_BUF_MAPPED;
  91. if (io_remap_pfn_range(vma, vma->vm_start,
  92. vma->vm_pgoff,
  93. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  94. return -EAGAIN;
  95. return 0;
  96. }
  97. static const struct file_operations i810_buffer_fops = {
  98. .open = drm_open,
  99. .release = drm_release,
  100. .unlocked_ioctl = drm_ioctl,
  101. .mmap = i810_mmap_buffers,
  102. .fasync = drm_fasync,
  103. .llseek = noop_llseek,
  104. };
  105. static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv)
  106. {
  107. struct drm_device *dev = file_priv->minor->dev;
  108. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  109. drm_i810_private_t *dev_priv = dev->dev_private;
  110. const struct file_operations *old_fops;
  111. int retcode = 0;
  112. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  113. return -EINVAL;
  114. down_write(&current->mm->mmap_sem);
  115. old_fops = file_priv->filp->f_op;
  116. file_priv->filp->f_op = &i810_buffer_fops;
  117. dev_priv->mmap_buffer = buf;
  118. buf_priv->virtual = (void *)do_mmap(file_priv->filp, 0, buf->total,
  119. PROT_READ | PROT_WRITE,
  120. MAP_SHARED, buf->bus_address);
  121. dev_priv->mmap_buffer = NULL;
  122. file_priv->filp->f_op = old_fops;
  123. if (IS_ERR(buf_priv->virtual)) {
  124. /* Real error */
  125. DRM_ERROR("mmap error\n");
  126. retcode = PTR_ERR(buf_priv->virtual);
  127. buf_priv->virtual = NULL;
  128. }
  129. up_write(&current->mm->mmap_sem);
  130. return retcode;
  131. }
  132. static int i810_unmap_buffer(struct drm_buf *buf)
  133. {
  134. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  135. int retcode = 0;
  136. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  137. return -EINVAL;
  138. down_write(&current->mm->mmap_sem);
  139. retcode = do_munmap(current->mm,
  140. (unsigned long)buf_priv->virtual,
  141. (size_t) buf->total);
  142. up_write(&current->mm->mmap_sem);
  143. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  144. buf_priv->virtual = NULL;
  145. return retcode;
  146. }
  147. static int i810_dma_get_buffer(struct drm_device *dev, drm_i810_dma_t *d,
  148. struct drm_file *file_priv)
  149. {
  150. struct drm_buf *buf;
  151. drm_i810_buf_priv_t *buf_priv;
  152. int retcode = 0;
  153. buf = i810_freelist_get(dev);
  154. if (!buf) {
  155. retcode = -ENOMEM;
  156. DRM_DEBUG("retcode=%d\n", retcode);
  157. return retcode;
  158. }
  159. retcode = i810_map_buffer(buf, file_priv);
  160. if (retcode) {
  161. i810_freelist_put(dev, buf);
  162. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  163. return retcode;
  164. }
  165. buf->file_priv = file_priv;
  166. buf_priv = buf->dev_private;
  167. d->granted = 1;
  168. d->request_idx = buf->idx;
  169. d->request_size = buf->total;
  170. d->virtual = buf_priv->virtual;
  171. return retcode;
  172. }
  173. static int i810_dma_cleanup(struct drm_device *dev)
  174. {
  175. struct drm_device_dma *dma = dev->dma;
  176. /* Make sure interrupts are disabled here because the uninstall ioctl
  177. * may not have been called from userspace and after dev_private
  178. * is freed, it's too late.
  179. */
  180. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  181. drm_irq_uninstall(dev);
  182. if (dev->dev_private) {
  183. int i;
  184. drm_i810_private_t *dev_priv =
  185. (drm_i810_private_t *) dev->dev_private;
  186. if (dev_priv->ring.virtual_start)
  187. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  188. if (dev_priv->hw_status_page) {
  189. pci_free_consistent(dev->pdev, PAGE_SIZE,
  190. dev_priv->hw_status_page,
  191. dev_priv->dma_status_page);
  192. /* Need to rewrite hardware status page */
  193. I810_WRITE(0x02080, 0x1ffff000);
  194. }
  195. kfree(dev->dev_private);
  196. dev->dev_private = NULL;
  197. for (i = 0; i < dma->buf_count; i++) {
  198. struct drm_buf *buf = dma->buflist[i];
  199. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  200. if (buf_priv->kernel_virtual && buf->total)
  201. drm_core_ioremapfree(&buf_priv->map, dev);
  202. }
  203. }
  204. return 0;
  205. }
  206. static int i810_wait_ring(struct drm_device *dev, int n)
  207. {
  208. drm_i810_private_t *dev_priv = dev->dev_private;
  209. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  210. int iters = 0;
  211. unsigned long end;
  212. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  213. end = jiffies + (HZ * 3);
  214. while (ring->space < n) {
  215. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  216. ring->space = ring->head - (ring->tail + 8);
  217. if (ring->space < 0)
  218. ring->space += ring->Size;
  219. if (ring->head != last_head) {
  220. end = jiffies + (HZ * 3);
  221. last_head = ring->head;
  222. }
  223. iters++;
  224. if (time_before(end, jiffies)) {
  225. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  226. DRM_ERROR("lockup\n");
  227. goto out_wait_ring;
  228. }
  229. udelay(1);
  230. }
  231. out_wait_ring:
  232. return iters;
  233. }
  234. static void i810_kernel_lost_context(struct drm_device *dev)
  235. {
  236. drm_i810_private_t *dev_priv = dev->dev_private;
  237. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  238. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  239. ring->tail = I810_READ(LP_RING + RING_TAIL);
  240. ring->space = ring->head - (ring->tail + 8);
  241. if (ring->space < 0)
  242. ring->space += ring->Size;
  243. }
  244. static int i810_freelist_init(struct drm_device *dev, drm_i810_private_t *dev_priv)
  245. {
  246. struct drm_device_dma *dma = dev->dma;
  247. int my_idx = 24;
  248. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  249. int i;
  250. if (dma->buf_count > 1019) {
  251. /* Not enough space in the status page for the freelist */
  252. return -EINVAL;
  253. }
  254. for (i = 0; i < dma->buf_count; i++) {
  255. struct drm_buf *buf = dma->buflist[i];
  256. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  257. buf_priv->in_use = hw_status++;
  258. buf_priv->my_use_idx = my_idx;
  259. my_idx += 4;
  260. *buf_priv->in_use = I810_BUF_FREE;
  261. buf_priv->map.offset = buf->bus_address;
  262. buf_priv->map.size = buf->total;
  263. buf_priv->map.type = _DRM_AGP;
  264. buf_priv->map.flags = 0;
  265. buf_priv->map.mtrr = 0;
  266. drm_core_ioremap(&buf_priv->map, dev);
  267. buf_priv->kernel_virtual = buf_priv->map.handle;
  268. }
  269. return 0;
  270. }
  271. static int i810_dma_initialize(struct drm_device *dev,
  272. drm_i810_private_t *dev_priv,
  273. drm_i810_init_t *init)
  274. {
  275. struct drm_map_list *r_list;
  276. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  277. list_for_each_entry(r_list, &dev->maplist, head) {
  278. if (r_list->map &&
  279. r_list->map->type == _DRM_SHM &&
  280. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  281. dev_priv->sarea_map = r_list->map;
  282. break;
  283. }
  284. }
  285. if (!dev_priv->sarea_map) {
  286. dev->dev_private = (void *)dev_priv;
  287. i810_dma_cleanup(dev);
  288. DRM_ERROR("can not find sarea!\n");
  289. return -EINVAL;
  290. }
  291. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  292. if (!dev_priv->mmio_map) {
  293. dev->dev_private = (void *)dev_priv;
  294. i810_dma_cleanup(dev);
  295. DRM_ERROR("can not find mmio map!\n");
  296. return -EINVAL;
  297. }
  298. dev->agp_buffer_token = init->buffers_offset;
  299. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  300. if (!dev->agp_buffer_map) {
  301. dev->dev_private = (void *)dev_priv;
  302. i810_dma_cleanup(dev);
  303. DRM_ERROR("can not find dma buffer map!\n");
  304. return -EINVAL;
  305. }
  306. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  307. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  308. dev_priv->ring.Start = init->ring_start;
  309. dev_priv->ring.End = init->ring_end;
  310. dev_priv->ring.Size = init->ring_size;
  311. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  312. dev_priv->ring.map.size = init->ring_size;
  313. dev_priv->ring.map.type = _DRM_AGP;
  314. dev_priv->ring.map.flags = 0;
  315. dev_priv->ring.map.mtrr = 0;
  316. drm_core_ioremap(&dev_priv->ring.map, dev);
  317. if (dev_priv->ring.map.handle == NULL) {
  318. dev->dev_private = (void *)dev_priv;
  319. i810_dma_cleanup(dev);
  320. DRM_ERROR("can not ioremap virtual address for"
  321. " ring buffer\n");
  322. return -ENOMEM;
  323. }
  324. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  325. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  326. dev_priv->w = init->w;
  327. dev_priv->h = init->h;
  328. dev_priv->pitch = init->pitch;
  329. dev_priv->back_offset = init->back_offset;
  330. dev_priv->depth_offset = init->depth_offset;
  331. dev_priv->front_offset = init->front_offset;
  332. dev_priv->overlay_offset = init->overlay_offset;
  333. dev_priv->overlay_physical = init->overlay_physical;
  334. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  335. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  336. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  337. /* Program Hardware Status Page */
  338. dev_priv->hw_status_page =
  339. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  340. &dev_priv->dma_status_page);
  341. if (!dev_priv->hw_status_page) {
  342. dev->dev_private = (void *)dev_priv;
  343. i810_dma_cleanup(dev);
  344. DRM_ERROR("Can not allocate hardware status page\n");
  345. return -ENOMEM;
  346. }
  347. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  348. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  349. I810_WRITE(0x02080, dev_priv->dma_status_page);
  350. DRM_DEBUG("Enabled hardware status page\n");
  351. /* Now we need to init our freelist */
  352. if (i810_freelist_init(dev, dev_priv) != 0) {
  353. dev->dev_private = (void *)dev_priv;
  354. i810_dma_cleanup(dev);
  355. DRM_ERROR("Not enough space in the status page for"
  356. " the freelist\n");
  357. return -ENOMEM;
  358. }
  359. dev->dev_private = (void *)dev_priv;
  360. return 0;
  361. }
  362. static int i810_dma_init(struct drm_device *dev, void *data,
  363. struct drm_file *file_priv)
  364. {
  365. drm_i810_private_t *dev_priv;
  366. drm_i810_init_t *init = data;
  367. int retcode = 0;
  368. switch (init->func) {
  369. case I810_INIT_DMA_1_4:
  370. DRM_INFO("Using v1.4 init.\n");
  371. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  372. if (dev_priv == NULL)
  373. return -ENOMEM;
  374. retcode = i810_dma_initialize(dev, dev_priv, init);
  375. break;
  376. case I810_CLEANUP_DMA:
  377. DRM_INFO("DMA Cleanup\n");
  378. retcode = i810_dma_cleanup(dev);
  379. break;
  380. default:
  381. return -EINVAL;
  382. }
  383. return retcode;
  384. }
  385. /* Most efficient way to verify state for the i810 is as it is
  386. * emitted. Non-conformant state is silently dropped.
  387. *
  388. * Use 'volatile' & local var tmp to force the emitted values to be
  389. * identical to the verified ones.
  390. */
  391. static void i810EmitContextVerified(struct drm_device *dev,
  392. volatile unsigned int *code)
  393. {
  394. drm_i810_private_t *dev_priv = dev->dev_private;
  395. int i, j = 0;
  396. unsigned int tmp;
  397. RING_LOCALS;
  398. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  399. OUT_RING(GFX_OP_COLOR_FACTOR);
  400. OUT_RING(code[I810_CTXREG_CF1]);
  401. OUT_RING(GFX_OP_STIPPLE);
  402. OUT_RING(code[I810_CTXREG_ST1]);
  403. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  404. tmp = code[i];
  405. if ((tmp & (7 << 29)) == (3 << 29) &&
  406. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  407. OUT_RING(tmp);
  408. j++;
  409. } else
  410. printk("constext state dropped!!!\n");
  411. }
  412. if (j & 1)
  413. OUT_RING(0);
  414. ADVANCE_LP_RING();
  415. }
  416. static void i810EmitTexVerified(struct drm_device *dev, volatile unsigned int *code)
  417. {
  418. drm_i810_private_t *dev_priv = dev->dev_private;
  419. int i, j = 0;
  420. unsigned int tmp;
  421. RING_LOCALS;
  422. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  423. OUT_RING(GFX_OP_MAP_INFO);
  424. OUT_RING(code[I810_TEXREG_MI1]);
  425. OUT_RING(code[I810_TEXREG_MI2]);
  426. OUT_RING(code[I810_TEXREG_MI3]);
  427. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  428. tmp = code[i];
  429. if ((tmp & (7 << 29)) == (3 << 29) &&
  430. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  431. OUT_RING(tmp);
  432. j++;
  433. } else
  434. printk("texture state dropped!!!\n");
  435. }
  436. if (j & 1)
  437. OUT_RING(0);
  438. ADVANCE_LP_RING();
  439. }
  440. /* Need to do some additional checking when setting the dest buffer.
  441. */
  442. static void i810EmitDestVerified(struct drm_device *dev,
  443. volatile unsigned int *code)
  444. {
  445. drm_i810_private_t *dev_priv = dev->dev_private;
  446. unsigned int tmp;
  447. RING_LOCALS;
  448. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  449. tmp = code[I810_DESTREG_DI1];
  450. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  451. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  452. OUT_RING(tmp);
  453. } else
  454. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  455. tmp, dev_priv->front_di1, dev_priv->back_di1);
  456. /* invarient:
  457. */
  458. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  459. OUT_RING(dev_priv->zi1);
  460. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  461. OUT_RING(code[I810_DESTREG_DV1]);
  462. OUT_RING(GFX_OP_DRAWRECT_INFO);
  463. OUT_RING(code[I810_DESTREG_DR1]);
  464. OUT_RING(code[I810_DESTREG_DR2]);
  465. OUT_RING(code[I810_DESTREG_DR3]);
  466. OUT_RING(code[I810_DESTREG_DR4]);
  467. OUT_RING(0);
  468. ADVANCE_LP_RING();
  469. }
  470. static void i810EmitState(struct drm_device *dev)
  471. {
  472. drm_i810_private_t *dev_priv = dev->dev_private;
  473. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  474. unsigned int dirty = sarea_priv->dirty;
  475. DRM_DEBUG("%x\n", dirty);
  476. if (dirty & I810_UPLOAD_BUFFERS) {
  477. i810EmitDestVerified(dev, sarea_priv->BufferState);
  478. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  479. }
  480. if (dirty & I810_UPLOAD_CTX) {
  481. i810EmitContextVerified(dev, sarea_priv->ContextState);
  482. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  483. }
  484. if (dirty & I810_UPLOAD_TEX0) {
  485. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  486. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  487. }
  488. if (dirty & I810_UPLOAD_TEX1) {
  489. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  490. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  491. }
  492. }
  493. /* need to verify
  494. */
  495. static void i810_dma_dispatch_clear(struct drm_device *dev, int flags,
  496. unsigned int clear_color,
  497. unsigned int clear_zval)
  498. {
  499. drm_i810_private_t *dev_priv = dev->dev_private;
  500. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  501. int nbox = sarea_priv->nbox;
  502. struct drm_clip_rect *pbox = sarea_priv->boxes;
  503. int pitch = dev_priv->pitch;
  504. int cpp = 2;
  505. int i;
  506. RING_LOCALS;
  507. if (dev_priv->current_page == 1) {
  508. unsigned int tmp = flags;
  509. flags &= ~(I810_FRONT | I810_BACK);
  510. if (tmp & I810_FRONT)
  511. flags |= I810_BACK;
  512. if (tmp & I810_BACK)
  513. flags |= I810_FRONT;
  514. }
  515. i810_kernel_lost_context(dev);
  516. if (nbox > I810_NR_SAREA_CLIPRECTS)
  517. nbox = I810_NR_SAREA_CLIPRECTS;
  518. for (i = 0; i < nbox; i++, pbox++) {
  519. unsigned int x = pbox->x1;
  520. unsigned int y = pbox->y1;
  521. unsigned int width = (pbox->x2 - x) * cpp;
  522. unsigned int height = pbox->y2 - y;
  523. unsigned int start = y * pitch + x * cpp;
  524. if (pbox->x1 > pbox->x2 ||
  525. pbox->y1 > pbox->y2 ||
  526. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  527. continue;
  528. if (flags & I810_FRONT) {
  529. BEGIN_LP_RING(6);
  530. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  531. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  532. OUT_RING((height << 16) | width);
  533. OUT_RING(start);
  534. OUT_RING(clear_color);
  535. OUT_RING(0);
  536. ADVANCE_LP_RING();
  537. }
  538. if (flags & I810_BACK) {
  539. BEGIN_LP_RING(6);
  540. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  541. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  542. OUT_RING((height << 16) | width);
  543. OUT_RING(dev_priv->back_offset + start);
  544. OUT_RING(clear_color);
  545. OUT_RING(0);
  546. ADVANCE_LP_RING();
  547. }
  548. if (flags & I810_DEPTH) {
  549. BEGIN_LP_RING(6);
  550. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  551. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  552. OUT_RING((height << 16) | width);
  553. OUT_RING(dev_priv->depth_offset + start);
  554. OUT_RING(clear_zval);
  555. OUT_RING(0);
  556. ADVANCE_LP_RING();
  557. }
  558. }
  559. }
  560. static void i810_dma_dispatch_swap(struct drm_device *dev)
  561. {
  562. drm_i810_private_t *dev_priv = dev->dev_private;
  563. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  564. int nbox = sarea_priv->nbox;
  565. struct drm_clip_rect *pbox = sarea_priv->boxes;
  566. int pitch = dev_priv->pitch;
  567. int cpp = 2;
  568. int i;
  569. RING_LOCALS;
  570. DRM_DEBUG("swapbuffers\n");
  571. i810_kernel_lost_context(dev);
  572. if (nbox > I810_NR_SAREA_CLIPRECTS)
  573. nbox = I810_NR_SAREA_CLIPRECTS;
  574. for (i = 0; i < nbox; i++, pbox++) {
  575. unsigned int w = pbox->x2 - pbox->x1;
  576. unsigned int h = pbox->y2 - pbox->y1;
  577. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  578. unsigned int start = dst;
  579. if (pbox->x1 > pbox->x2 ||
  580. pbox->y1 > pbox->y2 ||
  581. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  582. continue;
  583. BEGIN_LP_RING(6);
  584. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  585. OUT_RING(pitch | (0xCC << 16));
  586. OUT_RING((h << 16) | (w * cpp));
  587. if (dev_priv->current_page == 0)
  588. OUT_RING(dev_priv->front_offset + start);
  589. else
  590. OUT_RING(dev_priv->back_offset + start);
  591. OUT_RING(pitch);
  592. if (dev_priv->current_page == 0)
  593. OUT_RING(dev_priv->back_offset + start);
  594. else
  595. OUT_RING(dev_priv->front_offset + start);
  596. ADVANCE_LP_RING();
  597. }
  598. }
  599. static void i810_dma_dispatch_vertex(struct drm_device *dev,
  600. struct drm_buf *buf, int discard, int used)
  601. {
  602. drm_i810_private_t *dev_priv = dev->dev_private;
  603. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  604. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  605. struct drm_clip_rect *box = sarea_priv->boxes;
  606. int nbox = sarea_priv->nbox;
  607. unsigned long address = (unsigned long)buf->bus_address;
  608. unsigned long start = address - dev->agp->base;
  609. int i = 0;
  610. RING_LOCALS;
  611. i810_kernel_lost_context(dev);
  612. if (nbox > I810_NR_SAREA_CLIPRECTS)
  613. nbox = I810_NR_SAREA_CLIPRECTS;
  614. if (used > 4 * 1024)
  615. used = 0;
  616. if (sarea_priv->dirty)
  617. i810EmitState(dev);
  618. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  619. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  620. *(u32 *) buf_priv->kernel_virtual =
  621. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  622. if (used & 4) {
  623. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  624. used += 4;
  625. }
  626. i810_unmap_buffer(buf);
  627. }
  628. if (used) {
  629. do {
  630. if (i < nbox) {
  631. BEGIN_LP_RING(4);
  632. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  633. SC_ENABLE);
  634. OUT_RING(GFX_OP_SCISSOR_INFO);
  635. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  636. OUT_RING((box[i].x2 -
  637. 1) | ((box[i].y2 - 1) << 16));
  638. ADVANCE_LP_RING();
  639. }
  640. BEGIN_LP_RING(4);
  641. OUT_RING(CMD_OP_BATCH_BUFFER);
  642. OUT_RING(start | BB1_PROTECTED);
  643. OUT_RING(start + used - 4);
  644. OUT_RING(0);
  645. ADVANCE_LP_RING();
  646. } while (++i < nbox);
  647. }
  648. if (discard) {
  649. dev_priv->counter++;
  650. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  651. I810_BUF_HARDWARE);
  652. BEGIN_LP_RING(8);
  653. OUT_RING(CMD_STORE_DWORD_IDX);
  654. OUT_RING(20);
  655. OUT_RING(dev_priv->counter);
  656. OUT_RING(CMD_STORE_DWORD_IDX);
  657. OUT_RING(buf_priv->my_use_idx);
  658. OUT_RING(I810_BUF_FREE);
  659. OUT_RING(CMD_REPORT_HEAD);
  660. OUT_RING(0);
  661. ADVANCE_LP_RING();
  662. }
  663. }
  664. static void i810_dma_dispatch_flip(struct drm_device *dev)
  665. {
  666. drm_i810_private_t *dev_priv = dev->dev_private;
  667. int pitch = dev_priv->pitch;
  668. RING_LOCALS;
  669. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  670. dev_priv->current_page,
  671. dev_priv->sarea_priv->pf_current_page);
  672. i810_kernel_lost_context(dev);
  673. BEGIN_LP_RING(2);
  674. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  675. OUT_RING(0);
  676. ADVANCE_LP_RING();
  677. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  678. /* On i815 at least ASYNC is buggy */
  679. /* pitch<<5 is from 11.2.8 p158,
  680. its the pitch / 8 then left shifted 8,
  681. so (pitch >> 3) << 8 */
  682. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  683. if (dev_priv->current_page == 0) {
  684. OUT_RING(dev_priv->back_offset);
  685. dev_priv->current_page = 1;
  686. } else {
  687. OUT_RING(dev_priv->front_offset);
  688. dev_priv->current_page = 0;
  689. }
  690. OUT_RING(0);
  691. ADVANCE_LP_RING();
  692. BEGIN_LP_RING(2);
  693. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  694. OUT_RING(0);
  695. ADVANCE_LP_RING();
  696. /* Increment the frame counter. The client-side 3D driver must
  697. * throttle the framerate by waiting for this value before
  698. * performing the swapbuffer ioctl.
  699. */
  700. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  701. }
  702. static void i810_dma_quiescent(struct drm_device *dev)
  703. {
  704. drm_i810_private_t *dev_priv = dev->dev_private;
  705. RING_LOCALS;
  706. i810_kernel_lost_context(dev);
  707. BEGIN_LP_RING(4);
  708. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  709. OUT_RING(CMD_REPORT_HEAD);
  710. OUT_RING(0);
  711. OUT_RING(0);
  712. ADVANCE_LP_RING();
  713. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  714. }
  715. static int i810_flush_queue(struct drm_device *dev)
  716. {
  717. drm_i810_private_t *dev_priv = dev->dev_private;
  718. struct drm_device_dma *dma = dev->dma;
  719. int i, ret = 0;
  720. RING_LOCALS;
  721. i810_kernel_lost_context(dev);
  722. BEGIN_LP_RING(2);
  723. OUT_RING(CMD_REPORT_HEAD);
  724. OUT_RING(0);
  725. ADVANCE_LP_RING();
  726. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  727. for (i = 0; i < dma->buf_count; i++) {
  728. struct drm_buf *buf = dma->buflist[i];
  729. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  730. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  731. I810_BUF_FREE);
  732. if (used == I810_BUF_HARDWARE)
  733. DRM_DEBUG("reclaimed from HARDWARE\n");
  734. if (used == I810_BUF_CLIENT)
  735. DRM_DEBUG("still on client\n");
  736. }
  737. return ret;
  738. }
  739. /* Must be called with the lock held */
  740. static void i810_reclaim_buffers(struct drm_device *dev,
  741. struct drm_file *file_priv)
  742. {
  743. struct drm_device_dma *dma = dev->dma;
  744. int i;
  745. if (!dma)
  746. return;
  747. if (!dev->dev_private)
  748. return;
  749. if (!dma->buflist)
  750. return;
  751. i810_flush_queue(dev);
  752. for (i = 0; i < dma->buf_count; i++) {
  753. struct drm_buf *buf = dma->buflist[i];
  754. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  755. if (buf->file_priv == file_priv && buf_priv) {
  756. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  757. I810_BUF_FREE);
  758. if (used == I810_BUF_CLIENT)
  759. DRM_DEBUG("reclaimed from client\n");
  760. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  761. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  762. }
  763. }
  764. }
  765. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  766. struct drm_file *file_priv)
  767. {
  768. LOCK_TEST_WITH_RETURN(dev, file_priv);
  769. i810_flush_queue(dev);
  770. return 0;
  771. }
  772. static int i810_dma_vertex(struct drm_device *dev, void *data,
  773. struct drm_file *file_priv)
  774. {
  775. struct drm_device_dma *dma = dev->dma;
  776. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  777. u32 *hw_status = dev_priv->hw_status_page;
  778. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  779. dev_priv->sarea_priv;
  780. drm_i810_vertex_t *vertex = data;
  781. LOCK_TEST_WITH_RETURN(dev, file_priv);
  782. DRM_DEBUG("idx %d used %d discard %d\n",
  783. vertex->idx, vertex->used, vertex->discard);
  784. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  785. return -EINVAL;
  786. i810_dma_dispatch_vertex(dev,
  787. dma->buflist[vertex->idx],
  788. vertex->discard, vertex->used);
  789. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  790. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  791. sarea_priv->last_enqueue = dev_priv->counter - 1;
  792. sarea_priv->last_dispatch = (int)hw_status[5];
  793. return 0;
  794. }
  795. static int i810_clear_bufs(struct drm_device *dev, void *data,
  796. struct drm_file *file_priv)
  797. {
  798. drm_i810_clear_t *clear = data;
  799. LOCK_TEST_WITH_RETURN(dev, file_priv);
  800. /* GH: Someone's doing nasty things... */
  801. if (!dev->dev_private)
  802. return -EINVAL;
  803. i810_dma_dispatch_clear(dev, clear->flags,
  804. clear->clear_color, clear->clear_depth);
  805. return 0;
  806. }
  807. static int i810_swap_bufs(struct drm_device *dev, void *data,
  808. struct drm_file *file_priv)
  809. {
  810. DRM_DEBUG("\n");
  811. LOCK_TEST_WITH_RETURN(dev, file_priv);
  812. i810_dma_dispatch_swap(dev);
  813. return 0;
  814. }
  815. static int i810_getage(struct drm_device *dev, void *data,
  816. struct drm_file *file_priv)
  817. {
  818. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  819. u32 *hw_status = dev_priv->hw_status_page;
  820. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  821. dev_priv->sarea_priv;
  822. sarea_priv->last_dispatch = (int)hw_status[5];
  823. return 0;
  824. }
  825. static int i810_getbuf(struct drm_device *dev, void *data,
  826. struct drm_file *file_priv)
  827. {
  828. int retcode = 0;
  829. drm_i810_dma_t *d = data;
  830. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  831. u32 *hw_status = dev_priv->hw_status_page;
  832. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  833. dev_priv->sarea_priv;
  834. LOCK_TEST_WITH_RETURN(dev, file_priv);
  835. d->granted = 0;
  836. retcode = i810_dma_get_buffer(dev, d, file_priv);
  837. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  838. task_pid_nr(current), retcode, d->granted);
  839. sarea_priv->last_dispatch = (int)hw_status[5];
  840. return retcode;
  841. }
  842. static int i810_copybuf(struct drm_device *dev, void *data,
  843. struct drm_file *file_priv)
  844. {
  845. /* Never copy - 2.4.x doesn't need it */
  846. return 0;
  847. }
  848. static int i810_docopy(struct drm_device *dev, void *data,
  849. struct drm_file *file_priv)
  850. {
  851. /* Never copy - 2.4.x doesn't need it */
  852. return 0;
  853. }
  854. static void i810_dma_dispatch_mc(struct drm_device *dev, struct drm_buf *buf, int used,
  855. unsigned int last_render)
  856. {
  857. drm_i810_private_t *dev_priv = dev->dev_private;
  858. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  859. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  860. unsigned long address = (unsigned long)buf->bus_address;
  861. unsigned long start = address - dev->agp->base;
  862. int u;
  863. RING_LOCALS;
  864. i810_kernel_lost_context(dev);
  865. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  866. if (u != I810_BUF_CLIENT)
  867. DRM_DEBUG("MC found buffer that isn't mine!\n");
  868. if (used > 4 * 1024)
  869. used = 0;
  870. sarea_priv->dirty = 0x7f;
  871. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  872. dev_priv->counter++;
  873. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  874. DRM_DEBUG("start : %lx\n", start);
  875. DRM_DEBUG("used : %d\n", used);
  876. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  877. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  878. if (used & 4) {
  879. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  880. used += 4;
  881. }
  882. i810_unmap_buffer(buf);
  883. }
  884. BEGIN_LP_RING(4);
  885. OUT_RING(CMD_OP_BATCH_BUFFER);
  886. OUT_RING(start | BB1_PROTECTED);
  887. OUT_RING(start + used - 4);
  888. OUT_RING(0);
  889. ADVANCE_LP_RING();
  890. BEGIN_LP_RING(8);
  891. OUT_RING(CMD_STORE_DWORD_IDX);
  892. OUT_RING(buf_priv->my_use_idx);
  893. OUT_RING(I810_BUF_FREE);
  894. OUT_RING(0);
  895. OUT_RING(CMD_STORE_DWORD_IDX);
  896. OUT_RING(16);
  897. OUT_RING(last_render);
  898. OUT_RING(0);
  899. ADVANCE_LP_RING();
  900. }
  901. static int i810_dma_mc(struct drm_device *dev, void *data,
  902. struct drm_file *file_priv)
  903. {
  904. struct drm_device_dma *dma = dev->dma;
  905. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  906. u32 *hw_status = dev_priv->hw_status_page;
  907. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  908. dev_priv->sarea_priv;
  909. drm_i810_mc_t *mc = data;
  910. LOCK_TEST_WITH_RETURN(dev, file_priv);
  911. if (mc->idx >= dma->buf_count || mc->idx < 0)
  912. return -EINVAL;
  913. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  914. mc->last_render);
  915. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  916. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  917. sarea_priv->last_enqueue = dev_priv->counter - 1;
  918. sarea_priv->last_dispatch = (int)hw_status[5];
  919. return 0;
  920. }
  921. static int i810_rstatus(struct drm_device *dev, void *data,
  922. struct drm_file *file_priv)
  923. {
  924. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  925. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  926. }
  927. static int i810_ov0_info(struct drm_device *dev, void *data,
  928. struct drm_file *file_priv)
  929. {
  930. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  931. drm_i810_overlay_t *ov = data;
  932. ov->offset = dev_priv->overlay_offset;
  933. ov->physical = dev_priv->overlay_physical;
  934. return 0;
  935. }
  936. static int i810_fstatus(struct drm_device *dev, void *data,
  937. struct drm_file *file_priv)
  938. {
  939. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  940. LOCK_TEST_WITH_RETURN(dev, file_priv);
  941. return I810_READ(0x30008);
  942. }
  943. static int i810_ov0_flip(struct drm_device *dev, void *data,
  944. struct drm_file *file_priv)
  945. {
  946. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  947. LOCK_TEST_WITH_RETURN(dev, file_priv);
  948. /* Tell the overlay to update */
  949. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  950. return 0;
  951. }
  952. /* Not sure why this isn't set all the time:
  953. */
  954. static void i810_do_init_pageflip(struct drm_device *dev)
  955. {
  956. drm_i810_private_t *dev_priv = dev->dev_private;
  957. DRM_DEBUG("\n");
  958. dev_priv->page_flipping = 1;
  959. dev_priv->current_page = 0;
  960. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  961. }
  962. static int i810_do_cleanup_pageflip(struct drm_device *dev)
  963. {
  964. drm_i810_private_t *dev_priv = dev->dev_private;
  965. DRM_DEBUG("\n");
  966. if (dev_priv->current_page != 0)
  967. i810_dma_dispatch_flip(dev);
  968. dev_priv->page_flipping = 0;
  969. return 0;
  970. }
  971. static int i810_flip_bufs(struct drm_device *dev, void *data,
  972. struct drm_file *file_priv)
  973. {
  974. drm_i810_private_t *dev_priv = dev->dev_private;
  975. DRM_DEBUG("\n");
  976. LOCK_TEST_WITH_RETURN(dev, file_priv);
  977. if (!dev_priv->page_flipping)
  978. i810_do_init_pageflip(dev);
  979. i810_dma_dispatch_flip(dev);
  980. return 0;
  981. }
  982. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  983. {
  984. /* i810 has 4 more counters */
  985. dev->counters += 4;
  986. dev->types[6] = _DRM_STAT_IRQ;
  987. dev->types[7] = _DRM_STAT_PRIMARY;
  988. dev->types[8] = _DRM_STAT_SECONDARY;
  989. dev->types[9] = _DRM_STAT_DMA;
  990. return 0;
  991. }
  992. void i810_driver_lastclose(struct drm_device *dev)
  993. {
  994. i810_dma_cleanup(dev);
  995. }
  996. void i810_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
  997. {
  998. if (dev->dev_private) {
  999. drm_i810_private_t *dev_priv = dev->dev_private;
  1000. if (dev_priv->page_flipping)
  1001. i810_do_cleanup_pageflip(dev);
  1002. }
  1003. }
  1004. void i810_driver_reclaim_buffers_locked(struct drm_device *dev,
  1005. struct drm_file *file_priv)
  1006. {
  1007. i810_reclaim_buffers(dev, file_priv);
  1008. }
  1009. int i810_driver_dma_quiescent(struct drm_device *dev)
  1010. {
  1011. i810_dma_quiescent(dev);
  1012. return 0;
  1013. }
  1014. struct drm_ioctl_desc i810_ioctls[] = {
  1015. DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1016. DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
  1017. DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
  1018. DRM_IOCTL_DEF_DRV(I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1019. DRM_IOCTL_DEF_DRV(I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED),
  1020. DRM_IOCTL_DEF_DRV(I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED),
  1021. DRM_IOCTL_DEF_DRV(I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
  1022. DRM_IOCTL_DEF_DRV(I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED),
  1023. DRM_IOCTL_DEF_DRV(I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED),
  1024. DRM_IOCTL_DEF_DRV(I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED),
  1025. DRM_IOCTL_DEF_DRV(I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED),
  1026. DRM_IOCTL_DEF_DRV(I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED),
  1027. DRM_IOCTL_DEF_DRV(I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1028. DRM_IOCTL_DEF_DRV(I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED),
  1029. DRM_IOCTL_DEF_DRV(I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
  1030. };
  1031. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1032. /**
  1033. * Determine if the device really is AGP or not.
  1034. *
  1035. * All Intel graphics chipsets are treated as AGP, even if they are really
  1036. * PCI-e.
  1037. *
  1038. * \param dev The device to be tested.
  1039. *
  1040. * \returns
  1041. * A value of 1 is always retured to indictate every i810 is AGP.
  1042. */
  1043. int i810_driver_device_is_agp(struct drm_device *dev)
  1044. {
  1045. return 1;
  1046. }