gpio-pch.c 7.4 KB

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  1. /*
  2. * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/pci.h>
  19. #include <linux/gpio.h>
  20. #define PCH_GPIO_ALL_PINS 0xfff /* Mask for GPIO pins 0 to 11 */
  21. #define GPIO_NUM_PINS 12 /* Specifies number of GPIO PINS GPIO0-GPIO11 */
  22. struct pch_regs {
  23. u32 ien;
  24. u32 istatus;
  25. u32 idisp;
  26. u32 iclr;
  27. u32 imask;
  28. u32 imaskclr;
  29. u32 po;
  30. u32 pi;
  31. u32 pm;
  32. u32 im0;
  33. u32 im1;
  34. u32 reserved[4];
  35. u32 reset;
  36. };
  37. /**
  38. * struct pch_gpio_reg_data - The register store data.
  39. * @po_reg: To store contents of PO register.
  40. * @pm_reg: To store contents of PM register.
  41. */
  42. struct pch_gpio_reg_data {
  43. u32 po_reg;
  44. u32 pm_reg;
  45. };
  46. /**
  47. * struct pch_gpio - GPIO private data structure.
  48. * @base: PCI base address of Memory mapped I/O register.
  49. * @reg: Memory mapped PCH GPIO register list.
  50. * @dev: Pointer to device structure.
  51. * @gpio: Data for GPIO infrastructure.
  52. * @pch_gpio_reg: Memory mapped Register data is saved here
  53. * when suspend.
  54. */
  55. struct pch_gpio {
  56. void __iomem *base;
  57. struct pch_regs __iomem *reg;
  58. struct device *dev;
  59. struct gpio_chip gpio;
  60. struct pch_gpio_reg_data pch_gpio_reg;
  61. struct mutex lock;
  62. };
  63. static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
  64. {
  65. u32 reg_val;
  66. struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
  67. mutex_lock(&chip->lock);
  68. reg_val = ioread32(&chip->reg->po);
  69. if (val)
  70. reg_val |= (1 << nr);
  71. else
  72. reg_val &= ~(1 << nr);
  73. iowrite32(reg_val, &chip->reg->po);
  74. mutex_unlock(&chip->lock);
  75. }
  76. static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
  77. {
  78. struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
  79. return ioread32(&chip->reg->pi) & (1 << nr);
  80. }
  81. static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
  82. int val)
  83. {
  84. struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
  85. u32 pm;
  86. u32 reg_val;
  87. mutex_lock(&chip->lock);
  88. pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS;
  89. pm |= (1 << nr);
  90. iowrite32(pm, &chip->reg->pm);
  91. reg_val = ioread32(&chip->reg->po);
  92. if (val)
  93. reg_val |= (1 << nr);
  94. else
  95. reg_val &= ~(1 << nr);
  96. iowrite32(reg_val, &chip->reg->po);
  97. mutex_unlock(&chip->lock);
  98. return 0;
  99. }
  100. static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  101. {
  102. struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
  103. u32 pm;
  104. mutex_lock(&chip->lock);
  105. pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS; /*bits 0-11*/
  106. pm &= ~(1 << nr);
  107. iowrite32(pm, &chip->reg->pm);
  108. mutex_unlock(&chip->lock);
  109. return 0;
  110. }
  111. /*
  112. * Save register configuration and disable interrupts.
  113. */
  114. static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
  115. {
  116. chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
  117. chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
  118. }
  119. /*
  120. * This function restores the register configuration of the GPIO device.
  121. */
  122. static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
  123. {
  124. /* to store contents of PO register */
  125. iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
  126. /* to store contents of PM register */
  127. iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
  128. }
  129. static void pch_gpio_setup(struct pch_gpio *chip)
  130. {
  131. struct gpio_chip *gpio = &chip->gpio;
  132. gpio->label = dev_name(chip->dev);
  133. gpio->owner = THIS_MODULE;
  134. gpio->direction_input = pch_gpio_direction_input;
  135. gpio->get = pch_gpio_get;
  136. gpio->direction_output = pch_gpio_direction_output;
  137. gpio->set = pch_gpio_set;
  138. gpio->dbg_show = NULL;
  139. gpio->base = -1;
  140. gpio->ngpio = GPIO_NUM_PINS;
  141. gpio->can_sleep = 0;
  142. }
  143. static int __devinit pch_gpio_probe(struct pci_dev *pdev,
  144. const struct pci_device_id *id)
  145. {
  146. s32 ret;
  147. struct pch_gpio *chip;
  148. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  149. if (chip == NULL)
  150. return -ENOMEM;
  151. chip->dev = &pdev->dev;
  152. ret = pci_enable_device(pdev);
  153. if (ret) {
  154. dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
  155. goto err_pci_enable;
  156. }
  157. ret = pci_request_regions(pdev, KBUILD_MODNAME);
  158. if (ret) {
  159. dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
  160. goto err_request_regions;
  161. }
  162. chip->base = pci_iomap(pdev, 1, 0);
  163. if (chip->base == 0) {
  164. dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
  165. ret = -ENOMEM;
  166. goto err_iomap;
  167. }
  168. chip->reg = chip->base;
  169. pci_set_drvdata(pdev, chip);
  170. mutex_init(&chip->lock);
  171. pch_gpio_setup(chip);
  172. ret = gpiochip_add(&chip->gpio);
  173. if (ret) {
  174. dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
  175. goto err_gpiochip_add;
  176. }
  177. return 0;
  178. err_gpiochip_add:
  179. pci_iounmap(pdev, chip->base);
  180. err_iomap:
  181. pci_release_regions(pdev);
  182. err_request_regions:
  183. pci_disable_device(pdev);
  184. err_pci_enable:
  185. kfree(chip);
  186. dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
  187. return ret;
  188. }
  189. static void __devexit pch_gpio_remove(struct pci_dev *pdev)
  190. {
  191. int err;
  192. struct pch_gpio *chip = pci_get_drvdata(pdev);
  193. err = gpiochip_remove(&chip->gpio);
  194. if (err)
  195. dev_err(&pdev->dev, "Failed gpiochip_remove\n");
  196. pci_iounmap(pdev, chip->base);
  197. pci_release_regions(pdev);
  198. pci_disable_device(pdev);
  199. kfree(chip);
  200. }
  201. #ifdef CONFIG_PM
  202. static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
  203. {
  204. s32 ret;
  205. struct pch_gpio *chip = pci_get_drvdata(pdev);
  206. pch_gpio_save_reg_conf(chip);
  207. pch_gpio_restore_reg_conf(chip);
  208. ret = pci_save_state(pdev);
  209. if (ret) {
  210. dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
  211. return ret;
  212. }
  213. pci_disable_device(pdev);
  214. pci_set_power_state(pdev, PCI_D0);
  215. ret = pci_enable_wake(pdev, PCI_D0, 1);
  216. if (ret)
  217. dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
  218. return 0;
  219. }
  220. static int pch_gpio_resume(struct pci_dev *pdev)
  221. {
  222. s32 ret;
  223. struct pch_gpio *chip = pci_get_drvdata(pdev);
  224. ret = pci_enable_wake(pdev, PCI_D0, 0);
  225. pci_set_power_state(pdev, PCI_D0);
  226. ret = pci_enable_device(pdev);
  227. if (ret) {
  228. dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
  229. return ret;
  230. }
  231. pci_restore_state(pdev);
  232. iowrite32(0x01, &chip->reg->reset);
  233. iowrite32(0x00, &chip->reg->reset);
  234. pch_gpio_restore_reg_conf(chip);
  235. return 0;
  236. }
  237. #else
  238. #define pch_gpio_suspend NULL
  239. #define pch_gpio_resume NULL
  240. #endif
  241. #define PCI_VENDOR_ID_ROHM 0x10DB
  242. static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
  243. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
  244. { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
  245. { 0, }
  246. };
  247. MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
  248. static struct pci_driver pch_gpio_driver = {
  249. .name = "pch_gpio",
  250. .id_table = pch_gpio_pcidev_id,
  251. .probe = pch_gpio_probe,
  252. .remove = __devexit_p(pch_gpio_remove),
  253. .suspend = pch_gpio_suspend,
  254. .resume = pch_gpio_resume
  255. };
  256. static int __init pch_gpio_pci_init(void)
  257. {
  258. return pci_register_driver(&pch_gpio_driver);
  259. }
  260. module_init(pch_gpio_pci_init);
  261. static void __exit pch_gpio_pci_exit(void)
  262. {
  263. pci_unregister_driver(&pch_gpio_driver);
  264. }
  265. module_exit(pch_gpio_pci_exit);
  266. MODULE_DESCRIPTION("PCH GPIO PCI Driver");
  267. MODULE_LICENSE("GPL");