dmatest.c 17 KB

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  1. /*
  2. * DMA Engine test module
  3. *
  4. * Copyright (C) 2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/init.h>
  14. #include <linux/kthread.h>
  15. #include <linux/module.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/random.h>
  18. #include <linux/slab.h>
  19. #include <linux/wait.h>
  20. static unsigned int test_buf_size = 16384;
  21. module_param(test_buf_size, uint, S_IRUGO);
  22. MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
  23. static char test_channel[20];
  24. module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO);
  25. MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
  26. static char test_device[20];
  27. module_param_string(device, test_device, sizeof(test_device), S_IRUGO);
  28. MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
  29. static unsigned int threads_per_chan = 1;
  30. module_param(threads_per_chan, uint, S_IRUGO);
  31. MODULE_PARM_DESC(threads_per_chan,
  32. "Number of threads to start per channel (default: 1)");
  33. static unsigned int max_channels;
  34. module_param(max_channels, uint, S_IRUGO);
  35. MODULE_PARM_DESC(max_channels,
  36. "Maximum number of channels to use (default: all)");
  37. static unsigned int iterations;
  38. module_param(iterations, uint, S_IRUGO);
  39. MODULE_PARM_DESC(iterations,
  40. "Iterations before stopping test (default: infinite)");
  41. static unsigned int xor_sources = 3;
  42. module_param(xor_sources, uint, S_IRUGO);
  43. MODULE_PARM_DESC(xor_sources,
  44. "Number of xor source buffers (default: 3)");
  45. static unsigned int pq_sources = 3;
  46. module_param(pq_sources, uint, S_IRUGO);
  47. MODULE_PARM_DESC(pq_sources,
  48. "Number of p+q source buffers (default: 3)");
  49. static int timeout = 3000;
  50. module_param(timeout, uint, S_IRUGO);
  51. MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
  52. "Pass -1 for infinite timeout");
  53. /*
  54. * Initialization patterns. All bytes in the source buffer has bit 7
  55. * set, all bytes in the destination buffer has bit 7 cleared.
  56. *
  57. * Bit 6 is set for all bytes which are to be copied by the DMA
  58. * engine. Bit 5 is set for all bytes which are to be overwritten by
  59. * the DMA engine.
  60. *
  61. * The remaining bits are the inverse of a counter which increments by
  62. * one for each byte address.
  63. */
  64. #define PATTERN_SRC 0x80
  65. #define PATTERN_DST 0x00
  66. #define PATTERN_COPY 0x40
  67. #define PATTERN_OVERWRITE 0x20
  68. #define PATTERN_COUNT_MASK 0x1f
  69. struct dmatest_thread {
  70. struct list_head node;
  71. struct task_struct *task;
  72. struct dma_chan *chan;
  73. u8 **srcs;
  74. u8 **dsts;
  75. enum dma_transaction_type type;
  76. };
  77. struct dmatest_chan {
  78. struct list_head node;
  79. struct dma_chan *chan;
  80. struct list_head threads;
  81. };
  82. /*
  83. * These are protected by dma_list_mutex since they're only used by
  84. * the DMA filter function callback
  85. */
  86. static LIST_HEAD(dmatest_channels);
  87. static unsigned int nr_channels;
  88. static bool dmatest_match_channel(struct dma_chan *chan)
  89. {
  90. if (test_channel[0] == '\0')
  91. return true;
  92. return strcmp(dma_chan_name(chan), test_channel) == 0;
  93. }
  94. static bool dmatest_match_device(struct dma_device *device)
  95. {
  96. if (test_device[0] == '\0')
  97. return true;
  98. return strcmp(dev_name(device->dev), test_device) == 0;
  99. }
  100. static unsigned long dmatest_random(void)
  101. {
  102. unsigned long buf;
  103. get_random_bytes(&buf, sizeof(buf));
  104. return buf;
  105. }
  106. static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len)
  107. {
  108. unsigned int i;
  109. u8 *buf;
  110. for (; (buf = *bufs); bufs++) {
  111. for (i = 0; i < start; i++)
  112. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  113. for ( ; i < start + len; i++)
  114. buf[i] = PATTERN_SRC | PATTERN_COPY
  115. | (~i & PATTERN_COUNT_MASK);
  116. for ( ; i < test_buf_size; i++)
  117. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  118. buf++;
  119. }
  120. }
  121. static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len)
  122. {
  123. unsigned int i;
  124. u8 *buf;
  125. for (; (buf = *bufs); bufs++) {
  126. for (i = 0; i < start; i++)
  127. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  128. for ( ; i < start + len; i++)
  129. buf[i] = PATTERN_DST | PATTERN_OVERWRITE
  130. | (~i & PATTERN_COUNT_MASK);
  131. for ( ; i < test_buf_size; i++)
  132. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  133. }
  134. }
  135. static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
  136. unsigned int counter, bool is_srcbuf)
  137. {
  138. u8 diff = actual ^ pattern;
  139. u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
  140. const char *thread_name = current->comm;
  141. if (is_srcbuf)
  142. pr_warning("%s: srcbuf[0x%x] overwritten!"
  143. " Expected %02x, got %02x\n",
  144. thread_name, index, expected, actual);
  145. else if ((pattern & PATTERN_COPY)
  146. && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
  147. pr_warning("%s: dstbuf[0x%x] not copied!"
  148. " Expected %02x, got %02x\n",
  149. thread_name, index, expected, actual);
  150. else if (diff & PATTERN_SRC)
  151. pr_warning("%s: dstbuf[0x%x] was copied!"
  152. " Expected %02x, got %02x\n",
  153. thread_name, index, expected, actual);
  154. else
  155. pr_warning("%s: dstbuf[0x%x] mismatch!"
  156. " Expected %02x, got %02x\n",
  157. thread_name, index, expected, actual);
  158. }
  159. static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
  160. unsigned int end, unsigned int counter, u8 pattern,
  161. bool is_srcbuf)
  162. {
  163. unsigned int i;
  164. unsigned int error_count = 0;
  165. u8 actual;
  166. u8 expected;
  167. u8 *buf;
  168. unsigned int counter_orig = counter;
  169. for (; (buf = *bufs); bufs++) {
  170. counter = counter_orig;
  171. for (i = start; i < end; i++) {
  172. actual = buf[i];
  173. expected = pattern | (~counter & PATTERN_COUNT_MASK);
  174. if (actual != expected) {
  175. if (error_count < 32)
  176. dmatest_mismatch(actual, pattern, i,
  177. counter, is_srcbuf);
  178. error_count++;
  179. }
  180. counter++;
  181. }
  182. }
  183. if (error_count > 32)
  184. pr_warning("%s: %u errors suppressed\n",
  185. current->comm, error_count - 32);
  186. return error_count;
  187. }
  188. static void dmatest_callback(void *completion)
  189. {
  190. complete(completion);
  191. }
  192. /*
  193. * This function repeatedly tests DMA transfers of various lengths and
  194. * offsets for a given operation type until it is told to exit by
  195. * kthread_stop(). There may be multiple threads running this function
  196. * in parallel for a single channel, and there may be multiple channels
  197. * being tested in parallel.
  198. *
  199. * Before each test, the source and destination buffer is initialized
  200. * with a known pattern. This pattern is different depending on
  201. * whether it's in an area which is supposed to be copied or
  202. * overwritten, and different in the source and destination buffers.
  203. * So if the DMA engine doesn't copy exactly what we tell it to copy,
  204. * we'll notice.
  205. */
  206. static int dmatest_func(void *data)
  207. {
  208. struct dmatest_thread *thread = data;
  209. struct dma_chan *chan;
  210. const char *thread_name;
  211. unsigned int src_off, dst_off, len;
  212. unsigned int error_count;
  213. unsigned int failed_tests = 0;
  214. unsigned int total_tests = 0;
  215. dma_cookie_t cookie;
  216. enum dma_status status;
  217. enum dma_ctrl_flags flags;
  218. u8 pq_coefs[pq_sources + 1];
  219. int ret;
  220. int src_cnt;
  221. int dst_cnt;
  222. int i;
  223. thread_name = current->comm;
  224. ret = -ENOMEM;
  225. smp_rmb();
  226. chan = thread->chan;
  227. if (thread->type == DMA_MEMCPY)
  228. src_cnt = dst_cnt = 1;
  229. else if (thread->type == DMA_XOR) {
  230. src_cnt = xor_sources | 1; /* force odd to ensure dst = src */
  231. dst_cnt = 1;
  232. } else if (thread->type == DMA_PQ) {
  233. src_cnt = pq_sources | 1; /* force odd to ensure dst = src */
  234. dst_cnt = 2;
  235. for (i = 0; i < src_cnt; i++)
  236. pq_coefs[i] = 1;
  237. } else
  238. goto err_srcs;
  239. thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
  240. if (!thread->srcs)
  241. goto err_srcs;
  242. for (i = 0; i < src_cnt; i++) {
  243. thread->srcs[i] = kmalloc(test_buf_size, GFP_KERNEL);
  244. if (!thread->srcs[i])
  245. goto err_srcbuf;
  246. }
  247. thread->srcs[i] = NULL;
  248. thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
  249. if (!thread->dsts)
  250. goto err_dsts;
  251. for (i = 0; i < dst_cnt; i++) {
  252. thread->dsts[i] = kmalloc(test_buf_size, GFP_KERNEL);
  253. if (!thread->dsts[i])
  254. goto err_dstbuf;
  255. }
  256. thread->dsts[i] = NULL;
  257. set_user_nice(current, 10);
  258. /*
  259. * src buffers are freed by the DMAEngine code with dma_unmap_single()
  260. * dst buffers are freed by ourselves below
  261. */
  262. flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT
  263. | DMA_COMPL_SKIP_DEST_UNMAP | DMA_COMPL_SRC_UNMAP_SINGLE;
  264. while (!kthread_should_stop()
  265. && !(iterations && total_tests >= iterations)) {
  266. struct dma_device *dev = chan->device;
  267. struct dma_async_tx_descriptor *tx = NULL;
  268. dma_addr_t dma_srcs[src_cnt];
  269. dma_addr_t dma_dsts[dst_cnt];
  270. struct completion cmp;
  271. unsigned long tmo = msecs_to_jiffies(timeout);
  272. u8 align = 0;
  273. total_tests++;
  274. /* honor alignment restrictions */
  275. if (thread->type == DMA_MEMCPY)
  276. align = dev->copy_align;
  277. else if (thread->type == DMA_XOR)
  278. align = dev->xor_align;
  279. else if (thread->type == DMA_PQ)
  280. align = dev->pq_align;
  281. if (1 << align > test_buf_size) {
  282. pr_err("%u-byte buffer too small for %d-byte alignment\n",
  283. test_buf_size, 1 << align);
  284. break;
  285. }
  286. len = dmatest_random() % test_buf_size + 1;
  287. len = (len >> align) << align;
  288. if (!len)
  289. len = 1 << align;
  290. src_off = dmatest_random() % (test_buf_size - len + 1);
  291. dst_off = dmatest_random() % (test_buf_size - len + 1);
  292. src_off = (src_off >> align) << align;
  293. dst_off = (dst_off >> align) << align;
  294. dmatest_init_srcs(thread->srcs, src_off, len);
  295. dmatest_init_dsts(thread->dsts, dst_off, len);
  296. for (i = 0; i < src_cnt; i++) {
  297. u8 *buf = thread->srcs[i] + src_off;
  298. dma_srcs[i] = dma_map_single(dev->dev, buf, len,
  299. DMA_TO_DEVICE);
  300. }
  301. /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
  302. for (i = 0; i < dst_cnt; i++) {
  303. dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
  304. test_buf_size,
  305. DMA_BIDIRECTIONAL);
  306. }
  307. if (thread->type == DMA_MEMCPY)
  308. tx = dev->device_prep_dma_memcpy(chan,
  309. dma_dsts[0] + dst_off,
  310. dma_srcs[0], len,
  311. flags);
  312. else if (thread->type == DMA_XOR)
  313. tx = dev->device_prep_dma_xor(chan,
  314. dma_dsts[0] + dst_off,
  315. dma_srcs, src_cnt,
  316. len, flags);
  317. else if (thread->type == DMA_PQ) {
  318. dma_addr_t dma_pq[dst_cnt];
  319. for (i = 0; i < dst_cnt; i++)
  320. dma_pq[i] = dma_dsts[i] + dst_off;
  321. tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs,
  322. src_cnt, pq_coefs,
  323. len, flags);
  324. }
  325. if (!tx) {
  326. for (i = 0; i < src_cnt; i++)
  327. dma_unmap_single(dev->dev, dma_srcs[i], len,
  328. DMA_TO_DEVICE);
  329. for (i = 0; i < dst_cnt; i++)
  330. dma_unmap_single(dev->dev, dma_dsts[i],
  331. test_buf_size,
  332. DMA_BIDIRECTIONAL);
  333. pr_warning("%s: #%u: prep error with src_off=0x%x "
  334. "dst_off=0x%x len=0x%x\n",
  335. thread_name, total_tests - 1,
  336. src_off, dst_off, len);
  337. msleep(100);
  338. failed_tests++;
  339. continue;
  340. }
  341. init_completion(&cmp);
  342. tx->callback = dmatest_callback;
  343. tx->callback_param = &cmp;
  344. cookie = tx->tx_submit(tx);
  345. if (dma_submit_error(cookie)) {
  346. pr_warning("%s: #%u: submit error %d with src_off=0x%x "
  347. "dst_off=0x%x len=0x%x\n",
  348. thread_name, total_tests - 1, cookie,
  349. src_off, dst_off, len);
  350. msleep(100);
  351. failed_tests++;
  352. continue;
  353. }
  354. dma_async_issue_pending(chan);
  355. tmo = wait_for_completion_timeout(&cmp, tmo);
  356. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  357. if (tmo == 0) {
  358. pr_warning("%s: #%u: test timed out\n",
  359. thread_name, total_tests - 1);
  360. failed_tests++;
  361. continue;
  362. } else if (status != DMA_SUCCESS) {
  363. pr_warning("%s: #%u: got completion callback,"
  364. " but status is \'%s\'\n",
  365. thread_name, total_tests - 1,
  366. status == DMA_ERROR ? "error" : "in progress");
  367. failed_tests++;
  368. continue;
  369. }
  370. /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
  371. for (i = 0; i < dst_cnt; i++)
  372. dma_unmap_single(dev->dev, dma_dsts[i], test_buf_size,
  373. DMA_BIDIRECTIONAL);
  374. error_count = 0;
  375. pr_debug("%s: verifying source buffer...\n", thread_name);
  376. error_count += dmatest_verify(thread->srcs, 0, src_off,
  377. 0, PATTERN_SRC, true);
  378. error_count += dmatest_verify(thread->srcs, src_off,
  379. src_off + len, src_off,
  380. PATTERN_SRC | PATTERN_COPY, true);
  381. error_count += dmatest_verify(thread->srcs, src_off + len,
  382. test_buf_size, src_off + len,
  383. PATTERN_SRC, true);
  384. pr_debug("%s: verifying dest buffer...\n",
  385. thread->task->comm);
  386. error_count += dmatest_verify(thread->dsts, 0, dst_off,
  387. 0, PATTERN_DST, false);
  388. error_count += dmatest_verify(thread->dsts, dst_off,
  389. dst_off + len, src_off,
  390. PATTERN_SRC | PATTERN_COPY, false);
  391. error_count += dmatest_verify(thread->dsts, dst_off + len,
  392. test_buf_size, dst_off + len,
  393. PATTERN_DST, false);
  394. if (error_count) {
  395. pr_warning("%s: #%u: %u errors with "
  396. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  397. thread_name, total_tests - 1, error_count,
  398. src_off, dst_off, len);
  399. failed_tests++;
  400. } else {
  401. pr_debug("%s: #%u: No errors with "
  402. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  403. thread_name, total_tests - 1,
  404. src_off, dst_off, len);
  405. }
  406. }
  407. ret = 0;
  408. for (i = 0; thread->dsts[i]; i++)
  409. kfree(thread->dsts[i]);
  410. err_dstbuf:
  411. kfree(thread->dsts);
  412. err_dsts:
  413. for (i = 0; thread->srcs[i]; i++)
  414. kfree(thread->srcs[i]);
  415. err_srcbuf:
  416. kfree(thread->srcs);
  417. err_srcs:
  418. pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
  419. thread_name, total_tests, failed_tests, ret);
  420. if (iterations > 0)
  421. while (!kthread_should_stop()) {
  422. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit);
  423. interruptible_sleep_on(&wait_dmatest_exit);
  424. }
  425. return ret;
  426. }
  427. static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
  428. {
  429. struct dmatest_thread *thread;
  430. struct dmatest_thread *_thread;
  431. int ret;
  432. list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
  433. ret = kthread_stop(thread->task);
  434. pr_debug("dmatest: thread %s exited with status %d\n",
  435. thread->task->comm, ret);
  436. list_del(&thread->node);
  437. kfree(thread);
  438. }
  439. kfree(dtc);
  440. }
  441. static int dmatest_add_threads(struct dmatest_chan *dtc, enum dma_transaction_type type)
  442. {
  443. struct dmatest_thread *thread;
  444. struct dma_chan *chan = dtc->chan;
  445. char *op;
  446. unsigned int i;
  447. if (type == DMA_MEMCPY)
  448. op = "copy";
  449. else if (type == DMA_XOR)
  450. op = "xor";
  451. else if (type == DMA_PQ)
  452. op = "pq";
  453. else
  454. return -EINVAL;
  455. for (i = 0; i < threads_per_chan; i++) {
  456. thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
  457. if (!thread) {
  458. pr_warning("dmatest: No memory for %s-%s%u\n",
  459. dma_chan_name(chan), op, i);
  460. break;
  461. }
  462. thread->chan = dtc->chan;
  463. thread->type = type;
  464. smp_wmb();
  465. thread->task = kthread_run(dmatest_func, thread, "%s-%s%u",
  466. dma_chan_name(chan), op, i);
  467. if (IS_ERR(thread->task)) {
  468. pr_warning("dmatest: Failed to run thread %s-%s%u\n",
  469. dma_chan_name(chan), op, i);
  470. kfree(thread);
  471. break;
  472. }
  473. /* srcbuf and dstbuf are allocated by the thread itself */
  474. list_add_tail(&thread->node, &dtc->threads);
  475. }
  476. return i;
  477. }
  478. static int dmatest_add_channel(struct dma_chan *chan)
  479. {
  480. struct dmatest_chan *dtc;
  481. struct dma_device *dma_dev = chan->device;
  482. unsigned int thread_count = 0;
  483. int cnt;
  484. dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
  485. if (!dtc) {
  486. pr_warning("dmatest: No memory for %s\n", dma_chan_name(chan));
  487. return -ENOMEM;
  488. }
  489. dtc->chan = chan;
  490. INIT_LIST_HEAD(&dtc->threads);
  491. if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
  492. cnt = dmatest_add_threads(dtc, DMA_MEMCPY);
  493. thread_count += cnt > 0 ? cnt : 0;
  494. }
  495. if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
  496. cnt = dmatest_add_threads(dtc, DMA_XOR);
  497. thread_count += cnt > 0 ? cnt : 0;
  498. }
  499. if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
  500. cnt = dmatest_add_threads(dtc, DMA_PQ);
  501. thread_count += cnt > 0 ?: 0;
  502. }
  503. pr_info("dmatest: Started %u threads using %s\n",
  504. thread_count, dma_chan_name(chan));
  505. list_add_tail(&dtc->node, &dmatest_channels);
  506. nr_channels++;
  507. return 0;
  508. }
  509. static bool filter(struct dma_chan *chan, void *param)
  510. {
  511. if (!dmatest_match_channel(chan) || !dmatest_match_device(chan->device))
  512. return false;
  513. else
  514. return true;
  515. }
  516. static int __init dmatest_init(void)
  517. {
  518. dma_cap_mask_t mask;
  519. struct dma_chan *chan;
  520. int err = 0;
  521. dma_cap_zero(mask);
  522. dma_cap_set(DMA_MEMCPY, mask);
  523. for (;;) {
  524. chan = dma_request_channel(mask, filter, NULL);
  525. if (chan) {
  526. err = dmatest_add_channel(chan);
  527. if (err) {
  528. dma_release_channel(chan);
  529. break; /* add_channel failed, punt */
  530. }
  531. } else
  532. break; /* no more channels available */
  533. if (max_channels && nr_channels >= max_channels)
  534. break; /* we have all we need */
  535. }
  536. return err;
  537. }
  538. /* when compiled-in wait for drivers to load first */
  539. late_initcall(dmatest_init);
  540. static void __exit dmatest_exit(void)
  541. {
  542. struct dmatest_chan *dtc, *_dtc;
  543. struct dma_chan *chan;
  544. list_for_each_entry_safe(dtc, _dtc, &dmatest_channels, node) {
  545. list_del(&dtc->node);
  546. chan = dtc->chan;
  547. dmatest_cleanup_channel(dtc);
  548. pr_debug("dmatest: dropped channel %s\n",
  549. dma_chan_name(chan));
  550. dma_release_channel(chan);
  551. }
  552. }
  553. module_exit(dmatest_exit);
  554. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  555. MODULE_LICENSE("GPL v2");