dmaengine.c 28 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #include <linux/dma-mapping.h>
  47. #include <linux/init.h>
  48. #include <linux/module.h>
  49. #include <linux/mm.h>
  50. #include <linux/device.h>
  51. #include <linux/dmaengine.h>
  52. #include <linux/hardirq.h>
  53. #include <linux/spinlock.h>
  54. #include <linux/percpu.h>
  55. #include <linux/rcupdate.h>
  56. #include <linux/mutex.h>
  57. #include <linux/jiffies.h>
  58. #include <linux/rculist.h>
  59. #include <linux/idr.h>
  60. #include <linux/slab.h>
  61. static DEFINE_MUTEX(dma_list_mutex);
  62. static DEFINE_IDR(dma_idr);
  63. static LIST_HEAD(dma_device_list);
  64. static long dmaengine_ref_count;
  65. /* --- sysfs implementation --- */
  66. /**
  67. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  68. * @dev - device node
  69. *
  70. * Must be called under dma_list_mutex
  71. */
  72. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  73. {
  74. struct dma_chan_dev *chan_dev;
  75. chan_dev = container_of(dev, typeof(*chan_dev), device);
  76. return chan_dev->chan;
  77. }
  78. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  79. {
  80. struct dma_chan *chan;
  81. unsigned long count = 0;
  82. int i;
  83. int err;
  84. mutex_lock(&dma_list_mutex);
  85. chan = dev_to_dma_chan(dev);
  86. if (chan) {
  87. for_each_possible_cpu(i)
  88. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  89. err = sprintf(buf, "%lu\n", count);
  90. } else
  91. err = -ENODEV;
  92. mutex_unlock(&dma_list_mutex);
  93. return err;
  94. }
  95. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  96. char *buf)
  97. {
  98. struct dma_chan *chan;
  99. unsigned long count = 0;
  100. int i;
  101. int err;
  102. mutex_lock(&dma_list_mutex);
  103. chan = dev_to_dma_chan(dev);
  104. if (chan) {
  105. for_each_possible_cpu(i)
  106. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  107. err = sprintf(buf, "%lu\n", count);
  108. } else
  109. err = -ENODEV;
  110. mutex_unlock(&dma_list_mutex);
  111. return err;
  112. }
  113. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  114. {
  115. struct dma_chan *chan;
  116. int err;
  117. mutex_lock(&dma_list_mutex);
  118. chan = dev_to_dma_chan(dev);
  119. if (chan)
  120. err = sprintf(buf, "%d\n", chan->client_count);
  121. else
  122. err = -ENODEV;
  123. mutex_unlock(&dma_list_mutex);
  124. return err;
  125. }
  126. static struct device_attribute dma_attrs[] = {
  127. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  128. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  129. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  130. __ATTR_NULL
  131. };
  132. static void chan_dev_release(struct device *dev)
  133. {
  134. struct dma_chan_dev *chan_dev;
  135. chan_dev = container_of(dev, typeof(*chan_dev), device);
  136. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  137. mutex_lock(&dma_list_mutex);
  138. idr_remove(&dma_idr, chan_dev->dev_id);
  139. mutex_unlock(&dma_list_mutex);
  140. kfree(chan_dev->idr_ref);
  141. }
  142. kfree(chan_dev);
  143. }
  144. static struct class dma_devclass = {
  145. .name = "dma",
  146. .dev_attrs = dma_attrs,
  147. .dev_release = chan_dev_release,
  148. };
  149. /* --- client and device registration --- */
  150. #define dma_device_satisfies_mask(device, mask) \
  151. __dma_device_satisfies_mask((device), &(mask))
  152. static int
  153. __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
  154. {
  155. dma_cap_mask_t has;
  156. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  157. DMA_TX_TYPE_END);
  158. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  159. }
  160. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  161. {
  162. return chan->device->dev->driver->owner;
  163. }
  164. /**
  165. * balance_ref_count - catch up the channel reference count
  166. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  167. *
  168. * balance_ref_count must be called under dma_list_mutex
  169. */
  170. static void balance_ref_count(struct dma_chan *chan)
  171. {
  172. struct module *owner = dma_chan_to_owner(chan);
  173. while (chan->client_count < dmaengine_ref_count) {
  174. __module_get(owner);
  175. chan->client_count++;
  176. }
  177. }
  178. /**
  179. * dma_chan_get - try to grab a dma channel's parent driver module
  180. * @chan - channel to grab
  181. *
  182. * Must be called under dma_list_mutex
  183. */
  184. static int dma_chan_get(struct dma_chan *chan)
  185. {
  186. int err = -ENODEV;
  187. struct module *owner = dma_chan_to_owner(chan);
  188. if (chan->client_count) {
  189. __module_get(owner);
  190. err = 0;
  191. } else if (try_module_get(owner))
  192. err = 0;
  193. if (err == 0)
  194. chan->client_count++;
  195. /* allocate upon first client reference */
  196. if (chan->client_count == 1 && err == 0) {
  197. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  198. if (desc_cnt < 0) {
  199. err = desc_cnt;
  200. chan->client_count = 0;
  201. module_put(owner);
  202. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  203. balance_ref_count(chan);
  204. }
  205. return err;
  206. }
  207. /**
  208. * dma_chan_put - drop a reference to a dma channel's parent driver module
  209. * @chan - channel to release
  210. *
  211. * Must be called under dma_list_mutex
  212. */
  213. static void dma_chan_put(struct dma_chan *chan)
  214. {
  215. if (!chan->client_count)
  216. return; /* this channel failed alloc_chan_resources */
  217. chan->client_count--;
  218. module_put(dma_chan_to_owner(chan));
  219. if (chan->client_count == 0)
  220. chan->device->device_free_chan_resources(chan);
  221. }
  222. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  223. {
  224. enum dma_status status;
  225. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  226. dma_async_issue_pending(chan);
  227. do {
  228. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  229. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  230. printk(KERN_ERR "dma_sync_wait_timeout!\n");
  231. return DMA_ERROR;
  232. }
  233. } while (status == DMA_IN_PROGRESS);
  234. return status;
  235. }
  236. EXPORT_SYMBOL(dma_sync_wait);
  237. /**
  238. * dma_cap_mask_all - enable iteration over all operation types
  239. */
  240. static dma_cap_mask_t dma_cap_mask_all;
  241. /**
  242. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  243. * @chan - associated channel for this entry
  244. */
  245. struct dma_chan_tbl_ent {
  246. struct dma_chan *chan;
  247. };
  248. /**
  249. * channel_table - percpu lookup table for memory-to-memory offload providers
  250. */
  251. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  252. static int __init dma_channel_table_init(void)
  253. {
  254. enum dma_transaction_type cap;
  255. int err = 0;
  256. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  257. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  258. * but are not associated with an operation so they do not need
  259. * an entry in the channel_table
  260. */
  261. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  262. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  263. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  264. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  265. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  266. if (!channel_table[cap]) {
  267. err = -ENOMEM;
  268. break;
  269. }
  270. }
  271. if (err) {
  272. pr_err("dmaengine: initialization failure\n");
  273. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  274. if (channel_table[cap])
  275. free_percpu(channel_table[cap]);
  276. }
  277. return err;
  278. }
  279. arch_initcall(dma_channel_table_init);
  280. /**
  281. * dma_find_channel - find a channel to carry out the operation
  282. * @tx_type: transaction type
  283. */
  284. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  285. {
  286. return this_cpu_read(channel_table[tx_type]->chan);
  287. }
  288. EXPORT_SYMBOL(dma_find_channel);
  289. /**
  290. * dma_issue_pending_all - flush all pending operations across all channels
  291. */
  292. void dma_issue_pending_all(void)
  293. {
  294. struct dma_device *device;
  295. struct dma_chan *chan;
  296. rcu_read_lock();
  297. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  298. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  299. continue;
  300. list_for_each_entry(chan, &device->channels, device_node)
  301. if (chan->client_count)
  302. device->device_issue_pending(chan);
  303. }
  304. rcu_read_unlock();
  305. }
  306. EXPORT_SYMBOL(dma_issue_pending_all);
  307. /**
  308. * nth_chan - returns the nth channel of the given capability
  309. * @cap: capability to match
  310. * @n: nth channel desired
  311. *
  312. * Defaults to returning the channel with the desired capability and the
  313. * lowest reference count when 'n' cannot be satisfied. Must be called
  314. * under dma_list_mutex.
  315. */
  316. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  317. {
  318. struct dma_device *device;
  319. struct dma_chan *chan;
  320. struct dma_chan *ret = NULL;
  321. struct dma_chan *min = NULL;
  322. list_for_each_entry(device, &dma_device_list, global_node) {
  323. if (!dma_has_cap(cap, device->cap_mask) ||
  324. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  325. continue;
  326. list_for_each_entry(chan, &device->channels, device_node) {
  327. if (!chan->client_count)
  328. continue;
  329. if (!min)
  330. min = chan;
  331. else if (chan->table_count < min->table_count)
  332. min = chan;
  333. if (n-- == 0) {
  334. ret = chan;
  335. break; /* done */
  336. }
  337. }
  338. if (ret)
  339. break; /* done */
  340. }
  341. if (!ret)
  342. ret = min;
  343. if (ret)
  344. ret->table_count++;
  345. return ret;
  346. }
  347. /**
  348. * dma_channel_rebalance - redistribute the available channels
  349. *
  350. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  351. * operation type) in the SMP case, and operation isolation (avoid
  352. * multi-tasking channels) in the non-SMP case. Must be called under
  353. * dma_list_mutex.
  354. */
  355. static void dma_channel_rebalance(void)
  356. {
  357. struct dma_chan *chan;
  358. struct dma_device *device;
  359. int cpu;
  360. int cap;
  361. int n;
  362. /* undo the last distribution */
  363. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  364. for_each_possible_cpu(cpu)
  365. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  366. list_for_each_entry(device, &dma_device_list, global_node) {
  367. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  368. continue;
  369. list_for_each_entry(chan, &device->channels, device_node)
  370. chan->table_count = 0;
  371. }
  372. /* don't populate the channel_table if no clients are available */
  373. if (!dmaengine_ref_count)
  374. return;
  375. /* redistribute available channels */
  376. n = 0;
  377. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  378. for_each_online_cpu(cpu) {
  379. if (num_possible_cpus() > 1)
  380. chan = nth_chan(cap, n++);
  381. else
  382. chan = nth_chan(cap, -1);
  383. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  384. }
  385. }
  386. static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
  387. dma_filter_fn fn, void *fn_param)
  388. {
  389. struct dma_chan *chan;
  390. if (!__dma_device_satisfies_mask(dev, mask)) {
  391. pr_debug("%s: wrong capabilities\n", __func__);
  392. return NULL;
  393. }
  394. /* devices with multiple channels need special handling as we need to
  395. * ensure that all channels are either private or public.
  396. */
  397. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  398. list_for_each_entry(chan, &dev->channels, device_node) {
  399. /* some channels are already publicly allocated */
  400. if (chan->client_count)
  401. return NULL;
  402. }
  403. list_for_each_entry(chan, &dev->channels, device_node) {
  404. if (chan->client_count) {
  405. pr_debug("%s: %s busy\n",
  406. __func__, dma_chan_name(chan));
  407. continue;
  408. }
  409. if (fn && !fn(chan, fn_param)) {
  410. pr_debug("%s: %s filter said false\n",
  411. __func__, dma_chan_name(chan));
  412. continue;
  413. }
  414. return chan;
  415. }
  416. return NULL;
  417. }
  418. /**
  419. * dma_request_channel - try to allocate an exclusive channel
  420. * @mask: capabilities that the channel must satisfy
  421. * @fn: optional callback to disposition available channels
  422. * @fn_param: opaque parameter to pass to dma_filter_fn
  423. */
  424. struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
  425. {
  426. struct dma_device *device, *_d;
  427. struct dma_chan *chan = NULL;
  428. int err;
  429. /* Find a channel */
  430. mutex_lock(&dma_list_mutex);
  431. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  432. chan = private_candidate(mask, device, fn, fn_param);
  433. if (chan) {
  434. /* Found a suitable channel, try to grab, prep, and
  435. * return it. We first set DMA_PRIVATE to disable
  436. * balance_ref_count as this channel will not be
  437. * published in the general-purpose allocator
  438. */
  439. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  440. device->privatecnt++;
  441. err = dma_chan_get(chan);
  442. if (err == -ENODEV) {
  443. pr_debug("%s: %s module removed\n", __func__,
  444. dma_chan_name(chan));
  445. list_del_rcu(&device->global_node);
  446. } else if (err)
  447. pr_debug("dmaengine: failed to get %s: (%d)\n",
  448. dma_chan_name(chan), err);
  449. else
  450. break;
  451. if (--device->privatecnt == 0)
  452. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  453. chan = NULL;
  454. }
  455. }
  456. mutex_unlock(&dma_list_mutex);
  457. pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
  458. chan ? dma_chan_name(chan) : NULL);
  459. return chan;
  460. }
  461. EXPORT_SYMBOL_GPL(__dma_request_channel);
  462. void dma_release_channel(struct dma_chan *chan)
  463. {
  464. mutex_lock(&dma_list_mutex);
  465. WARN_ONCE(chan->client_count != 1,
  466. "chan reference count %d != 1\n", chan->client_count);
  467. dma_chan_put(chan);
  468. /* drop PRIVATE cap enabled by __dma_request_channel() */
  469. if (--chan->device->privatecnt == 0)
  470. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  471. mutex_unlock(&dma_list_mutex);
  472. }
  473. EXPORT_SYMBOL_GPL(dma_release_channel);
  474. /**
  475. * dmaengine_get - register interest in dma_channels
  476. */
  477. void dmaengine_get(void)
  478. {
  479. struct dma_device *device, *_d;
  480. struct dma_chan *chan;
  481. int err;
  482. mutex_lock(&dma_list_mutex);
  483. dmaengine_ref_count++;
  484. /* try to grab channels */
  485. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  486. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  487. continue;
  488. list_for_each_entry(chan, &device->channels, device_node) {
  489. err = dma_chan_get(chan);
  490. if (err == -ENODEV) {
  491. /* module removed before we could use it */
  492. list_del_rcu(&device->global_node);
  493. break;
  494. } else if (err)
  495. pr_err("dmaengine: failed to get %s: (%d)\n",
  496. dma_chan_name(chan), err);
  497. }
  498. }
  499. /* if this is the first reference and there were channels
  500. * waiting we need to rebalance to get those channels
  501. * incorporated into the channel table
  502. */
  503. if (dmaengine_ref_count == 1)
  504. dma_channel_rebalance();
  505. mutex_unlock(&dma_list_mutex);
  506. }
  507. EXPORT_SYMBOL(dmaengine_get);
  508. /**
  509. * dmaengine_put - let dma drivers be removed when ref_count == 0
  510. */
  511. void dmaengine_put(void)
  512. {
  513. struct dma_device *device;
  514. struct dma_chan *chan;
  515. mutex_lock(&dma_list_mutex);
  516. dmaengine_ref_count--;
  517. BUG_ON(dmaengine_ref_count < 0);
  518. /* drop channel references */
  519. list_for_each_entry(device, &dma_device_list, global_node) {
  520. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  521. continue;
  522. list_for_each_entry(chan, &device->channels, device_node)
  523. dma_chan_put(chan);
  524. }
  525. mutex_unlock(&dma_list_mutex);
  526. }
  527. EXPORT_SYMBOL(dmaengine_put);
  528. static bool device_has_all_tx_types(struct dma_device *device)
  529. {
  530. /* A device that satisfies this test has channels that will never cause
  531. * an async_tx channel switch event as all possible operation types can
  532. * be handled.
  533. */
  534. #ifdef CONFIG_ASYNC_TX_DMA
  535. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  536. return false;
  537. #endif
  538. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  539. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  540. return false;
  541. #endif
  542. #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
  543. if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
  544. return false;
  545. #endif
  546. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  547. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  548. return false;
  549. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  550. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  551. return false;
  552. #endif
  553. #endif
  554. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  555. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  556. return false;
  557. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  558. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  559. return false;
  560. #endif
  561. #endif
  562. return true;
  563. }
  564. static int get_dma_id(struct dma_device *device)
  565. {
  566. int rc;
  567. idr_retry:
  568. if (!idr_pre_get(&dma_idr, GFP_KERNEL))
  569. return -ENOMEM;
  570. mutex_lock(&dma_list_mutex);
  571. rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
  572. mutex_unlock(&dma_list_mutex);
  573. if (rc == -EAGAIN)
  574. goto idr_retry;
  575. else if (rc != 0)
  576. return rc;
  577. return 0;
  578. }
  579. /**
  580. * dma_async_device_register - registers DMA devices found
  581. * @device: &dma_device
  582. */
  583. int dma_async_device_register(struct dma_device *device)
  584. {
  585. int chancnt = 0, rc;
  586. struct dma_chan* chan;
  587. atomic_t *idr_ref;
  588. if (!device)
  589. return -ENODEV;
  590. /* validate device routines */
  591. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  592. !device->device_prep_dma_memcpy);
  593. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  594. !device->device_prep_dma_xor);
  595. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  596. !device->device_prep_dma_xor_val);
  597. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  598. !device->device_prep_dma_pq);
  599. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  600. !device->device_prep_dma_pq_val);
  601. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  602. !device->device_prep_dma_memset);
  603. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  604. !device->device_prep_dma_interrupt);
  605. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  606. !device->device_prep_dma_sg);
  607. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  608. !device->device_prep_slave_sg);
  609. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  610. !device->device_prep_dma_cyclic);
  611. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  612. !device->device_control);
  613. BUG_ON(!device->device_alloc_chan_resources);
  614. BUG_ON(!device->device_free_chan_resources);
  615. BUG_ON(!device->device_tx_status);
  616. BUG_ON(!device->device_issue_pending);
  617. BUG_ON(!device->dev);
  618. /* note: this only matters in the
  619. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  620. */
  621. if (device_has_all_tx_types(device))
  622. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  623. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  624. if (!idr_ref)
  625. return -ENOMEM;
  626. rc = get_dma_id(device);
  627. if (rc != 0) {
  628. kfree(idr_ref);
  629. return rc;
  630. }
  631. atomic_set(idr_ref, 0);
  632. /* represent channels in sysfs. Probably want devs too */
  633. list_for_each_entry(chan, &device->channels, device_node) {
  634. rc = -ENOMEM;
  635. chan->local = alloc_percpu(typeof(*chan->local));
  636. if (chan->local == NULL)
  637. goto err_out;
  638. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  639. if (chan->dev == NULL) {
  640. free_percpu(chan->local);
  641. chan->local = NULL;
  642. goto err_out;
  643. }
  644. chan->chan_id = chancnt++;
  645. chan->dev->device.class = &dma_devclass;
  646. chan->dev->device.parent = device->dev;
  647. chan->dev->chan = chan;
  648. chan->dev->idr_ref = idr_ref;
  649. chan->dev->dev_id = device->dev_id;
  650. atomic_inc(idr_ref);
  651. dev_set_name(&chan->dev->device, "dma%dchan%d",
  652. device->dev_id, chan->chan_id);
  653. rc = device_register(&chan->dev->device);
  654. if (rc) {
  655. free_percpu(chan->local);
  656. chan->local = NULL;
  657. kfree(chan->dev);
  658. atomic_dec(idr_ref);
  659. goto err_out;
  660. }
  661. chan->client_count = 0;
  662. }
  663. device->chancnt = chancnt;
  664. mutex_lock(&dma_list_mutex);
  665. /* take references on public channels */
  666. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  667. list_for_each_entry(chan, &device->channels, device_node) {
  668. /* if clients are already waiting for channels we need
  669. * to take references on their behalf
  670. */
  671. if (dma_chan_get(chan) == -ENODEV) {
  672. /* note we can only get here for the first
  673. * channel as the remaining channels are
  674. * guaranteed to get a reference
  675. */
  676. rc = -ENODEV;
  677. mutex_unlock(&dma_list_mutex);
  678. goto err_out;
  679. }
  680. }
  681. list_add_tail_rcu(&device->global_node, &dma_device_list);
  682. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  683. device->privatecnt++; /* Always private */
  684. dma_channel_rebalance();
  685. mutex_unlock(&dma_list_mutex);
  686. return 0;
  687. err_out:
  688. /* if we never registered a channel just release the idr */
  689. if (atomic_read(idr_ref) == 0) {
  690. mutex_lock(&dma_list_mutex);
  691. idr_remove(&dma_idr, device->dev_id);
  692. mutex_unlock(&dma_list_mutex);
  693. kfree(idr_ref);
  694. return rc;
  695. }
  696. list_for_each_entry(chan, &device->channels, device_node) {
  697. if (chan->local == NULL)
  698. continue;
  699. mutex_lock(&dma_list_mutex);
  700. chan->dev->chan = NULL;
  701. mutex_unlock(&dma_list_mutex);
  702. device_unregister(&chan->dev->device);
  703. free_percpu(chan->local);
  704. }
  705. return rc;
  706. }
  707. EXPORT_SYMBOL(dma_async_device_register);
  708. /**
  709. * dma_async_device_unregister - unregister a DMA device
  710. * @device: &dma_device
  711. *
  712. * This routine is called by dma driver exit routines, dmaengine holds module
  713. * references to prevent it being called while channels are in use.
  714. */
  715. void dma_async_device_unregister(struct dma_device *device)
  716. {
  717. struct dma_chan *chan;
  718. mutex_lock(&dma_list_mutex);
  719. list_del_rcu(&device->global_node);
  720. dma_channel_rebalance();
  721. mutex_unlock(&dma_list_mutex);
  722. list_for_each_entry(chan, &device->channels, device_node) {
  723. WARN_ONCE(chan->client_count,
  724. "%s called while %d clients hold a reference\n",
  725. __func__, chan->client_count);
  726. mutex_lock(&dma_list_mutex);
  727. chan->dev->chan = NULL;
  728. mutex_unlock(&dma_list_mutex);
  729. device_unregister(&chan->dev->device);
  730. free_percpu(chan->local);
  731. }
  732. }
  733. EXPORT_SYMBOL(dma_async_device_unregister);
  734. /**
  735. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  736. * @chan: DMA channel to offload copy to
  737. * @dest: destination address (virtual)
  738. * @src: source address (virtual)
  739. * @len: length
  740. *
  741. * Both @dest and @src must be mappable to a bus address according to the
  742. * DMA mapping API rules for streaming mappings.
  743. * Both @dest and @src must stay memory resident (kernel memory or locked
  744. * user space pages).
  745. */
  746. dma_cookie_t
  747. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  748. void *src, size_t len)
  749. {
  750. struct dma_device *dev = chan->device;
  751. struct dma_async_tx_descriptor *tx;
  752. dma_addr_t dma_dest, dma_src;
  753. dma_cookie_t cookie;
  754. unsigned long flags;
  755. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  756. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  757. flags = DMA_CTRL_ACK |
  758. DMA_COMPL_SRC_UNMAP_SINGLE |
  759. DMA_COMPL_DEST_UNMAP_SINGLE;
  760. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  761. if (!tx) {
  762. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  763. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  764. return -ENOMEM;
  765. }
  766. tx->callback = NULL;
  767. cookie = tx->tx_submit(tx);
  768. preempt_disable();
  769. __this_cpu_add(chan->local->bytes_transferred, len);
  770. __this_cpu_inc(chan->local->memcpy_count);
  771. preempt_enable();
  772. return cookie;
  773. }
  774. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  775. /**
  776. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  777. * @chan: DMA channel to offload copy to
  778. * @page: destination page
  779. * @offset: offset in page to copy to
  780. * @kdata: source address (virtual)
  781. * @len: length
  782. *
  783. * Both @page/@offset and @kdata must be mappable to a bus address according
  784. * to the DMA mapping API rules for streaming mappings.
  785. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  786. * locked user space pages)
  787. */
  788. dma_cookie_t
  789. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  790. unsigned int offset, void *kdata, size_t len)
  791. {
  792. struct dma_device *dev = chan->device;
  793. struct dma_async_tx_descriptor *tx;
  794. dma_addr_t dma_dest, dma_src;
  795. dma_cookie_t cookie;
  796. unsigned long flags;
  797. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  798. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  799. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  800. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  801. if (!tx) {
  802. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  803. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  804. return -ENOMEM;
  805. }
  806. tx->callback = NULL;
  807. cookie = tx->tx_submit(tx);
  808. preempt_disable();
  809. __this_cpu_add(chan->local->bytes_transferred, len);
  810. __this_cpu_inc(chan->local->memcpy_count);
  811. preempt_enable();
  812. return cookie;
  813. }
  814. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  815. /**
  816. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  817. * @chan: DMA channel to offload copy to
  818. * @dest_pg: destination page
  819. * @dest_off: offset in page to copy to
  820. * @src_pg: source page
  821. * @src_off: offset in page to copy from
  822. * @len: length
  823. *
  824. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  825. * address according to the DMA mapping API rules for streaming mappings.
  826. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  827. * (kernel memory or locked user space pages).
  828. */
  829. dma_cookie_t
  830. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  831. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  832. size_t len)
  833. {
  834. struct dma_device *dev = chan->device;
  835. struct dma_async_tx_descriptor *tx;
  836. dma_addr_t dma_dest, dma_src;
  837. dma_cookie_t cookie;
  838. unsigned long flags;
  839. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  840. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  841. DMA_FROM_DEVICE);
  842. flags = DMA_CTRL_ACK;
  843. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  844. if (!tx) {
  845. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  846. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  847. return -ENOMEM;
  848. }
  849. tx->callback = NULL;
  850. cookie = tx->tx_submit(tx);
  851. preempt_disable();
  852. __this_cpu_add(chan->local->bytes_transferred, len);
  853. __this_cpu_inc(chan->local->memcpy_count);
  854. preempt_enable();
  855. return cookie;
  856. }
  857. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  858. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  859. struct dma_chan *chan)
  860. {
  861. tx->chan = chan;
  862. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  863. spin_lock_init(&tx->lock);
  864. #endif
  865. }
  866. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  867. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  868. * @tx: in-flight transaction to wait on
  869. */
  870. enum dma_status
  871. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  872. {
  873. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  874. if (!tx)
  875. return DMA_SUCCESS;
  876. while (tx->cookie == -EBUSY) {
  877. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  878. pr_err("%s timeout waiting for descriptor submission\n",
  879. __func__);
  880. return DMA_ERROR;
  881. }
  882. cpu_relax();
  883. }
  884. return dma_sync_wait(tx->chan, tx->cookie);
  885. }
  886. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  887. /* dma_run_dependencies - helper routine for dma drivers to process
  888. * (start) dependent operations on their target channel
  889. * @tx: transaction with dependencies
  890. */
  891. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  892. {
  893. struct dma_async_tx_descriptor *dep = txd_next(tx);
  894. struct dma_async_tx_descriptor *dep_next;
  895. struct dma_chan *chan;
  896. if (!dep)
  897. return;
  898. /* we'll submit tx->next now, so clear the link */
  899. txd_clear_next(tx);
  900. chan = dep->chan;
  901. /* keep submitting up until a channel switch is detected
  902. * in that case we will be called again as a result of
  903. * processing the interrupt from async_tx_channel_switch
  904. */
  905. for (; dep; dep = dep_next) {
  906. txd_lock(dep);
  907. txd_clear_parent(dep);
  908. dep_next = txd_next(dep);
  909. if (dep_next && dep_next->chan == chan)
  910. txd_clear_next(dep); /* ->next will be submitted */
  911. else
  912. dep_next = NULL; /* submit current dep and terminate */
  913. txd_unlock(dep);
  914. dep->tx_submit(dep);
  915. }
  916. chan->device->device_issue_pending(chan);
  917. }
  918. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  919. static int __init dma_bus_init(void)
  920. {
  921. return class_register(&dma_devclass);
  922. }
  923. arch_initcall(dma_bus_init);