talitos.c 70 KB

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  1. /*
  2. * talitos - Freescale Integrated Security Engine (SEC) device driver
  3. *
  4. * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
  5. *
  6. * Scatterlist Crypto API glue code copied from files with the following:
  7. * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
  8. *
  9. * Crypto algorithm registration code copied from hifn driver:
  10. * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11. * All rights reserved.
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. */
  27. #include <linux/kernel.h>
  28. #include <linux/module.h>
  29. #include <linux/mod_devicetable.h>
  30. #include <linux/device.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/crypto.h>
  33. #include <linux/hw_random.h>
  34. #include <linux/of_platform.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/io.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/rtnetlink.h>
  39. #include <linux/slab.h>
  40. #include <crypto/algapi.h>
  41. #include <crypto/aes.h>
  42. #include <crypto/des.h>
  43. #include <crypto/sha.h>
  44. #include <crypto/md5.h>
  45. #include <crypto/aead.h>
  46. #include <crypto/authenc.h>
  47. #include <crypto/skcipher.h>
  48. #include <crypto/hash.h>
  49. #include <crypto/internal/hash.h>
  50. #include <crypto/scatterwalk.h>
  51. #include "talitos.h"
  52. #define TALITOS_TIMEOUT 100000
  53. #define TALITOS_MAX_DATA_LEN 65535
  54. #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
  55. #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
  56. #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
  57. /* descriptor pointer entry */
  58. struct talitos_ptr {
  59. __be16 len; /* length */
  60. u8 j_extent; /* jump to sg link table and/or extent */
  61. u8 eptr; /* extended address */
  62. __be32 ptr; /* address */
  63. };
  64. static const struct talitos_ptr zero_entry = {
  65. .len = 0,
  66. .j_extent = 0,
  67. .eptr = 0,
  68. .ptr = 0
  69. };
  70. /* descriptor */
  71. struct talitos_desc {
  72. __be32 hdr; /* header high bits */
  73. __be32 hdr_lo; /* header low bits */
  74. struct talitos_ptr ptr[7]; /* ptr/len pair array */
  75. };
  76. /**
  77. * talitos_request - descriptor submission request
  78. * @desc: descriptor pointer (kernel virtual)
  79. * @dma_desc: descriptor's physical bus address
  80. * @callback: whom to call when descriptor processing is done
  81. * @context: caller context (optional)
  82. */
  83. struct talitos_request {
  84. struct talitos_desc *desc;
  85. dma_addr_t dma_desc;
  86. void (*callback) (struct device *dev, struct talitos_desc *desc,
  87. void *context, int error);
  88. void *context;
  89. };
  90. /* per-channel fifo management */
  91. struct talitos_channel {
  92. /* request fifo */
  93. struct talitos_request *fifo;
  94. /* number of requests pending in channel h/w fifo */
  95. atomic_t submit_count ____cacheline_aligned;
  96. /* request submission (head) lock */
  97. spinlock_t head_lock ____cacheline_aligned;
  98. /* index to next free descriptor request */
  99. int head;
  100. /* request release (tail) lock */
  101. spinlock_t tail_lock ____cacheline_aligned;
  102. /* index to next in-progress/done descriptor request */
  103. int tail;
  104. };
  105. struct talitos_private {
  106. struct device *dev;
  107. struct platform_device *ofdev;
  108. void __iomem *reg;
  109. int irq;
  110. /* SEC version geometry (from device tree node) */
  111. unsigned int num_channels;
  112. unsigned int chfifo_len;
  113. unsigned int exec_units;
  114. unsigned int desc_types;
  115. /* SEC Compatibility info */
  116. unsigned long features;
  117. /*
  118. * length of the request fifo
  119. * fifo_len is chfifo_len rounded up to next power of 2
  120. * so we can use bitwise ops to wrap
  121. */
  122. unsigned int fifo_len;
  123. struct talitos_channel *chan;
  124. /* next channel to be assigned next incoming descriptor */
  125. atomic_t last_chan ____cacheline_aligned;
  126. /* request callback tasklet */
  127. struct tasklet_struct done_task;
  128. /* list of registered algorithms */
  129. struct list_head alg_list;
  130. /* hwrng device */
  131. struct hwrng rng;
  132. };
  133. /* .features flag */
  134. #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
  135. #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
  136. #define TALITOS_FTR_SHA224_HWINIT 0x00000004
  137. static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
  138. {
  139. talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
  140. talitos_ptr->eptr = upper_32_bits(dma_addr);
  141. }
  142. /*
  143. * map virtual single (contiguous) pointer to h/w descriptor pointer
  144. */
  145. static void map_single_talitos_ptr(struct device *dev,
  146. struct talitos_ptr *talitos_ptr,
  147. unsigned short len, void *data,
  148. unsigned char extent,
  149. enum dma_data_direction dir)
  150. {
  151. dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
  152. talitos_ptr->len = cpu_to_be16(len);
  153. to_talitos_ptr(talitos_ptr, dma_addr);
  154. talitos_ptr->j_extent = extent;
  155. }
  156. /*
  157. * unmap bus single (contiguous) h/w descriptor pointer
  158. */
  159. static void unmap_single_talitos_ptr(struct device *dev,
  160. struct talitos_ptr *talitos_ptr,
  161. enum dma_data_direction dir)
  162. {
  163. dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
  164. be16_to_cpu(talitos_ptr->len), dir);
  165. }
  166. static int reset_channel(struct device *dev, int ch)
  167. {
  168. struct talitos_private *priv = dev_get_drvdata(dev);
  169. unsigned int timeout = TALITOS_TIMEOUT;
  170. setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
  171. while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
  172. && --timeout)
  173. cpu_relax();
  174. if (timeout == 0) {
  175. dev_err(dev, "failed to reset channel %d\n", ch);
  176. return -EIO;
  177. }
  178. /* set 36-bit addressing, done writeback enable and done IRQ enable */
  179. setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
  180. TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
  181. /* and ICCR writeback, if available */
  182. if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
  183. setbits32(priv->reg + TALITOS_CCCR_LO(ch),
  184. TALITOS_CCCR_LO_IWSE);
  185. return 0;
  186. }
  187. static int reset_device(struct device *dev)
  188. {
  189. struct talitos_private *priv = dev_get_drvdata(dev);
  190. unsigned int timeout = TALITOS_TIMEOUT;
  191. setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
  192. while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
  193. && --timeout)
  194. cpu_relax();
  195. if (timeout == 0) {
  196. dev_err(dev, "failed to reset device\n");
  197. return -EIO;
  198. }
  199. return 0;
  200. }
  201. /*
  202. * Reset and initialize the device
  203. */
  204. static int init_device(struct device *dev)
  205. {
  206. struct talitos_private *priv = dev_get_drvdata(dev);
  207. int ch, err;
  208. /*
  209. * Master reset
  210. * errata documentation: warning: certain SEC interrupts
  211. * are not fully cleared by writing the MCR:SWR bit,
  212. * set bit twice to completely reset
  213. */
  214. err = reset_device(dev);
  215. if (err)
  216. return err;
  217. err = reset_device(dev);
  218. if (err)
  219. return err;
  220. /* reset channels */
  221. for (ch = 0; ch < priv->num_channels; ch++) {
  222. err = reset_channel(dev, ch);
  223. if (err)
  224. return err;
  225. }
  226. /* enable channel done and error interrupts */
  227. setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
  228. setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
  229. /* disable integrity check error interrupts (use writeback instead) */
  230. if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
  231. setbits32(priv->reg + TALITOS_MDEUICR_LO,
  232. TALITOS_MDEUICR_LO_ICE);
  233. return 0;
  234. }
  235. /**
  236. * talitos_submit - submits a descriptor to the device for processing
  237. * @dev: the SEC device to be used
  238. * @ch: the SEC device channel to be used
  239. * @desc: the descriptor to be processed by the device
  240. * @callback: whom to call when processing is complete
  241. * @context: a handle for use by caller (optional)
  242. *
  243. * desc must contain valid dma-mapped (bus physical) address pointers.
  244. * callback must check err and feedback in descriptor header
  245. * for device processing status.
  246. */
  247. static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
  248. void (*callback)(struct device *dev,
  249. struct talitos_desc *desc,
  250. void *context, int error),
  251. void *context)
  252. {
  253. struct talitos_private *priv = dev_get_drvdata(dev);
  254. struct talitos_request *request;
  255. unsigned long flags;
  256. int head;
  257. spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
  258. if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
  259. /* h/w fifo is full */
  260. spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
  261. return -EAGAIN;
  262. }
  263. head = priv->chan[ch].head;
  264. request = &priv->chan[ch].fifo[head];
  265. /* map descriptor and save caller data */
  266. request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
  267. DMA_BIDIRECTIONAL);
  268. request->callback = callback;
  269. request->context = context;
  270. /* increment fifo head */
  271. priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
  272. smp_wmb();
  273. request->desc = desc;
  274. /* GO! */
  275. wmb();
  276. out_be32(priv->reg + TALITOS_FF(ch), upper_32_bits(request->dma_desc));
  277. out_be32(priv->reg + TALITOS_FF_LO(ch),
  278. lower_32_bits(request->dma_desc));
  279. spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
  280. return -EINPROGRESS;
  281. }
  282. /*
  283. * process what was done, notify callback of error if not
  284. */
  285. static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
  286. {
  287. struct talitos_private *priv = dev_get_drvdata(dev);
  288. struct talitos_request *request, saved_req;
  289. unsigned long flags;
  290. int tail, status;
  291. spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
  292. tail = priv->chan[ch].tail;
  293. while (priv->chan[ch].fifo[tail].desc) {
  294. request = &priv->chan[ch].fifo[tail];
  295. /* descriptors with their done bits set don't get the error */
  296. rmb();
  297. if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
  298. status = 0;
  299. else
  300. if (!error)
  301. break;
  302. else
  303. status = error;
  304. dma_unmap_single(dev, request->dma_desc,
  305. sizeof(struct talitos_desc),
  306. DMA_BIDIRECTIONAL);
  307. /* copy entries so we can call callback outside lock */
  308. saved_req.desc = request->desc;
  309. saved_req.callback = request->callback;
  310. saved_req.context = request->context;
  311. /* release request entry in fifo */
  312. smp_wmb();
  313. request->desc = NULL;
  314. /* increment fifo tail */
  315. priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
  316. spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
  317. atomic_dec(&priv->chan[ch].submit_count);
  318. saved_req.callback(dev, saved_req.desc, saved_req.context,
  319. status);
  320. /* channel may resume processing in single desc error case */
  321. if (error && !reset_ch && status == error)
  322. return;
  323. spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
  324. tail = priv->chan[ch].tail;
  325. }
  326. spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
  327. }
  328. /*
  329. * process completed requests for channels that have done status
  330. */
  331. static void talitos_done(unsigned long data)
  332. {
  333. struct device *dev = (struct device *)data;
  334. struct talitos_private *priv = dev_get_drvdata(dev);
  335. int ch;
  336. for (ch = 0; ch < priv->num_channels; ch++)
  337. flush_channel(dev, ch, 0, 0);
  338. /* At this point, all completed channels have been processed.
  339. * Unmask done interrupts for channels completed later on.
  340. */
  341. setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
  342. setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
  343. }
  344. /*
  345. * locate current (offending) descriptor
  346. */
  347. static struct talitos_desc *current_desc(struct device *dev, int ch)
  348. {
  349. struct talitos_private *priv = dev_get_drvdata(dev);
  350. int tail = priv->chan[ch].tail;
  351. dma_addr_t cur_desc;
  352. cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
  353. while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
  354. tail = (tail + 1) & (priv->fifo_len - 1);
  355. if (tail == priv->chan[ch].tail) {
  356. dev_err(dev, "couldn't locate current descriptor\n");
  357. return NULL;
  358. }
  359. }
  360. return priv->chan[ch].fifo[tail].desc;
  361. }
  362. /*
  363. * user diagnostics; report root cause of error based on execution unit status
  364. */
  365. static void report_eu_error(struct device *dev, int ch,
  366. struct talitos_desc *desc)
  367. {
  368. struct talitos_private *priv = dev_get_drvdata(dev);
  369. int i;
  370. switch (desc->hdr & DESC_HDR_SEL0_MASK) {
  371. case DESC_HDR_SEL0_AFEU:
  372. dev_err(dev, "AFEUISR 0x%08x_%08x\n",
  373. in_be32(priv->reg + TALITOS_AFEUISR),
  374. in_be32(priv->reg + TALITOS_AFEUISR_LO));
  375. break;
  376. case DESC_HDR_SEL0_DEU:
  377. dev_err(dev, "DEUISR 0x%08x_%08x\n",
  378. in_be32(priv->reg + TALITOS_DEUISR),
  379. in_be32(priv->reg + TALITOS_DEUISR_LO));
  380. break;
  381. case DESC_HDR_SEL0_MDEUA:
  382. case DESC_HDR_SEL0_MDEUB:
  383. dev_err(dev, "MDEUISR 0x%08x_%08x\n",
  384. in_be32(priv->reg + TALITOS_MDEUISR),
  385. in_be32(priv->reg + TALITOS_MDEUISR_LO));
  386. break;
  387. case DESC_HDR_SEL0_RNG:
  388. dev_err(dev, "RNGUISR 0x%08x_%08x\n",
  389. in_be32(priv->reg + TALITOS_RNGUISR),
  390. in_be32(priv->reg + TALITOS_RNGUISR_LO));
  391. break;
  392. case DESC_HDR_SEL0_PKEU:
  393. dev_err(dev, "PKEUISR 0x%08x_%08x\n",
  394. in_be32(priv->reg + TALITOS_PKEUISR),
  395. in_be32(priv->reg + TALITOS_PKEUISR_LO));
  396. break;
  397. case DESC_HDR_SEL0_AESU:
  398. dev_err(dev, "AESUISR 0x%08x_%08x\n",
  399. in_be32(priv->reg + TALITOS_AESUISR),
  400. in_be32(priv->reg + TALITOS_AESUISR_LO));
  401. break;
  402. case DESC_HDR_SEL0_CRCU:
  403. dev_err(dev, "CRCUISR 0x%08x_%08x\n",
  404. in_be32(priv->reg + TALITOS_CRCUISR),
  405. in_be32(priv->reg + TALITOS_CRCUISR_LO));
  406. break;
  407. case DESC_HDR_SEL0_KEU:
  408. dev_err(dev, "KEUISR 0x%08x_%08x\n",
  409. in_be32(priv->reg + TALITOS_KEUISR),
  410. in_be32(priv->reg + TALITOS_KEUISR_LO));
  411. break;
  412. }
  413. switch (desc->hdr & DESC_HDR_SEL1_MASK) {
  414. case DESC_HDR_SEL1_MDEUA:
  415. case DESC_HDR_SEL1_MDEUB:
  416. dev_err(dev, "MDEUISR 0x%08x_%08x\n",
  417. in_be32(priv->reg + TALITOS_MDEUISR),
  418. in_be32(priv->reg + TALITOS_MDEUISR_LO));
  419. break;
  420. case DESC_HDR_SEL1_CRCU:
  421. dev_err(dev, "CRCUISR 0x%08x_%08x\n",
  422. in_be32(priv->reg + TALITOS_CRCUISR),
  423. in_be32(priv->reg + TALITOS_CRCUISR_LO));
  424. break;
  425. }
  426. for (i = 0; i < 8; i++)
  427. dev_err(dev, "DESCBUF 0x%08x_%08x\n",
  428. in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
  429. in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
  430. }
  431. /*
  432. * recover from error interrupts
  433. */
  434. static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
  435. {
  436. struct device *dev = (struct device *)data;
  437. struct talitos_private *priv = dev_get_drvdata(dev);
  438. unsigned int timeout = TALITOS_TIMEOUT;
  439. int ch, error, reset_dev = 0, reset_ch = 0;
  440. u32 v, v_lo;
  441. for (ch = 0; ch < priv->num_channels; ch++) {
  442. /* skip channels without errors */
  443. if (!(isr & (1 << (ch * 2 + 1))))
  444. continue;
  445. error = -EINVAL;
  446. v = in_be32(priv->reg + TALITOS_CCPSR(ch));
  447. v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
  448. if (v_lo & TALITOS_CCPSR_LO_DOF) {
  449. dev_err(dev, "double fetch fifo overflow error\n");
  450. error = -EAGAIN;
  451. reset_ch = 1;
  452. }
  453. if (v_lo & TALITOS_CCPSR_LO_SOF) {
  454. /* h/w dropped descriptor */
  455. dev_err(dev, "single fetch fifo overflow error\n");
  456. error = -EAGAIN;
  457. }
  458. if (v_lo & TALITOS_CCPSR_LO_MDTE)
  459. dev_err(dev, "master data transfer error\n");
  460. if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
  461. dev_err(dev, "s/g data length zero error\n");
  462. if (v_lo & TALITOS_CCPSR_LO_FPZ)
  463. dev_err(dev, "fetch pointer zero error\n");
  464. if (v_lo & TALITOS_CCPSR_LO_IDH)
  465. dev_err(dev, "illegal descriptor header error\n");
  466. if (v_lo & TALITOS_CCPSR_LO_IEU)
  467. dev_err(dev, "invalid execution unit error\n");
  468. if (v_lo & TALITOS_CCPSR_LO_EU)
  469. report_eu_error(dev, ch, current_desc(dev, ch));
  470. if (v_lo & TALITOS_CCPSR_LO_GB)
  471. dev_err(dev, "gather boundary error\n");
  472. if (v_lo & TALITOS_CCPSR_LO_GRL)
  473. dev_err(dev, "gather return/length error\n");
  474. if (v_lo & TALITOS_CCPSR_LO_SB)
  475. dev_err(dev, "scatter boundary error\n");
  476. if (v_lo & TALITOS_CCPSR_LO_SRL)
  477. dev_err(dev, "scatter return/length error\n");
  478. flush_channel(dev, ch, error, reset_ch);
  479. if (reset_ch) {
  480. reset_channel(dev, ch);
  481. } else {
  482. setbits32(priv->reg + TALITOS_CCCR(ch),
  483. TALITOS_CCCR_CONT);
  484. setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
  485. while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
  486. TALITOS_CCCR_CONT) && --timeout)
  487. cpu_relax();
  488. if (timeout == 0) {
  489. dev_err(dev, "failed to restart channel %d\n",
  490. ch);
  491. reset_dev = 1;
  492. }
  493. }
  494. }
  495. if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
  496. dev_err(dev, "done overflow, internal time out, or rngu error: "
  497. "ISR 0x%08x_%08x\n", isr, isr_lo);
  498. /* purge request queues */
  499. for (ch = 0; ch < priv->num_channels; ch++)
  500. flush_channel(dev, ch, -EIO, 1);
  501. /* reset and reinitialize the device */
  502. init_device(dev);
  503. }
  504. }
  505. static irqreturn_t talitos_interrupt(int irq, void *data)
  506. {
  507. struct device *dev = data;
  508. struct talitos_private *priv = dev_get_drvdata(dev);
  509. u32 isr, isr_lo;
  510. isr = in_be32(priv->reg + TALITOS_ISR);
  511. isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
  512. /* Acknowledge interrupt */
  513. out_be32(priv->reg + TALITOS_ICR, isr);
  514. out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
  515. if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
  516. talitos_error((unsigned long)data, isr, isr_lo);
  517. else
  518. if (likely(isr & TALITOS_ISR_CHDONE)) {
  519. /* mask further done interrupts. */
  520. clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
  521. /* done_task will unmask done interrupts at exit */
  522. tasklet_schedule(&priv->done_task);
  523. }
  524. return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
  525. }
  526. /*
  527. * hwrng
  528. */
  529. static int talitos_rng_data_present(struct hwrng *rng, int wait)
  530. {
  531. struct device *dev = (struct device *)rng->priv;
  532. struct talitos_private *priv = dev_get_drvdata(dev);
  533. u32 ofl;
  534. int i;
  535. for (i = 0; i < 20; i++) {
  536. ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
  537. TALITOS_RNGUSR_LO_OFL;
  538. if (ofl || !wait)
  539. break;
  540. udelay(10);
  541. }
  542. return !!ofl;
  543. }
  544. static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
  545. {
  546. struct device *dev = (struct device *)rng->priv;
  547. struct talitos_private *priv = dev_get_drvdata(dev);
  548. /* rng fifo requires 64-bit accesses */
  549. *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
  550. *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
  551. return sizeof(u32);
  552. }
  553. static int talitos_rng_init(struct hwrng *rng)
  554. {
  555. struct device *dev = (struct device *)rng->priv;
  556. struct talitos_private *priv = dev_get_drvdata(dev);
  557. unsigned int timeout = TALITOS_TIMEOUT;
  558. setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
  559. while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
  560. && --timeout)
  561. cpu_relax();
  562. if (timeout == 0) {
  563. dev_err(dev, "failed to reset rng hw\n");
  564. return -ENODEV;
  565. }
  566. /* start generating */
  567. setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
  568. return 0;
  569. }
  570. static int talitos_register_rng(struct device *dev)
  571. {
  572. struct talitos_private *priv = dev_get_drvdata(dev);
  573. priv->rng.name = dev_driver_string(dev),
  574. priv->rng.init = talitos_rng_init,
  575. priv->rng.data_present = talitos_rng_data_present,
  576. priv->rng.data_read = talitos_rng_data_read,
  577. priv->rng.priv = (unsigned long)dev;
  578. return hwrng_register(&priv->rng);
  579. }
  580. static void talitos_unregister_rng(struct device *dev)
  581. {
  582. struct talitos_private *priv = dev_get_drvdata(dev);
  583. hwrng_unregister(&priv->rng);
  584. }
  585. /*
  586. * crypto alg
  587. */
  588. #define TALITOS_CRA_PRIORITY 3000
  589. #define TALITOS_MAX_KEY_SIZE 64
  590. #define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
  591. #define MD5_BLOCK_SIZE 64
  592. struct talitos_ctx {
  593. struct device *dev;
  594. int ch;
  595. __be32 desc_hdr_template;
  596. u8 key[TALITOS_MAX_KEY_SIZE];
  597. u8 iv[TALITOS_MAX_IV_LENGTH];
  598. unsigned int keylen;
  599. unsigned int enckeylen;
  600. unsigned int authkeylen;
  601. unsigned int authsize;
  602. };
  603. #define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
  604. #define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
  605. struct talitos_ahash_req_ctx {
  606. u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
  607. unsigned int hw_context_size;
  608. u8 buf[HASH_MAX_BLOCK_SIZE];
  609. u8 bufnext[HASH_MAX_BLOCK_SIZE];
  610. unsigned int swinit;
  611. unsigned int first;
  612. unsigned int last;
  613. unsigned int to_hash_later;
  614. u64 nbuf;
  615. struct scatterlist bufsl[2];
  616. struct scatterlist *psrc;
  617. };
  618. static int aead_setauthsize(struct crypto_aead *authenc,
  619. unsigned int authsize)
  620. {
  621. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  622. ctx->authsize = authsize;
  623. return 0;
  624. }
  625. static int aead_setkey(struct crypto_aead *authenc,
  626. const u8 *key, unsigned int keylen)
  627. {
  628. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  629. struct rtattr *rta = (void *)key;
  630. struct crypto_authenc_key_param *param;
  631. unsigned int authkeylen;
  632. unsigned int enckeylen;
  633. if (!RTA_OK(rta, keylen))
  634. goto badkey;
  635. if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
  636. goto badkey;
  637. if (RTA_PAYLOAD(rta) < sizeof(*param))
  638. goto badkey;
  639. param = RTA_DATA(rta);
  640. enckeylen = be32_to_cpu(param->enckeylen);
  641. key += RTA_ALIGN(rta->rta_len);
  642. keylen -= RTA_ALIGN(rta->rta_len);
  643. if (keylen < enckeylen)
  644. goto badkey;
  645. authkeylen = keylen - enckeylen;
  646. if (keylen > TALITOS_MAX_KEY_SIZE)
  647. goto badkey;
  648. memcpy(&ctx->key, key, keylen);
  649. ctx->keylen = keylen;
  650. ctx->enckeylen = enckeylen;
  651. ctx->authkeylen = authkeylen;
  652. return 0;
  653. badkey:
  654. crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
  655. return -EINVAL;
  656. }
  657. /*
  658. * talitos_edesc - s/w-extended descriptor
  659. * @src_nents: number of segments in input scatterlist
  660. * @dst_nents: number of segments in output scatterlist
  661. * @dma_len: length of dma mapped link_tbl space
  662. * @dma_link_tbl: bus physical address of link_tbl
  663. * @desc: h/w descriptor
  664. * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
  665. *
  666. * if decrypting (with authcheck), or either one of src_nents or dst_nents
  667. * is greater than 1, an integrity check value is concatenated to the end
  668. * of link_tbl data
  669. */
  670. struct talitos_edesc {
  671. int src_nents;
  672. int dst_nents;
  673. int src_is_chained;
  674. int dst_is_chained;
  675. int dma_len;
  676. dma_addr_t dma_link_tbl;
  677. struct talitos_desc desc;
  678. struct talitos_ptr link_tbl[0];
  679. };
  680. static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
  681. unsigned int nents, enum dma_data_direction dir,
  682. int chained)
  683. {
  684. if (unlikely(chained))
  685. while (sg) {
  686. dma_map_sg(dev, sg, 1, dir);
  687. sg = scatterwalk_sg_next(sg);
  688. }
  689. else
  690. dma_map_sg(dev, sg, nents, dir);
  691. return nents;
  692. }
  693. static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
  694. enum dma_data_direction dir)
  695. {
  696. while (sg) {
  697. dma_unmap_sg(dev, sg, 1, dir);
  698. sg = scatterwalk_sg_next(sg);
  699. }
  700. }
  701. static void talitos_sg_unmap(struct device *dev,
  702. struct talitos_edesc *edesc,
  703. struct scatterlist *src,
  704. struct scatterlist *dst)
  705. {
  706. unsigned int src_nents = edesc->src_nents ? : 1;
  707. unsigned int dst_nents = edesc->dst_nents ? : 1;
  708. if (src != dst) {
  709. if (edesc->src_is_chained)
  710. talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
  711. else
  712. dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
  713. if (dst) {
  714. if (edesc->dst_is_chained)
  715. talitos_unmap_sg_chain(dev, dst,
  716. DMA_FROM_DEVICE);
  717. else
  718. dma_unmap_sg(dev, dst, dst_nents,
  719. DMA_FROM_DEVICE);
  720. }
  721. } else
  722. if (edesc->src_is_chained)
  723. talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
  724. else
  725. dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
  726. }
  727. static void ipsec_esp_unmap(struct device *dev,
  728. struct talitos_edesc *edesc,
  729. struct aead_request *areq)
  730. {
  731. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
  732. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
  733. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
  734. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
  735. dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
  736. talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
  737. if (edesc->dma_len)
  738. dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
  739. DMA_BIDIRECTIONAL);
  740. }
  741. /*
  742. * ipsec_esp descriptor callbacks
  743. */
  744. static void ipsec_esp_encrypt_done(struct device *dev,
  745. struct talitos_desc *desc, void *context,
  746. int err)
  747. {
  748. struct aead_request *areq = context;
  749. struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
  750. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  751. struct talitos_edesc *edesc;
  752. struct scatterlist *sg;
  753. void *icvdata;
  754. edesc = container_of(desc, struct talitos_edesc, desc);
  755. ipsec_esp_unmap(dev, edesc, areq);
  756. /* copy the generated ICV to dst */
  757. if (edesc->dma_len) {
  758. icvdata = &edesc->link_tbl[edesc->src_nents +
  759. edesc->dst_nents + 2];
  760. sg = sg_last(areq->dst, edesc->dst_nents);
  761. memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
  762. icvdata, ctx->authsize);
  763. }
  764. kfree(edesc);
  765. aead_request_complete(areq, err);
  766. }
  767. static void ipsec_esp_decrypt_swauth_done(struct device *dev,
  768. struct talitos_desc *desc,
  769. void *context, int err)
  770. {
  771. struct aead_request *req = context;
  772. struct crypto_aead *authenc = crypto_aead_reqtfm(req);
  773. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  774. struct talitos_edesc *edesc;
  775. struct scatterlist *sg;
  776. void *icvdata;
  777. edesc = container_of(desc, struct talitos_edesc, desc);
  778. ipsec_esp_unmap(dev, edesc, req);
  779. if (!err) {
  780. /* auth check */
  781. if (edesc->dma_len)
  782. icvdata = &edesc->link_tbl[edesc->src_nents +
  783. edesc->dst_nents + 2];
  784. else
  785. icvdata = &edesc->link_tbl[0];
  786. sg = sg_last(req->dst, edesc->dst_nents ? : 1);
  787. err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
  788. ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
  789. }
  790. kfree(edesc);
  791. aead_request_complete(req, err);
  792. }
  793. static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
  794. struct talitos_desc *desc,
  795. void *context, int err)
  796. {
  797. struct aead_request *req = context;
  798. struct talitos_edesc *edesc;
  799. edesc = container_of(desc, struct talitos_edesc, desc);
  800. ipsec_esp_unmap(dev, edesc, req);
  801. /* check ICV auth status */
  802. if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
  803. DESC_HDR_LO_ICCR1_PASS))
  804. err = -EBADMSG;
  805. kfree(edesc);
  806. aead_request_complete(req, err);
  807. }
  808. /*
  809. * convert scatterlist to SEC h/w link table format
  810. * stop at cryptlen bytes
  811. */
  812. static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
  813. int cryptlen, struct talitos_ptr *link_tbl_ptr)
  814. {
  815. int n_sg = sg_count;
  816. while (n_sg--) {
  817. to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
  818. link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
  819. link_tbl_ptr->j_extent = 0;
  820. link_tbl_ptr++;
  821. cryptlen -= sg_dma_len(sg);
  822. sg = scatterwalk_sg_next(sg);
  823. }
  824. /* adjust (decrease) last one (or two) entry's len to cryptlen */
  825. link_tbl_ptr--;
  826. while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
  827. /* Empty this entry, and move to previous one */
  828. cryptlen += be16_to_cpu(link_tbl_ptr->len);
  829. link_tbl_ptr->len = 0;
  830. sg_count--;
  831. link_tbl_ptr--;
  832. }
  833. link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
  834. + cryptlen);
  835. /* tag end of link table */
  836. link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
  837. return sg_count;
  838. }
  839. /*
  840. * fill in and submit ipsec_esp descriptor
  841. */
  842. static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
  843. u8 *giv, u64 seq,
  844. void (*callback) (struct device *dev,
  845. struct talitos_desc *desc,
  846. void *context, int error))
  847. {
  848. struct crypto_aead *aead = crypto_aead_reqtfm(areq);
  849. struct talitos_ctx *ctx = crypto_aead_ctx(aead);
  850. struct device *dev = ctx->dev;
  851. struct talitos_desc *desc = &edesc->desc;
  852. unsigned int cryptlen = areq->cryptlen;
  853. unsigned int authsize = ctx->authsize;
  854. unsigned int ivsize = crypto_aead_ivsize(aead);
  855. int sg_count, ret;
  856. int sg_link_tbl_len;
  857. /* hmac key */
  858. map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
  859. 0, DMA_TO_DEVICE);
  860. /* hmac data */
  861. map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
  862. sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
  863. /* cipher iv */
  864. map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
  865. DMA_TO_DEVICE);
  866. /* cipher key */
  867. map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
  868. (char *)&ctx->key + ctx->authkeylen, 0,
  869. DMA_TO_DEVICE);
  870. /*
  871. * cipher in
  872. * map and adjust cipher len to aead request cryptlen.
  873. * extent is bytes of HMAC postpended to ciphertext,
  874. * typically 12 for ipsec
  875. */
  876. desc->ptr[4].len = cpu_to_be16(cryptlen);
  877. desc->ptr[4].j_extent = authsize;
  878. sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
  879. (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
  880. : DMA_TO_DEVICE,
  881. edesc->src_is_chained);
  882. if (sg_count == 1) {
  883. to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
  884. } else {
  885. sg_link_tbl_len = cryptlen;
  886. if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
  887. sg_link_tbl_len = cryptlen + authsize;
  888. sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
  889. &edesc->link_tbl[0]);
  890. if (sg_count > 1) {
  891. desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
  892. to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
  893. dma_sync_single_for_device(dev, edesc->dma_link_tbl,
  894. edesc->dma_len,
  895. DMA_BIDIRECTIONAL);
  896. } else {
  897. /* Only one segment now, so no link tbl needed */
  898. to_talitos_ptr(&desc->ptr[4],
  899. sg_dma_address(areq->src));
  900. }
  901. }
  902. /* cipher out */
  903. desc->ptr[5].len = cpu_to_be16(cryptlen);
  904. desc->ptr[5].j_extent = authsize;
  905. if (areq->src != areq->dst)
  906. sg_count = talitos_map_sg(dev, areq->dst,
  907. edesc->dst_nents ? : 1,
  908. DMA_FROM_DEVICE,
  909. edesc->dst_is_chained);
  910. if (sg_count == 1) {
  911. to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
  912. } else {
  913. struct talitos_ptr *link_tbl_ptr =
  914. &edesc->link_tbl[edesc->src_nents + 1];
  915. to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
  916. (edesc->src_nents + 1) *
  917. sizeof(struct talitos_ptr));
  918. sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
  919. link_tbl_ptr);
  920. /* Add an entry to the link table for ICV data */
  921. link_tbl_ptr += sg_count - 1;
  922. link_tbl_ptr->j_extent = 0;
  923. sg_count++;
  924. link_tbl_ptr++;
  925. link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
  926. link_tbl_ptr->len = cpu_to_be16(authsize);
  927. /* icv data follows link tables */
  928. to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
  929. (edesc->src_nents + edesc->dst_nents + 2) *
  930. sizeof(struct talitos_ptr));
  931. desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
  932. dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
  933. edesc->dma_len, DMA_BIDIRECTIONAL);
  934. }
  935. /* iv out */
  936. map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
  937. DMA_FROM_DEVICE);
  938. ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
  939. if (ret != -EINPROGRESS) {
  940. ipsec_esp_unmap(dev, edesc, areq);
  941. kfree(edesc);
  942. }
  943. return ret;
  944. }
  945. /*
  946. * derive number of elements in scatterlist
  947. */
  948. static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
  949. {
  950. struct scatterlist *sg = sg_list;
  951. int sg_nents = 0;
  952. *chained = 0;
  953. while (nbytes > 0) {
  954. sg_nents++;
  955. nbytes -= sg->length;
  956. if (!sg_is_last(sg) && (sg + 1)->length == 0)
  957. *chained = 1;
  958. sg = scatterwalk_sg_next(sg);
  959. }
  960. return sg_nents;
  961. }
  962. /**
  963. * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
  964. * @sgl: The SG list
  965. * @nents: Number of SG entries
  966. * @buf: Where to copy to
  967. * @buflen: The number of bytes to copy
  968. * @skip: The number of bytes to skip before copying.
  969. * Note: skip + buflen should equal SG total size.
  970. *
  971. * Returns the number of copied bytes.
  972. *
  973. **/
  974. static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
  975. void *buf, size_t buflen, unsigned int skip)
  976. {
  977. unsigned int offset = 0;
  978. unsigned int boffset = 0;
  979. struct sg_mapping_iter miter;
  980. unsigned long flags;
  981. unsigned int sg_flags = SG_MITER_ATOMIC;
  982. size_t total_buffer = buflen + skip;
  983. sg_flags |= SG_MITER_FROM_SG;
  984. sg_miter_start(&miter, sgl, nents, sg_flags);
  985. local_irq_save(flags);
  986. while (sg_miter_next(&miter) && offset < total_buffer) {
  987. unsigned int len;
  988. unsigned int ignore;
  989. if ((offset + miter.length) > skip) {
  990. if (offset < skip) {
  991. /* Copy part of this segment */
  992. ignore = skip - offset;
  993. len = miter.length - ignore;
  994. if (boffset + len > buflen)
  995. len = buflen - boffset;
  996. memcpy(buf + boffset, miter.addr + ignore, len);
  997. } else {
  998. /* Copy all of this segment (up to buflen) */
  999. len = miter.length;
  1000. if (boffset + len > buflen)
  1001. len = buflen - boffset;
  1002. memcpy(buf + boffset, miter.addr, len);
  1003. }
  1004. boffset += len;
  1005. }
  1006. offset += miter.length;
  1007. }
  1008. sg_miter_stop(&miter);
  1009. local_irq_restore(flags);
  1010. return boffset;
  1011. }
  1012. /*
  1013. * allocate and map the extended descriptor
  1014. */
  1015. static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
  1016. struct scatterlist *src,
  1017. struct scatterlist *dst,
  1018. int hash_result,
  1019. unsigned int cryptlen,
  1020. unsigned int authsize,
  1021. int icv_stashing,
  1022. u32 cryptoflags)
  1023. {
  1024. struct talitos_edesc *edesc;
  1025. int src_nents, dst_nents, alloc_len, dma_len;
  1026. int src_chained, dst_chained = 0;
  1027. gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
  1028. GFP_ATOMIC;
  1029. if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
  1030. dev_err(dev, "length exceeds h/w max limit\n");
  1031. return ERR_PTR(-EINVAL);
  1032. }
  1033. src_nents = sg_count(src, cryptlen + authsize, &src_chained);
  1034. src_nents = (src_nents == 1) ? 0 : src_nents;
  1035. if (hash_result) {
  1036. dst_nents = 0;
  1037. } else {
  1038. if (dst == src) {
  1039. dst_nents = src_nents;
  1040. } else {
  1041. dst_nents = sg_count(dst, cryptlen + authsize,
  1042. &dst_chained);
  1043. dst_nents = (dst_nents == 1) ? 0 : dst_nents;
  1044. }
  1045. }
  1046. /*
  1047. * allocate space for base edesc plus the link tables,
  1048. * allowing for two separate entries for ICV and generated ICV (+ 2),
  1049. * and the ICV data itself
  1050. */
  1051. alloc_len = sizeof(struct talitos_edesc);
  1052. if (src_nents || dst_nents) {
  1053. dma_len = (src_nents + dst_nents + 2) *
  1054. sizeof(struct talitos_ptr) + authsize;
  1055. alloc_len += dma_len;
  1056. } else {
  1057. dma_len = 0;
  1058. alloc_len += icv_stashing ? authsize : 0;
  1059. }
  1060. edesc = kmalloc(alloc_len, GFP_DMA | flags);
  1061. if (!edesc) {
  1062. dev_err(dev, "could not allocate edescriptor\n");
  1063. return ERR_PTR(-ENOMEM);
  1064. }
  1065. edesc->src_nents = src_nents;
  1066. edesc->dst_nents = dst_nents;
  1067. edesc->src_is_chained = src_chained;
  1068. edesc->dst_is_chained = dst_chained;
  1069. edesc->dma_len = dma_len;
  1070. if (dma_len)
  1071. edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
  1072. edesc->dma_len,
  1073. DMA_BIDIRECTIONAL);
  1074. return edesc;
  1075. }
  1076. static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
  1077. int icv_stashing)
  1078. {
  1079. struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
  1080. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  1081. return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
  1082. areq->cryptlen, ctx->authsize, icv_stashing,
  1083. areq->base.flags);
  1084. }
  1085. static int aead_encrypt(struct aead_request *req)
  1086. {
  1087. struct crypto_aead *authenc = crypto_aead_reqtfm(req);
  1088. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  1089. struct talitos_edesc *edesc;
  1090. /* allocate extended descriptor */
  1091. edesc = aead_edesc_alloc(req, 0);
  1092. if (IS_ERR(edesc))
  1093. return PTR_ERR(edesc);
  1094. /* set encrypt */
  1095. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
  1096. return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
  1097. }
  1098. static int aead_decrypt(struct aead_request *req)
  1099. {
  1100. struct crypto_aead *authenc = crypto_aead_reqtfm(req);
  1101. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  1102. unsigned int authsize = ctx->authsize;
  1103. struct talitos_private *priv = dev_get_drvdata(ctx->dev);
  1104. struct talitos_edesc *edesc;
  1105. struct scatterlist *sg;
  1106. void *icvdata;
  1107. req->cryptlen -= authsize;
  1108. /* allocate extended descriptor */
  1109. edesc = aead_edesc_alloc(req, 1);
  1110. if (IS_ERR(edesc))
  1111. return PTR_ERR(edesc);
  1112. if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
  1113. ((!edesc->src_nents && !edesc->dst_nents) ||
  1114. priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
  1115. /* decrypt and check the ICV */
  1116. edesc->desc.hdr = ctx->desc_hdr_template |
  1117. DESC_HDR_DIR_INBOUND |
  1118. DESC_HDR_MODE1_MDEU_CICV;
  1119. /* reset integrity check result bits */
  1120. edesc->desc.hdr_lo = 0;
  1121. return ipsec_esp(edesc, req, NULL, 0,
  1122. ipsec_esp_decrypt_hwauth_done);
  1123. }
  1124. /* Have to check the ICV with software */
  1125. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
  1126. /* stash incoming ICV for later cmp with ICV generated by the h/w */
  1127. if (edesc->dma_len)
  1128. icvdata = &edesc->link_tbl[edesc->src_nents +
  1129. edesc->dst_nents + 2];
  1130. else
  1131. icvdata = &edesc->link_tbl[0];
  1132. sg = sg_last(req->src, edesc->src_nents ? : 1);
  1133. memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
  1134. ctx->authsize);
  1135. return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
  1136. }
  1137. static int aead_givencrypt(struct aead_givcrypt_request *req)
  1138. {
  1139. struct aead_request *areq = &req->areq;
  1140. struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
  1141. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  1142. struct talitos_edesc *edesc;
  1143. /* allocate extended descriptor */
  1144. edesc = aead_edesc_alloc(areq, 0);
  1145. if (IS_ERR(edesc))
  1146. return PTR_ERR(edesc);
  1147. /* set encrypt */
  1148. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
  1149. memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
  1150. /* avoid consecutive packets going out with same IV */
  1151. *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
  1152. return ipsec_esp(edesc, areq, req->giv, req->seq,
  1153. ipsec_esp_encrypt_done);
  1154. }
  1155. static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
  1156. const u8 *key, unsigned int keylen)
  1157. {
  1158. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1159. memcpy(&ctx->key, key, keylen);
  1160. ctx->keylen = keylen;
  1161. return 0;
  1162. }
  1163. static void common_nonsnoop_unmap(struct device *dev,
  1164. struct talitos_edesc *edesc,
  1165. struct ablkcipher_request *areq)
  1166. {
  1167. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
  1168. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
  1169. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
  1170. talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
  1171. if (edesc->dma_len)
  1172. dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
  1173. DMA_BIDIRECTIONAL);
  1174. }
  1175. static void ablkcipher_done(struct device *dev,
  1176. struct talitos_desc *desc, void *context,
  1177. int err)
  1178. {
  1179. struct ablkcipher_request *areq = context;
  1180. struct talitos_edesc *edesc;
  1181. edesc = container_of(desc, struct talitos_edesc, desc);
  1182. common_nonsnoop_unmap(dev, edesc, areq);
  1183. kfree(edesc);
  1184. areq->base.complete(&areq->base, err);
  1185. }
  1186. static int common_nonsnoop(struct talitos_edesc *edesc,
  1187. struct ablkcipher_request *areq,
  1188. void (*callback) (struct device *dev,
  1189. struct talitos_desc *desc,
  1190. void *context, int error))
  1191. {
  1192. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  1193. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1194. struct device *dev = ctx->dev;
  1195. struct talitos_desc *desc = &edesc->desc;
  1196. unsigned int cryptlen = areq->nbytes;
  1197. unsigned int ivsize;
  1198. int sg_count, ret;
  1199. /* first DWORD empty */
  1200. desc->ptr[0].len = 0;
  1201. to_talitos_ptr(&desc->ptr[0], 0);
  1202. desc->ptr[0].j_extent = 0;
  1203. /* cipher iv */
  1204. ivsize = crypto_ablkcipher_ivsize(cipher);
  1205. map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, areq->info, 0,
  1206. DMA_TO_DEVICE);
  1207. /* cipher key */
  1208. map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
  1209. (char *)&ctx->key, 0, DMA_TO_DEVICE);
  1210. /*
  1211. * cipher in
  1212. */
  1213. desc->ptr[3].len = cpu_to_be16(cryptlen);
  1214. desc->ptr[3].j_extent = 0;
  1215. sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
  1216. (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
  1217. : DMA_TO_DEVICE,
  1218. edesc->src_is_chained);
  1219. if (sg_count == 1) {
  1220. to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
  1221. } else {
  1222. sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
  1223. &edesc->link_tbl[0]);
  1224. if (sg_count > 1) {
  1225. to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
  1226. desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
  1227. dma_sync_single_for_device(dev, edesc->dma_link_tbl,
  1228. edesc->dma_len,
  1229. DMA_BIDIRECTIONAL);
  1230. } else {
  1231. /* Only one segment now, so no link tbl needed */
  1232. to_talitos_ptr(&desc->ptr[3],
  1233. sg_dma_address(areq->src));
  1234. }
  1235. }
  1236. /* cipher out */
  1237. desc->ptr[4].len = cpu_to_be16(cryptlen);
  1238. desc->ptr[4].j_extent = 0;
  1239. if (areq->src != areq->dst)
  1240. sg_count = talitos_map_sg(dev, areq->dst,
  1241. edesc->dst_nents ? : 1,
  1242. DMA_FROM_DEVICE,
  1243. edesc->dst_is_chained);
  1244. if (sg_count == 1) {
  1245. to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
  1246. } else {
  1247. struct talitos_ptr *link_tbl_ptr =
  1248. &edesc->link_tbl[edesc->src_nents + 1];
  1249. to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
  1250. (edesc->src_nents + 1) *
  1251. sizeof(struct talitos_ptr));
  1252. desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
  1253. sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
  1254. link_tbl_ptr);
  1255. dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
  1256. edesc->dma_len, DMA_BIDIRECTIONAL);
  1257. }
  1258. /* iv out */
  1259. map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
  1260. DMA_FROM_DEVICE);
  1261. /* last DWORD empty */
  1262. desc->ptr[6].len = 0;
  1263. to_talitos_ptr(&desc->ptr[6], 0);
  1264. desc->ptr[6].j_extent = 0;
  1265. ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
  1266. if (ret != -EINPROGRESS) {
  1267. common_nonsnoop_unmap(dev, edesc, areq);
  1268. kfree(edesc);
  1269. }
  1270. return ret;
  1271. }
  1272. static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
  1273. areq)
  1274. {
  1275. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  1276. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1277. return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
  1278. areq->nbytes, 0, 0, areq->base.flags);
  1279. }
  1280. static int ablkcipher_encrypt(struct ablkcipher_request *areq)
  1281. {
  1282. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  1283. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1284. struct talitos_edesc *edesc;
  1285. /* allocate extended descriptor */
  1286. edesc = ablkcipher_edesc_alloc(areq);
  1287. if (IS_ERR(edesc))
  1288. return PTR_ERR(edesc);
  1289. /* set encrypt */
  1290. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
  1291. return common_nonsnoop(edesc, areq, ablkcipher_done);
  1292. }
  1293. static int ablkcipher_decrypt(struct ablkcipher_request *areq)
  1294. {
  1295. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  1296. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1297. struct talitos_edesc *edesc;
  1298. /* allocate extended descriptor */
  1299. edesc = ablkcipher_edesc_alloc(areq);
  1300. if (IS_ERR(edesc))
  1301. return PTR_ERR(edesc);
  1302. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
  1303. return common_nonsnoop(edesc, areq, ablkcipher_done);
  1304. }
  1305. static void common_nonsnoop_hash_unmap(struct device *dev,
  1306. struct talitos_edesc *edesc,
  1307. struct ahash_request *areq)
  1308. {
  1309. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1310. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
  1311. /* When using hashctx-in, must unmap it. */
  1312. if (edesc->desc.ptr[1].len)
  1313. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
  1314. DMA_TO_DEVICE);
  1315. if (edesc->desc.ptr[2].len)
  1316. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
  1317. DMA_TO_DEVICE);
  1318. talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
  1319. if (edesc->dma_len)
  1320. dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
  1321. DMA_BIDIRECTIONAL);
  1322. }
  1323. static void ahash_done(struct device *dev,
  1324. struct talitos_desc *desc, void *context,
  1325. int err)
  1326. {
  1327. struct ahash_request *areq = context;
  1328. struct talitos_edesc *edesc =
  1329. container_of(desc, struct talitos_edesc, desc);
  1330. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1331. if (!req_ctx->last && req_ctx->to_hash_later) {
  1332. /* Position any partial block for next update/final/finup */
  1333. memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
  1334. req_ctx->nbuf = req_ctx->to_hash_later;
  1335. }
  1336. common_nonsnoop_hash_unmap(dev, edesc, areq);
  1337. kfree(edesc);
  1338. areq->base.complete(&areq->base, err);
  1339. }
  1340. static int common_nonsnoop_hash(struct talitos_edesc *edesc,
  1341. struct ahash_request *areq, unsigned int length,
  1342. void (*callback) (struct device *dev,
  1343. struct talitos_desc *desc,
  1344. void *context, int error))
  1345. {
  1346. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  1347. struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
  1348. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1349. struct device *dev = ctx->dev;
  1350. struct talitos_desc *desc = &edesc->desc;
  1351. int sg_count, ret;
  1352. /* first DWORD empty */
  1353. desc->ptr[0] = zero_entry;
  1354. /* hash context in */
  1355. if (!req_ctx->first || req_ctx->swinit) {
  1356. map_single_talitos_ptr(dev, &desc->ptr[1],
  1357. req_ctx->hw_context_size,
  1358. (char *)req_ctx->hw_context, 0,
  1359. DMA_TO_DEVICE);
  1360. req_ctx->swinit = 0;
  1361. } else {
  1362. desc->ptr[1] = zero_entry;
  1363. /* Indicate next op is not the first. */
  1364. req_ctx->first = 0;
  1365. }
  1366. /* HMAC key */
  1367. if (ctx->keylen)
  1368. map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
  1369. (char *)&ctx->key, 0, DMA_TO_DEVICE);
  1370. else
  1371. desc->ptr[2] = zero_entry;
  1372. /*
  1373. * data in
  1374. */
  1375. desc->ptr[3].len = cpu_to_be16(length);
  1376. desc->ptr[3].j_extent = 0;
  1377. sg_count = talitos_map_sg(dev, req_ctx->psrc,
  1378. edesc->src_nents ? : 1,
  1379. DMA_TO_DEVICE,
  1380. edesc->src_is_chained);
  1381. if (sg_count == 1) {
  1382. to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
  1383. } else {
  1384. sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
  1385. &edesc->link_tbl[0]);
  1386. if (sg_count > 1) {
  1387. desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
  1388. to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
  1389. dma_sync_single_for_device(ctx->dev,
  1390. edesc->dma_link_tbl,
  1391. edesc->dma_len,
  1392. DMA_BIDIRECTIONAL);
  1393. } else {
  1394. /* Only one segment now, so no link tbl needed */
  1395. to_talitos_ptr(&desc->ptr[3],
  1396. sg_dma_address(req_ctx->psrc));
  1397. }
  1398. }
  1399. /* fifth DWORD empty */
  1400. desc->ptr[4] = zero_entry;
  1401. /* hash/HMAC out -or- hash context out */
  1402. if (req_ctx->last)
  1403. map_single_talitos_ptr(dev, &desc->ptr[5],
  1404. crypto_ahash_digestsize(tfm),
  1405. areq->result, 0, DMA_FROM_DEVICE);
  1406. else
  1407. map_single_talitos_ptr(dev, &desc->ptr[5],
  1408. req_ctx->hw_context_size,
  1409. req_ctx->hw_context, 0, DMA_FROM_DEVICE);
  1410. /* last DWORD empty */
  1411. desc->ptr[6] = zero_entry;
  1412. ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
  1413. if (ret != -EINPROGRESS) {
  1414. common_nonsnoop_hash_unmap(dev, edesc, areq);
  1415. kfree(edesc);
  1416. }
  1417. return ret;
  1418. }
  1419. static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
  1420. unsigned int nbytes)
  1421. {
  1422. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  1423. struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
  1424. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1425. return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, 1,
  1426. nbytes, 0, 0, areq->base.flags);
  1427. }
  1428. static int ahash_init(struct ahash_request *areq)
  1429. {
  1430. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  1431. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1432. /* Initialize the context */
  1433. req_ctx->nbuf = 0;
  1434. req_ctx->first = 1; /* first indicates h/w must init its context */
  1435. req_ctx->swinit = 0; /* assume h/w init of context */
  1436. req_ctx->hw_context_size =
  1437. (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
  1438. ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
  1439. : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
  1440. return 0;
  1441. }
  1442. /*
  1443. * on h/w without explicit sha224 support, we initialize h/w context
  1444. * manually with sha224 constants, and tell it to run sha256.
  1445. */
  1446. static int ahash_init_sha224_swinit(struct ahash_request *areq)
  1447. {
  1448. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1449. ahash_init(areq);
  1450. req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
  1451. req_ctx->hw_context[0] = SHA224_H0;
  1452. req_ctx->hw_context[1] = SHA224_H1;
  1453. req_ctx->hw_context[2] = SHA224_H2;
  1454. req_ctx->hw_context[3] = SHA224_H3;
  1455. req_ctx->hw_context[4] = SHA224_H4;
  1456. req_ctx->hw_context[5] = SHA224_H5;
  1457. req_ctx->hw_context[6] = SHA224_H6;
  1458. req_ctx->hw_context[7] = SHA224_H7;
  1459. /* init 64-bit count */
  1460. req_ctx->hw_context[8] = 0;
  1461. req_ctx->hw_context[9] = 0;
  1462. return 0;
  1463. }
  1464. static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
  1465. {
  1466. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  1467. struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
  1468. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1469. struct talitos_edesc *edesc;
  1470. unsigned int blocksize =
  1471. crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
  1472. unsigned int nbytes_to_hash;
  1473. unsigned int to_hash_later;
  1474. unsigned int nsg;
  1475. int chained;
  1476. if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
  1477. /* Buffer up to one whole block */
  1478. sg_copy_to_buffer(areq->src,
  1479. sg_count(areq->src, nbytes, &chained),
  1480. req_ctx->buf + req_ctx->nbuf, nbytes);
  1481. req_ctx->nbuf += nbytes;
  1482. return 0;
  1483. }
  1484. /* At least (blocksize + 1) bytes are available to hash */
  1485. nbytes_to_hash = nbytes + req_ctx->nbuf;
  1486. to_hash_later = nbytes_to_hash & (blocksize - 1);
  1487. if (req_ctx->last)
  1488. to_hash_later = 0;
  1489. else if (to_hash_later)
  1490. /* There is a partial block. Hash the full block(s) now */
  1491. nbytes_to_hash -= to_hash_later;
  1492. else {
  1493. /* Keep one block buffered */
  1494. nbytes_to_hash -= blocksize;
  1495. to_hash_later = blocksize;
  1496. }
  1497. /* Chain in any previously buffered data */
  1498. if (req_ctx->nbuf) {
  1499. nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
  1500. sg_init_table(req_ctx->bufsl, nsg);
  1501. sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
  1502. if (nsg > 1)
  1503. scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
  1504. req_ctx->psrc = req_ctx->bufsl;
  1505. } else
  1506. req_ctx->psrc = areq->src;
  1507. if (to_hash_later) {
  1508. int nents = sg_count(areq->src, nbytes, &chained);
  1509. sg_copy_end_to_buffer(areq->src, nents,
  1510. req_ctx->bufnext,
  1511. to_hash_later,
  1512. nbytes - to_hash_later);
  1513. }
  1514. req_ctx->to_hash_later = to_hash_later;
  1515. /* Allocate extended descriptor */
  1516. edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
  1517. if (IS_ERR(edesc))
  1518. return PTR_ERR(edesc);
  1519. edesc->desc.hdr = ctx->desc_hdr_template;
  1520. /* On last one, request SEC to pad; otherwise continue */
  1521. if (req_ctx->last)
  1522. edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
  1523. else
  1524. edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
  1525. /* request SEC to INIT hash. */
  1526. if (req_ctx->first && !req_ctx->swinit)
  1527. edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
  1528. /* When the tfm context has a keylen, it's an HMAC.
  1529. * A first or last (ie. not middle) descriptor must request HMAC.
  1530. */
  1531. if (ctx->keylen && (req_ctx->first || req_ctx->last))
  1532. edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
  1533. return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
  1534. ahash_done);
  1535. }
  1536. static int ahash_update(struct ahash_request *areq)
  1537. {
  1538. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1539. req_ctx->last = 0;
  1540. return ahash_process_req(areq, areq->nbytes);
  1541. }
  1542. static int ahash_final(struct ahash_request *areq)
  1543. {
  1544. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1545. req_ctx->last = 1;
  1546. return ahash_process_req(areq, 0);
  1547. }
  1548. static int ahash_finup(struct ahash_request *areq)
  1549. {
  1550. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1551. req_ctx->last = 1;
  1552. return ahash_process_req(areq, areq->nbytes);
  1553. }
  1554. static int ahash_digest(struct ahash_request *areq)
  1555. {
  1556. struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
  1557. struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
  1558. ahash->init(areq);
  1559. req_ctx->last = 1;
  1560. return ahash_process_req(areq, areq->nbytes);
  1561. }
  1562. struct talitos_alg_template {
  1563. u32 type;
  1564. union {
  1565. struct crypto_alg crypto;
  1566. struct ahash_alg hash;
  1567. } alg;
  1568. __be32 desc_hdr_template;
  1569. };
  1570. static struct talitos_alg_template driver_algs[] = {
  1571. /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
  1572. { .type = CRYPTO_ALG_TYPE_AEAD,
  1573. .alg.crypto = {
  1574. .cra_name = "authenc(hmac(sha1),cbc(aes))",
  1575. .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
  1576. .cra_blocksize = AES_BLOCK_SIZE,
  1577. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1578. .cra_type = &crypto_aead_type,
  1579. .cra_aead = {
  1580. .setkey = aead_setkey,
  1581. .setauthsize = aead_setauthsize,
  1582. .encrypt = aead_encrypt,
  1583. .decrypt = aead_decrypt,
  1584. .givencrypt = aead_givencrypt,
  1585. .geniv = "<built-in>",
  1586. .ivsize = AES_BLOCK_SIZE,
  1587. .maxauthsize = SHA1_DIGEST_SIZE,
  1588. }
  1589. },
  1590. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1591. DESC_HDR_SEL0_AESU |
  1592. DESC_HDR_MODE0_AESU_CBC |
  1593. DESC_HDR_SEL1_MDEUA |
  1594. DESC_HDR_MODE1_MDEU_INIT |
  1595. DESC_HDR_MODE1_MDEU_PAD |
  1596. DESC_HDR_MODE1_MDEU_SHA1_HMAC,
  1597. },
  1598. { .type = CRYPTO_ALG_TYPE_AEAD,
  1599. .alg.crypto = {
  1600. .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
  1601. .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
  1602. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1603. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1604. .cra_type = &crypto_aead_type,
  1605. .cra_aead = {
  1606. .setkey = aead_setkey,
  1607. .setauthsize = aead_setauthsize,
  1608. .encrypt = aead_encrypt,
  1609. .decrypt = aead_decrypt,
  1610. .givencrypt = aead_givencrypt,
  1611. .geniv = "<built-in>",
  1612. .ivsize = DES3_EDE_BLOCK_SIZE,
  1613. .maxauthsize = SHA1_DIGEST_SIZE,
  1614. }
  1615. },
  1616. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1617. DESC_HDR_SEL0_DEU |
  1618. DESC_HDR_MODE0_DEU_CBC |
  1619. DESC_HDR_MODE0_DEU_3DES |
  1620. DESC_HDR_SEL1_MDEUA |
  1621. DESC_HDR_MODE1_MDEU_INIT |
  1622. DESC_HDR_MODE1_MDEU_PAD |
  1623. DESC_HDR_MODE1_MDEU_SHA1_HMAC,
  1624. },
  1625. { .type = CRYPTO_ALG_TYPE_AEAD,
  1626. .alg.crypto = {
  1627. .cra_name = "authenc(hmac(sha256),cbc(aes))",
  1628. .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
  1629. .cra_blocksize = AES_BLOCK_SIZE,
  1630. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1631. .cra_type = &crypto_aead_type,
  1632. .cra_aead = {
  1633. .setkey = aead_setkey,
  1634. .setauthsize = aead_setauthsize,
  1635. .encrypt = aead_encrypt,
  1636. .decrypt = aead_decrypt,
  1637. .givencrypt = aead_givencrypt,
  1638. .geniv = "<built-in>",
  1639. .ivsize = AES_BLOCK_SIZE,
  1640. .maxauthsize = SHA256_DIGEST_SIZE,
  1641. }
  1642. },
  1643. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1644. DESC_HDR_SEL0_AESU |
  1645. DESC_HDR_MODE0_AESU_CBC |
  1646. DESC_HDR_SEL1_MDEUA |
  1647. DESC_HDR_MODE1_MDEU_INIT |
  1648. DESC_HDR_MODE1_MDEU_PAD |
  1649. DESC_HDR_MODE1_MDEU_SHA256_HMAC,
  1650. },
  1651. { .type = CRYPTO_ALG_TYPE_AEAD,
  1652. .alg.crypto = {
  1653. .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
  1654. .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
  1655. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1656. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1657. .cra_type = &crypto_aead_type,
  1658. .cra_aead = {
  1659. .setkey = aead_setkey,
  1660. .setauthsize = aead_setauthsize,
  1661. .encrypt = aead_encrypt,
  1662. .decrypt = aead_decrypt,
  1663. .givencrypt = aead_givencrypt,
  1664. .geniv = "<built-in>",
  1665. .ivsize = DES3_EDE_BLOCK_SIZE,
  1666. .maxauthsize = SHA256_DIGEST_SIZE,
  1667. }
  1668. },
  1669. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1670. DESC_HDR_SEL0_DEU |
  1671. DESC_HDR_MODE0_DEU_CBC |
  1672. DESC_HDR_MODE0_DEU_3DES |
  1673. DESC_HDR_SEL1_MDEUA |
  1674. DESC_HDR_MODE1_MDEU_INIT |
  1675. DESC_HDR_MODE1_MDEU_PAD |
  1676. DESC_HDR_MODE1_MDEU_SHA256_HMAC,
  1677. },
  1678. { .type = CRYPTO_ALG_TYPE_AEAD,
  1679. .alg.crypto = {
  1680. .cra_name = "authenc(hmac(md5),cbc(aes))",
  1681. .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
  1682. .cra_blocksize = AES_BLOCK_SIZE,
  1683. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1684. .cra_type = &crypto_aead_type,
  1685. .cra_aead = {
  1686. .setkey = aead_setkey,
  1687. .setauthsize = aead_setauthsize,
  1688. .encrypt = aead_encrypt,
  1689. .decrypt = aead_decrypt,
  1690. .givencrypt = aead_givencrypt,
  1691. .geniv = "<built-in>",
  1692. .ivsize = AES_BLOCK_SIZE,
  1693. .maxauthsize = MD5_DIGEST_SIZE,
  1694. }
  1695. },
  1696. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1697. DESC_HDR_SEL0_AESU |
  1698. DESC_HDR_MODE0_AESU_CBC |
  1699. DESC_HDR_SEL1_MDEUA |
  1700. DESC_HDR_MODE1_MDEU_INIT |
  1701. DESC_HDR_MODE1_MDEU_PAD |
  1702. DESC_HDR_MODE1_MDEU_MD5_HMAC,
  1703. },
  1704. { .type = CRYPTO_ALG_TYPE_AEAD,
  1705. .alg.crypto = {
  1706. .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
  1707. .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
  1708. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1709. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1710. .cra_type = &crypto_aead_type,
  1711. .cra_aead = {
  1712. .setkey = aead_setkey,
  1713. .setauthsize = aead_setauthsize,
  1714. .encrypt = aead_encrypt,
  1715. .decrypt = aead_decrypt,
  1716. .givencrypt = aead_givencrypt,
  1717. .geniv = "<built-in>",
  1718. .ivsize = DES3_EDE_BLOCK_SIZE,
  1719. .maxauthsize = MD5_DIGEST_SIZE,
  1720. }
  1721. },
  1722. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1723. DESC_HDR_SEL0_DEU |
  1724. DESC_HDR_MODE0_DEU_CBC |
  1725. DESC_HDR_MODE0_DEU_3DES |
  1726. DESC_HDR_SEL1_MDEUA |
  1727. DESC_HDR_MODE1_MDEU_INIT |
  1728. DESC_HDR_MODE1_MDEU_PAD |
  1729. DESC_HDR_MODE1_MDEU_MD5_HMAC,
  1730. },
  1731. /* ABLKCIPHER algorithms. */
  1732. { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1733. .alg.crypto = {
  1734. .cra_name = "cbc(aes)",
  1735. .cra_driver_name = "cbc-aes-talitos",
  1736. .cra_blocksize = AES_BLOCK_SIZE,
  1737. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1738. CRYPTO_ALG_ASYNC,
  1739. .cra_type = &crypto_ablkcipher_type,
  1740. .cra_ablkcipher = {
  1741. .setkey = ablkcipher_setkey,
  1742. .encrypt = ablkcipher_encrypt,
  1743. .decrypt = ablkcipher_decrypt,
  1744. .geniv = "eseqiv",
  1745. .min_keysize = AES_MIN_KEY_SIZE,
  1746. .max_keysize = AES_MAX_KEY_SIZE,
  1747. .ivsize = AES_BLOCK_SIZE,
  1748. }
  1749. },
  1750. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1751. DESC_HDR_SEL0_AESU |
  1752. DESC_HDR_MODE0_AESU_CBC,
  1753. },
  1754. { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1755. .alg.crypto = {
  1756. .cra_name = "cbc(des3_ede)",
  1757. .cra_driver_name = "cbc-3des-talitos",
  1758. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1759. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1760. CRYPTO_ALG_ASYNC,
  1761. .cra_type = &crypto_ablkcipher_type,
  1762. .cra_ablkcipher = {
  1763. .setkey = ablkcipher_setkey,
  1764. .encrypt = ablkcipher_encrypt,
  1765. .decrypt = ablkcipher_decrypt,
  1766. .geniv = "eseqiv",
  1767. .min_keysize = DES3_EDE_KEY_SIZE,
  1768. .max_keysize = DES3_EDE_KEY_SIZE,
  1769. .ivsize = DES3_EDE_BLOCK_SIZE,
  1770. }
  1771. },
  1772. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1773. DESC_HDR_SEL0_DEU |
  1774. DESC_HDR_MODE0_DEU_CBC |
  1775. DESC_HDR_MODE0_DEU_3DES,
  1776. },
  1777. /* AHASH algorithms. */
  1778. { .type = CRYPTO_ALG_TYPE_AHASH,
  1779. .alg.hash = {
  1780. .init = ahash_init,
  1781. .update = ahash_update,
  1782. .final = ahash_final,
  1783. .finup = ahash_finup,
  1784. .digest = ahash_digest,
  1785. .halg.digestsize = MD5_DIGEST_SIZE,
  1786. .halg.base = {
  1787. .cra_name = "md5",
  1788. .cra_driver_name = "md5-talitos",
  1789. .cra_blocksize = MD5_BLOCK_SIZE,
  1790. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1791. CRYPTO_ALG_ASYNC,
  1792. .cra_type = &crypto_ahash_type
  1793. }
  1794. },
  1795. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1796. DESC_HDR_SEL0_MDEUA |
  1797. DESC_HDR_MODE0_MDEU_MD5,
  1798. },
  1799. { .type = CRYPTO_ALG_TYPE_AHASH,
  1800. .alg.hash = {
  1801. .init = ahash_init,
  1802. .update = ahash_update,
  1803. .final = ahash_final,
  1804. .finup = ahash_finup,
  1805. .digest = ahash_digest,
  1806. .halg.digestsize = SHA1_DIGEST_SIZE,
  1807. .halg.base = {
  1808. .cra_name = "sha1",
  1809. .cra_driver_name = "sha1-talitos",
  1810. .cra_blocksize = SHA1_BLOCK_SIZE,
  1811. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1812. CRYPTO_ALG_ASYNC,
  1813. .cra_type = &crypto_ahash_type
  1814. }
  1815. },
  1816. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1817. DESC_HDR_SEL0_MDEUA |
  1818. DESC_HDR_MODE0_MDEU_SHA1,
  1819. },
  1820. { .type = CRYPTO_ALG_TYPE_AHASH,
  1821. .alg.hash = {
  1822. .init = ahash_init,
  1823. .update = ahash_update,
  1824. .final = ahash_final,
  1825. .finup = ahash_finup,
  1826. .digest = ahash_digest,
  1827. .halg.digestsize = SHA224_DIGEST_SIZE,
  1828. .halg.base = {
  1829. .cra_name = "sha224",
  1830. .cra_driver_name = "sha224-talitos",
  1831. .cra_blocksize = SHA224_BLOCK_SIZE,
  1832. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1833. CRYPTO_ALG_ASYNC,
  1834. .cra_type = &crypto_ahash_type
  1835. }
  1836. },
  1837. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1838. DESC_HDR_SEL0_MDEUA |
  1839. DESC_HDR_MODE0_MDEU_SHA224,
  1840. },
  1841. { .type = CRYPTO_ALG_TYPE_AHASH,
  1842. .alg.hash = {
  1843. .init = ahash_init,
  1844. .update = ahash_update,
  1845. .final = ahash_final,
  1846. .finup = ahash_finup,
  1847. .digest = ahash_digest,
  1848. .halg.digestsize = SHA256_DIGEST_SIZE,
  1849. .halg.base = {
  1850. .cra_name = "sha256",
  1851. .cra_driver_name = "sha256-talitos",
  1852. .cra_blocksize = SHA256_BLOCK_SIZE,
  1853. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1854. CRYPTO_ALG_ASYNC,
  1855. .cra_type = &crypto_ahash_type
  1856. }
  1857. },
  1858. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1859. DESC_HDR_SEL0_MDEUA |
  1860. DESC_HDR_MODE0_MDEU_SHA256,
  1861. },
  1862. { .type = CRYPTO_ALG_TYPE_AHASH,
  1863. .alg.hash = {
  1864. .init = ahash_init,
  1865. .update = ahash_update,
  1866. .final = ahash_final,
  1867. .finup = ahash_finup,
  1868. .digest = ahash_digest,
  1869. .halg.digestsize = SHA384_DIGEST_SIZE,
  1870. .halg.base = {
  1871. .cra_name = "sha384",
  1872. .cra_driver_name = "sha384-talitos",
  1873. .cra_blocksize = SHA384_BLOCK_SIZE,
  1874. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1875. CRYPTO_ALG_ASYNC,
  1876. .cra_type = &crypto_ahash_type
  1877. }
  1878. },
  1879. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1880. DESC_HDR_SEL0_MDEUB |
  1881. DESC_HDR_MODE0_MDEUB_SHA384,
  1882. },
  1883. { .type = CRYPTO_ALG_TYPE_AHASH,
  1884. .alg.hash = {
  1885. .init = ahash_init,
  1886. .update = ahash_update,
  1887. .final = ahash_final,
  1888. .finup = ahash_finup,
  1889. .digest = ahash_digest,
  1890. .halg.digestsize = SHA512_DIGEST_SIZE,
  1891. .halg.base = {
  1892. .cra_name = "sha512",
  1893. .cra_driver_name = "sha512-talitos",
  1894. .cra_blocksize = SHA512_BLOCK_SIZE,
  1895. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1896. CRYPTO_ALG_ASYNC,
  1897. .cra_type = &crypto_ahash_type
  1898. }
  1899. },
  1900. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1901. DESC_HDR_SEL0_MDEUB |
  1902. DESC_HDR_MODE0_MDEUB_SHA512,
  1903. },
  1904. };
  1905. struct talitos_crypto_alg {
  1906. struct list_head entry;
  1907. struct device *dev;
  1908. struct talitos_alg_template algt;
  1909. };
  1910. static int talitos_cra_init(struct crypto_tfm *tfm)
  1911. {
  1912. struct crypto_alg *alg = tfm->__crt_alg;
  1913. struct talitos_crypto_alg *talitos_alg;
  1914. struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
  1915. struct talitos_private *priv;
  1916. if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
  1917. talitos_alg = container_of(__crypto_ahash_alg(alg),
  1918. struct talitos_crypto_alg,
  1919. algt.alg.hash);
  1920. else
  1921. talitos_alg = container_of(alg, struct talitos_crypto_alg,
  1922. algt.alg.crypto);
  1923. /* update context with ptr to dev */
  1924. ctx->dev = talitos_alg->dev;
  1925. /* assign SEC channel to tfm in round-robin fashion */
  1926. priv = dev_get_drvdata(ctx->dev);
  1927. ctx->ch = atomic_inc_return(&priv->last_chan) &
  1928. (priv->num_channels - 1);
  1929. /* copy descriptor header template value */
  1930. ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
  1931. /* select done notification */
  1932. ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
  1933. return 0;
  1934. }
  1935. static int talitos_cra_init_aead(struct crypto_tfm *tfm)
  1936. {
  1937. struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
  1938. talitos_cra_init(tfm);
  1939. /* random first IV */
  1940. get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
  1941. return 0;
  1942. }
  1943. static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
  1944. {
  1945. struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
  1946. talitos_cra_init(tfm);
  1947. ctx->keylen = 0;
  1948. crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
  1949. sizeof(struct talitos_ahash_req_ctx));
  1950. return 0;
  1951. }
  1952. /*
  1953. * given the alg's descriptor header template, determine whether descriptor
  1954. * type and primary/secondary execution units required match the hw
  1955. * capabilities description provided in the device tree node.
  1956. */
  1957. static int hw_supports(struct device *dev, __be32 desc_hdr_template)
  1958. {
  1959. struct talitos_private *priv = dev_get_drvdata(dev);
  1960. int ret;
  1961. ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
  1962. (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
  1963. if (SECONDARY_EU(desc_hdr_template))
  1964. ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
  1965. & priv->exec_units);
  1966. return ret;
  1967. }
  1968. static int talitos_remove(struct platform_device *ofdev)
  1969. {
  1970. struct device *dev = &ofdev->dev;
  1971. struct talitos_private *priv = dev_get_drvdata(dev);
  1972. struct talitos_crypto_alg *t_alg, *n;
  1973. int i;
  1974. list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
  1975. switch (t_alg->algt.type) {
  1976. case CRYPTO_ALG_TYPE_ABLKCIPHER:
  1977. case CRYPTO_ALG_TYPE_AEAD:
  1978. crypto_unregister_alg(&t_alg->algt.alg.crypto);
  1979. break;
  1980. case CRYPTO_ALG_TYPE_AHASH:
  1981. crypto_unregister_ahash(&t_alg->algt.alg.hash);
  1982. break;
  1983. }
  1984. list_del(&t_alg->entry);
  1985. kfree(t_alg);
  1986. }
  1987. if (hw_supports(dev, DESC_HDR_SEL0_RNG))
  1988. talitos_unregister_rng(dev);
  1989. for (i = 0; i < priv->num_channels; i++)
  1990. kfree(priv->chan[i].fifo);
  1991. kfree(priv->chan);
  1992. if (priv->irq != NO_IRQ) {
  1993. free_irq(priv->irq, dev);
  1994. irq_dispose_mapping(priv->irq);
  1995. }
  1996. tasklet_kill(&priv->done_task);
  1997. iounmap(priv->reg);
  1998. dev_set_drvdata(dev, NULL);
  1999. kfree(priv);
  2000. return 0;
  2001. }
  2002. static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
  2003. struct talitos_alg_template
  2004. *template)
  2005. {
  2006. struct talitos_private *priv = dev_get_drvdata(dev);
  2007. struct talitos_crypto_alg *t_alg;
  2008. struct crypto_alg *alg;
  2009. t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
  2010. if (!t_alg)
  2011. return ERR_PTR(-ENOMEM);
  2012. t_alg->algt = *template;
  2013. switch (t_alg->algt.type) {
  2014. case CRYPTO_ALG_TYPE_ABLKCIPHER:
  2015. alg = &t_alg->algt.alg.crypto;
  2016. alg->cra_init = talitos_cra_init;
  2017. break;
  2018. case CRYPTO_ALG_TYPE_AEAD:
  2019. alg = &t_alg->algt.alg.crypto;
  2020. alg->cra_init = talitos_cra_init_aead;
  2021. break;
  2022. case CRYPTO_ALG_TYPE_AHASH:
  2023. alg = &t_alg->algt.alg.hash.halg.base;
  2024. alg->cra_init = talitos_cra_init_ahash;
  2025. if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
  2026. !strcmp(alg->cra_name, "sha224")) {
  2027. t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
  2028. t_alg->algt.desc_hdr_template =
  2029. DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  2030. DESC_HDR_SEL0_MDEUA |
  2031. DESC_HDR_MODE0_MDEU_SHA256;
  2032. }
  2033. break;
  2034. default:
  2035. dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
  2036. return ERR_PTR(-EINVAL);
  2037. }
  2038. alg->cra_module = THIS_MODULE;
  2039. alg->cra_priority = TALITOS_CRA_PRIORITY;
  2040. alg->cra_alignmask = 0;
  2041. alg->cra_ctxsize = sizeof(struct talitos_ctx);
  2042. t_alg->dev = dev;
  2043. return t_alg;
  2044. }
  2045. static int talitos_probe(struct platform_device *ofdev)
  2046. {
  2047. struct device *dev = &ofdev->dev;
  2048. struct device_node *np = ofdev->dev.of_node;
  2049. struct talitos_private *priv;
  2050. const unsigned int *prop;
  2051. int i, err;
  2052. priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
  2053. if (!priv)
  2054. return -ENOMEM;
  2055. dev_set_drvdata(dev, priv);
  2056. priv->ofdev = ofdev;
  2057. tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
  2058. INIT_LIST_HEAD(&priv->alg_list);
  2059. priv->irq = irq_of_parse_and_map(np, 0);
  2060. if (priv->irq == NO_IRQ) {
  2061. dev_err(dev, "failed to map irq\n");
  2062. err = -EINVAL;
  2063. goto err_out;
  2064. }
  2065. /* get the irq line */
  2066. err = request_irq(priv->irq, talitos_interrupt, 0,
  2067. dev_driver_string(dev), dev);
  2068. if (err) {
  2069. dev_err(dev, "failed to request irq %d\n", priv->irq);
  2070. irq_dispose_mapping(priv->irq);
  2071. priv->irq = NO_IRQ;
  2072. goto err_out;
  2073. }
  2074. priv->reg = of_iomap(np, 0);
  2075. if (!priv->reg) {
  2076. dev_err(dev, "failed to of_iomap\n");
  2077. err = -ENOMEM;
  2078. goto err_out;
  2079. }
  2080. /* get SEC version capabilities from device tree */
  2081. prop = of_get_property(np, "fsl,num-channels", NULL);
  2082. if (prop)
  2083. priv->num_channels = *prop;
  2084. prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
  2085. if (prop)
  2086. priv->chfifo_len = *prop;
  2087. prop = of_get_property(np, "fsl,exec-units-mask", NULL);
  2088. if (prop)
  2089. priv->exec_units = *prop;
  2090. prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
  2091. if (prop)
  2092. priv->desc_types = *prop;
  2093. if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
  2094. !priv->exec_units || !priv->desc_types) {
  2095. dev_err(dev, "invalid property data in device tree node\n");
  2096. err = -EINVAL;
  2097. goto err_out;
  2098. }
  2099. if (of_device_is_compatible(np, "fsl,sec3.0"))
  2100. priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
  2101. if (of_device_is_compatible(np, "fsl,sec2.1"))
  2102. priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
  2103. TALITOS_FTR_SHA224_HWINIT;
  2104. priv->chan = kzalloc(sizeof(struct talitos_channel) *
  2105. priv->num_channels, GFP_KERNEL);
  2106. if (!priv->chan) {
  2107. dev_err(dev, "failed to allocate channel management space\n");
  2108. err = -ENOMEM;
  2109. goto err_out;
  2110. }
  2111. for (i = 0; i < priv->num_channels; i++) {
  2112. spin_lock_init(&priv->chan[i].head_lock);
  2113. spin_lock_init(&priv->chan[i].tail_lock);
  2114. }
  2115. priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
  2116. for (i = 0; i < priv->num_channels; i++) {
  2117. priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
  2118. priv->fifo_len, GFP_KERNEL);
  2119. if (!priv->chan[i].fifo) {
  2120. dev_err(dev, "failed to allocate request fifo %d\n", i);
  2121. err = -ENOMEM;
  2122. goto err_out;
  2123. }
  2124. }
  2125. for (i = 0; i < priv->num_channels; i++)
  2126. atomic_set(&priv->chan[i].submit_count,
  2127. -(priv->chfifo_len - 1));
  2128. dma_set_mask(dev, DMA_BIT_MASK(36));
  2129. /* reset and initialize the h/w */
  2130. err = init_device(dev);
  2131. if (err) {
  2132. dev_err(dev, "failed to initialize device\n");
  2133. goto err_out;
  2134. }
  2135. /* register the RNG, if available */
  2136. if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
  2137. err = talitos_register_rng(dev);
  2138. if (err) {
  2139. dev_err(dev, "failed to register hwrng: %d\n", err);
  2140. goto err_out;
  2141. } else
  2142. dev_info(dev, "hwrng\n");
  2143. }
  2144. /* register crypto algorithms the device supports */
  2145. for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
  2146. if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
  2147. struct talitos_crypto_alg *t_alg;
  2148. char *name = NULL;
  2149. t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
  2150. if (IS_ERR(t_alg)) {
  2151. err = PTR_ERR(t_alg);
  2152. goto err_out;
  2153. }
  2154. switch (t_alg->algt.type) {
  2155. case CRYPTO_ALG_TYPE_ABLKCIPHER:
  2156. case CRYPTO_ALG_TYPE_AEAD:
  2157. err = crypto_register_alg(
  2158. &t_alg->algt.alg.crypto);
  2159. name = t_alg->algt.alg.crypto.cra_driver_name;
  2160. break;
  2161. case CRYPTO_ALG_TYPE_AHASH:
  2162. err = crypto_register_ahash(
  2163. &t_alg->algt.alg.hash);
  2164. name =
  2165. t_alg->algt.alg.hash.halg.base.cra_driver_name;
  2166. break;
  2167. }
  2168. if (err) {
  2169. dev_err(dev, "%s alg registration failed\n",
  2170. name);
  2171. kfree(t_alg);
  2172. } else {
  2173. list_add_tail(&t_alg->entry, &priv->alg_list);
  2174. dev_info(dev, "%s\n", name);
  2175. }
  2176. }
  2177. }
  2178. return 0;
  2179. err_out:
  2180. talitos_remove(ofdev);
  2181. return err;
  2182. }
  2183. static const struct of_device_id talitos_match[] = {
  2184. {
  2185. .compatible = "fsl,sec2.0",
  2186. },
  2187. {},
  2188. };
  2189. MODULE_DEVICE_TABLE(of, talitos_match);
  2190. static struct platform_driver talitos_driver = {
  2191. .driver = {
  2192. .name = "talitos",
  2193. .owner = THIS_MODULE,
  2194. .of_match_table = talitos_match,
  2195. },
  2196. .probe = talitos_probe,
  2197. .remove = talitos_remove,
  2198. };
  2199. static int __init talitos_init(void)
  2200. {
  2201. return platform_driver_register(&talitos_driver);
  2202. }
  2203. module_init(talitos_init);
  2204. static void __exit talitos_exit(void)
  2205. {
  2206. platform_driver_unregister(&talitos_driver);
  2207. }
  2208. module_exit(talitos_exit);
  2209. MODULE_LICENSE("GPL");
  2210. MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
  2211. MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");