tpm_tis.c 23 KB

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  1. /*
  2. * Copyright (C) 2005, 2006 IBM Corporation
  3. *
  4. * Authors:
  5. * Leendert van Doorn <leendert@watson.ibm.com>
  6. * Kylene Hall <kjhall@us.ibm.com>
  7. *
  8. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  9. *
  10. * Device driver for TCG/TCPA TPM (trusted platform module).
  11. * Specifications at www.trustedcomputinggroup.org
  12. *
  13. * This device driver implements the TPM interface as defined in
  14. * the TCG TPM Interface Spec version 1.2, revision 1.0.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation, version 2 of the
  19. * License.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/moduleparam.h>
  24. #include <linux/pnp.h>
  25. #include <linux/slab.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/wait.h>
  28. #include <linux/acpi.h>
  29. #include <linux/freezer.h>
  30. #include "tpm.h"
  31. #define TPM_HEADER_SIZE 10
  32. enum tis_access {
  33. TPM_ACCESS_VALID = 0x80,
  34. TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
  35. TPM_ACCESS_REQUEST_PENDING = 0x04,
  36. TPM_ACCESS_REQUEST_USE = 0x02,
  37. };
  38. enum tis_status {
  39. TPM_STS_VALID = 0x80,
  40. TPM_STS_COMMAND_READY = 0x40,
  41. TPM_STS_GO = 0x20,
  42. TPM_STS_DATA_AVAIL = 0x10,
  43. TPM_STS_DATA_EXPECT = 0x08,
  44. };
  45. enum tis_int_flags {
  46. TPM_GLOBAL_INT_ENABLE = 0x80000000,
  47. TPM_INTF_BURST_COUNT_STATIC = 0x100,
  48. TPM_INTF_CMD_READY_INT = 0x080,
  49. TPM_INTF_INT_EDGE_FALLING = 0x040,
  50. TPM_INTF_INT_EDGE_RISING = 0x020,
  51. TPM_INTF_INT_LEVEL_LOW = 0x010,
  52. TPM_INTF_INT_LEVEL_HIGH = 0x008,
  53. TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
  54. TPM_INTF_STS_VALID_INT = 0x002,
  55. TPM_INTF_DATA_AVAIL_INT = 0x001,
  56. };
  57. enum tis_defaults {
  58. TIS_MEM_BASE = 0xFED40000,
  59. TIS_MEM_LEN = 0x5000,
  60. TIS_SHORT_TIMEOUT = 750, /* ms */
  61. TIS_LONG_TIMEOUT = 2000, /* 2 sec */
  62. };
  63. #define TPM_ACCESS(l) (0x0000 | ((l) << 12))
  64. #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
  65. #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
  66. #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
  67. #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
  68. #define TPM_STS(l) (0x0018 | ((l) << 12))
  69. #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
  70. #define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
  71. #define TPM_RID(l) (0x0F04 | ((l) << 12))
  72. static LIST_HEAD(tis_chips);
  73. static DEFINE_SPINLOCK(tis_lock);
  74. #if defined(CONFIG_PNP) && defined(CONFIG_ACPI)
  75. static int is_itpm(struct pnp_dev *dev)
  76. {
  77. struct acpi_device *acpi = pnp_acpi_device(dev);
  78. struct acpi_hardware_id *id;
  79. list_for_each_entry(id, &acpi->pnp.ids, list) {
  80. if (!strcmp("INTC0102", id->id))
  81. return 1;
  82. }
  83. return 0;
  84. }
  85. #else
  86. static inline int is_itpm(struct pnp_dev *dev)
  87. {
  88. return 0;
  89. }
  90. #endif
  91. static int check_locality(struct tpm_chip *chip, int l)
  92. {
  93. if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
  94. (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
  95. (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
  96. return chip->vendor.locality = l;
  97. return -1;
  98. }
  99. static void release_locality(struct tpm_chip *chip, int l, int force)
  100. {
  101. if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
  102. (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
  103. (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
  104. iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
  105. chip->vendor.iobase + TPM_ACCESS(l));
  106. }
  107. static int request_locality(struct tpm_chip *chip, int l)
  108. {
  109. unsigned long stop, timeout;
  110. long rc;
  111. if (check_locality(chip, l) >= 0)
  112. return l;
  113. iowrite8(TPM_ACCESS_REQUEST_USE,
  114. chip->vendor.iobase + TPM_ACCESS(l));
  115. stop = jiffies + chip->vendor.timeout_a;
  116. if (chip->vendor.irq) {
  117. again:
  118. timeout = stop - jiffies;
  119. if ((long)timeout <= 0)
  120. return -1;
  121. rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
  122. (check_locality
  123. (chip, l) >= 0),
  124. timeout);
  125. if (rc > 0)
  126. return l;
  127. if (rc == -ERESTARTSYS && freezing(current)) {
  128. clear_thread_flag(TIF_SIGPENDING);
  129. goto again;
  130. }
  131. } else {
  132. /* wait for burstcount */
  133. do {
  134. if (check_locality(chip, l) >= 0)
  135. return l;
  136. msleep(TPM_TIMEOUT);
  137. }
  138. while (time_before(jiffies, stop));
  139. }
  140. return -1;
  141. }
  142. static u8 tpm_tis_status(struct tpm_chip *chip)
  143. {
  144. return ioread8(chip->vendor.iobase +
  145. TPM_STS(chip->vendor.locality));
  146. }
  147. static void tpm_tis_ready(struct tpm_chip *chip)
  148. {
  149. /* this causes the current command to be aborted */
  150. iowrite8(TPM_STS_COMMAND_READY,
  151. chip->vendor.iobase + TPM_STS(chip->vendor.locality));
  152. }
  153. static int get_burstcount(struct tpm_chip *chip)
  154. {
  155. unsigned long stop;
  156. int burstcnt;
  157. /* wait for burstcount */
  158. /* which timeout value, spec has 2 answers (c & d) */
  159. stop = jiffies + chip->vendor.timeout_d;
  160. do {
  161. burstcnt = ioread8(chip->vendor.iobase +
  162. TPM_STS(chip->vendor.locality) + 1);
  163. burstcnt += ioread8(chip->vendor.iobase +
  164. TPM_STS(chip->vendor.locality) +
  165. 2) << 8;
  166. if (burstcnt)
  167. return burstcnt;
  168. msleep(TPM_TIMEOUT);
  169. } while (time_before(jiffies, stop));
  170. return -EBUSY;
  171. }
  172. static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout,
  173. wait_queue_head_t *queue)
  174. {
  175. unsigned long stop;
  176. long rc;
  177. u8 status;
  178. /* check current status */
  179. status = tpm_tis_status(chip);
  180. if ((status & mask) == mask)
  181. return 0;
  182. stop = jiffies + timeout;
  183. if (chip->vendor.irq) {
  184. again:
  185. timeout = stop - jiffies;
  186. if ((long)timeout <= 0)
  187. return -ETIME;
  188. rc = wait_event_interruptible_timeout(*queue,
  189. ((tpm_tis_status
  190. (chip) & mask) ==
  191. mask), timeout);
  192. if (rc > 0)
  193. return 0;
  194. if (rc == -ERESTARTSYS && freezing(current)) {
  195. clear_thread_flag(TIF_SIGPENDING);
  196. goto again;
  197. }
  198. } else {
  199. do {
  200. msleep(TPM_TIMEOUT);
  201. status = tpm_tis_status(chip);
  202. if ((status & mask) == mask)
  203. return 0;
  204. } while (time_before(jiffies, stop));
  205. }
  206. return -ETIME;
  207. }
  208. static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
  209. {
  210. int size = 0, burstcnt;
  211. while (size < count &&
  212. wait_for_stat(chip,
  213. TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  214. chip->vendor.timeout_c,
  215. &chip->vendor.read_queue)
  216. == 0) {
  217. burstcnt = get_burstcount(chip);
  218. for (; burstcnt > 0 && size < count; burstcnt--)
  219. buf[size++] = ioread8(chip->vendor.iobase +
  220. TPM_DATA_FIFO(chip->vendor.
  221. locality));
  222. }
  223. return size;
  224. }
  225. static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
  226. {
  227. int size = 0;
  228. int expected, status;
  229. if (count < TPM_HEADER_SIZE) {
  230. size = -EIO;
  231. goto out;
  232. }
  233. /* read first 10 bytes, including tag, paramsize, and result */
  234. if ((size =
  235. recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
  236. dev_err(chip->dev, "Unable to read header\n");
  237. goto out;
  238. }
  239. expected = be32_to_cpu(*(__be32 *) (buf + 2));
  240. if (expected > count) {
  241. size = -EIO;
  242. goto out;
  243. }
  244. if ((size +=
  245. recv_data(chip, &buf[TPM_HEADER_SIZE],
  246. expected - TPM_HEADER_SIZE)) < expected) {
  247. dev_err(chip->dev, "Unable to read remainder of result\n");
  248. size = -ETIME;
  249. goto out;
  250. }
  251. wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
  252. &chip->vendor.int_queue);
  253. status = tpm_tis_status(chip);
  254. if (status & TPM_STS_DATA_AVAIL) { /* retry? */
  255. dev_err(chip->dev, "Error left over data\n");
  256. size = -EIO;
  257. goto out;
  258. }
  259. out:
  260. tpm_tis_ready(chip);
  261. release_locality(chip, chip->vendor.locality, 0);
  262. return size;
  263. }
  264. static int itpm;
  265. module_param(itpm, bool, 0444);
  266. MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)");
  267. /*
  268. * If interrupts are used (signaled by an irq set in the vendor structure)
  269. * tpm.c can skip polling for the data to be available as the interrupt is
  270. * waited for here
  271. */
  272. static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
  273. {
  274. int rc, status, burstcnt;
  275. size_t count = 0;
  276. if (request_locality(chip, 0) < 0)
  277. return -EBUSY;
  278. status = tpm_tis_status(chip);
  279. if ((status & TPM_STS_COMMAND_READY) == 0) {
  280. tpm_tis_ready(chip);
  281. if (wait_for_stat
  282. (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
  283. &chip->vendor.int_queue) < 0) {
  284. rc = -ETIME;
  285. goto out_err;
  286. }
  287. }
  288. while (count < len - 1) {
  289. burstcnt = get_burstcount(chip);
  290. for (; burstcnt > 0 && count < len - 1; burstcnt--) {
  291. iowrite8(buf[count], chip->vendor.iobase +
  292. TPM_DATA_FIFO(chip->vendor.locality));
  293. count++;
  294. }
  295. wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
  296. &chip->vendor.int_queue);
  297. status = tpm_tis_status(chip);
  298. if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
  299. rc = -EIO;
  300. goto out_err;
  301. }
  302. }
  303. /* write last byte */
  304. iowrite8(buf[count],
  305. chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality));
  306. wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
  307. &chip->vendor.int_queue);
  308. status = tpm_tis_status(chip);
  309. if ((status & TPM_STS_DATA_EXPECT) != 0) {
  310. rc = -EIO;
  311. goto out_err;
  312. }
  313. return 0;
  314. out_err:
  315. tpm_tis_ready(chip);
  316. release_locality(chip, chip->vendor.locality, 0);
  317. return rc;
  318. }
  319. /*
  320. * If interrupts are used (signaled by an irq set in the vendor structure)
  321. * tpm.c can skip polling for the data to be available as the interrupt is
  322. * waited for here
  323. */
  324. static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
  325. {
  326. int rc;
  327. u32 ordinal;
  328. rc = tpm_tis_send_data(chip, buf, len);
  329. if (rc < 0)
  330. return rc;
  331. /* go and do it */
  332. iowrite8(TPM_STS_GO,
  333. chip->vendor.iobase + TPM_STS(chip->vendor.locality));
  334. if (chip->vendor.irq) {
  335. ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
  336. if (wait_for_stat
  337. (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  338. tpm_calc_ordinal_duration(chip, ordinal),
  339. &chip->vendor.read_queue) < 0) {
  340. rc = -ETIME;
  341. goto out_err;
  342. }
  343. }
  344. return len;
  345. out_err:
  346. tpm_tis_ready(chip);
  347. release_locality(chip, chip->vendor.locality, 0);
  348. return rc;
  349. }
  350. /*
  351. * Early probing for iTPM with STS_DATA_EXPECT flaw.
  352. * Try sending command without itpm flag set and if that
  353. * fails, repeat with itpm flag set.
  354. */
  355. static int probe_itpm(struct tpm_chip *chip)
  356. {
  357. int rc = 0;
  358. u8 cmd_getticks[] = {
  359. 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
  360. 0x00, 0x00, 0x00, 0xf1
  361. };
  362. size_t len = sizeof(cmd_getticks);
  363. int rem_itpm = itpm;
  364. itpm = 0;
  365. rc = tpm_tis_send_data(chip, cmd_getticks, len);
  366. if (rc == 0)
  367. goto out;
  368. tpm_tis_ready(chip);
  369. release_locality(chip, chip->vendor.locality, 0);
  370. itpm = 1;
  371. rc = tpm_tis_send_data(chip, cmd_getticks, len);
  372. if (rc == 0) {
  373. dev_info(chip->dev, "Detected an iTPM.\n");
  374. rc = 1;
  375. } else
  376. rc = -EFAULT;
  377. out:
  378. itpm = rem_itpm;
  379. tpm_tis_ready(chip);
  380. release_locality(chip, chip->vendor.locality, 0);
  381. return rc;
  382. }
  383. static const struct file_operations tis_ops = {
  384. .owner = THIS_MODULE,
  385. .llseek = no_llseek,
  386. .open = tpm_open,
  387. .read = tpm_read,
  388. .write = tpm_write,
  389. .release = tpm_release,
  390. };
  391. static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
  392. static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
  393. static DEVICE_ATTR(enabled, S_IRUGO, tpm_show_enabled, NULL);
  394. static DEVICE_ATTR(active, S_IRUGO, tpm_show_active, NULL);
  395. static DEVICE_ATTR(owned, S_IRUGO, tpm_show_owned, NULL);
  396. static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated,
  397. NULL);
  398. static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL);
  399. static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel);
  400. static DEVICE_ATTR(durations, S_IRUGO, tpm_show_durations, NULL);
  401. static DEVICE_ATTR(timeouts, S_IRUGO, tpm_show_timeouts, NULL);
  402. static struct attribute *tis_attrs[] = {
  403. &dev_attr_pubek.attr,
  404. &dev_attr_pcrs.attr,
  405. &dev_attr_enabled.attr,
  406. &dev_attr_active.attr,
  407. &dev_attr_owned.attr,
  408. &dev_attr_temp_deactivated.attr,
  409. &dev_attr_caps.attr,
  410. &dev_attr_cancel.attr,
  411. &dev_attr_durations.attr,
  412. &dev_attr_timeouts.attr, NULL,
  413. };
  414. static struct attribute_group tis_attr_grp = {
  415. .attrs = tis_attrs
  416. };
  417. static struct tpm_vendor_specific tpm_tis = {
  418. .status = tpm_tis_status,
  419. .recv = tpm_tis_recv,
  420. .send = tpm_tis_send,
  421. .cancel = tpm_tis_ready,
  422. .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  423. .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  424. .req_canceled = TPM_STS_COMMAND_READY,
  425. .attr_group = &tis_attr_grp,
  426. .miscdev = {
  427. .fops = &tis_ops,},
  428. };
  429. static irqreturn_t tis_int_probe(int irq, void *dev_id)
  430. {
  431. struct tpm_chip *chip = dev_id;
  432. u32 interrupt;
  433. interrupt = ioread32(chip->vendor.iobase +
  434. TPM_INT_STATUS(chip->vendor.locality));
  435. if (interrupt == 0)
  436. return IRQ_NONE;
  437. chip->vendor.probed_irq = irq;
  438. /* Clear interrupts handled with TPM_EOI */
  439. iowrite32(interrupt,
  440. chip->vendor.iobase +
  441. TPM_INT_STATUS(chip->vendor.locality));
  442. return IRQ_HANDLED;
  443. }
  444. static irqreturn_t tis_int_handler(int dummy, void *dev_id)
  445. {
  446. struct tpm_chip *chip = dev_id;
  447. u32 interrupt;
  448. int i;
  449. interrupt = ioread32(chip->vendor.iobase +
  450. TPM_INT_STATUS(chip->vendor.locality));
  451. if (interrupt == 0)
  452. return IRQ_NONE;
  453. if (interrupt & TPM_INTF_DATA_AVAIL_INT)
  454. wake_up_interruptible(&chip->vendor.read_queue);
  455. if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
  456. for (i = 0; i < 5; i++)
  457. if (check_locality(chip, i) >= 0)
  458. break;
  459. if (interrupt &
  460. (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
  461. TPM_INTF_CMD_READY_INT))
  462. wake_up_interruptible(&chip->vendor.int_queue);
  463. /* Clear interrupts handled with TPM_EOI */
  464. iowrite32(interrupt,
  465. chip->vendor.iobase +
  466. TPM_INT_STATUS(chip->vendor.locality));
  467. ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
  468. return IRQ_HANDLED;
  469. }
  470. static int interrupts = 1;
  471. module_param(interrupts, bool, 0444);
  472. MODULE_PARM_DESC(interrupts, "Enable interrupts");
  473. static int tpm_tis_init(struct device *dev, resource_size_t start,
  474. resource_size_t len, unsigned int irq)
  475. {
  476. u32 vendor, intfcaps, intmask;
  477. int rc, i, irq_s, irq_e;
  478. struct tpm_chip *chip;
  479. if (!(chip = tpm_register_hardware(dev, &tpm_tis)))
  480. return -ENODEV;
  481. chip->vendor.iobase = ioremap(start, len);
  482. if (!chip->vendor.iobase) {
  483. rc = -EIO;
  484. goto out_err;
  485. }
  486. /* Default timeouts */
  487. chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
  488. chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
  489. chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
  490. chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
  491. if (request_locality(chip, 0) != 0) {
  492. rc = -ENODEV;
  493. goto out_err;
  494. }
  495. vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
  496. dev_info(dev,
  497. "1.2 TPM (device-id 0x%X, rev-id %d)\n",
  498. vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
  499. if (!itpm) {
  500. itpm = probe_itpm(chip);
  501. if (itpm < 0) {
  502. rc = -ENODEV;
  503. goto out_err;
  504. }
  505. }
  506. if (itpm)
  507. dev_info(dev, "Intel iTPM workaround enabled\n");
  508. /* Figure out the capabilities */
  509. intfcaps =
  510. ioread32(chip->vendor.iobase +
  511. TPM_INTF_CAPS(chip->vendor.locality));
  512. dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
  513. intfcaps);
  514. if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
  515. dev_dbg(dev, "\tBurst Count Static\n");
  516. if (intfcaps & TPM_INTF_CMD_READY_INT)
  517. dev_dbg(dev, "\tCommand Ready Int Support\n");
  518. if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
  519. dev_dbg(dev, "\tInterrupt Edge Falling\n");
  520. if (intfcaps & TPM_INTF_INT_EDGE_RISING)
  521. dev_dbg(dev, "\tInterrupt Edge Rising\n");
  522. if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
  523. dev_dbg(dev, "\tInterrupt Level Low\n");
  524. if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
  525. dev_dbg(dev, "\tInterrupt Level High\n");
  526. if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
  527. dev_dbg(dev, "\tLocality Change Int Support\n");
  528. if (intfcaps & TPM_INTF_STS_VALID_INT)
  529. dev_dbg(dev, "\tSts Valid Int Support\n");
  530. if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
  531. dev_dbg(dev, "\tData Avail Int Support\n");
  532. /* get the timeouts before testing for irqs */
  533. tpm_get_timeouts(chip);
  534. /* INTERRUPT Setup */
  535. init_waitqueue_head(&chip->vendor.read_queue);
  536. init_waitqueue_head(&chip->vendor.int_queue);
  537. intmask =
  538. ioread32(chip->vendor.iobase +
  539. TPM_INT_ENABLE(chip->vendor.locality));
  540. intmask |= TPM_INTF_CMD_READY_INT
  541. | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
  542. | TPM_INTF_STS_VALID_INT;
  543. iowrite32(intmask,
  544. chip->vendor.iobase +
  545. TPM_INT_ENABLE(chip->vendor.locality));
  546. if (interrupts)
  547. chip->vendor.irq = irq;
  548. if (interrupts && !chip->vendor.irq) {
  549. irq_s =
  550. ioread8(chip->vendor.iobase +
  551. TPM_INT_VECTOR(chip->vendor.locality));
  552. if (irq_s) {
  553. irq_e = irq_s;
  554. } else {
  555. irq_s = 3;
  556. irq_e = 15;
  557. }
  558. for (i = irq_s; i <= irq_e && chip->vendor.irq == 0; i++) {
  559. iowrite8(i, chip->vendor.iobase +
  560. TPM_INT_VECTOR(chip->vendor.locality));
  561. if (request_irq
  562. (i, tis_int_probe, IRQF_SHARED,
  563. chip->vendor.miscdev.name, chip) != 0) {
  564. dev_info(chip->dev,
  565. "Unable to request irq: %d for probe\n",
  566. i);
  567. continue;
  568. }
  569. /* Clear all existing */
  570. iowrite32(ioread32
  571. (chip->vendor.iobase +
  572. TPM_INT_STATUS(chip->vendor.locality)),
  573. chip->vendor.iobase +
  574. TPM_INT_STATUS(chip->vendor.locality));
  575. /* Turn on */
  576. iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
  577. chip->vendor.iobase +
  578. TPM_INT_ENABLE(chip->vendor.locality));
  579. chip->vendor.probed_irq = 0;
  580. /* Generate Interrupts */
  581. tpm_gen_interrupt(chip);
  582. chip->vendor.irq = chip->vendor.probed_irq;
  583. /* free_irq will call into tis_int_probe;
  584. clear all irqs we haven't seen while doing
  585. tpm_gen_interrupt */
  586. iowrite32(ioread32
  587. (chip->vendor.iobase +
  588. TPM_INT_STATUS(chip->vendor.locality)),
  589. chip->vendor.iobase +
  590. TPM_INT_STATUS(chip->vendor.locality));
  591. /* Turn off */
  592. iowrite32(intmask,
  593. chip->vendor.iobase +
  594. TPM_INT_ENABLE(chip->vendor.locality));
  595. free_irq(i, chip);
  596. }
  597. }
  598. if (chip->vendor.irq) {
  599. iowrite8(chip->vendor.irq,
  600. chip->vendor.iobase +
  601. TPM_INT_VECTOR(chip->vendor.locality));
  602. if (request_irq
  603. (chip->vendor.irq, tis_int_handler, IRQF_SHARED,
  604. chip->vendor.miscdev.name, chip) != 0) {
  605. dev_info(chip->dev,
  606. "Unable to request irq: %d for use\n",
  607. chip->vendor.irq);
  608. chip->vendor.irq = 0;
  609. } else {
  610. /* Clear all existing */
  611. iowrite32(ioread32
  612. (chip->vendor.iobase +
  613. TPM_INT_STATUS(chip->vendor.locality)),
  614. chip->vendor.iobase +
  615. TPM_INT_STATUS(chip->vendor.locality));
  616. /* Turn on */
  617. iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
  618. chip->vendor.iobase +
  619. TPM_INT_ENABLE(chip->vendor.locality));
  620. }
  621. }
  622. INIT_LIST_HEAD(&chip->vendor.list);
  623. spin_lock(&tis_lock);
  624. list_add(&chip->vendor.list, &tis_chips);
  625. spin_unlock(&tis_lock);
  626. tpm_continue_selftest(chip);
  627. return 0;
  628. out_err:
  629. if (chip->vendor.iobase)
  630. iounmap(chip->vendor.iobase);
  631. tpm_remove_hardware(chip->dev);
  632. return rc;
  633. }
  634. static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
  635. {
  636. u32 intmask;
  637. /* reenable interrupts that device may have lost or
  638. BIOS/firmware may have disabled */
  639. iowrite8(chip->vendor.irq, chip->vendor.iobase +
  640. TPM_INT_VECTOR(chip->vendor.locality));
  641. intmask =
  642. ioread32(chip->vendor.iobase +
  643. TPM_INT_ENABLE(chip->vendor.locality));
  644. intmask |= TPM_INTF_CMD_READY_INT
  645. | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
  646. | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
  647. iowrite32(intmask,
  648. chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
  649. }
  650. #ifdef CONFIG_PNP
  651. static int __devinit tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
  652. const struct pnp_device_id *pnp_id)
  653. {
  654. resource_size_t start, len;
  655. unsigned int irq = 0;
  656. start = pnp_mem_start(pnp_dev, 0);
  657. len = pnp_mem_len(pnp_dev, 0);
  658. if (pnp_irq_valid(pnp_dev, 0))
  659. irq = pnp_irq(pnp_dev, 0);
  660. else
  661. interrupts = 0;
  662. if (is_itpm(pnp_dev))
  663. itpm = 1;
  664. return tpm_tis_init(&pnp_dev->dev, start, len, irq);
  665. }
  666. static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg)
  667. {
  668. return tpm_pm_suspend(&dev->dev, msg);
  669. }
  670. static int tpm_tis_pnp_resume(struct pnp_dev *dev)
  671. {
  672. struct tpm_chip *chip = pnp_get_drvdata(dev);
  673. int ret;
  674. if (chip->vendor.irq)
  675. tpm_tis_reenable_interrupts(chip);
  676. ret = tpm_pm_resume(&dev->dev);
  677. if (!ret)
  678. tpm_continue_selftest(chip);
  679. return ret;
  680. }
  681. static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = {
  682. {"PNP0C31", 0}, /* TPM */
  683. {"ATM1200", 0}, /* Atmel */
  684. {"IFX0102", 0}, /* Infineon */
  685. {"BCM0101", 0}, /* Broadcom */
  686. {"BCM0102", 0}, /* Broadcom */
  687. {"NSC1200", 0}, /* National */
  688. {"ICO0102", 0}, /* Intel */
  689. /* Add new here */
  690. {"", 0}, /* User Specified */
  691. {"", 0} /* Terminator */
  692. };
  693. MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl);
  694. static __devexit void tpm_tis_pnp_remove(struct pnp_dev *dev)
  695. {
  696. struct tpm_chip *chip = pnp_get_drvdata(dev);
  697. tpm_dev_vendor_release(chip);
  698. kfree(chip);
  699. }
  700. static struct pnp_driver tis_pnp_driver = {
  701. .name = "tpm_tis",
  702. .id_table = tpm_pnp_tbl,
  703. .probe = tpm_tis_pnp_init,
  704. .suspend = tpm_tis_pnp_suspend,
  705. .resume = tpm_tis_pnp_resume,
  706. .remove = tpm_tis_pnp_remove,
  707. };
  708. #define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2
  709. module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id,
  710. sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444);
  711. MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe");
  712. #endif
  713. static int tpm_tis_suspend(struct platform_device *dev, pm_message_t msg)
  714. {
  715. return tpm_pm_suspend(&dev->dev, msg);
  716. }
  717. static int tpm_tis_resume(struct platform_device *dev)
  718. {
  719. struct tpm_chip *chip = dev_get_drvdata(&dev->dev);
  720. if (chip->vendor.irq)
  721. tpm_tis_reenable_interrupts(chip);
  722. return tpm_pm_resume(&dev->dev);
  723. }
  724. static struct platform_driver tis_drv = {
  725. .driver = {
  726. .name = "tpm_tis",
  727. .owner = THIS_MODULE,
  728. },
  729. .suspend = tpm_tis_suspend,
  730. .resume = tpm_tis_resume,
  731. };
  732. static struct platform_device *pdev;
  733. static int force;
  734. module_param(force, bool, 0444);
  735. MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry");
  736. static int __init init_tis(void)
  737. {
  738. int rc;
  739. #ifdef CONFIG_PNP
  740. if (!force)
  741. return pnp_register_driver(&tis_pnp_driver);
  742. #endif
  743. rc = platform_driver_register(&tis_drv);
  744. if (rc < 0)
  745. return rc;
  746. if (IS_ERR(pdev=platform_device_register_simple("tpm_tis", -1, NULL, 0)))
  747. return PTR_ERR(pdev);
  748. if((rc=tpm_tis_init(&pdev->dev, TIS_MEM_BASE, TIS_MEM_LEN, 0)) != 0) {
  749. platform_device_unregister(pdev);
  750. platform_driver_unregister(&tis_drv);
  751. }
  752. return rc;
  753. }
  754. static void __exit cleanup_tis(void)
  755. {
  756. struct tpm_vendor_specific *i, *j;
  757. struct tpm_chip *chip;
  758. spin_lock(&tis_lock);
  759. list_for_each_entry_safe(i, j, &tis_chips, list) {
  760. chip = to_tpm_chip(i);
  761. tpm_remove_hardware(chip->dev);
  762. iowrite32(~TPM_GLOBAL_INT_ENABLE &
  763. ioread32(chip->vendor.iobase +
  764. TPM_INT_ENABLE(chip->vendor.
  765. locality)),
  766. chip->vendor.iobase +
  767. TPM_INT_ENABLE(chip->vendor.locality));
  768. release_locality(chip, chip->vendor.locality, 1);
  769. if (chip->vendor.irq)
  770. free_irq(chip->vendor.irq, chip);
  771. iounmap(i->iobase);
  772. list_del(&i->list);
  773. }
  774. spin_unlock(&tis_lock);
  775. #ifdef CONFIG_PNP
  776. if (!force) {
  777. pnp_unregister_driver(&tis_pnp_driver);
  778. return;
  779. }
  780. #endif
  781. platform_device_unregister(pdev);
  782. platform_driver_unregister(&tis_drv);
  783. }
  784. module_init(init_tis);
  785. module_exit(cleanup_tis);
  786. MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
  787. MODULE_DESCRIPTION("TPM Driver");
  788. MODULE_VERSION("2.0");
  789. MODULE_LICENSE("GPL");