book3s_hv_interrupts.S 4.4 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License, version 2, as
  4. * published by the Free Software Foundation.
  5. *
  6. * This program is distributed in the hope that it will be useful,
  7. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. *
  11. * You should have received a copy of the GNU General Public License
  12. * along with this program; if not, write to the Free Software
  13. * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  14. *
  15. * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
  16. *
  17. * Derived from book3s_interrupts.S, which is:
  18. * Copyright SUSE Linux Products GmbH 2009
  19. *
  20. * Authors: Alexander Graf <agraf@suse.de>
  21. */
  22. #include <asm/ppc_asm.h>
  23. #include <asm/kvm_asm.h>
  24. #include <asm/reg.h>
  25. #include <asm/page.h>
  26. #include <asm/asm-offsets.h>
  27. #include <asm/exception-64s.h>
  28. #include <asm/ppc-opcode.h>
  29. /*****************************************************************************
  30. * *
  31. * Guest entry / exit code that is in kernel module memory (vmalloc) *
  32. * *
  33. ****************************************************************************/
  34. /* Registers:
  35. * r4: vcpu pointer
  36. */
  37. _GLOBAL(__kvmppc_vcore_entry)
  38. /* Write correct stack frame */
  39. mflr r0
  40. std r0,PPC_LR_STKOFF(r1)
  41. /* Save host state to the stack */
  42. stdu r1, -SWITCH_FRAME_SIZE(r1)
  43. /* Save non-volatile registers (r14 - r31) */
  44. SAVE_NVGPRS(r1)
  45. /* Save host DSCR */
  46. BEGIN_FTR_SECTION
  47. mfspr r3, SPRN_DSCR
  48. std r3, HSTATE_DSCR(r13)
  49. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
  50. /* Save host DABR */
  51. mfspr r3, SPRN_DABR
  52. std r3, HSTATE_DABR(r13)
  53. /* Hard-disable interrupts */
  54. mfmsr r10
  55. std r10, HSTATE_HOST_MSR(r13)
  56. rldicl r10,r10,48,1
  57. rotldi r10,r10,16
  58. mtmsrd r10,1
  59. /* Save host PMU registers and load guest PMU registers */
  60. /* R4 is live here (vcpu pointer) but not r3 or r5 */
  61. li r3, 1
  62. sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
  63. mfspr r7, SPRN_MMCR0 /* save MMCR0 */
  64. mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
  65. isync
  66. ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
  67. lbz r5, LPPACA_PMCINUSE(r3)
  68. cmpwi r5, 0
  69. beq 31f /* skip if not */
  70. mfspr r5, SPRN_MMCR1
  71. mfspr r6, SPRN_MMCRA
  72. std r7, HSTATE_MMCR(r13)
  73. std r5, HSTATE_MMCR + 8(r13)
  74. std r6, HSTATE_MMCR + 16(r13)
  75. mfspr r3, SPRN_PMC1
  76. mfspr r5, SPRN_PMC2
  77. mfspr r6, SPRN_PMC3
  78. mfspr r7, SPRN_PMC4
  79. mfspr r8, SPRN_PMC5
  80. mfspr r9, SPRN_PMC6
  81. BEGIN_FTR_SECTION
  82. mfspr r10, SPRN_PMC7
  83. mfspr r11, SPRN_PMC8
  84. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
  85. stw r3, HSTATE_PMC(r13)
  86. stw r5, HSTATE_PMC + 4(r13)
  87. stw r6, HSTATE_PMC + 8(r13)
  88. stw r7, HSTATE_PMC + 12(r13)
  89. stw r8, HSTATE_PMC + 16(r13)
  90. stw r9, HSTATE_PMC + 20(r13)
  91. BEGIN_FTR_SECTION
  92. stw r10, HSTATE_PMC + 24(r13)
  93. stw r11, HSTATE_PMC + 28(r13)
  94. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
  95. 31:
  96. /*
  97. * Put whatever is in the decrementer into the
  98. * hypervisor decrementer.
  99. */
  100. mfspr r8,SPRN_DEC
  101. mftb r7
  102. mtspr SPRN_HDEC,r8
  103. extsw r8,r8
  104. add r8,r8,r7
  105. std r8,HSTATE_DECEXP(r13)
  106. /*
  107. * On PPC970, if the guest vcpu has an external interrupt pending,
  108. * send ourselves an IPI so as to interrupt the guest once it
  109. * enables interrupts. (It must have interrupts disabled,
  110. * otherwise we would already have delivered the interrupt.)
  111. */
  112. BEGIN_FTR_SECTION
  113. ld r0, VCPU_PENDING_EXC(r4)
  114. li r7, (1 << BOOK3S_IRQPRIO_EXTERNAL)
  115. oris r7, r7, (1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
  116. and. r0, r0, r7
  117. beq 32f
  118. mr r31, r4
  119. lhz r3, PACAPACAINDEX(r13)
  120. bl smp_send_reschedule
  121. nop
  122. mr r4, r31
  123. 32:
  124. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
  125. /* Jump to partition switch code */
  126. bl .kvmppc_hv_entry_trampoline
  127. nop
  128. /*
  129. * We return here in virtual mode after the guest exits
  130. * with something that we can't handle in real mode.
  131. * Interrupts are enabled again at this point.
  132. */
  133. .global kvmppc_handler_highmem
  134. kvmppc_handler_highmem:
  135. /*
  136. * Register usage at this point:
  137. *
  138. * R1 = host R1
  139. * R2 = host R2
  140. * R12 = exit handler id
  141. * R13 = PACA
  142. */
  143. /* Restore non-volatile host registers (r14 - r31) */
  144. REST_NVGPRS(r1)
  145. addi r1, r1, SWITCH_FRAME_SIZE
  146. ld r0, PPC_LR_STKOFF(r1)
  147. mtlr r0
  148. blr