p3041si.dtsi 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660
  1. /*
  2. * P3041 Silicon Device Tree Source
  3. *
  4. * Copyright 2010-2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. /dts-v1/;
  35. / {
  36. compatible = "fsl,P3041";
  37. #address-cells = <2>;
  38. #size-cells = <2>;
  39. interrupt-parent = <&mpic>;
  40. aliases {
  41. ccsr = &soc;
  42. serial0 = &serial0;
  43. serial1 = &serial1;
  44. serial2 = &serial2;
  45. serial3 = &serial3;
  46. pci0 = &pci0;
  47. pci1 = &pci1;
  48. pci2 = &pci2;
  49. pci3 = &pci3;
  50. usb0 = &usb0;
  51. usb1 = &usb1;
  52. dma0 = &dma0;
  53. dma1 = &dma1;
  54. sdhc = &sdhc;
  55. msi0 = &msi0;
  56. msi1 = &msi1;
  57. msi2 = &msi2;
  58. crypto = &crypto;
  59. sec_jr0 = &sec_jr0;
  60. sec_jr1 = &sec_jr1;
  61. sec_jr2 = &sec_jr2;
  62. sec_jr3 = &sec_jr3;
  63. rtic_a = &rtic_a;
  64. rtic_b = &rtic_b;
  65. rtic_c = &rtic_c;
  66. rtic_d = &rtic_d;
  67. sec_mon = &sec_mon;
  68. /*
  69. rio0 = &rapidio0;
  70. */
  71. };
  72. cpus {
  73. #address-cells = <1>;
  74. #size-cells = <0>;
  75. cpu0: PowerPC,e500mc@0 {
  76. device_type = "cpu";
  77. reg = <0>;
  78. next-level-cache = <&L2_0>;
  79. L2_0: l2-cache {
  80. next-level-cache = <&cpc>;
  81. };
  82. };
  83. cpu1: PowerPC,e500mc@1 {
  84. device_type = "cpu";
  85. reg = <1>;
  86. next-level-cache = <&L2_1>;
  87. L2_1: l2-cache {
  88. next-level-cache = <&cpc>;
  89. };
  90. };
  91. cpu2: PowerPC,e500mc@2 {
  92. device_type = "cpu";
  93. reg = <2>;
  94. next-level-cache = <&L2_2>;
  95. L2_2: l2-cache {
  96. next-level-cache = <&cpc>;
  97. };
  98. };
  99. cpu3: PowerPC,e500mc@3 {
  100. device_type = "cpu";
  101. reg = <3>;
  102. next-level-cache = <&L2_3>;
  103. L2_3: l2-cache {
  104. next-level-cache = <&cpc>;
  105. };
  106. };
  107. };
  108. soc: soc@ffe000000 {
  109. #address-cells = <1>;
  110. #size-cells = <1>;
  111. device_type = "soc";
  112. compatible = "simple-bus";
  113. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  114. reg = <0xf 0xfe000000 0 0x00001000>;
  115. soc-sram-error {
  116. compatible = "fsl,soc-sram-error";
  117. interrupts = <16 2 1 29>;
  118. };
  119. corenet-law@0 {
  120. compatible = "fsl,corenet-law";
  121. reg = <0x0 0x1000>;
  122. fsl,num-laws = <32>;
  123. };
  124. memory-controller@8000 {
  125. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  126. reg = <0x8000 0x1000>;
  127. interrupts = <16 2 1 23>;
  128. };
  129. cpc: l3-cache-controller@10000 {
  130. compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  131. reg = <0x10000 0x1000>;
  132. interrupts = <16 2 1 27>;
  133. };
  134. corenet-cf@18000 {
  135. compatible = "fsl,corenet-cf";
  136. reg = <0x18000 0x1000>;
  137. interrupts = <16 2 1 31>;
  138. fsl,ccf-num-csdids = <32>;
  139. fsl,ccf-num-snoopids = <32>;
  140. };
  141. iommu@20000 {
  142. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  143. reg = <0x20000 0x4000>;
  144. interrupts = <
  145. 24 2 0 0
  146. 16 2 1 30>;
  147. };
  148. mpic: pic@40000 {
  149. clock-frequency = <0>;
  150. interrupt-controller;
  151. #address-cells = <0>;
  152. #interrupt-cells = <4>;
  153. reg = <0x40000 0x40000>;
  154. compatible = "fsl,mpic", "chrp,open-pic";
  155. device_type = "open-pic";
  156. };
  157. msi0: msi@41600 {
  158. compatible = "fsl,mpic-msi";
  159. reg = <0x41600 0x200>;
  160. msi-available-ranges = <0 0x100>;
  161. interrupts = <
  162. 0xe0 0 0 0
  163. 0xe1 0 0 0
  164. 0xe2 0 0 0
  165. 0xe3 0 0 0
  166. 0xe4 0 0 0
  167. 0xe5 0 0 0
  168. 0xe6 0 0 0
  169. 0xe7 0 0 0>;
  170. };
  171. msi1: msi@41800 {
  172. compatible = "fsl,mpic-msi";
  173. reg = <0x41800 0x200>;
  174. msi-available-ranges = <0 0x100>;
  175. interrupts = <
  176. 0xe8 0 0 0
  177. 0xe9 0 0 0
  178. 0xea 0 0 0
  179. 0xeb 0 0 0
  180. 0xec 0 0 0
  181. 0xed 0 0 0
  182. 0xee 0 0 0
  183. 0xef 0 0 0>;
  184. };
  185. msi2: msi@41a00 {
  186. compatible = "fsl,mpic-msi";
  187. reg = <0x41a00 0x200>;
  188. msi-available-ranges = <0 0x100>;
  189. interrupts = <
  190. 0xf0 0 0 0
  191. 0xf1 0 0 0
  192. 0xf2 0 0 0
  193. 0xf3 0 0 0
  194. 0xf4 0 0 0
  195. 0xf5 0 0 0
  196. 0xf6 0 0 0
  197. 0xf7 0 0 0>;
  198. };
  199. guts: global-utilities@e0000 {
  200. compatible = "fsl,qoriq-device-config-1.0";
  201. reg = <0xe0000 0xe00>;
  202. fsl,has-rstcr;
  203. #sleep-cells = <1>;
  204. fsl,liodn-bits = <12>;
  205. };
  206. pins: global-utilities@e0e00 {
  207. compatible = "fsl,qoriq-pin-control-1.0";
  208. reg = <0xe0e00 0x200>;
  209. #sleep-cells = <2>;
  210. };
  211. clockgen: global-utilities@e1000 {
  212. compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
  213. reg = <0xe1000 0x1000>;
  214. clock-frequency = <0>;
  215. };
  216. rcpm: global-utilities@e2000 {
  217. compatible = "fsl,qoriq-rcpm-1.0";
  218. reg = <0xe2000 0x1000>;
  219. #sleep-cells = <1>;
  220. };
  221. sfp: sfp@e8000 {
  222. compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
  223. reg = <0xe8000 0x1000>;
  224. };
  225. serdes: serdes@ea000 {
  226. compatible = "fsl,p3041-serdes";
  227. reg = <0xea000 0x1000>;
  228. };
  229. dma0: dma@100300 {
  230. #address-cells = <1>;
  231. #size-cells = <1>;
  232. compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
  233. reg = <0x100300 0x4>;
  234. ranges = <0x0 0x100100 0x200>;
  235. cell-index = <0>;
  236. dma-channel@0 {
  237. compatible = "fsl,p3041-dma-channel",
  238. "fsl,eloplus-dma-channel";
  239. reg = <0x0 0x80>;
  240. cell-index = <0>;
  241. interrupts = <28 2 0 0>;
  242. };
  243. dma-channel@80 {
  244. compatible = "fsl,p3041-dma-channel",
  245. "fsl,eloplus-dma-channel";
  246. reg = <0x80 0x80>;
  247. cell-index = <1>;
  248. interrupts = <29 2 0 0>;
  249. };
  250. dma-channel@100 {
  251. compatible = "fsl,p3041-dma-channel",
  252. "fsl,eloplus-dma-channel";
  253. reg = <0x100 0x80>;
  254. cell-index = <2>;
  255. interrupts = <30 2 0 0>;
  256. };
  257. dma-channel@180 {
  258. compatible = "fsl,p3041-dma-channel",
  259. "fsl,eloplus-dma-channel";
  260. reg = <0x180 0x80>;
  261. cell-index = <3>;
  262. interrupts = <31 2 0 0>;
  263. };
  264. };
  265. dma1: dma@101300 {
  266. #address-cells = <1>;
  267. #size-cells = <1>;
  268. compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
  269. reg = <0x101300 0x4>;
  270. ranges = <0x0 0x101100 0x200>;
  271. cell-index = <1>;
  272. dma-channel@0 {
  273. compatible = "fsl,p3041-dma-channel",
  274. "fsl,eloplus-dma-channel";
  275. reg = <0x0 0x80>;
  276. cell-index = <0>;
  277. interrupts = <32 2 0 0>;
  278. };
  279. dma-channel@80 {
  280. compatible = "fsl,p3041-dma-channel",
  281. "fsl,eloplus-dma-channel";
  282. reg = <0x80 0x80>;
  283. cell-index = <1>;
  284. interrupts = <33 2 0 0>;
  285. };
  286. dma-channel@100 {
  287. compatible = "fsl,p3041-dma-channel",
  288. "fsl,eloplus-dma-channel";
  289. reg = <0x100 0x80>;
  290. cell-index = <2>;
  291. interrupts = <34 2 0 0>;
  292. };
  293. dma-channel@180 {
  294. compatible = "fsl,p3041-dma-channel",
  295. "fsl,eloplus-dma-channel";
  296. reg = <0x180 0x80>;
  297. cell-index = <3>;
  298. interrupts = <35 2 0 0>;
  299. };
  300. };
  301. spi@110000 {
  302. #address-cells = <1>;
  303. #size-cells = <0>;
  304. compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
  305. reg = <0x110000 0x1000>;
  306. interrupts = <53 0x2 0 0>;
  307. fsl,espi-num-chipselects = <4>;
  308. };
  309. sdhc: sdhc@114000 {
  310. compatible = "fsl,p3041-esdhc", "fsl,esdhc";
  311. reg = <0x114000 0x1000>;
  312. interrupts = <48 2 0 0>;
  313. sdhci,auto-cmd12;
  314. clock-frequency = <0>;
  315. };
  316. i2c@118000 {
  317. #address-cells = <1>;
  318. #size-cells = <0>;
  319. cell-index = <0>;
  320. compatible = "fsl-i2c";
  321. reg = <0x118000 0x100>;
  322. interrupts = <38 2 0 0>;
  323. dfsrr;
  324. };
  325. i2c@118100 {
  326. #address-cells = <1>;
  327. #size-cells = <0>;
  328. cell-index = <1>;
  329. compatible = "fsl-i2c";
  330. reg = <0x118100 0x100>;
  331. interrupts = <38 2 0 0>;
  332. dfsrr;
  333. };
  334. i2c@119000 {
  335. #address-cells = <1>;
  336. #size-cells = <0>;
  337. cell-index = <2>;
  338. compatible = "fsl-i2c";
  339. reg = <0x119000 0x100>;
  340. interrupts = <39 2 0 0>;
  341. dfsrr;
  342. };
  343. i2c@119100 {
  344. #address-cells = <1>;
  345. #size-cells = <0>;
  346. cell-index = <3>;
  347. compatible = "fsl-i2c";
  348. reg = <0x119100 0x100>;
  349. interrupts = <39 2 0 0>;
  350. dfsrr;
  351. };
  352. serial0: serial@11c500 {
  353. cell-index = <0>;
  354. device_type = "serial";
  355. compatible = "ns16550";
  356. reg = <0x11c500 0x100>;
  357. clock-frequency = <0>;
  358. interrupts = <36 2 0 0>;
  359. };
  360. serial1: serial@11c600 {
  361. cell-index = <1>;
  362. device_type = "serial";
  363. compatible = "ns16550";
  364. reg = <0x11c600 0x100>;
  365. clock-frequency = <0>;
  366. interrupts = <36 2 0 0>;
  367. };
  368. serial2: serial@11d500 {
  369. cell-index = <2>;
  370. device_type = "serial";
  371. compatible = "ns16550";
  372. reg = <0x11d500 0x100>;
  373. clock-frequency = <0>;
  374. interrupts = <37 2 0 0>;
  375. };
  376. serial3: serial@11d600 {
  377. cell-index = <3>;
  378. device_type = "serial";
  379. compatible = "ns16550";
  380. reg = <0x11d600 0x100>;
  381. clock-frequency = <0>;
  382. interrupts = <37 2 0 0>;
  383. };
  384. gpio0: gpio@130000 {
  385. compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
  386. reg = <0x130000 0x1000>;
  387. interrupts = <55 2 0 0>;
  388. #gpio-cells = <2>;
  389. gpio-controller;
  390. };
  391. usb0: usb@210000 {
  392. compatible = "fsl,p3041-usb2-mph",
  393. "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  394. reg = <0x210000 0x1000>;
  395. #address-cells = <1>;
  396. #size-cells = <0>;
  397. interrupts = <44 0x2 0 0>;
  398. phy_type = "utmi";
  399. port0;
  400. };
  401. usb1: usb@211000 {
  402. compatible = "fsl,p3041-usb2-dr",
  403. "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  404. reg = <0x211000 0x1000>;
  405. #address-cells = <1>;
  406. #size-cells = <0>;
  407. interrupts = <45 0x2 0 0>;
  408. dr_mode = "host";
  409. phy_type = "utmi";
  410. };
  411. sata@220000 {
  412. compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
  413. reg = <0x220000 0x1000>;
  414. interrupts = <68 0x2 0 0>;
  415. };
  416. sata@221000 {
  417. compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
  418. reg = <0x221000 0x1000>;
  419. interrupts = <69 0x2 0 0>;
  420. };
  421. crypto: crypto@300000 {
  422. compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
  423. #address-cells = <1>;
  424. #size-cells = <1>;
  425. reg = <0x300000 0x10000>;
  426. ranges = <0 0x300000 0x10000>;
  427. interrupts = <92 2 0 0>;
  428. sec_jr0: jr@1000 {
  429. compatible = "fsl,sec-v4.2-job-ring",
  430. "fsl,sec-v4.0-job-ring";
  431. reg = <0x1000 0x1000>;
  432. interrupts = <88 2 0 0>;
  433. };
  434. sec_jr1: jr@2000 {
  435. compatible = "fsl,sec-v4.2-job-ring",
  436. "fsl,sec-v4.0-job-ring";
  437. reg = <0x2000 0x1000>;
  438. interrupts = <89 2 0 0>;
  439. };
  440. sec_jr2: jr@3000 {
  441. compatible = "fsl,sec-v4.2-job-ring",
  442. "fsl,sec-v4.0-job-ring";
  443. reg = <0x3000 0x1000>;
  444. interrupts = <90 2 0 0>;
  445. };
  446. sec_jr3: jr@4000 {
  447. compatible = "fsl,sec-v4.2-job-ring",
  448. "fsl,sec-v4.0-job-ring";
  449. reg = <0x4000 0x1000>;
  450. interrupts = <91 2 0 0>;
  451. };
  452. rtic@6000 {
  453. compatible = "fsl,sec-v4.2-rtic",
  454. "fsl,sec-v4.0-rtic";
  455. #address-cells = <1>;
  456. #size-cells = <1>;
  457. reg = <0x6000 0x100>;
  458. ranges = <0x0 0x6100 0xe00>;
  459. rtic_a: rtic-a@0 {
  460. compatible = "fsl,sec-v4.2-rtic-memory",
  461. "fsl,sec-v4.0-rtic-memory";
  462. reg = <0x00 0x20 0x100 0x80>;
  463. };
  464. rtic_b: rtic-b@20 {
  465. compatible = "fsl,sec-v4.2-rtic-memory",
  466. "fsl,sec-v4.0-rtic-memory";
  467. reg = <0x20 0x20 0x200 0x80>;
  468. };
  469. rtic_c: rtic-c@40 {
  470. compatible = "fsl,sec-v4.2-rtic-memory",
  471. "fsl,sec-v4.0-rtic-memory";
  472. reg = <0x40 0x20 0x300 0x80>;
  473. };
  474. rtic_d: rtic-d@60 {
  475. compatible = "fsl,sec-v4.2-rtic-memory",
  476. "fsl,sec-v4.0-rtic-memory";
  477. reg = <0x60 0x20 0x500 0x80>;
  478. };
  479. };
  480. };
  481. sec_mon: sec_mon@314000 {
  482. compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
  483. reg = <0x314000 0x1000>;
  484. interrupts = <93 2 0 0>;
  485. };
  486. };
  487. /*
  488. rapidio0: rapidio@ffe0c0000
  489. */
  490. localbus@ffe124000 {
  491. compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
  492. interrupts = <25 2 0 0>;
  493. #address-cells = <2>;
  494. #size-cells = <1>;
  495. };
  496. pci0: pcie@ffe200000 {
  497. compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
  498. device_type = "pci";
  499. #size-cells = <2>;
  500. #address-cells = <3>;
  501. bus-range = <0x0 0xff>;
  502. clock-frequency = <0x1fca055>;
  503. fsl,msi = <&msi0>;
  504. interrupts = <16 2 1 15>;
  505. pcie@0 {
  506. reg = <0 0 0 0 0>;
  507. #interrupt-cells = <1>;
  508. #size-cells = <2>;
  509. #address-cells = <3>;
  510. device_type = "pci";
  511. interrupts = <16 2 1 15>;
  512. interrupt-map-mask = <0xf800 0 0 7>;
  513. interrupt-map = <
  514. /* IDSEL 0x0 */
  515. 0000 0 0 1 &mpic 40 1 0 0
  516. 0000 0 0 2 &mpic 1 1 0 0
  517. 0000 0 0 3 &mpic 2 1 0 0
  518. 0000 0 0 4 &mpic 3 1 0 0
  519. >;
  520. };
  521. };
  522. pci1: pcie@ffe201000 {
  523. compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
  524. device_type = "pci";
  525. #size-cells = <2>;
  526. #address-cells = <3>;
  527. bus-range = <0 0xff>;
  528. clock-frequency = <0x1fca055>;
  529. fsl,msi = <&msi1>;
  530. interrupts = <16 2 1 14>;
  531. pcie@0 {
  532. reg = <0 0 0 0 0>;
  533. #interrupt-cells = <1>;
  534. #size-cells = <2>;
  535. #address-cells = <3>;
  536. device_type = "pci";
  537. interrupts = <16 2 1 14>;
  538. interrupt-map-mask = <0xf800 0 0 7>;
  539. interrupt-map = <
  540. /* IDSEL 0x0 */
  541. 0000 0 0 1 &mpic 41 1 0 0
  542. 0000 0 0 2 &mpic 5 1 0 0
  543. 0000 0 0 3 &mpic 6 1 0 0
  544. 0000 0 0 4 &mpic 7 1 0 0
  545. >;
  546. };
  547. };
  548. pci2: pcie@ffe202000 {
  549. compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
  550. device_type = "pci";
  551. #size-cells = <2>;
  552. #address-cells = <3>;
  553. bus-range = <0x0 0xff>;
  554. clock-frequency = <0x1fca055>;
  555. fsl,msi = <&msi2>;
  556. interrupts = <16 2 1 13>;
  557. pcie@0 {
  558. reg = <0 0 0 0 0>;
  559. #interrupt-cells = <1>;
  560. #size-cells = <2>;
  561. #address-cells = <3>;
  562. device_type = "pci";
  563. interrupts = <16 2 1 13>;
  564. interrupt-map-mask = <0xf800 0 0 7>;
  565. interrupt-map = <
  566. /* IDSEL 0x0 */
  567. 0000 0 0 1 &mpic 42 1 0 0
  568. 0000 0 0 2 &mpic 9 1 0 0
  569. 0000 0 0 3 &mpic 10 1 0 0
  570. 0000 0 0 4 &mpic 11 1 0 0
  571. >;
  572. };
  573. };
  574. pci3: pcie@ffe203000 {
  575. compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
  576. device_type = "pci";
  577. #size-cells = <2>;
  578. #address-cells = <3>;
  579. bus-range = <0x0 0xff>;
  580. clock-frequency = <0x1fca055>;
  581. fsl,msi = <&msi2>;
  582. interrupts = <16 2 1 12>;
  583. pcie@0 {
  584. reg = <0 0 0 0 0>;
  585. #interrupt-cells = <1>;
  586. #size-cells = <2>;
  587. #address-cells = <3>;
  588. device_type = "pci";
  589. interrupts = <16 2 1 12>;
  590. interrupt-map-mask = <0xf800 0 0 7>;
  591. interrupt-map = <
  592. /* IDSEL 0x0 */
  593. 0000 0 0 1 &mpic 43 1 0 0
  594. 0000 0 0 2 &mpic 0 1 0 0
  595. 0000 0 0 3 &mpic 4 1 0 0
  596. 0000 0 0 4 &mpic 8 1 0 0
  597. >;
  598. };
  599. };
  600. };