p2040si.dtsi 14 KB

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  1. /*
  2. * P2040 Silicon Device Tree Source
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. /dts-v1/;
  35. / {
  36. compatible = "fsl,P2040";
  37. #address-cells = <2>;
  38. #size-cells = <2>;
  39. interrupt-parent = <&mpic>;
  40. aliases {
  41. ccsr = &soc;
  42. serial0 = &serial0;
  43. serial1 = &serial1;
  44. serial2 = &serial2;
  45. serial3 = &serial3;
  46. pci0 = &pci0;
  47. pci1 = &pci1;
  48. pci2 = &pci2;
  49. usb0 = &usb0;
  50. usb1 = &usb1;
  51. dma0 = &dma0;
  52. dma1 = &dma1;
  53. sdhc = &sdhc;
  54. msi0 = &msi0;
  55. msi1 = &msi1;
  56. msi2 = &msi2;
  57. crypto = &crypto;
  58. sec_jr0 = &sec_jr0;
  59. sec_jr1 = &sec_jr1;
  60. sec_jr2 = &sec_jr2;
  61. sec_jr3 = &sec_jr3;
  62. rtic_a = &rtic_a;
  63. rtic_b = &rtic_b;
  64. rtic_c = &rtic_c;
  65. rtic_d = &rtic_d;
  66. sec_mon = &sec_mon;
  67. };
  68. cpus {
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. cpu0: PowerPC,e500mc@0 {
  72. device_type = "cpu";
  73. reg = <0>;
  74. next-level-cache = <&L2_0>;
  75. L2_0: l2-cache {
  76. next-level-cache = <&cpc>;
  77. };
  78. };
  79. cpu1: PowerPC,e500mc@1 {
  80. device_type = "cpu";
  81. reg = <1>;
  82. next-level-cache = <&L2_1>;
  83. L2_1: l2-cache {
  84. next-level-cache = <&cpc>;
  85. };
  86. };
  87. cpu2: PowerPC,e500mc@2 {
  88. device_type = "cpu";
  89. reg = <2>;
  90. next-level-cache = <&L2_2>;
  91. L2_2: l2-cache {
  92. next-level-cache = <&cpc>;
  93. };
  94. };
  95. cpu3: PowerPC,e500mc@3 {
  96. device_type = "cpu";
  97. reg = <3>;
  98. next-level-cache = <&L2_3>;
  99. L2_3: l2-cache {
  100. next-level-cache = <&cpc>;
  101. };
  102. };
  103. };
  104. soc: soc@ffe000000 {
  105. #address-cells = <1>;
  106. #size-cells = <1>;
  107. device_type = "soc";
  108. compatible = "simple-bus";
  109. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  110. reg = <0xf 0xfe000000 0 0x00001000>;
  111. soc-sram-error {
  112. compatible = "fsl,soc-sram-error";
  113. interrupts = <16 2 1 29>;
  114. };
  115. corenet-law@0 {
  116. compatible = "fsl,corenet-law";
  117. reg = <0x0 0x1000>;
  118. fsl,num-laws = <32>;
  119. };
  120. memory-controller@8000 {
  121. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  122. reg = <0x8000 0x1000>;
  123. interrupts = <16 2 1 23>;
  124. };
  125. cpc: l3-cache-controller@10000 {
  126. compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  127. reg = <0x10000 0x1000>;
  128. interrupts = <16 2 1 27>;
  129. };
  130. corenet-cf@18000 {
  131. compatible = "fsl,corenet-cf";
  132. reg = <0x18000 0x1000>;
  133. interrupts = <16 2 1 31>;
  134. fsl,ccf-num-csdids = <32>;
  135. fsl,ccf-num-snoopids = <32>;
  136. };
  137. iommu@20000 {
  138. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  139. reg = <0x20000 0x4000>;
  140. interrupts = <
  141. 24 2 0 0
  142. 16 2 1 30>;
  143. };
  144. mpic: pic@40000 {
  145. clock-frequency = <0>;
  146. interrupt-controller;
  147. #address-cells = <0>;
  148. #interrupt-cells = <4>;
  149. reg = <0x40000 0x40000>;
  150. compatible = "fsl,mpic", "chrp,open-pic";
  151. device_type = "open-pic";
  152. };
  153. msi0: msi@41600 {
  154. compatible = "fsl,mpic-msi";
  155. reg = <0x41600 0x200>;
  156. msi-available-ranges = <0 0x100>;
  157. interrupts = <
  158. 0xe0 0 0 0
  159. 0xe1 0 0 0
  160. 0xe2 0 0 0
  161. 0xe3 0 0 0
  162. 0xe4 0 0 0
  163. 0xe5 0 0 0
  164. 0xe6 0 0 0
  165. 0xe7 0 0 0>;
  166. };
  167. msi1: msi@41800 {
  168. compatible = "fsl,mpic-msi";
  169. reg = <0x41800 0x200>;
  170. msi-available-ranges = <0 0x100>;
  171. interrupts = <
  172. 0xe8 0 0 0
  173. 0xe9 0 0 0
  174. 0xea 0 0 0
  175. 0xeb 0 0 0
  176. 0xec 0 0 0
  177. 0xed 0 0 0
  178. 0xee 0 0 0
  179. 0xef 0 0 0>;
  180. };
  181. msi2: msi@41a00 {
  182. compatible = "fsl,mpic-msi";
  183. reg = <0x41a00 0x200>;
  184. msi-available-ranges = <0 0x100>;
  185. interrupts = <
  186. 0xf0 0 0 0
  187. 0xf1 0 0 0
  188. 0xf2 0 0 0
  189. 0xf3 0 0 0
  190. 0xf4 0 0 0
  191. 0xf5 0 0 0
  192. 0xf6 0 0 0
  193. 0xf7 0 0 0>;
  194. };
  195. guts: global-utilities@e0000 {
  196. compatible = "fsl,qoriq-device-config-1.0";
  197. reg = <0xe0000 0xe00>;
  198. fsl,has-rstcr;
  199. #sleep-cells = <1>;
  200. fsl,liodn-bits = <12>;
  201. };
  202. pins: global-utilities@e0e00 {
  203. compatible = "fsl,qoriq-pin-control-1.0";
  204. reg = <0xe0e00 0x200>;
  205. #sleep-cells = <2>;
  206. };
  207. clockgen: global-utilities@e1000 {
  208. compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0";
  209. reg = <0xe1000 0x1000>;
  210. clock-frequency = <0>;
  211. };
  212. rcpm: global-utilities@e2000 {
  213. compatible = "fsl,qoriq-rcpm-1.0";
  214. reg = <0xe2000 0x1000>;
  215. #sleep-cells = <1>;
  216. };
  217. sfp: sfp@e8000 {
  218. compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0";
  219. reg = <0xe8000 0x1000>;
  220. };
  221. serdes: serdes@ea000 {
  222. compatible = "fsl,p2040-serdes";
  223. reg = <0xea000 0x1000>;
  224. };
  225. dma0: dma@100300 {
  226. #address-cells = <1>;
  227. #size-cells = <1>;
  228. compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
  229. reg = <0x100300 0x4>;
  230. ranges = <0x0 0x100100 0x200>;
  231. cell-index = <0>;
  232. dma-channel@0 {
  233. compatible = "fsl,p2040-dma-channel",
  234. "fsl,eloplus-dma-channel";
  235. reg = <0x0 0x80>;
  236. cell-index = <0>;
  237. interrupts = <28 2 0 0>;
  238. };
  239. dma-channel@80 {
  240. compatible = "fsl,p2040-dma-channel",
  241. "fsl,eloplus-dma-channel";
  242. reg = <0x80 0x80>;
  243. cell-index = <1>;
  244. interrupts = <29 2 0 0>;
  245. };
  246. dma-channel@100 {
  247. compatible = "fsl,p2040-dma-channel",
  248. "fsl,eloplus-dma-channel";
  249. reg = <0x100 0x80>;
  250. cell-index = <2>;
  251. interrupts = <30 2 0 0>;
  252. };
  253. dma-channel@180 {
  254. compatible = "fsl,p2040-dma-channel",
  255. "fsl,eloplus-dma-channel";
  256. reg = <0x180 0x80>;
  257. cell-index = <3>;
  258. interrupts = <31 2 0 0>;
  259. };
  260. };
  261. dma1: dma@101300 {
  262. #address-cells = <1>;
  263. #size-cells = <1>;
  264. compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
  265. reg = <0x101300 0x4>;
  266. ranges = <0x0 0x101100 0x200>;
  267. cell-index = <1>;
  268. dma-channel@0 {
  269. compatible = "fsl,p2040-dma-channel",
  270. "fsl,eloplus-dma-channel";
  271. reg = <0x0 0x80>;
  272. cell-index = <0>;
  273. interrupts = <32 2 0 0>;
  274. };
  275. dma-channel@80 {
  276. compatible = "fsl,p2040-dma-channel",
  277. "fsl,eloplus-dma-channel";
  278. reg = <0x80 0x80>;
  279. cell-index = <1>;
  280. interrupts = <33 2 0 0>;
  281. };
  282. dma-channel@100 {
  283. compatible = "fsl,p2040-dma-channel",
  284. "fsl,eloplus-dma-channel";
  285. reg = <0x100 0x80>;
  286. cell-index = <2>;
  287. interrupts = <34 2 0 0>;
  288. };
  289. dma-channel@180 {
  290. compatible = "fsl,p2040-dma-channel",
  291. "fsl,eloplus-dma-channel";
  292. reg = <0x180 0x80>;
  293. cell-index = <3>;
  294. interrupts = <35 2 0 0>;
  295. };
  296. };
  297. spi@110000 {
  298. #address-cells = <1>;
  299. #size-cells = <0>;
  300. compatible = "fsl,p2040-espi", "fsl,mpc8536-espi";
  301. reg = <0x110000 0x1000>;
  302. interrupts = <53 0x2 0 0>;
  303. fsl,espi-num-chipselects = <4>;
  304. };
  305. sdhc: sdhc@114000 {
  306. compatible = "fsl,p2040-esdhc", "fsl,esdhc";
  307. reg = <0x114000 0x1000>;
  308. interrupts = <48 2 0 0>;
  309. sdhci,auto-cmd12;
  310. clock-frequency = <0>;
  311. };
  312. i2c@118000 {
  313. #address-cells = <1>;
  314. #size-cells = <0>;
  315. cell-index = <0>;
  316. compatible = "fsl-i2c";
  317. reg = <0x118000 0x100>;
  318. interrupts = <38 2 0 0>;
  319. dfsrr;
  320. };
  321. i2c@118100 {
  322. #address-cells = <1>;
  323. #size-cells = <0>;
  324. cell-index = <1>;
  325. compatible = "fsl-i2c";
  326. reg = <0x118100 0x100>;
  327. interrupts = <38 2 0 0>;
  328. dfsrr;
  329. };
  330. i2c@119000 {
  331. #address-cells = <1>;
  332. #size-cells = <0>;
  333. cell-index = <2>;
  334. compatible = "fsl-i2c";
  335. reg = <0x119000 0x100>;
  336. interrupts = <39 2 0 0>;
  337. dfsrr;
  338. };
  339. i2c@119100 {
  340. #address-cells = <1>;
  341. #size-cells = <0>;
  342. cell-index = <3>;
  343. compatible = "fsl-i2c";
  344. reg = <0x119100 0x100>;
  345. interrupts = <39 2 0 0>;
  346. dfsrr;
  347. };
  348. serial0: serial@11c500 {
  349. cell-index = <0>;
  350. device_type = "serial";
  351. compatible = "ns16550";
  352. reg = <0x11c500 0x100>;
  353. clock-frequency = <0>;
  354. interrupts = <36 2 0 0>;
  355. };
  356. serial1: serial@11c600 {
  357. cell-index = <1>;
  358. device_type = "serial";
  359. compatible = "ns16550";
  360. reg = <0x11c600 0x100>;
  361. clock-frequency = <0>;
  362. interrupts = <36 2 0 0>;
  363. };
  364. serial2: serial@11d500 {
  365. cell-index = <2>;
  366. device_type = "serial";
  367. compatible = "ns16550";
  368. reg = <0x11d500 0x100>;
  369. clock-frequency = <0>;
  370. interrupts = <37 2 0 0>;
  371. };
  372. serial3: serial@11d600 {
  373. cell-index = <3>;
  374. device_type = "serial";
  375. compatible = "ns16550";
  376. reg = <0x11d600 0x100>;
  377. clock-frequency = <0>;
  378. interrupts = <37 2 0 0>;
  379. };
  380. gpio0: gpio@130000 {
  381. compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio";
  382. reg = <0x130000 0x1000>;
  383. interrupts = <55 2 0 0>;
  384. #gpio-cells = <2>;
  385. gpio-controller;
  386. };
  387. usb0: usb@210000 {
  388. compatible = "fsl,p2040-usb2-mph",
  389. "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  390. reg = <0x210000 0x1000>;
  391. #address-cells = <1>;
  392. #size-cells = <0>;
  393. interrupts = <44 0x2 0 0>;
  394. port0;
  395. };
  396. usb1: usb@211000 {
  397. compatible = "fsl,p2040-usb2-dr",
  398. "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  399. reg = <0x211000 0x1000>;
  400. #address-cells = <1>;
  401. #size-cells = <0>;
  402. interrupts = <45 0x2 0 0>;
  403. };
  404. sata@220000 {
  405. compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
  406. reg = <0x220000 0x1000>;
  407. interrupts = <68 0x2 0 0>;
  408. };
  409. sata@221000 {
  410. compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
  411. reg = <0x221000 0x1000>;
  412. interrupts = <69 0x2 0 0>;
  413. };
  414. crypto: crypto@300000 {
  415. compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
  416. #address-cells = <1>;
  417. #size-cells = <1>;
  418. reg = <0x300000 0x10000>;
  419. ranges = <0 0x300000 0x10000>;
  420. interrupts = <92 2 0 0>;
  421. sec_jr0: jr@1000 {
  422. compatible = "fsl,sec-v4.2-job-ring",
  423. "fsl,sec-v4.0-job-ring";
  424. reg = <0x1000 0x1000>;
  425. interrupts = <88 2 0 0>;
  426. };
  427. sec_jr1: jr@2000 {
  428. compatible = "fsl,sec-v4.2-job-ring",
  429. "fsl,sec-v4.0-job-ring";
  430. reg = <0x2000 0x1000>;
  431. interrupts = <89 2 0 0>;
  432. };
  433. sec_jr2: jr@3000 {
  434. compatible = "fsl,sec-v4.2-job-ring",
  435. "fsl,sec-v4.0-job-ring";
  436. reg = <0x3000 0x1000>;
  437. interrupts = <90 2 0 0>;
  438. };
  439. sec_jr3: jr@4000 {
  440. compatible = "fsl,sec-v4.2-job-ring",
  441. "fsl,sec-v4.0-job-ring";
  442. reg = <0x4000 0x1000>;
  443. interrupts = <91 2 0 0>;
  444. };
  445. rtic@6000 {
  446. compatible = "fsl,sec-v4.2-rtic",
  447. "fsl,sec-v4.0-rtic";
  448. #address-cells = <1>;
  449. #size-cells = <1>;
  450. reg = <0x6000 0x100>;
  451. ranges = <0x0 0x6100 0xe00>;
  452. rtic_a: rtic-a@0 {
  453. compatible = "fsl,sec-v4.2-rtic-memory",
  454. "fsl,sec-v4.0-rtic-memory";
  455. reg = <0x00 0x20 0x100 0x80>;
  456. };
  457. rtic_b: rtic-b@20 {
  458. compatible = "fsl,sec-v4.2-rtic-memory",
  459. "fsl,sec-v4.0-rtic-memory";
  460. reg = <0x20 0x20 0x200 0x80>;
  461. };
  462. rtic_c: rtic-c@40 {
  463. compatible = "fsl,sec-v4.2-rtic-memory",
  464. "fsl,sec-v4.0-rtic-memory";
  465. reg = <0x40 0x20 0x300 0x80>;
  466. };
  467. rtic_d: rtic-d@60 {
  468. compatible = "fsl,sec-v4.2-rtic-memory",
  469. "fsl,sec-v4.0-rtic-memory";
  470. reg = <0x60 0x20 0x500 0x80>;
  471. };
  472. };
  473. };
  474. sec_mon: sec_mon@314000 {
  475. compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
  476. reg = <0x314000 0x1000>;
  477. interrupts = <93 2 0 0>;
  478. };
  479. };
  480. localbus@ffe124000 {
  481. compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus";
  482. interrupts = <25 2 0 0>;
  483. #address-cells = <2>;
  484. #size-cells = <1>;
  485. };
  486. pci0: pcie@ffe200000 {
  487. compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
  488. device_type = "pci";
  489. #size-cells = <2>;
  490. #address-cells = <3>;
  491. bus-range = <0x0 0xff>;
  492. clock-frequency = <0x1fca055>;
  493. fsl,msi = <&msi0>;
  494. interrupts = <16 2 1 15>;
  495. pcie@0 {
  496. reg = <0 0 0 0 0>;
  497. #interrupt-cells = <1>;
  498. #size-cells = <2>;
  499. #address-cells = <3>;
  500. device_type = "pci";
  501. interrupts = <16 2 1 15>;
  502. interrupt-map-mask = <0xf800 0 0 7>;
  503. interrupt-map = <
  504. /* IDSEL 0x0 */
  505. 0000 0 0 1 &mpic 40 1 0 0
  506. 0000 0 0 2 &mpic 1 1 0 0
  507. 0000 0 0 3 &mpic 2 1 0 0
  508. 0000 0 0 4 &mpic 3 1 0 0
  509. >;
  510. };
  511. };
  512. pci1: pcie@ffe201000 {
  513. compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
  514. device_type = "pci";
  515. #size-cells = <2>;
  516. #address-cells = <3>;
  517. bus-range = <0 0xff>;
  518. clock-frequency = <0x1fca055>;
  519. fsl,msi = <&msi1>;
  520. interrupts = <16 2 1 14>;
  521. pcie@0 {
  522. reg = <0 0 0 0 0>;
  523. #interrupt-cells = <1>;
  524. #size-cells = <2>;
  525. #address-cells = <3>;
  526. device_type = "pci";
  527. interrupts = <16 2 1 14>;
  528. interrupt-map-mask = <0xf800 0 0 7>;
  529. interrupt-map = <
  530. /* IDSEL 0x0 */
  531. 0000 0 0 1 &mpic 41 1 0 0
  532. 0000 0 0 2 &mpic 5 1 0 0
  533. 0000 0 0 3 &mpic 6 1 0 0
  534. 0000 0 0 4 &mpic 7 1 0 0
  535. >;
  536. };
  537. };
  538. pci2: pcie@ffe202000 {
  539. compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
  540. device_type = "pci";
  541. #size-cells = <2>;
  542. #address-cells = <3>;
  543. bus-range = <0x0 0xff>;
  544. clock-frequency = <0x1fca055>;
  545. fsl,msi = <&msi2>;
  546. interrupts = <16 2 1 13>;
  547. pcie@0 {
  548. reg = <0 0 0 0 0>;
  549. #interrupt-cells = <1>;
  550. #size-cells = <2>;
  551. #address-cells = <3>;
  552. device_type = "pci";
  553. interrupts = <16 2 1 13>;
  554. interrupt-map-mask = <0xf800 0 0 7>;
  555. interrupt-map = <
  556. /* IDSEL 0x0 */
  557. 0000 0 0 1 &mpic 42 1 0 0
  558. 0000 0 0 2 &mpic 9 1 0 0
  559. 0000 0 0 3 &mpic 10 1 0 0
  560. 0000 0 0 4 &mpic 11 1 0 0
  561. >;
  562. };
  563. };
  564. };