p1010rdb.dts 6.0 KB

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  1. /*
  2. * P1010 RDB Device Tree Source
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /include/ "p1010si.dtsi"
  12. / {
  13. model = "fsl,P1010RDB";
  14. compatible = "fsl,P1010RDB";
  15. aliases {
  16. serial0 = &serial0;
  17. serial1 = &serial1;
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. ethernet2 = &enet2;
  21. pci0 = &pci0;
  22. pci1 = &pci1;
  23. };
  24. memory {
  25. device_type = "memory";
  26. };
  27. ifc@ffe1e000 {
  28. /* NOR, NAND Flashes and CPLD on board */
  29. ranges = <0x0 0x0 0x0 0xee000000 0x02000000
  30. 0x1 0x0 0x0 0xff800000 0x00010000
  31. 0x3 0x0 0x0 0xffb00000 0x00000020>;
  32. nor@0,0 {
  33. #address-cells = <1>;
  34. #size-cells = <1>;
  35. compatible = "cfi-flash";
  36. reg = <0x0 0x0 0x2000000>;
  37. bank-width = <2>;
  38. device-width = <1>;
  39. partition@40000 {
  40. /* 256KB for DTB Image */
  41. reg = <0x00040000 0x00040000>;
  42. label = "NOR DTB Image";
  43. };
  44. partition@80000 {
  45. /* 7 MB for Linux Kernel Image */
  46. reg = <0x00080000 0x00700000>;
  47. label = "NOR Linux Kernel Image";
  48. };
  49. partition@800000 {
  50. /* 20MB for JFFS2 based Root file System */
  51. reg = <0x00800000 0x01400000>;
  52. label = "NOR JFFS2 Root File System";
  53. };
  54. partition@1f00000 {
  55. /* This location must not be altered */
  56. /* 512KB for u-boot Bootloader Image */
  57. /* 512KB for u-boot Environment Variables */
  58. reg = <0x01f00000 0x00100000>;
  59. label = "NOR U-Boot Image";
  60. read-only;
  61. };
  62. };
  63. nand@1,0 {
  64. #address-cells = <1>;
  65. #size-cells = <1>;
  66. compatible = "fsl,ifc-nand";
  67. reg = <0x1 0x0 0x10000>;
  68. partition@0 {
  69. /* This location must not be altered */
  70. /* 1MB for u-boot Bootloader Image */
  71. reg = <0x0 0x00100000>;
  72. label = "NAND U-Boot Image";
  73. read-only;
  74. };
  75. partition@100000 {
  76. /* 1MB for DTB Image */
  77. reg = <0x00100000 0x00100000>;
  78. label = "NAND DTB Image";
  79. };
  80. partition@200000 {
  81. /* 4MB for Linux Kernel Image */
  82. reg = <0x00200000 0x00400000>;
  83. label = "NAND Linux Kernel Image";
  84. };
  85. partition@600000 {
  86. /* 4MB for Compressed Root file System Image */
  87. reg = <0x00600000 0x00400000>;
  88. label = "NAND Compressed RFS Image";
  89. };
  90. partition@a00000 {
  91. /* 15MB for JFFS2 based Root file System */
  92. reg = <0x00a00000 0x00f00000>;
  93. label = "NAND JFFS2 Root File System";
  94. };
  95. partition@1900000 {
  96. /* 7MB for User Area */
  97. reg = <0x01900000 0x00700000>;
  98. label = "NAND User area";
  99. };
  100. };
  101. cpld@3,0 {
  102. #address-cells = <1>;
  103. #size-cells = <1>;
  104. compatible = "fsl,p1010rdb-cpld";
  105. reg = <0x3 0x0 0x0000020>;
  106. bank-width = <1>;
  107. device-width = <1>;
  108. };
  109. };
  110. soc@ffe00000 {
  111. spi@7000 {
  112. flash@0 {
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. compatible = "spansion,s25sl12801";
  116. reg = <0>;
  117. spi-max-frequency = <50000000>;
  118. partition@0 {
  119. /* 1MB for u-boot Bootloader Image */
  120. /* 1MB for Environment */
  121. reg = <0x0 0x00100000>;
  122. label = "SPI Flash U-Boot Image";
  123. read-only;
  124. };
  125. partition@100000 {
  126. /* 512KB for DTB Image */
  127. reg = <0x00100000 0x00080000>;
  128. label = "SPI Flash DTB Image";
  129. };
  130. partition@180000 {
  131. /* 4MB for Linux Kernel Image */
  132. reg = <0x00180000 0x00400000>;
  133. label = "SPI Flash Linux Kernel Image";
  134. };
  135. partition@580000 {
  136. /* 4MB for Compressed RFS Image */
  137. reg = <0x00580000 0x00400000>;
  138. label = "SPI Flash Compressed RFSImage";
  139. };
  140. partition@980000 {
  141. /* 6.5MB for JFFS2 based RFS */
  142. reg = <0x00980000 0x00680000>;
  143. label = "SPI Flash JFFS2 RFS";
  144. };
  145. };
  146. };
  147. can0@1c000 {
  148. fsl,flexcan-clock-source = "platform";
  149. };
  150. can1@1d000 {
  151. fsl,flexcan-clock-source = "platform";
  152. };
  153. usb@22000 {
  154. phy_type = "utmi";
  155. };
  156. mdio@24000 {
  157. phy0: ethernet-phy@0 {
  158. interrupt-parent = <&mpic>;
  159. interrupts = <3 1>;
  160. reg = <0x1>;
  161. };
  162. phy1: ethernet-phy@1 {
  163. interrupt-parent = <&mpic>;
  164. interrupts = <2 1>;
  165. reg = <0x0>;
  166. };
  167. phy2: ethernet-phy@2 {
  168. interrupt-parent = <&mpic>;
  169. interrupts = <2 1>;
  170. reg = <0x2>;
  171. };
  172. };
  173. enet0: ethernet@b0000 {
  174. phy-handle = <&phy0>;
  175. phy-connection-type = "rgmii-id";
  176. };
  177. enet1: ethernet@b1000 {
  178. phy-handle = <&phy1>;
  179. tbi-handle = <&tbi0>;
  180. phy-connection-type = "sgmii";
  181. };
  182. enet2: ethernet@b2000 {
  183. phy-handle = <&phy2>;
  184. tbi-handle = <&tbi1>;
  185. phy-connection-type = "sgmii";
  186. };
  187. };
  188. pci0: pcie@ffe09000 {
  189. ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
  190. 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
  191. pcie@0 {
  192. reg = <0x0 0x0 0x0 0x0 0x0>;
  193. #interrupt-cells = <1>;
  194. #size-cells = <2>;
  195. #address-cells = <3>;
  196. device_type = "pci";
  197. interrupt-parent = <&mpic>;
  198. interrupts = <16 2>;
  199. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  200. interrupt-map = <
  201. /* IDSEL 0x0 */
  202. 0000 0x0 0x0 0x1 &mpic 0x4 0x1
  203. 0000 0x0 0x0 0x2 &mpic 0x5 0x1
  204. 0000 0x0 0x0 0x3 &mpic 0x6 0x1
  205. 0000 0x0 0x0 0x4 &mpic 0x7 0x1
  206. >;
  207. ranges = <0x2000000 0x0 0xa0000000
  208. 0x2000000 0x0 0xa0000000
  209. 0x0 0x20000000
  210. 0x1000000 0x0 0x0
  211. 0x1000000 0x0 0x0
  212. 0x0 0x100000>;
  213. };
  214. };
  215. pci1: pcie@ffe0a000 {
  216. ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
  217. 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
  218. pcie@0 {
  219. reg = <0x0 0x0 0x0 0x0 0x0>;
  220. #interrupt-cells = <1>;
  221. #size-cells = <2>;
  222. #address-cells = <3>;
  223. device_type = "pci";
  224. interrupt-parent = <&mpic>;
  225. interrupts = <16 2>;
  226. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  227. interrupt-map = <
  228. /* IDSEL 0x0 */
  229. 0000 0x0 0x0 0x1 &mpic 0x4 0x1
  230. 0000 0x0 0x0 0x2 &mpic 0x5 0x1
  231. 0000 0x0 0x0 0x3 &mpic 0x6 0x1
  232. 0000 0x0 0x0 0x4 &mpic 0x7 0x1
  233. >;
  234. ranges = <0x2000000 0x0 0x80000000
  235. 0x2000000 0x0 0x80000000
  236. 0x0 0x20000000
  237. 0x1000000 0x0 0x0
  238. 0x1000000 0x0 0x0
  239. 0x0 0x100000>;
  240. };
  241. };
  242. };