fsl-flexcan.txt 2.2 KB

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  1. CAN Device Tree Bindings
  2. ------------------------
  3. 2011 Freescale Semiconductor, Inc.
  4. fsl,flexcan-v1.0 nodes
  5. -----------------------
  6. In addition to the required compatible-, reg- and interrupt-properties, you can
  7. also specify which clock source shall be used for the controller.
  8. CPI Clock- Can Protocol Interface Clock
  9. This CLK_SRC bit of CTRL(control register) selects the clock source to
  10. the CAN Protocol Interface(CPI) to be either the peripheral clock
  11. (driven by the PLL) or the crystal oscillator clock. The selected clock
  12. is the one fed to the prescaler to generate the Serial Clock (Sclock).
  13. The PRESDIV field of CTRL(control register) controls a prescaler that
  14. generates the Serial Clock (Sclock), whose period defines the
  15. time quantum used to compose the CAN waveform.
  16. Can Engine Clock Source
  17. There are two sources for CAN clock
  18. - Platform Clock It represents the bus clock
  19. - Oscillator Clock
  20. Peripheral Clock (PLL)
  21. --------------
  22. |
  23. --------- -------------
  24. | |CPI Clock | Prescaler | Sclock
  25. | |---------------->| (1.. 256) |------------>
  26. --------- -------------
  27. | |
  28. -------------- ---------------------CLK_SRC
  29. Oscillator Clock
  30. - fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
  31. the peripheral clock. PLL clock is fed to the
  32. prescaler to generate the Serial Clock (Sclock).
  33. Valid values are "oscillator" and "platform"
  34. "oscillator": CAN engine clock source is oscillator clock.
  35. "platform" The CAN engine clock source is the bus clock
  36. (platform clock).
  37. - fsl,flexcan-clock-divider : for the reference and system clock, an additional
  38. clock divider can be specified.
  39. - clock-frequency: frequency required to calculate the bitrate for FlexCAN.
  40. Note:
  41. - v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
  42. - P1010 does not have oscillator as the Clock Source.So the default
  43. Clock Source is platform clock.
  44. Examples:
  45. can0@1c000 {
  46. compatible = "fsl,flexcan-v1.0";
  47. reg = <0x1c000 0x1000>;
  48. interrupts = <48 0x2>;
  49. interrupt-parent = <&mpic>;
  50. fsl,flexcan-clock-source = "platform";
  51. fsl,flexcan-clock-divider = <2>;
  52. clock-frequency = <fixed by u-boot>;
  53. };