musb_dsps.c 21 KB

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  1. /*
  2. * Texas Instruments DSPS platforms "glue layer"
  3. *
  4. * Copyright (C) 2012, by Texas Instruments
  5. *
  6. * Based on the am35x "glue layer" code.
  7. *
  8. * This file is part of the Inventra Controller Driver for Linux.
  9. *
  10. * The Inventra Controller Driver for Linux is free software; you
  11. * can redistribute it and/or modify it under the terms of the GNU
  12. * General Public License version 2 as published by the Free Software
  13. * Foundation.
  14. *
  15. * The Inventra Controller Driver for Linux is distributed in
  16. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  17. * without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  19. * License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with The Inventra Controller Driver for Linux ; if not,
  23. * write to the Free Software Foundation, Inc., 59 Temple Place,
  24. * Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. * musb_dsps.c will be a common file for all the TI DSPS platforms
  27. * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
  28. * For now only ti81x is using this and in future davinci.c, am35x.c
  29. * da8xx.c would be merged to this file after testing.
  30. */
  31. #include <linux/init.h>
  32. #include <linux/io.h>
  33. #include <linux/of.h>
  34. #include <linux/err.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/pm_runtime.h>
  38. #include <linux/module.h>
  39. #include <linux/usb/nop-usb-xceiv.h>
  40. #include <linux/of.h>
  41. #include <linux/of_device.h>
  42. #include <linux/of_address.h>
  43. #include <plat/usb.h>
  44. #include "musb_core.h"
  45. #ifdef CONFIG_OF
  46. static const struct of_device_id musb_dsps_of_match[];
  47. #endif
  48. /**
  49. * avoid using musb_readx()/musb_writex() as glue layer should not be
  50. * dependent on musb core layer symbols.
  51. */
  52. static inline u8 dsps_readb(const void __iomem *addr, unsigned offset)
  53. { return __raw_readb(addr + offset); }
  54. static inline u32 dsps_readl(const void __iomem *addr, unsigned offset)
  55. { return __raw_readl(addr + offset); }
  56. static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data)
  57. { __raw_writeb(data, addr + offset); }
  58. static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data)
  59. { __raw_writel(data, addr + offset); }
  60. /**
  61. * DSPS musb wrapper register offset.
  62. * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
  63. * musb ips.
  64. */
  65. struct dsps_musb_wrapper {
  66. u16 revision;
  67. u16 control;
  68. u16 status;
  69. u16 eoi;
  70. u16 epintr_set;
  71. u16 epintr_clear;
  72. u16 epintr_status;
  73. u16 coreintr_set;
  74. u16 coreintr_clear;
  75. u16 coreintr_status;
  76. u16 phy_utmi;
  77. u16 mode;
  78. /* bit positions for control */
  79. unsigned reset:5;
  80. /* bit positions for interrupt */
  81. unsigned usb_shift:5;
  82. u32 usb_mask;
  83. u32 usb_bitmap;
  84. unsigned drvvbus:5;
  85. unsigned txep_shift:5;
  86. u32 txep_mask;
  87. u32 txep_bitmap;
  88. unsigned rxep_shift:5;
  89. u32 rxep_mask;
  90. u32 rxep_bitmap;
  91. /* bit positions for phy_utmi */
  92. unsigned otg_disable:5;
  93. /* bit positions for mode */
  94. unsigned iddig:5;
  95. /* miscellaneous stuff */
  96. u32 musb_core_offset;
  97. u8 poll_seconds;
  98. /* number of musb instances */
  99. u8 instances;
  100. };
  101. /**
  102. * DSPS glue structure.
  103. */
  104. struct dsps_glue {
  105. struct device *dev;
  106. struct platform_device *musb[2]; /* child musb pdev */
  107. const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
  108. struct timer_list timer[2]; /* otg_workaround timer */
  109. unsigned long last_timer[2]; /* last timer data for each instance */
  110. };
  111. /**
  112. * dsps_musb_enable - enable interrupts
  113. */
  114. static void dsps_musb_enable(struct musb *musb)
  115. {
  116. struct device *dev = musb->controller;
  117. struct platform_device *pdev = to_platform_device(dev->parent);
  118. struct dsps_glue *glue = platform_get_drvdata(pdev);
  119. const struct dsps_musb_wrapper *wrp = glue->wrp;
  120. void __iomem *reg_base = musb->ctrl_base;
  121. u32 epmask, coremask;
  122. /* Workaround: setup IRQs through both register sets. */
  123. epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
  124. ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
  125. coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
  126. dsps_writel(reg_base, wrp->epintr_set, epmask);
  127. dsps_writel(reg_base, wrp->coreintr_set, coremask);
  128. /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  129. dsps_writel(reg_base, wrp->coreintr_set,
  130. (1 << wrp->drvvbus) << wrp->usb_shift);
  131. }
  132. /**
  133. * dsps_musb_disable - disable HDRC and flush interrupts
  134. */
  135. static void dsps_musb_disable(struct musb *musb)
  136. {
  137. struct device *dev = musb->controller;
  138. struct platform_device *pdev = to_platform_device(dev->parent);
  139. struct dsps_glue *glue = platform_get_drvdata(pdev);
  140. const struct dsps_musb_wrapper *wrp = glue->wrp;
  141. void __iomem *reg_base = musb->ctrl_base;
  142. dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
  143. dsps_writel(reg_base, wrp->epintr_clear,
  144. wrp->txep_bitmap | wrp->rxep_bitmap);
  145. dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
  146. dsps_writel(reg_base, wrp->eoi, 0);
  147. }
  148. static void otg_timer(unsigned long _musb)
  149. {
  150. struct musb *musb = (void *)_musb;
  151. void __iomem *mregs = musb->mregs;
  152. struct device *dev = musb->controller;
  153. struct platform_device *pdev = to_platform_device(dev);
  154. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  155. const struct dsps_musb_wrapper *wrp = glue->wrp;
  156. u8 devctl;
  157. unsigned long flags;
  158. /*
  159. * We poll because DSPS IP's won't expose several OTG-critical
  160. * status change events (from the transceiver) otherwise.
  161. */
  162. devctl = dsps_readb(mregs, MUSB_DEVCTL);
  163. dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
  164. otg_state_string(musb->xceiv->state));
  165. spin_lock_irqsave(&musb->lock, flags);
  166. switch (musb->xceiv->state) {
  167. case OTG_STATE_A_WAIT_BCON:
  168. devctl &= ~MUSB_DEVCTL_SESSION;
  169. dsps_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  170. devctl = dsps_readb(musb->mregs, MUSB_DEVCTL);
  171. if (devctl & MUSB_DEVCTL_BDEVICE) {
  172. musb->xceiv->state = OTG_STATE_B_IDLE;
  173. MUSB_DEV_MODE(musb);
  174. } else {
  175. musb->xceiv->state = OTG_STATE_A_IDLE;
  176. MUSB_HST_MODE(musb);
  177. }
  178. break;
  179. case OTG_STATE_A_WAIT_VFALL:
  180. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  181. dsps_writel(musb->ctrl_base, wrp->coreintr_set,
  182. MUSB_INTR_VBUSERROR << wrp->usb_shift);
  183. break;
  184. case OTG_STATE_B_IDLE:
  185. devctl = dsps_readb(mregs, MUSB_DEVCTL);
  186. if (devctl & MUSB_DEVCTL_BDEVICE)
  187. mod_timer(&glue->timer[pdev->id],
  188. jiffies + wrp->poll_seconds * HZ);
  189. else
  190. musb->xceiv->state = OTG_STATE_A_IDLE;
  191. break;
  192. default:
  193. break;
  194. }
  195. spin_unlock_irqrestore(&musb->lock, flags);
  196. }
  197. static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout)
  198. {
  199. struct device *dev = musb->controller;
  200. struct platform_device *pdev = to_platform_device(dev);
  201. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  202. if (timeout == 0)
  203. timeout = jiffies + msecs_to_jiffies(3);
  204. /* Never idle if active, or when VBUS timeout is not set as host */
  205. if (musb->is_active || (musb->a_wait_bcon == 0 &&
  206. musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
  207. dev_dbg(musb->controller, "%s active, deleting timer\n",
  208. otg_state_string(musb->xceiv->state));
  209. del_timer(&glue->timer[pdev->id]);
  210. glue->last_timer[pdev->id] = jiffies;
  211. return;
  212. }
  213. if (time_after(glue->last_timer[pdev->id], timeout) &&
  214. timer_pending(&glue->timer[pdev->id])) {
  215. dev_dbg(musb->controller,
  216. "Longer idle timer already pending, ignoring...\n");
  217. return;
  218. }
  219. glue->last_timer[pdev->id] = timeout;
  220. dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
  221. otg_state_string(musb->xceiv->state),
  222. jiffies_to_msecs(timeout - jiffies));
  223. mod_timer(&glue->timer[pdev->id], timeout);
  224. }
  225. static irqreturn_t dsps_interrupt(int irq, void *hci)
  226. {
  227. struct musb *musb = hci;
  228. void __iomem *reg_base = musb->ctrl_base;
  229. struct device *dev = musb->controller;
  230. struct platform_device *pdev = to_platform_device(dev);
  231. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  232. const struct dsps_musb_wrapper *wrp = glue->wrp;
  233. unsigned long flags;
  234. irqreturn_t ret = IRQ_NONE;
  235. u32 epintr, usbintr;
  236. spin_lock_irqsave(&musb->lock, flags);
  237. /* Get endpoint interrupts */
  238. epintr = dsps_readl(reg_base, wrp->epintr_status);
  239. musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
  240. musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
  241. if (epintr)
  242. dsps_writel(reg_base, wrp->epintr_status, epintr);
  243. /* Get usb core interrupts */
  244. usbintr = dsps_readl(reg_base, wrp->coreintr_status);
  245. if (!usbintr && !epintr)
  246. goto eoi;
  247. musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
  248. if (usbintr)
  249. dsps_writel(reg_base, wrp->coreintr_status, usbintr);
  250. dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
  251. usbintr, epintr);
  252. /*
  253. * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
  254. * DSPS IP's missing ID change IRQ. We need an ID change IRQ to
  255. * switch appropriately between halves of the OTG state machine.
  256. * Managing DEVCTL.SESSION per Mentor docs requires that we know its
  257. * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
  258. * Also, DRVVBUS pulses for SRP (but not at 5V) ...
  259. */
  260. if (usbintr & MUSB_INTR_BABBLE)
  261. pr_info("CAUTION: musb: Babble Interrupt Occured\n");
  262. if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
  263. int drvvbus = dsps_readl(reg_base, wrp->status);
  264. void __iomem *mregs = musb->mregs;
  265. u8 devctl = dsps_readb(mregs, MUSB_DEVCTL);
  266. int err;
  267. err = musb->int_usb & MUSB_INTR_VBUSERROR;
  268. if (err) {
  269. /*
  270. * The Mentor core doesn't debounce VBUS as needed
  271. * to cope with device connect current spikes. This
  272. * means it's not uncommon for bus-powered devices
  273. * to get VBUS errors during enumeration.
  274. *
  275. * This is a workaround, but newer RTL from Mentor
  276. * seems to allow a better one: "re"-starting sessions
  277. * without waiting for VBUS to stop registering in
  278. * devctl.
  279. */
  280. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  281. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  282. mod_timer(&glue->timer[pdev->id],
  283. jiffies + wrp->poll_seconds * HZ);
  284. WARNING("VBUS error workaround (delay coming)\n");
  285. } else if (drvvbus) {
  286. musb->is_active = 1;
  287. MUSB_HST_MODE(musb);
  288. musb->xceiv->otg->default_a = 1;
  289. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  290. del_timer(&glue->timer[pdev->id]);
  291. } else {
  292. musb->is_active = 0;
  293. MUSB_DEV_MODE(musb);
  294. musb->xceiv->otg->default_a = 0;
  295. musb->xceiv->state = OTG_STATE_B_IDLE;
  296. }
  297. /* NOTE: this must complete power-on within 100 ms. */
  298. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  299. drvvbus ? "on" : "off",
  300. otg_state_string(musb->xceiv->state),
  301. err ? " ERROR" : "",
  302. devctl);
  303. ret = IRQ_HANDLED;
  304. }
  305. if (musb->int_tx || musb->int_rx || musb->int_usb)
  306. ret |= musb_interrupt(musb);
  307. eoi:
  308. /* EOI needs to be written for the IRQ to be re-asserted. */
  309. if (ret == IRQ_HANDLED || epintr || usbintr)
  310. dsps_writel(reg_base, wrp->eoi, 1);
  311. /* Poll for ID change */
  312. if (musb->xceiv->state == OTG_STATE_B_IDLE)
  313. mod_timer(&glue->timer[pdev->id],
  314. jiffies + wrp->poll_seconds * HZ);
  315. spin_unlock_irqrestore(&musb->lock, flags);
  316. return ret;
  317. }
  318. static int dsps_musb_init(struct musb *musb)
  319. {
  320. struct device *dev = musb->controller;
  321. struct musb_hdrc_platform_data *plat = dev->platform_data;
  322. struct platform_device *pdev = to_platform_device(dev);
  323. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  324. const struct dsps_musb_wrapper *wrp = glue->wrp;
  325. struct omap_musb_board_data *data = plat->board_data;
  326. void __iomem *reg_base = musb->ctrl_base;
  327. u32 rev, val;
  328. int status;
  329. /* mentor core register starts at offset of 0x400 from musb base */
  330. musb->mregs += wrp->musb_core_offset;
  331. /* Get the NOP PHY */
  332. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  333. if (IS_ERR_OR_NULL(musb->xceiv))
  334. return -ENODEV;
  335. /* Returns zero if e.g. not clocked */
  336. rev = dsps_readl(reg_base, wrp->revision);
  337. if (!rev) {
  338. status = -ENODEV;
  339. goto err0;
  340. }
  341. setup_timer(&glue->timer[pdev->id], otg_timer, (unsigned long) musb);
  342. /* Reset the musb */
  343. dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
  344. /* Start the on-chip PHY and its PLL. */
  345. if (data->set_phy_power)
  346. data->set_phy_power(1);
  347. musb->isr = dsps_interrupt;
  348. /* reset the otgdisable bit, needed for host mode to work */
  349. val = dsps_readl(reg_base, wrp->phy_utmi);
  350. val &= ~(1 << wrp->otg_disable);
  351. dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
  352. /* clear level interrupt */
  353. dsps_writel(reg_base, wrp->eoi, 0);
  354. return 0;
  355. err0:
  356. usb_put_phy(musb->xceiv);
  357. usb_nop_xceiv_unregister();
  358. return status;
  359. }
  360. static int dsps_musb_exit(struct musb *musb)
  361. {
  362. struct device *dev = musb->controller;
  363. struct musb_hdrc_platform_data *plat = dev->platform_data;
  364. struct omap_musb_board_data *data = plat->board_data;
  365. struct platform_device *pdev = to_platform_device(dev);
  366. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  367. del_timer_sync(&glue->timer[pdev->id]);
  368. /* Shutdown the on-chip PHY and its PLL. */
  369. if (data->set_phy_power)
  370. data->set_phy_power(0);
  371. /* NOP driver needs change if supporting dual instance */
  372. usb_put_phy(musb->xceiv);
  373. usb_nop_xceiv_unregister();
  374. return 0;
  375. }
  376. static struct musb_platform_ops dsps_ops = {
  377. .init = dsps_musb_init,
  378. .exit = dsps_musb_exit,
  379. .enable = dsps_musb_enable,
  380. .disable = dsps_musb_disable,
  381. .try_idle = dsps_musb_try_idle,
  382. };
  383. static u64 musb_dmamask = DMA_BIT_MASK(32);
  384. static int __devinit dsps_create_musb_pdev(struct dsps_glue *glue, u8 id)
  385. {
  386. struct device *dev = glue->dev;
  387. struct platform_device *pdev = to_platform_device(dev);
  388. struct musb_hdrc_platform_data *pdata = dev->platform_data;
  389. struct device_node *np = pdev->dev.of_node;
  390. struct musb_hdrc_config *config;
  391. struct platform_device *musb;
  392. struct resource *res;
  393. struct resource resources[2];
  394. char res_name[11];
  395. int ret, musbid;
  396. /* get memory resource */
  397. snprintf(res_name, sizeof(res_name), "musb%d", id);
  398. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
  399. if (!res) {
  400. dev_err(dev, "%s get mem resource failed\n", res_name);
  401. ret = -ENODEV;
  402. goto err0;
  403. }
  404. res->parent = NULL;
  405. resources[0] = *res;
  406. /* get irq resource */
  407. snprintf(res_name, sizeof(res_name), "musb%d-irq", id);
  408. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
  409. if (!res) {
  410. dev_err(dev, "%s get irq resource failed\n", res_name);
  411. ret = -ENODEV;
  412. goto err0;
  413. }
  414. res->parent = NULL;
  415. resources[1] = *res;
  416. resources[1].name = "mc";
  417. /* get the musb id */
  418. musbid = musb_get_id(dev, GFP_KERNEL);
  419. if (musbid < 0) {
  420. dev_err(dev, "failed to allocate musb id\n");
  421. ret = -ENOMEM;
  422. goto err0;
  423. }
  424. /* allocate the child platform device */
  425. musb = platform_device_alloc("musb-hdrc", musbid);
  426. if (!musb) {
  427. dev_err(dev, "failed to allocate musb device\n");
  428. ret = -ENOMEM;
  429. goto err1;
  430. }
  431. musb->id = musbid;
  432. musb->dev.parent = dev;
  433. musb->dev.dma_mask = &musb_dmamask;
  434. musb->dev.coherent_dma_mask = musb_dmamask;
  435. glue->musb[id] = musb;
  436. ret = platform_device_add_resources(musb, resources, 2);
  437. if (ret) {
  438. dev_err(dev, "failed to add resources\n");
  439. goto err2;
  440. }
  441. if (np) {
  442. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  443. if (!pdata) {
  444. dev_err(&pdev->dev,
  445. "failed to allocate musb platfrom data\n");
  446. ret = -ENOMEM;
  447. goto err2;
  448. }
  449. config = devm_kzalloc(&pdev->dev, sizeof(*config), GFP_KERNEL);
  450. if (!config) {
  451. dev_err(&pdev->dev,
  452. "failed to allocate musb hdrc config\n");
  453. goto err2;
  454. }
  455. of_property_read_u32(np, "num-eps", (u32 *)&config->num_eps);
  456. of_property_read_u32(np, "ram-bits", (u32 *)&config->ram_bits);
  457. snprintf(res_name, sizeof(res_name), "port%d-mode", id);
  458. of_property_read_u32(np, res_name, (u32 *)&pdata->mode);
  459. of_property_read_u32(np, "power", (u32 *)&pdata->power);
  460. config->multipoint = of_property_read_bool(np, "multipoint");
  461. pdata->config = config;
  462. }
  463. pdata->platform_ops = &dsps_ops;
  464. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  465. if (ret) {
  466. dev_err(dev, "failed to add platform_data\n");
  467. goto err2;
  468. }
  469. ret = platform_device_add(musb);
  470. if (ret) {
  471. dev_err(dev, "failed to register musb device\n");
  472. goto err2;
  473. }
  474. return 0;
  475. err2:
  476. platform_device_put(musb);
  477. err1:
  478. musb_put_id(dev, musbid);
  479. err0:
  480. return ret;
  481. }
  482. static void dsps_delete_musb_pdev(struct dsps_glue *glue, u8 id)
  483. {
  484. musb_put_id(glue->dev, glue->musb[id]->id);
  485. platform_device_del(glue->musb[id]);
  486. platform_device_put(glue->musb[id]);
  487. }
  488. static int __devinit dsps_probe(struct platform_device *pdev)
  489. {
  490. struct device_node *np = pdev->dev.of_node;
  491. const struct of_device_id *match;
  492. const struct dsps_musb_wrapper *wrp;
  493. struct dsps_glue *glue;
  494. struct resource *iomem;
  495. int ret, i;
  496. match = of_match_node(musb_dsps_of_match, np);
  497. if (!match) {
  498. dev_err(&pdev->dev, "fail to get matching of_match struct\n");
  499. ret = -EINVAL;
  500. goto err0;
  501. }
  502. wrp = match->data;
  503. /* allocate glue */
  504. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  505. if (!glue) {
  506. dev_err(&pdev->dev, "unable to allocate glue memory\n");
  507. ret = -ENOMEM;
  508. goto err0;
  509. }
  510. /* get memory resource */
  511. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  512. if (!iomem) {
  513. dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
  514. ret = -ENODEV;
  515. goto err1;
  516. }
  517. glue->dev = &pdev->dev;
  518. glue->wrp = kmemdup(wrp, sizeof(*wrp), GFP_KERNEL);
  519. if (!glue->wrp) {
  520. dev_err(&pdev->dev, "failed to duplicate wrapper struct memory\n");
  521. ret = -ENOMEM;
  522. goto err1;
  523. }
  524. platform_set_drvdata(pdev, glue);
  525. /* enable the usbss clocks */
  526. pm_runtime_enable(&pdev->dev);
  527. ret = pm_runtime_get_sync(&pdev->dev);
  528. if (ret < 0) {
  529. dev_err(&pdev->dev, "pm_runtime_get_sync FAILED");
  530. goto err2;
  531. }
  532. /* create the child platform device for all instances of musb */
  533. for (i = 0; i < wrp->instances ; i++) {
  534. ret = dsps_create_musb_pdev(glue, i);
  535. if (ret != 0) {
  536. dev_err(&pdev->dev, "failed to create child pdev\n");
  537. /* release resources of previously created instances */
  538. for (i--; i >= 0 ; i--)
  539. dsps_delete_musb_pdev(glue, i);
  540. goto err3;
  541. }
  542. }
  543. return 0;
  544. err3:
  545. pm_runtime_put(&pdev->dev);
  546. err2:
  547. pm_runtime_disable(&pdev->dev);
  548. kfree(glue->wrp);
  549. err1:
  550. kfree(glue);
  551. err0:
  552. return ret;
  553. }
  554. static int __devexit dsps_remove(struct platform_device *pdev)
  555. {
  556. struct dsps_glue *glue = platform_get_drvdata(pdev);
  557. const struct dsps_musb_wrapper *wrp = glue->wrp;
  558. int i;
  559. /* delete the child platform device */
  560. for (i = 0; i < wrp->instances ; i++)
  561. dsps_delete_musb_pdev(glue, i);
  562. /* disable usbss clocks */
  563. pm_runtime_put(&pdev->dev);
  564. pm_runtime_disable(&pdev->dev);
  565. kfree(glue->wrp);
  566. kfree(glue);
  567. return 0;
  568. }
  569. #ifdef CONFIG_PM_SLEEP
  570. static int dsps_suspend(struct device *dev)
  571. {
  572. struct musb_hdrc_platform_data *plat = dev->platform_data;
  573. struct omap_musb_board_data *data = plat->board_data;
  574. /* Shutdown the on-chip PHY and its PLL. */
  575. if (data->set_phy_power)
  576. data->set_phy_power(0);
  577. return 0;
  578. }
  579. static int dsps_resume(struct device *dev)
  580. {
  581. struct musb_hdrc_platform_data *plat = dev->platform_data;
  582. struct omap_musb_board_data *data = plat->board_data;
  583. /* Start the on-chip PHY and its PLL. */
  584. if (data->set_phy_power)
  585. data->set_phy_power(1);
  586. return 0;
  587. }
  588. #endif
  589. static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
  590. static const struct dsps_musb_wrapper ti81xx_driver_data __devinitconst = {
  591. .revision = 0x00,
  592. .control = 0x14,
  593. .status = 0x18,
  594. .eoi = 0x24,
  595. .epintr_set = 0x38,
  596. .epintr_clear = 0x40,
  597. .epintr_status = 0x30,
  598. .coreintr_set = 0x3c,
  599. .coreintr_clear = 0x44,
  600. .coreintr_status = 0x34,
  601. .phy_utmi = 0xe0,
  602. .mode = 0xe8,
  603. .reset = 0,
  604. .otg_disable = 21,
  605. .iddig = 8,
  606. .usb_shift = 0,
  607. .usb_mask = 0x1ff,
  608. .usb_bitmap = (0x1ff << 0),
  609. .drvvbus = 8,
  610. .txep_shift = 0,
  611. .txep_mask = 0xffff,
  612. .txep_bitmap = (0xffff << 0),
  613. .rxep_shift = 16,
  614. .rxep_mask = 0xfffe,
  615. .rxep_bitmap = (0xfffe << 16),
  616. .musb_core_offset = 0x400,
  617. .poll_seconds = 2,
  618. .instances = 2,
  619. };
  620. static const struct platform_device_id musb_dsps_id_table[] __devinitconst = {
  621. {
  622. .name = "musb-ti81xx",
  623. .driver_data = (kernel_ulong_t) &ti81xx_driver_data,
  624. },
  625. { }, /* Terminating Entry */
  626. };
  627. MODULE_DEVICE_TABLE(platform, musb_dsps_id_table);
  628. #ifdef CONFIG_OF
  629. static const struct of_device_id musb_dsps_of_match[] __devinitconst = {
  630. { .compatible = "ti,musb-am33xx",
  631. .data = (void *) &ti81xx_driver_data, },
  632. { },
  633. };
  634. MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
  635. #endif
  636. static struct platform_driver dsps_usbss_driver = {
  637. .probe = dsps_probe,
  638. .remove = __devexit_p(dsps_remove),
  639. .driver = {
  640. .name = "musb-dsps",
  641. .pm = &dsps_pm_ops,
  642. .of_match_table = of_match_ptr(musb_dsps_of_match),
  643. },
  644. .id_table = musb_dsps_id_table,
  645. };
  646. MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
  647. MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
  648. MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
  649. MODULE_LICENSE("GPL v2");
  650. static int __init dsps_init(void)
  651. {
  652. return platform_driver_register(&dsps_usbss_driver);
  653. }
  654. subsys_initcall(dsps_init);
  655. static void __exit dsps_exit(void)
  656. {
  657. platform_driver_unregister(&dsps_usbss_driver);
  658. }
  659. module_exit(dsps_exit);