am35x.c 17 KB

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  1. /*
  2. * Texas Instruments AM35x "glue layer"
  3. *
  4. * Copyright (c) 2010, by Texas Instruments
  5. *
  6. * Based on the DA8xx "glue layer" code.
  7. * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
  8. *
  9. * This file is part of the Inventra Controller Driver for Linux.
  10. *
  11. * The Inventra Controller Driver for Linux is free software; you
  12. * can redistribute it and/or modify it under the terms of the GNU
  13. * General Public License version 2 as published by the Free Software
  14. * Foundation.
  15. *
  16. * The Inventra Controller Driver for Linux is distributed in
  17. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  18. * without even the implied warranty of MERCHANTABILITY or
  19. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  20. * License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with The Inventra Controller Driver for Linux ; if not,
  24. * write to the Free Software Foundation, Inc., 59 Temple Place,
  25. * Suite 330, Boston, MA 02111-1307 USA
  26. *
  27. */
  28. #include <linux/init.h>
  29. #include <linux/module.h>
  30. #include <linux/clk.h>
  31. #include <linux/err.h>
  32. #include <linux/io.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/usb/nop-usb-xceiv.h>
  36. #include <plat/usb.h>
  37. #include "musb_core.h"
  38. /*
  39. * AM35x specific definitions
  40. */
  41. /* USB 2.0 OTG module registers */
  42. #define USB_REVISION_REG 0x00
  43. #define USB_CTRL_REG 0x04
  44. #define USB_STAT_REG 0x08
  45. #define USB_EMULATION_REG 0x0c
  46. /* 0x10 Reserved */
  47. #define USB_AUTOREQ_REG 0x14
  48. #define USB_SRP_FIX_TIME_REG 0x18
  49. #define USB_TEARDOWN_REG 0x1c
  50. #define EP_INTR_SRC_REG 0x20
  51. #define EP_INTR_SRC_SET_REG 0x24
  52. #define EP_INTR_SRC_CLEAR_REG 0x28
  53. #define EP_INTR_MASK_REG 0x2c
  54. #define EP_INTR_MASK_SET_REG 0x30
  55. #define EP_INTR_MASK_CLEAR_REG 0x34
  56. #define EP_INTR_SRC_MASKED_REG 0x38
  57. #define CORE_INTR_SRC_REG 0x40
  58. #define CORE_INTR_SRC_SET_REG 0x44
  59. #define CORE_INTR_SRC_CLEAR_REG 0x48
  60. #define CORE_INTR_MASK_REG 0x4c
  61. #define CORE_INTR_MASK_SET_REG 0x50
  62. #define CORE_INTR_MASK_CLEAR_REG 0x54
  63. #define CORE_INTR_SRC_MASKED_REG 0x58
  64. /* 0x5c Reserved */
  65. #define USB_END_OF_INTR_REG 0x60
  66. /* Control register bits */
  67. #define AM35X_SOFT_RESET_MASK 1
  68. /* USB interrupt register bits */
  69. #define AM35X_INTR_USB_SHIFT 16
  70. #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
  71. #define AM35X_INTR_DRVVBUS 0x100
  72. #define AM35X_INTR_RX_SHIFT 16
  73. #define AM35X_INTR_TX_SHIFT 0
  74. #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
  75. #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
  76. #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
  77. #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
  78. #define USB_MENTOR_CORE_OFFSET 0x400
  79. struct am35x_glue {
  80. struct device *dev;
  81. struct platform_device *musb;
  82. struct clk *phy_clk;
  83. struct clk *clk;
  84. };
  85. #define glue_to_musb(g) platform_get_drvdata(g->musb)
  86. /*
  87. * am35x_musb_enable - enable interrupts
  88. */
  89. static void am35x_musb_enable(struct musb *musb)
  90. {
  91. void __iomem *reg_base = musb->ctrl_base;
  92. u32 epmask;
  93. /* Workaround: setup IRQs through both register sets. */
  94. epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
  95. ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
  96. musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
  97. musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
  98. /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  99. musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
  100. AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
  101. }
  102. /*
  103. * am35x_musb_disable - disable HDRC and flush interrupts
  104. */
  105. static void am35x_musb_disable(struct musb *musb)
  106. {
  107. void __iomem *reg_base = musb->ctrl_base;
  108. musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
  109. musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
  110. AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
  111. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  112. musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
  113. }
  114. #define portstate(stmt) stmt
  115. static void am35x_musb_set_vbus(struct musb *musb, int is_on)
  116. {
  117. WARN_ON(is_on && is_peripheral_active(musb));
  118. }
  119. #define POLL_SECONDS 2
  120. static struct timer_list otg_workaround;
  121. static void otg_timer(unsigned long _musb)
  122. {
  123. struct musb *musb = (void *)_musb;
  124. void __iomem *mregs = musb->mregs;
  125. u8 devctl;
  126. unsigned long flags;
  127. /*
  128. * We poll because AM35x's won't expose several OTG-critical
  129. * status change events (from the transceiver) otherwise.
  130. */
  131. devctl = musb_readb(mregs, MUSB_DEVCTL);
  132. dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
  133. otg_state_string(musb->xceiv->state));
  134. spin_lock_irqsave(&musb->lock, flags);
  135. switch (musb->xceiv->state) {
  136. case OTG_STATE_A_WAIT_BCON:
  137. devctl &= ~MUSB_DEVCTL_SESSION;
  138. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  139. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  140. if (devctl & MUSB_DEVCTL_BDEVICE) {
  141. musb->xceiv->state = OTG_STATE_B_IDLE;
  142. MUSB_DEV_MODE(musb);
  143. } else {
  144. musb->xceiv->state = OTG_STATE_A_IDLE;
  145. MUSB_HST_MODE(musb);
  146. }
  147. break;
  148. case OTG_STATE_A_WAIT_VFALL:
  149. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  150. musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
  151. MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
  152. break;
  153. case OTG_STATE_B_IDLE:
  154. devctl = musb_readb(mregs, MUSB_DEVCTL);
  155. if (devctl & MUSB_DEVCTL_BDEVICE)
  156. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  157. else
  158. musb->xceiv->state = OTG_STATE_A_IDLE;
  159. break;
  160. default:
  161. break;
  162. }
  163. spin_unlock_irqrestore(&musb->lock, flags);
  164. }
  165. static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
  166. {
  167. static unsigned long last_timer;
  168. if (timeout == 0)
  169. timeout = jiffies + msecs_to_jiffies(3);
  170. /* Never idle if active, or when VBUS timeout is not set as host */
  171. if (musb->is_active || (musb->a_wait_bcon == 0 &&
  172. musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
  173. dev_dbg(musb->controller, "%s active, deleting timer\n",
  174. otg_state_string(musb->xceiv->state));
  175. del_timer(&otg_workaround);
  176. last_timer = jiffies;
  177. return;
  178. }
  179. if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
  180. dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
  181. return;
  182. }
  183. last_timer = timeout;
  184. dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
  185. otg_state_string(musb->xceiv->state),
  186. jiffies_to_msecs(timeout - jiffies));
  187. mod_timer(&otg_workaround, timeout);
  188. }
  189. static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
  190. {
  191. struct musb *musb = hci;
  192. void __iomem *reg_base = musb->ctrl_base;
  193. struct device *dev = musb->controller;
  194. struct musb_hdrc_platform_data *plat = dev->platform_data;
  195. struct omap_musb_board_data *data = plat->board_data;
  196. struct usb_otg *otg = musb->xceiv->otg;
  197. unsigned long flags;
  198. irqreturn_t ret = IRQ_NONE;
  199. u32 epintr, usbintr;
  200. spin_lock_irqsave(&musb->lock, flags);
  201. /* Get endpoint interrupts */
  202. epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
  203. if (epintr) {
  204. musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
  205. musb->int_rx =
  206. (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
  207. musb->int_tx =
  208. (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
  209. }
  210. /* Get usb core interrupts */
  211. usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
  212. if (!usbintr && !epintr)
  213. goto eoi;
  214. if (usbintr) {
  215. musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
  216. musb->int_usb =
  217. (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
  218. }
  219. /*
  220. * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
  221. * AM35x's missing ID change IRQ. We need an ID change IRQ to
  222. * switch appropriately between halves of the OTG state machine.
  223. * Managing DEVCTL.SESSION per Mentor docs requires that we know its
  224. * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
  225. * Also, DRVVBUS pulses for SRP (but not at 5V) ...
  226. */
  227. if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
  228. int drvvbus = musb_readl(reg_base, USB_STAT_REG);
  229. void __iomem *mregs = musb->mregs;
  230. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  231. int err;
  232. err = musb->int_usb & MUSB_INTR_VBUSERROR;
  233. if (err) {
  234. /*
  235. * The Mentor core doesn't debounce VBUS as needed
  236. * to cope with device connect current spikes. This
  237. * means it's not uncommon for bus-powered devices
  238. * to get VBUS errors during enumeration.
  239. *
  240. * This is a workaround, but newer RTL from Mentor
  241. * seems to allow a better one: "re"-starting sessions
  242. * without waiting for VBUS to stop registering in
  243. * devctl.
  244. */
  245. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  246. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  247. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  248. WARNING("VBUS error workaround (delay coming)\n");
  249. } else if (drvvbus) {
  250. MUSB_HST_MODE(musb);
  251. otg->default_a = 1;
  252. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  253. portstate(musb->port1_status |= USB_PORT_STAT_POWER);
  254. del_timer(&otg_workaround);
  255. } else {
  256. musb->is_active = 0;
  257. MUSB_DEV_MODE(musb);
  258. otg->default_a = 0;
  259. musb->xceiv->state = OTG_STATE_B_IDLE;
  260. portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
  261. }
  262. /* NOTE: this must complete power-on within 100 ms. */
  263. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  264. drvvbus ? "on" : "off",
  265. otg_state_string(musb->xceiv->state),
  266. err ? " ERROR" : "",
  267. devctl);
  268. ret = IRQ_HANDLED;
  269. }
  270. /* Drop spurious RX and TX if device is disconnected */
  271. if (musb->int_usb & MUSB_INTR_DISCONNECT) {
  272. musb->int_tx = 0;
  273. musb->int_rx = 0;
  274. }
  275. if (musb->int_tx || musb->int_rx || musb->int_usb)
  276. ret |= musb_interrupt(musb);
  277. eoi:
  278. /* EOI needs to be written for the IRQ to be re-asserted. */
  279. if (ret == IRQ_HANDLED || epintr || usbintr) {
  280. /* clear level interrupt */
  281. if (data->clear_irq)
  282. data->clear_irq();
  283. /* write EOI */
  284. musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
  285. }
  286. /* Poll for ID change */
  287. if (musb->xceiv->state == OTG_STATE_B_IDLE)
  288. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  289. spin_unlock_irqrestore(&musb->lock, flags);
  290. return ret;
  291. }
  292. static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
  293. {
  294. struct device *dev = musb->controller;
  295. struct musb_hdrc_platform_data *plat = dev->platform_data;
  296. struct omap_musb_board_data *data = plat->board_data;
  297. int retval = 0;
  298. if (data->set_mode)
  299. data->set_mode(musb_mode);
  300. else
  301. retval = -EIO;
  302. return retval;
  303. }
  304. static int am35x_musb_init(struct musb *musb)
  305. {
  306. struct device *dev = musb->controller;
  307. struct musb_hdrc_platform_data *plat = dev->platform_data;
  308. struct omap_musb_board_data *data = plat->board_data;
  309. void __iomem *reg_base = musb->ctrl_base;
  310. u32 rev;
  311. musb->mregs += USB_MENTOR_CORE_OFFSET;
  312. /* Returns zero if e.g. not clocked */
  313. rev = musb_readl(reg_base, USB_REVISION_REG);
  314. if (!rev)
  315. return -ENODEV;
  316. usb_nop_xceiv_register();
  317. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  318. if (IS_ERR_OR_NULL(musb->xceiv))
  319. return -ENODEV;
  320. setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
  321. /* Reset the musb */
  322. if (data->reset)
  323. data->reset();
  324. /* Reset the controller */
  325. musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
  326. /* Start the on-chip PHY and its PLL. */
  327. if (data->set_phy_power)
  328. data->set_phy_power(1);
  329. msleep(5);
  330. musb->isr = am35x_musb_interrupt;
  331. /* clear level interrupt */
  332. if (data->clear_irq)
  333. data->clear_irq();
  334. return 0;
  335. }
  336. static int am35x_musb_exit(struct musb *musb)
  337. {
  338. struct device *dev = musb->controller;
  339. struct musb_hdrc_platform_data *plat = dev->platform_data;
  340. struct omap_musb_board_data *data = plat->board_data;
  341. del_timer_sync(&otg_workaround);
  342. /* Shutdown the on-chip PHY and its PLL. */
  343. if (data->set_phy_power)
  344. data->set_phy_power(0);
  345. usb_put_phy(musb->xceiv);
  346. usb_nop_xceiv_unregister();
  347. return 0;
  348. }
  349. /* AM35x supports only 32bit read operation */
  350. void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  351. {
  352. void __iomem *fifo = hw_ep->fifo;
  353. u32 val;
  354. int i;
  355. /* Read for 32bit-aligned destination address */
  356. if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
  357. readsl(fifo, dst, len >> 2);
  358. dst += len & ~0x03;
  359. len &= 0x03;
  360. }
  361. /*
  362. * Now read the remaining 1 to 3 byte or complete length if
  363. * unaligned address.
  364. */
  365. if (len > 4) {
  366. for (i = 0; i < (len >> 2); i++) {
  367. *(u32 *) dst = musb_readl(fifo, 0);
  368. dst += 4;
  369. }
  370. len &= 0x03;
  371. }
  372. if (len > 0) {
  373. val = musb_readl(fifo, 0);
  374. memcpy(dst, &val, len);
  375. }
  376. }
  377. static const struct musb_platform_ops am35x_ops = {
  378. .init = am35x_musb_init,
  379. .exit = am35x_musb_exit,
  380. .enable = am35x_musb_enable,
  381. .disable = am35x_musb_disable,
  382. .set_mode = am35x_musb_set_mode,
  383. .try_idle = am35x_musb_try_idle,
  384. .set_vbus = am35x_musb_set_vbus,
  385. };
  386. static u64 am35x_dmamask = DMA_BIT_MASK(32);
  387. static int __devinit am35x_probe(struct platform_device *pdev)
  388. {
  389. struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
  390. struct platform_device *musb;
  391. struct am35x_glue *glue;
  392. struct clk *phy_clk;
  393. struct clk *clk;
  394. int ret = -ENOMEM;
  395. int musbid;
  396. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  397. if (!glue) {
  398. dev_err(&pdev->dev, "failed to allocate glue context\n");
  399. goto err0;
  400. }
  401. /* get the musb id */
  402. musbid = musb_get_id(&pdev->dev, GFP_KERNEL);
  403. if (musbid < 0) {
  404. dev_err(&pdev->dev, "failed to allocate musb id\n");
  405. ret = -ENOMEM;
  406. goto err1;
  407. }
  408. musb = platform_device_alloc("musb-hdrc", musbid);
  409. if (!musb) {
  410. dev_err(&pdev->dev, "failed to allocate musb device\n");
  411. goto err2;
  412. }
  413. phy_clk = clk_get(&pdev->dev, "fck");
  414. if (IS_ERR(phy_clk)) {
  415. dev_err(&pdev->dev, "failed to get PHY clock\n");
  416. ret = PTR_ERR(phy_clk);
  417. goto err3;
  418. }
  419. clk = clk_get(&pdev->dev, "ick");
  420. if (IS_ERR(clk)) {
  421. dev_err(&pdev->dev, "failed to get clock\n");
  422. ret = PTR_ERR(clk);
  423. goto err4;
  424. }
  425. ret = clk_enable(phy_clk);
  426. if (ret) {
  427. dev_err(&pdev->dev, "failed to enable PHY clock\n");
  428. goto err5;
  429. }
  430. ret = clk_enable(clk);
  431. if (ret) {
  432. dev_err(&pdev->dev, "failed to enable clock\n");
  433. goto err6;
  434. }
  435. musb->id = musbid;
  436. musb->dev.parent = &pdev->dev;
  437. musb->dev.dma_mask = &am35x_dmamask;
  438. musb->dev.coherent_dma_mask = am35x_dmamask;
  439. glue->dev = &pdev->dev;
  440. glue->musb = musb;
  441. glue->phy_clk = phy_clk;
  442. glue->clk = clk;
  443. pdata->platform_ops = &am35x_ops;
  444. platform_set_drvdata(pdev, glue);
  445. ret = platform_device_add_resources(musb, pdev->resource,
  446. pdev->num_resources);
  447. if (ret) {
  448. dev_err(&pdev->dev, "failed to add resources\n");
  449. goto err7;
  450. }
  451. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  452. if (ret) {
  453. dev_err(&pdev->dev, "failed to add platform_data\n");
  454. goto err7;
  455. }
  456. ret = platform_device_add(musb);
  457. if (ret) {
  458. dev_err(&pdev->dev, "failed to register musb device\n");
  459. goto err7;
  460. }
  461. return 0;
  462. err7:
  463. clk_disable(clk);
  464. err6:
  465. clk_disable(phy_clk);
  466. err5:
  467. clk_put(clk);
  468. err4:
  469. clk_put(phy_clk);
  470. err3:
  471. platform_device_put(musb);
  472. err2:
  473. musb_put_id(&pdev->dev, musbid);
  474. err1:
  475. kfree(glue);
  476. err0:
  477. return ret;
  478. }
  479. static int __devexit am35x_remove(struct platform_device *pdev)
  480. {
  481. struct am35x_glue *glue = platform_get_drvdata(pdev);
  482. musb_put_id(&pdev->dev, glue->musb->id);
  483. platform_device_del(glue->musb);
  484. platform_device_put(glue->musb);
  485. clk_disable(glue->clk);
  486. clk_disable(glue->phy_clk);
  487. clk_put(glue->clk);
  488. clk_put(glue->phy_clk);
  489. kfree(glue);
  490. return 0;
  491. }
  492. #ifdef CONFIG_PM
  493. static int am35x_suspend(struct device *dev)
  494. {
  495. struct am35x_glue *glue = dev_get_drvdata(dev);
  496. struct musb_hdrc_platform_data *plat = dev->platform_data;
  497. struct omap_musb_board_data *data = plat->board_data;
  498. /* Shutdown the on-chip PHY and its PLL. */
  499. if (data->set_phy_power)
  500. data->set_phy_power(0);
  501. clk_disable(glue->phy_clk);
  502. clk_disable(glue->clk);
  503. return 0;
  504. }
  505. static int am35x_resume(struct device *dev)
  506. {
  507. struct am35x_glue *glue = dev_get_drvdata(dev);
  508. struct musb_hdrc_platform_data *plat = dev->platform_data;
  509. struct omap_musb_board_data *data = plat->board_data;
  510. int ret;
  511. /* Start the on-chip PHY and its PLL. */
  512. if (data->set_phy_power)
  513. data->set_phy_power(1);
  514. ret = clk_enable(glue->phy_clk);
  515. if (ret) {
  516. dev_err(dev, "failed to enable PHY clock\n");
  517. return ret;
  518. }
  519. ret = clk_enable(glue->clk);
  520. if (ret) {
  521. dev_err(dev, "failed to enable clock\n");
  522. return ret;
  523. }
  524. return 0;
  525. }
  526. static struct dev_pm_ops am35x_pm_ops = {
  527. .suspend = am35x_suspend,
  528. .resume = am35x_resume,
  529. };
  530. #define DEV_PM_OPS &am35x_pm_ops
  531. #else
  532. #define DEV_PM_OPS NULL
  533. #endif
  534. static struct platform_driver am35x_driver = {
  535. .probe = am35x_probe,
  536. .remove = __devexit_p(am35x_remove),
  537. .driver = {
  538. .name = "musb-am35x",
  539. .pm = DEV_PM_OPS,
  540. },
  541. };
  542. MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
  543. MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
  544. MODULE_LICENSE("GPL v2");
  545. static int __init am35x_init(void)
  546. {
  547. return platform_driver_register(&am35x_driver);
  548. }
  549. module_init(am35x_init);
  550. static void __exit am35x_exit(void)
  551. {
  552. platform_driver_unregister(&am35x_driver);
  553. }
  554. module_exit(am35x_exit);