pn544_hci.c 24 KB

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  1. /*
  2. * HCI based Driver for NXP PN544 NFC Chip
  3. *
  4. * Copyright (C) 2012 Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the
  17. * Free Software Foundation, Inc.,
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. */
  20. #include <linux/crc-ccitt.h>
  21. #include <linux/module.h>
  22. #include <linux/delay.h>
  23. #include <linux/slab.h>
  24. #include <linux/miscdevice.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/gpio.h>
  27. #include <linux/i2c.h>
  28. #include <linux/nfc.h>
  29. #include <net/nfc/hci.h>
  30. #include <net/nfc/llc.h>
  31. #include <linux/nfc/pn544.h>
  32. #define DRIVER_DESC "HCI NFC driver for PN544"
  33. #define PN544_HCI_DRIVER_NAME "pn544_hci"
  34. /* Timing restrictions (ms) */
  35. #define PN544_HCI_RESETVEN_TIME 30
  36. static struct i2c_device_id pn544_hci_id_table[] = {
  37. {"pn544", 0},
  38. {}
  39. };
  40. MODULE_DEVICE_TABLE(i2c, pn544_hci_id_table);
  41. #define HCI_MODE 0
  42. #define FW_MODE 1
  43. /* framing in HCI mode */
  44. #define PN544_HCI_LLC_LEN 1
  45. #define PN544_HCI_LLC_CRC 2
  46. #define PN544_HCI_LLC_LEN_CRC (PN544_HCI_LLC_LEN + PN544_HCI_LLC_CRC)
  47. #define PN544_HCI_LLC_MIN_SIZE (1 + PN544_HCI_LLC_LEN_CRC)
  48. #define PN544_HCI_LLC_MAX_PAYLOAD 29
  49. #define PN544_HCI_LLC_MAX_SIZE (PN544_HCI_LLC_LEN_CRC + 1 + \
  50. PN544_HCI_LLC_MAX_PAYLOAD)
  51. enum pn544_state {
  52. PN544_ST_COLD,
  53. PN544_ST_FW_READY,
  54. PN544_ST_READY,
  55. };
  56. #define FULL_VERSION_LEN 11
  57. /* Proprietary commands */
  58. #define PN544_WRITE 0x3f
  59. /* Proprietary gates, events, commands and registers */
  60. /* NFC_HCI_RF_READER_A_GATE additional registers and commands */
  61. #define PN544_RF_READER_A_AUTO_ACTIVATION 0x10
  62. #define PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION 0x12
  63. #define PN544_MIFARE_CMD 0x21
  64. /* Commands that apply to all RF readers */
  65. #define PN544_RF_READER_CMD_PRESENCE_CHECK 0x30
  66. #define PN544_RF_READER_CMD_ACTIVATE_NEXT 0x32
  67. /* NFC_HCI_ID_MGMT_GATE additional registers */
  68. #define PN544_ID_MGMT_FULL_VERSION_SW 0x10
  69. #define PN544_RF_READER_ISO15693_GATE 0x12
  70. #define PN544_RF_READER_F_GATE 0x14
  71. #define PN544_FELICA_ID 0x04
  72. #define PN544_FELICA_RAW 0x20
  73. #define PN544_RF_READER_JEWEL_GATE 0x15
  74. #define PN544_JEWEL_RAW_CMD 0x23
  75. #define PN544_RF_READER_NFCIP1_INITIATOR_GATE 0x30
  76. #define PN544_RF_READER_NFCIP1_TARGET_GATE 0x31
  77. #define PN544_SYS_MGMT_GATE 0x90
  78. #define PN544_SYS_MGMT_INFO_NOTIFICATION 0x02
  79. #define PN544_POLLING_LOOP_MGMT_GATE 0x94
  80. #define PN544_PL_RDPHASES 0x06
  81. #define PN544_PL_EMULATION 0x07
  82. #define PN544_PL_NFCT_DEACTIVATED 0x09
  83. #define PN544_SWP_MGMT_GATE 0xA0
  84. #define PN544_NFC_WI_MGMT_GATE 0xA1
  85. static struct nfc_hci_gate pn544_gates[] = {
  86. {NFC_HCI_ADMIN_GATE, NFC_HCI_INVALID_PIPE},
  87. {NFC_HCI_LOOPBACK_GATE, NFC_HCI_INVALID_PIPE},
  88. {NFC_HCI_ID_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  89. {NFC_HCI_LINK_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  90. {NFC_HCI_RF_READER_B_GATE, NFC_HCI_INVALID_PIPE},
  91. {NFC_HCI_RF_READER_A_GATE, NFC_HCI_INVALID_PIPE},
  92. {PN544_SYS_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  93. {PN544_SWP_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  94. {PN544_POLLING_LOOP_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  95. {PN544_NFC_WI_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  96. {PN544_RF_READER_F_GATE, NFC_HCI_INVALID_PIPE},
  97. {PN544_RF_READER_JEWEL_GATE, NFC_HCI_INVALID_PIPE},
  98. {PN544_RF_READER_ISO15693_GATE, NFC_HCI_INVALID_PIPE},
  99. {PN544_RF_READER_NFCIP1_INITIATOR_GATE, NFC_HCI_INVALID_PIPE},
  100. {PN544_RF_READER_NFCIP1_TARGET_GATE, NFC_HCI_INVALID_PIPE}
  101. };
  102. /* Largest headroom needed for outgoing custom commands */
  103. #define PN544_CMDS_HEADROOM 2
  104. #define PN544_FRAME_HEADROOM 1
  105. #define PN544_FRAME_TAILROOM 2
  106. struct pn544_hci_info {
  107. struct i2c_client *i2c_dev;
  108. struct nfc_hci_dev *hdev;
  109. enum pn544_state state;
  110. struct mutex info_lock;
  111. unsigned int gpio_en;
  112. unsigned int gpio_irq;
  113. unsigned int gpio_fw;
  114. unsigned int en_polarity;
  115. int hard_fault; /*
  116. * < 0 if hardware error occured (e.g. i2c err)
  117. * and prevents normal operation.
  118. */
  119. int async_cb_type;
  120. data_exchange_cb_t async_cb;
  121. void *async_cb_context;
  122. };
  123. static void pn544_hci_platform_init(struct pn544_hci_info *info)
  124. {
  125. int polarity, retry, ret;
  126. char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
  127. int count = sizeof(rset_cmd);
  128. pr_info(DRIVER_DESC ": %s\n", __func__);
  129. dev_info(&info->i2c_dev->dev, "Detecting nfc_en polarity\n");
  130. /* Disable fw download */
  131. gpio_set_value(info->gpio_fw, 0);
  132. for (polarity = 0; polarity < 2; polarity++) {
  133. info->en_polarity = polarity;
  134. retry = 3;
  135. while (retry--) {
  136. /* power off */
  137. gpio_set_value(info->gpio_en, !info->en_polarity);
  138. usleep_range(10000, 15000);
  139. /* power on */
  140. gpio_set_value(info->gpio_en, info->en_polarity);
  141. usleep_range(10000, 15000);
  142. /* send reset */
  143. dev_dbg(&info->i2c_dev->dev, "Sending reset cmd\n");
  144. ret = i2c_master_send(info->i2c_dev, rset_cmd, count);
  145. if (ret == count) {
  146. dev_info(&info->i2c_dev->dev,
  147. "nfc_en polarity : active %s\n",
  148. (polarity == 0 ? "low" : "high"));
  149. goto out;
  150. }
  151. }
  152. }
  153. dev_err(&info->i2c_dev->dev,
  154. "Could not detect nfc_en polarity, fallback to active high\n");
  155. out:
  156. gpio_set_value(info->gpio_en, !info->en_polarity);
  157. }
  158. static int pn544_hci_enable(struct pn544_hci_info *info, int mode)
  159. {
  160. pr_info(DRIVER_DESC ": %s\n", __func__);
  161. gpio_set_value(info->gpio_fw, 0);
  162. gpio_set_value(info->gpio_en, info->en_polarity);
  163. usleep_range(10000, 15000);
  164. return 0;
  165. }
  166. static void pn544_hci_disable(struct pn544_hci_info *info)
  167. {
  168. pr_info(DRIVER_DESC ": %s\n", __func__);
  169. gpio_set_value(info->gpio_fw, 0);
  170. gpio_set_value(info->gpio_en, !info->en_polarity);
  171. usleep_range(10000, 15000);
  172. gpio_set_value(info->gpio_en, info->en_polarity);
  173. usleep_range(10000, 15000);
  174. gpio_set_value(info->gpio_en, !info->en_polarity);
  175. usleep_range(10000, 15000);
  176. }
  177. static int pn544_hci_i2c_write(struct i2c_client *client, u8 *buf, int len)
  178. {
  179. int r;
  180. usleep_range(3000, 6000);
  181. r = i2c_master_send(client, buf, len);
  182. if (r == -EREMOTEIO) { /* Retry, chip was in standby */
  183. usleep_range(6000, 10000);
  184. r = i2c_master_send(client, buf, len);
  185. }
  186. if (r >= 0) {
  187. if (r != len)
  188. return -EREMOTEIO;
  189. else
  190. return 0;
  191. }
  192. return r;
  193. }
  194. static int check_crc(u8 *buf, int buflen)
  195. {
  196. int len;
  197. u16 crc;
  198. len = buf[0] + 1;
  199. crc = crc_ccitt(0xffff, buf, len - 2);
  200. crc = ~crc;
  201. if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) {
  202. pr_err(PN544_HCI_DRIVER_NAME ": CRC error 0x%x != 0x%x 0x%x\n",
  203. crc, buf[len - 1], buf[len - 2]);
  204. pr_info(DRIVER_DESC ": %s : BAD CRC\n", __func__);
  205. print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE,
  206. 16, 2, buf, buflen, false);
  207. return -EPERM;
  208. }
  209. return 0;
  210. }
  211. /*
  212. * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
  213. * that i2c bus will be flushed and that next read will start on a new frame.
  214. * returned skb contains only LLC header and payload.
  215. * returns:
  216. * -EREMOTEIO : i2c read error (fatal)
  217. * -EBADMSG : frame was incorrect and discarded
  218. * -ENOMEM : cannot allocate skb, frame dropped
  219. */
  220. static int pn544_hci_i2c_read(struct i2c_client *client, struct sk_buff **skb)
  221. {
  222. int r;
  223. u8 len;
  224. u8 tmp[PN544_HCI_LLC_MAX_SIZE - 1];
  225. r = i2c_master_recv(client, &len, 1);
  226. if (r != 1) {
  227. dev_err(&client->dev, "cannot read len byte\n");
  228. return -EREMOTEIO;
  229. }
  230. if ((len < (PN544_HCI_LLC_MIN_SIZE - 1)) ||
  231. (len > (PN544_HCI_LLC_MAX_SIZE - 1))) {
  232. dev_err(&client->dev, "invalid len byte\n");
  233. r = -EBADMSG;
  234. goto flush;
  235. }
  236. *skb = alloc_skb(1 + len, GFP_KERNEL);
  237. if (*skb == NULL) {
  238. r = -ENOMEM;
  239. goto flush;
  240. }
  241. *skb_put(*skb, 1) = len;
  242. r = i2c_master_recv(client, skb_put(*skb, len), len);
  243. if (r != len) {
  244. kfree_skb(*skb);
  245. return -EREMOTEIO;
  246. }
  247. r = check_crc((*skb)->data, (*skb)->len);
  248. if (r != 0) {
  249. kfree_skb(*skb);
  250. r = -EBADMSG;
  251. goto flush;
  252. }
  253. skb_pull(*skb, 1);
  254. skb_trim(*skb, (*skb)->len - 2);
  255. usleep_range(3000, 6000);
  256. return 0;
  257. flush:
  258. if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0)
  259. r = -EREMOTEIO;
  260. usleep_range(3000, 6000);
  261. return r;
  262. }
  263. /*
  264. * Reads an shdlc frame from the chip. This is not as straightforward as it
  265. * seems. There are cases where we could loose the frame start synchronization.
  266. * The frame format is len-data-crc, and corruption can occur anywhere while
  267. * transiting on i2c bus, such that we could read an invalid len.
  268. * In order to recover synchronization with the next frame, we must be sure
  269. * to read the real amount of data without using the len byte. We do this by
  270. * assuming the following:
  271. * - the chip will always present only one single complete frame on the bus
  272. * before triggering the interrupt
  273. * - the chip will not present a new frame until we have completely read
  274. * the previous one (or until we have handled the interrupt).
  275. * The tricky case is when we read a corrupted len that is less than the real
  276. * len. We must detect this here in order to determine that we need to flush
  277. * the bus. This is the reason why we check the crc here.
  278. */
  279. static irqreturn_t pn544_hci_irq_thread_fn(int irq, void *dev_id)
  280. {
  281. struct pn544_hci_info *info = dev_id;
  282. struct i2c_client *client;
  283. struct sk_buff *skb = NULL;
  284. int r;
  285. if (!info || irq != info->i2c_dev->irq) {
  286. WARN_ON_ONCE(1);
  287. return IRQ_NONE;
  288. }
  289. client = info->i2c_dev;
  290. dev_dbg(&client->dev, "IRQ\n");
  291. if (info->hard_fault != 0)
  292. return IRQ_HANDLED;
  293. r = pn544_hci_i2c_read(client, &skb);
  294. if (r == -EREMOTEIO) {
  295. info->hard_fault = r;
  296. nfc_hci_recv_frame(info->hdev, NULL);
  297. return IRQ_HANDLED;
  298. } else if ((r == -ENOMEM) || (r == -EBADMSG)) {
  299. return IRQ_HANDLED;
  300. }
  301. nfc_hci_recv_frame(info->hdev, skb);
  302. return IRQ_HANDLED;
  303. }
  304. static int pn544_hci_open(struct nfc_hci_dev *hdev)
  305. {
  306. struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
  307. int r = 0;
  308. mutex_lock(&info->info_lock);
  309. if (info->state != PN544_ST_COLD) {
  310. r = -EBUSY;
  311. goto out;
  312. }
  313. r = pn544_hci_enable(info, HCI_MODE);
  314. if (r == 0)
  315. info->state = PN544_ST_READY;
  316. out:
  317. mutex_unlock(&info->info_lock);
  318. return r;
  319. }
  320. static void pn544_hci_close(struct nfc_hci_dev *hdev)
  321. {
  322. struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
  323. mutex_lock(&info->info_lock);
  324. if (info->state == PN544_ST_COLD)
  325. goto out;
  326. pn544_hci_disable(info);
  327. info->state = PN544_ST_COLD;
  328. out:
  329. mutex_unlock(&info->info_lock);
  330. }
  331. static int pn544_hci_ready(struct nfc_hci_dev *hdev)
  332. {
  333. struct sk_buff *skb;
  334. static struct hw_config {
  335. u8 adr[2];
  336. u8 value;
  337. } hw_config[] = {
  338. {{0x9f, 0x9a}, 0x00},
  339. {{0x98, 0x10}, 0xbc},
  340. {{0x9e, 0x71}, 0x00},
  341. {{0x98, 0x09}, 0x00},
  342. {{0x9e, 0xb4}, 0x00},
  343. {{0x9e, 0xd9}, 0xff},
  344. {{0x9e, 0xda}, 0xff},
  345. {{0x9e, 0xdb}, 0x23},
  346. {{0x9e, 0xdc}, 0x21},
  347. {{0x9e, 0xdd}, 0x22},
  348. {{0x9e, 0xde}, 0x24},
  349. {{0x9c, 0x01}, 0x08},
  350. {{0x9e, 0xaa}, 0x01},
  351. {{0x9b, 0xd1}, 0x0d},
  352. {{0x9b, 0xd2}, 0x24},
  353. {{0x9b, 0xd3}, 0x0a},
  354. {{0x9b, 0xd4}, 0x22},
  355. {{0x9b, 0xd5}, 0x08},
  356. {{0x9b, 0xd6}, 0x1e},
  357. {{0x9b, 0xdd}, 0x1c},
  358. {{0x9b, 0x84}, 0x13},
  359. {{0x99, 0x81}, 0x7f},
  360. {{0x99, 0x31}, 0x70},
  361. {{0x98, 0x00}, 0x3f},
  362. {{0x9f, 0x09}, 0x00},
  363. {{0x9f, 0x0a}, 0x05},
  364. {{0x9e, 0xd1}, 0xa1},
  365. {{0x99, 0x23}, 0x00},
  366. {{0x9e, 0x74}, 0x80},
  367. {{0x9f, 0x28}, 0x10},
  368. {{0x9f, 0x35}, 0x14},
  369. {{0x9f, 0x36}, 0x60},
  370. {{0x9c, 0x31}, 0x00},
  371. {{0x9c, 0x32}, 0xc8},
  372. {{0x9c, 0x19}, 0x40},
  373. {{0x9c, 0x1a}, 0x40},
  374. {{0x9c, 0x0c}, 0x00},
  375. {{0x9c, 0x0d}, 0x00},
  376. {{0x9c, 0x12}, 0x00},
  377. {{0x9c, 0x13}, 0x00},
  378. {{0x98, 0xa2}, 0x0e},
  379. {{0x98, 0x93}, 0x40},
  380. {{0x98, 0x7d}, 0x02},
  381. {{0x98, 0x7e}, 0x00},
  382. {{0x9f, 0xc8}, 0x01},
  383. };
  384. struct hw_config *p = hw_config;
  385. int count = ARRAY_SIZE(hw_config);
  386. struct sk_buff *res_skb;
  387. u8 param[4];
  388. int r;
  389. param[0] = 0;
  390. while (count--) {
  391. param[1] = p->adr[0];
  392. param[2] = p->adr[1];
  393. param[3] = p->value;
  394. r = nfc_hci_send_cmd(hdev, PN544_SYS_MGMT_GATE, PN544_WRITE,
  395. param, 4, &res_skb);
  396. if (r < 0)
  397. return r;
  398. if (res_skb->len != 1) {
  399. kfree_skb(res_skb);
  400. return -EPROTO;
  401. }
  402. if (res_skb->data[0] != p->value) {
  403. kfree_skb(res_skb);
  404. return -EIO;
  405. }
  406. kfree_skb(res_skb);
  407. p++;
  408. }
  409. param[0] = NFC_HCI_UICC_HOST_ID;
  410. r = nfc_hci_set_param(hdev, NFC_HCI_ADMIN_GATE,
  411. NFC_HCI_ADMIN_WHITELIST, param, 1);
  412. if (r < 0)
  413. return r;
  414. param[0] = 0x3d;
  415. r = nfc_hci_set_param(hdev, PN544_SYS_MGMT_GATE,
  416. PN544_SYS_MGMT_INFO_NOTIFICATION, param, 1);
  417. if (r < 0)
  418. return r;
  419. param[0] = 0x0;
  420. r = nfc_hci_set_param(hdev, NFC_HCI_RF_READER_A_GATE,
  421. PN544_RF_READER_A_AUTO_ACTIVATION, param, 1);
  422. if (r < 0)
  423. return r;
  424. r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  425. NFC_HCI_EVT_END_OPERATION, NULL, 0);
  426. if (r < 0)
  427. return r;
  428. param[0] = 0x1;
  429. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  430. PN544_PL_NFCT_DEACTIVATED, param, 1);
  431. if (r < 0)
  432. return r;
  433. param[0] = 0x0;
  434. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  435. PN544_PL_RDPHASES, param, 1);
  436. if (r < 0)
  437. return r;
  438. r = nfc_hci_get_param(hdev, NFC_HCI_ID_MGMT_GATE,
  439. PN544_ID_MGMT_FULL_VERSION_SW, &skb);
  440. if (r < 0)
  441. return r;
  442. if (skb->len != FULL_VERSION_LEN) {
  443. kfree_skb(skb);
  444. return -EINVAL;
  445. }
  446. print_hex_dump(KERN_DEBUG, "FULL VERSION SOFTWARE INFO: ",
  447. DUMP_PREFIX_NONE, 16, 1,
  448. skb->data, FULL_VERSION_LEN, false);
  449. kfree_skb(skb);
  450. return 0;
  451. }
  452. static void pn544_hci_add_len_crc(struct sk_buff *skb)
  453. {
  454. u16 crc;
  455. int len;
  456. len = skb->len + 2;
  457. *skb_push(skb, 1) = len;
  458. crc = crc_ccitt(0xffff, skb->data, skb->len);
  459. crc = ~crc;
  460. *skb_put(skb, 1) = crc & 0xff;
  461. *skb_put(skb, 1) = crc >> 8;
  462. }
  463. static void pn544_hci_remove_len_crc(struct sk_buff *skb)
  464. {
  465. skb_pull(skb, PN544_FRAME_HEADROOM);
  466. skb_trim(skb, PN544_FRAME_TAILROOM);
  467. }
  468. static int pn544_hci_xmit(struct nfc_hci_dev *hdev, struct sk_buff *skb)
  469. {
  470. struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
  471. struct i2c_client *client = info->i2c_dev;
  472. int r;
  473. if (info->hard_fault != 0)
  474. return info->hard_fault;
  475. pn544_hci_add_len_crc(skb);
  476. r = pn544_hci_i2c_write(client, skb->data, skb->len);
  477. pn544_hci_remove_len_crc(skb);
  478. return r;
  479. }
  480. static int pn544_hci_start_poll(struct nfc_hci_dev *hdev,
  481. u32 im_protocols, u32 tm_protocols)
  482. {
  483. u8 phases = 0;
  484. int r;
  485. u8 duration[2];
  486. u8 activated;
  487. pr_info(DRIVER_DESC ": %s protocols 0x%x 0x%x\n",
  488. __func__, im_protocols, tm_protocols);
  489. r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  490. NFC_HCI_EVT_END_OPERATION, NULL, 0);
  491. if (r < 0)
  492. return r;
  493. duration[0] = 0x18;
  494. duration[1] = 0x6a;
  495. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  496. PN544_PL_EMULATION, duration, 2);
  497. if (r < 0)
  498. return r;
  499. activated = 0;
  500. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  501. PN544_PL_NFCT_DEACTIVATED, &activated, 1);
  502. if (r < 0)
  503. return r;
  504. if (im_protocols & (NFC_PROTO_ISO14443_MASK | NFC_PROTO_MIFARE_MASK |
  505. NFC_PROTO_JEWEL_MASK))
  506. phases |= 1; /* Type A */
  507. if (im_protocols & NFC_PROTO_FELICA_MASK) {
  508. phases |= (1 << 2); /* Type F 212 */
  509. phases |= (1 << 3); /* Type F 424 */
  510. }
  511. phases |= (1 << 5); /* NFC active */
  512. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  513. PN544_PL_RDPHASES, &phases, 1);
  514. if (r < 0)
  515. return r;
  516. r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  517. NFC_HCI_EVT_READER_REQUESTED, NULL, 0);
  518. if (r < 0)
  519. nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  520. NFC_HCI_EVT_END_OPERATION, NULL, 0);
  521. return r;
  522. }
  523. static int pn544_hci_target_from_gate(struct nfc_hci_dev *hdev, u8 gate,
  524. struct nfc_target *target)
  525. {
  526. switch (gate) {
  527. case PN544_RF_READER_F_GATE:
  528. target->supported_protocols = NFC_PROTO_FELICA_MASK;
  529. break;
  530. case PN544_RF_READER_JEWEL_GATE:
  531. target->supported_protocols = NFC_PROTO_JEWEL_MASK;
  532. target->sens_res = 0x0c00;
  533. break;
  534. default:
  535. return -EPROTO;
  536. }
  537. return 0;
  538. }
  539. static int pn544_hci_complete_target_discovered(struct nfc_hci_dev *hdev,
  540. u8 gate,
  541. struct nfc_target *target)
  542. {
  543. struct sk_buff *uid_skb;
  544. int r = 0;
  545. if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
  546. if (target->nfcid1_len != 4 && target->nfcid1_len != 7 &&
  547. target->nfcid1_len != 10)
  548. return -EPROTO;
  549. r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
  550. PN544_RF_READER_CMD_ACTIVATE_NEXT,
  551. target->nfcid1, target->nfcid1_len, NULL);
  552. } else if (target->supported_protocols & NFC_PROTO_FELICA_MASK) {
  553. r = nfc_hci_get_param(hdev, PN544_RF_READER_F_GATE,
  554. PN544_FELICA_ID, &uid_skb);
  555. if (r < 0)
  556. return r;
  557. if (uid_skb->len != 8) {
  558. kfree_skb(uid_skb);
  559. return -EPROTO;
  560. }
  561. r = nfc_hci_send_cmd(hdev, PN544_RF_READER_F_GATE,
  562. PN544_RF_READER_CMD_ACTIVATE_NEXT,
  563. uid_skb->data, uid_skb->len, NULL);
  564. kfree_skb(uid_skb);
  565. } else if (target->supported_protocols & NFC_PROTO_ISO14443_MASK) {
  566. /*
  567. * TODO: maybe other ISO 14443 require some kind of continue
  568. * activation, but for now we've seen only this one below.
  569. */
  570. if (target->sens_res == 0x4403) /* Type 4 Mifare DESFire */
  571. r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
  572. PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION,
  573. NULL, 0, NULL);
  574. }
  575. return r;
  576. }
  577. #define PN544_CB_TYPE_READER_F 1
  578. static void pn544_hci_data_exchange_cb(void *context, struct sk_buff *skb,
  579. int err)
  580. {
  581. struct pn544_hci_info *info = context;
  582. switch (info->async_cb_type) {
  583. case PN544_CB_TYPE_READER_F:
  584. if (err == 0)
  585. skb_pull(skb, 1);
  586. info->async_cb(info->async_cb_context, skb, err);
  587. break;
  588. default:
  589. if (err == 0)
  590. kfree_skb(skb);
  591. break;
  592. }
  593. }
  594. #define MIFARE_CMD_AUTH_KEY_A 0x60
  595. #define MIFARE_CMD_AUTH_KEY_B 0x61
  596. #define MIFARE_CMD_HEADER 2
  597. #define MIFARE_UID_LEN 4
  598. #define MIFARE_KEY_LEN 6
  599. #define MIFARE_CMD_LEN 12
  600. /*
  601. * Returns:
  602. * <= 0: driver handled the data exchange
  603. * 1: driver doesn't especially handle, please do standard processing
  604. */
  605. static int pn544_hci_data_exchange(struct nfc_hci_dev *hdev,
  606. struct nfc_target *target,
  607. struct sk_buff *skb, data_exchange_cb_t cb,
  608. void *cb_context)
  609. {
  610. struct pn544_hci_info *info = nfc_hci_get_clientdata(hdev);
  611. pr_info(DRIVER_DESC ": %s for gate=%d\n", __func__,
  612. target->hci_reader_gate);
  613. switch (target->hci_reader_gate) {
  614. case NFC_HCI_RF_READER_A_GATE:
  615. if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
  616. /*
  617. * It seems that pn544 is inverting key and UID for
  618. * MIFARE authentication commands.
  619. */
  620. if (skb->len == MIFARE_CMD_LEN &&
  621. (skb->data[0] == MIFARE_CMD_AUTH_KEY_A ||
  622. skb->data[0] == MIFARE_CMD_AUTH_KEY_B)) {
  623. u8 uid[MIFARE_UID_LEN];
  624. u8 *data = skb->data + MIFARE_CMD_HEADER;
  625. memcpy(uid, data + MIFARE_KEY_LEN,
  626. MIFARE_UID_LEN);
  627. memmove(data + MIFARE_UID_LEN, data,
  628. MIFARE_KEY_LEN);
  629. memcpy(data, uid, MIFARE_UID_LEN);
  630. }
  631. return nfc_hci_send_cmd_async(hdev,
  632. target->hci_reader_gate,
  633. PN544_MIFARE_CMD,
  634. skb->data, skb->len,
  635. cb, cb_context);
  636. } else
  637. return 1;
  638. case PN544_RF_READER_F_GATE:
  639. *skb_push(skb, 1) = 0;
  640. *skb_push(skb, 1) = 0;
  641. info->async_cb_type = PN544_CB_TYPE_READER_F;
  642. info->async_cb = cb;
  643. info->async_cb_context = cb_context;
  644. return nfc_hci_send_cmd_async(hdev, target->hci_reader_gate,
  645. PN544_FELICA_RAW, skb->data,
  646. skb->len,
  647. pn544_hci_data_exchange_cb, info);
  648. case PN544_RF_READER_JEWEL_GATE:
  649. return nfc_hci_send_cmd_async(hdev, target->hci_reader_gate,
  650. PN544_JEWEL_RAW_CMD, skb->data,
  651. skb->len, cb, cb_context);
  652. default:
  653. return 1;
  654. }
  655. }
  656. static int pn544_hci_check_presence(struct nfc_hci_dev *hdev,
  657. struct nfc_target *target)
  658. {
  659. return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
  660. PN544_RF_READER_CMD_PRESENCE_CHECK,
  661. NULL, 0, NULL);
  662. }
  663. static struct nfc_hci_ops pn544_hci_ops = {
  664. .open = pn544_hci_open,
  665. .close = pn544_hci_close,
  666. .hci_ready = pn544_hci_ready,
  667. .xmit = pn544_hci_xmit,
  668. .start_poll = pn544_hci_start_poll,
  669. .target_from_gate = pn544_hci_target_from_gate,
  670. .complete_target_discovered = pn544_hci_complete_target_discovered,
  671. .data_exchange = pn544_hci_data_exchange,
  672. .check_presence = pn544_hci_check_presence,
  673. };
  674. static int __devinit pn544_hci_probe(struct i2c_client *client,
  675. const struct i2c_device_id *id)
  676. {
  677. struct pn544_hci_info *info;
  678. struct pn544_nfc_platform_data *pdata;
  679. int r = 0;
  680. u32 protocols;
  681. struct nfc_hci_init_data init_data;
  682. dev_dbg(&client->dev, "%s\n", __func__);
  683. dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
  684. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
  685. dev_err(&client->dev, "Need I2C_FUNC_I2C\n");
  686. return -ENODEV;
  687. }
  688. info = kzalloc(sizeof(struct pn544_hci_info), GFP_KERNEL);
  689. if (!info) {
  690. dev_err(&client->dev,
  691. "Cannot allocate memory for pn544_hci_info.\n");
  692. r = -ENOMEM;
  693. goto err_info_alloc;
  694. }
  695. info->i2c_dev = client;
  696. info->state = PN544_ST_COLD;
  697. mutex_init(&info->info_lock);
  698. i2c_set_clientdata(client, info);
  699. pdata = client->dev.platform_data;
  700. if (pdata == NULL) {
  701. dev_err(&client->dev, "No platform data\n");
  702. r = -EINVAL;
  703. goto err_pdata;
  704. }
  705. if (pdata->request_resources == NULL) {
  706. dev_err(&client->dev, "request_resources() missing\n");
  707. r = -EINVAL;
  708. goto err_pdata;
  709. }
  710. r = pdata->request_resources(client);
  711. if (r) {
  712. dev_err(&client->dev, "Cannot get platform resources\n");
  713. goto err_pdata;
  714. }
  715. info->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE);
  716. info->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET);
  717. info->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ);
  718. pn544_hci_platform_init(info);
  719. r = request_threaded_irq(client->irq, NULL, pn544_hci_irq_thread_fn,
  720. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  721. PN544_HCI_DRIVER_NAME, info);
  722. if (r < 0) {
  723. dev_err(&client->dev, "Unable to register IRQ handler\n");
  724. goto err_rti;
  725. }
  726. init_data.gate_count = ARRAY_SIZE(pn544_gates);
  727. memcpy(init_data.gates, pn544_gates, sizeof(pn544_gates));
  728. /*
  729. * TODO: Session id must include the driver name + some bus addr
  730. * persistent info to discriminate 2 identical chips
  731. */
  732. strcpy(init_data.session_id, "ID544HCI");
  733. protocols = NFC_PROTO_JEWEL_MASK |
  734. NFC_PROTO_MIFARE_MASK |
  735. NFC_PROTO_FELICA_MASK |
  736. NFC_PROTO_ISO14443_MASK |
  737. NFC_PROTO_ISO14443_B_MASK |
  738. NFC_PROTO_NFC_DEP_MASK;
  739. info->hdev = nfc_hci_allocate_device(&pn544_hci_ops, &init_data,
  740. protocols, LLC_SHDLC_NAME,
  741. PN544_FRAME_HEADROOM +
  742. PN544_CMDS_HEADROOM,
  743. PN544_FRAME_TAILROOM,
  744. PN544_HCI_LLC_MAX_PAYLOAD);
  745. if (!info->hdev) {
  746. dev_err(&client->dev, "Cannot allocate nfc hdev.\n");
  747. r = -ENOMEM;
  748. goto err_alloc_hdev;
  749. }
  750. nfc_hci_set_clientdata(info->hdev, info);
  751. r = nfc_hci_register_device(info->hdev);
  752. if (r)
  753. goto err_regdev;
  754. return 0;
  755. err_regdev:
  756. nfc_hci_free_device(info->hdev);
  757. err_alloc_hdev:
  758. free_irq(client->irq, info);
  759. err_rti:
  760. if (pdata->free_resources != NULL)
  761. pdata->free_resources();
  762. err_pdata:
  763. kfree(info);
  764. err_info_alloc:
  765. return r;
  766. }
  767. static __devexit int pn544_hci_remove(struct i2c_client *client)
  768. {
  769. struct pn544_hci_info *info = i2c_get_clientdata(client);
  770. struct pn544_nfc_platform_data *pdata = client->dev.platform_data;
  771. dev_dbg(&client->dev, "%s\n", __func__);
  772. nfc_hci_free_device(info->hdev);
  773. if (info->state != PN544_ST_COLD) {
  774. if (pdata->disable)
  775. pdata->disable();
  776. }
  777. free_irq(client->irq, info);
  778. if (pdata->free_resources)
  779. pdata->free_resources();
  780. kfree(info);
  781. return 0;
  782. }
  783. static struct i2c_driver pn544_hci_driver = {
  784. .driver = {
  785. .name = PN544_HCI_DRIVER_NAME,
  786. },
  787. .probe = pn544_hci_probe,
  788. .id_table = pn544_hci_id_table,
  789. .remove = __devexit_p(pn544_hci_remove),
  790. };
  791. static int __init pn544_hci_init(void)
  792. {
  793. int r;
  794. pr_debug(DRIVER_DESC ": %s\n", __func__);
  795. r = i2c_add_driver(&pn544_hci_driver);
  796. if (r) {
  797. pr_err(PN544_HCI_DRIVER_NAME ": driver registration failed\n");
  798. return r;
  799. }
  800. return 0;
  801. }
  802. static void __exit pn544_hci_exit(void)
  803. {
  804. i2c_del_driver(&pn544_hci_driver);
  805. }
  806. module_init(pn544_hci_init);
  807. module_exit(pn544_hci_exit);
  808. MODULE_LICENSE("GPL");
  809. MODULE_DESCRIPTION(DRIVER_DESC);