main.c 58 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK))) {
  117. mode = ATH9K_PM_NETWORK_SLEEP;
  118. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  119. ath9k_btcoex_stop_gen_timer(sc);
  120. } else {
  121. goto unlock;
  122. }
  123. spin_lock(&common->cc_lock);
  124. ath_hw_cycle_counters_update(common);
  125. spin_unlock(&common->cc_lock);
  126. ath9k_hw_setpower(sc->sc_ah, mode);
  127. unlock:
  128. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  129. }
  130. static void __ath_cancel_work(struct ath_softc *sc)
  131. {
  132. cancel_work_sync(&sc->paprd_work);
  133. cancel_work_sync(&sc->hw_check_work);
  134. cancel_delayed_work_sync(&sc->tx_complete_work);
  135. cancel_delayed_work_sync(&sc->hw_pll_work);
  136. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  137. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  138. cancel_work_sync(&sc->mci_work);
  139. #endif
  140. }
  141. static void ath_cancel_work(struct ath_softc *sc)
  142. {
  143. __ath_cancel_work(sc);
  144. cancel_work_sync(&sc->hw_reset_work);
  145. }
  146. static void ath_restart_work(struct ath_softc *sc)
  147. {
  148. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  149. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  150. AR_SREV_9550(sc->sc_ah))
  151. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  152. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  153. ath_start_rx_poll(sc, 3);
  154. ath_start_ani(sc);
  155. }
  156. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  157. {
  158. struct ath_hw *ah = sc->sc_ah;
  159. bool ret = true;
  160. ieee80211_stop_queues(sc->hw);
  161. sc->hw_busy_count = 0;
  162. ath_stop_ani(sc);
  163. del_timer_sync(&sc->rx_poll_timer);
  164. ath9k_debug_samp_bb_mac(sc);
  165. ath9k_hw_disable_interrupts(ah);
  166. if (!ath_stoprecv(sc))
  167. ret = false;
  168. if (!ath_drain_all_txq(sc, retry_tx))
  169. ret = false;
  170. if (!flush) {
  171. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  172. ath_rx_tasklet(sc, 1, true);
  173. ath_rx_tasklet(sc, 1, false);
  174. } else {
  175. ath_flushrecv(sc);
  176. }
  177. return ret;
  178. }
  179. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  180. {
  181. struct ath_hw *ah = sc->sc_ah;
  182. struct ath_common *common = ath9k_hw_common(ah);
  183. unsigned long flags;
  184. if (ath_startrecv(sc) != 0) {
  185. ath_err(common, "Unable to restart recv logic\n");
  186. return false;
  187. }
  188. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  189. sc->config.txpowlimit, &sc->curtxpow);
  190. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  191. ath9k_hw_set_interrupts(ah);
  192. ath9k_hw_enable_interrupts(ah);
  193. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  194. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  195. goto work;
  196. ath9k_set_beacon(sc);
  197. if (ah->opmode == NL80211_IFTYPE_STATION &&
  198. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  199. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  200. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  201. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  202. }
  203. work:
  204. ath_restart_work(sc);
  205. }
  206. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  207. ath_ant_comb_update(sc);
  208. ieee80211_wake_queues(sc->hw);
  209. return true;
  210. }
  211. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  212. bool retry_tx)
  213. {
  214. struct ath_hw *ah = sc->sc_ah;
  215. struct ath_common *common = ath9k_hw_common(ah);
  216. struct ath9k_hw_cal_data *caldata = NULL;
  217. bool fastcc = true;
  218. bool flush = false;
  219. int r;
  220. __ath_cancel_work(sc);
  221. spin_lock_bh(&sc->sc_pcu_lock);
  222. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  223. fastcc = false;
  224. caldata = &sc->caldata;
  225. }
  226. if (!hchan) {
  227. fastcc = false;
  228. flush = true;
  229. hchan = ah->curchan;
  230. }
  231. if (!ath_prepare_reset(sc, retry_tx, flush))
  232. fastcc = false;
  233. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  234. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  235. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  236. if (r) {
  237. ath_err(common,
  238. "Unable to reset channel, reset status %d\n", r);
  239. goto out;
  240. }
  241. if (!ath_complete_reset(sc, true))
  242. r = -EIO;
  243. out:
  244. spin_unlock_bh(&sc->sc_pcu_lock);
  245. return r;
  246. }
  247. /*
  248. * Set/change channels. If the channel is really being changed, it's done
  249. * by reseting the chip. To accomplish this we must first cleanup any pending
  250. * DMA, then restart stuff.
  251. */
  252. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  253. struct ath9k_channel *hchan)
  254. {
  255. int r;
  256. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  257. return -EIO;
  258. r = ath_reset_internal(sc, hchan, false);
  259. return r;
  260. }
  261. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  262. struct ieee80211_vif *vif)
  263. {
  264. struct ath_node *an;
  265. u8 density;
  266. an = (struct ath_node *)sta->drv_priv;
  267. #ifdef CONFIG_ATH9K_DEBUGFS
  268. spin_lock(&sc->nodes_lock);
  269. list_add(&an->list, &sc->nodes);
  270. spin_unlock(&sc->nodes_lock);
  271. #endif
  272. an->sta = sta;
  273. an->vif = vif;
  274. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  275. ath_tx_node_init(sc, an);
  276. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  277. sta->ht_cap.ampdu_factor);
  278. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  279. an->mpdudensity = density;
  280. }
  281. }
  282. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  283. {
  284. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  285. #ifdef CONFIG_ATH9K_DEBUGFS
  286. spin_lock(&sc->nodes_lock);
  287. list_del(&an->list);
  288. spin_unlock(&sc->nodes_lock);
  289. an->sta = NULL;
  290. #endif
  291. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  292. ath_tx_node_cleanup(sc, an);
  293. }
  294. void ath9k_tasklet(unsigned long data)
  295. {
  296. struct ath_softc *sc = (struct ath_softc *)data;
  297. struct ath_hw *ah = sc->sc_ah;
  298. struct ath_common *common = ath9k_hw_common(ah);
  299. enum ath_reset_type type;
  300. unsigned long flags;
  301. u32 status = sc->intrstatus;
  302. u32 rxmask;
  303. ath9k_ps_wakeup(sc);
  304. spin_lock(&sc->sc_pcu_lock);
  305. if ((status & ATH9K_INT_FATAL) ||
  306. (status & ATH9K_INT_BB_WATCHDOG)) {
  307. if (status & ATH9K_INT_FATAL)
  308. type = RESET_TYPE_FATAL_INT;
  309. else
  310. type = RESET_TYPE_BB_WATCHDOG;
  311. ath9k_queue_reset(sc, type);
  312. goto out;
  313. }
  314. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  315. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  316. /*
  317. * TSF sync does not look correct; remain awake to sync with
  318. * the next Beacon.
  319. */
  320. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  321. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  322. }
  323. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  324. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  325. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  326. ATH9K_INT_RXORN);
  327. else
  328. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  329. if (status & rxmask) {
  330. /* Check for high priority Rx first */
  331. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  332. (status & ATH9K_INT_RXHP))
  333. ath_rx_tasklet(sc, 0, true);
  334. ath_rx_tasklet(sc, 0, false);
  335. }
  336. if (status & ATH9K_INT_TX) {
  337. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  338. ath_tx_edma_tasklet(sc);
  339. else
  340. ath_tx_tasklet(sc);
  341. }
  342. ath9k_btcoex_handle_interrupt(sc, status);
  343. out:
  344. /* re-enable hardware interrupt */
  345. ath9k_hw_enable_interrupts(ah);
  346. spin_unlock(&sc->sc_pcu_lock);
  347. ath9k_ps_restore(sc);
  348. }
  349. irqreturn_t ath_isr(int irq, void *dev)
  350. {
  351. #define SCHED_INTR ( \
  352. ATH9K_INT_FATAL | \
  353. ATH9K_INT_BB_WATCHDOG | \
  354. ATH9K_INT_RXORN | \
  355. ATH9K_INT_RXEOL | \
  356. ATH9K_INT_RX | \
  357. ATH9K_INT_RXLP | \
  358. ATH9K_INT_RXHP | \
  359. ATH9K_INT_TX | \
  360. ATH9K_INT_BMISS | \
  361. ATH9K_INT_CST | \
  362. ATH9K_INT_TSFOOR | \
  363. ATH9K_INT_GENTIMER | \
  364. ATH9K_INT_MCI)
  365. struct ath_softc *sc = dev;
  366. struct ath_hw *ah = sc->sc_ah;
  367. struct ath_common *common = ath9k_hw_common(ah);
  368. enum ath9k_int status;
  369. bool sched = false;
  370. /*
  371. * The hardware is not ready/present, don't
  372. * touch anything. Note this can happen early
  373. * on if the IRQ is shared.
  374. */
  375. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  376. return IRQ_NONE;
  377. /* shared irq, not for us */
  378. if (!ath9k_hw_intrpend(ah))
  379. return IRQ_NONE;
  380. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  381. ath9k_hw_kill_interrupts(ah);
  382. return IRQ_HANDLED;
  383. }
  384. /*
  385. * Figure out the reason(s) for the interrupt. Note
  386. * that the hal returns a pseudo-ISR that may include
  387. * bits we haven't explicitly enabled so we mask the
  388. * value to insure we only process bits we requested.
  389. */
  390. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  391. status &= ah->imask; /* discard unasked-for bits */
  392. /*
  393. * If there are no status bits set, then this interrupt was not
  394. * for me (should have been caught above).
  395. */
  396. if (!status)
  397. return IRQ_NONE;
  398. /* Cache the status */
  399. sc->intrstatus = status;
  400. if (status & SCHED_INTR)
  401. sched = true;
  402. #ifdef CONFIG_PM_SLEEP
  403. if (status & ATH9K_INT_BMISS) {
  404. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  405. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  406. atomic_inc(&sc->wow_got_bmiss_intr);
  407. atomic_dec(&sc->wow_sleep_proc_intr);
  408. }
  409. ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
  410. }
  411. #endif
  412. /*
  413. * If a FATAL or RXORN interrupt is received, we have to reset the
  414. * chip immediately.
  415. */
  416. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  417. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  418. goto chip_reset;
  419. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  420. (status & ATH9K_INT_BB_WATCHDOG)) {
  421. spin_lock(&common->cc_lock);
  422. ath_hw_cycle_counters_update(common);
  423. ar9003_hw_bb_watchdog_dbg_info(ah);
  424. spin_unlock(&common->cc_lock);
  425. goto chip_reset;
  426. }
  427. if (status & ATH9K_INT_SWBA)
  428. tasklet_schedule(&sc->bcon_tasklet);
  429. if (status & ATH9K_INT_TXURN)
  430. ath9k_hw_updatetxtriglevel(ah, true);
  431. if (status & ATH9K_INT_RXEOL) {
  432. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  433. ath9k_hw_set_interrupts(ah);
  434. }
  435. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  436. if (status & ATH9K_INT_TIM_TIMER) {
  437. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  438. goto chip_reset;
  439. /* Clear RxAbort bit so that we can
  440. * receive frames */
  441. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  442. spin_lock(&sc->sc_pm_lock);
  443. ath9k_hw_setrxabort(sc->sc_ah, 0);
  444. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  445. spin_unlock(&sc->sc_pm_lock);
  446. }
  447. chip_reset:
  448. ath_debug_stat_interrupt(sc, status);
  449. if (sched) {
  450. /* turn off every interrupt */
  451. ath9k_hw_disable_interrupts(ah);
  452. tasklet_schedule(&sc->intr_tq);
  453. }
  454. return IRQ_HANDLED;
  455. #undef SCHED_INTR
  456. }
  457. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  458. {
  459. int r;
  460. ath9k_ps_wakeup(sc);
  461. r = ath_reset_internal(sc, NULL, retry_tx);
  462. if (retry_tx) {
  463. int i;
  464. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  465. if (ATH_TXQ_SETUP(sc, i)) {
  466. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  467. ath_txq_schedule(sc, &sc->tx.txq[i]);
  468. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  469. }
  470. }
  471. }
  472. ath9k_ps_restore(sc);
  473. return r;
  474. }
  475. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  476. {
  477. #ifdef CONFIG_ATH9K_DEBUGFS
  478. RESET_STAT_INC(sc, type);
  479. #endif
  480. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  481. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  482. }
  483. void ath_reset_work(struct work_struct *work)
  484. {
  485. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  486. ath_reset(sc, true);
  487. }
  488. /**********************/
  489. /* mac80211 callbacks */
  490. /**********************/
  491. static int ath9k_start(struct ieee80211_hw *hw)
  492. {
  493. struct ath_softc *sc = hw->priv;
  494. struct ath_hw *ah = sc->sc_ah;
  495. struct ath_common *common = ath9k_hw_common(ah);
  496. struct ieee80211_channel *curchan = hw->conf.channel;
  497. struct ath9k_channel *init_channel;
  498. int r;
  499. ath_dbg(common, CONFIG,
  500. "Starting driver with initial channel: %d MHz\n",
  501. curchan->center_freq);
  502. ath9k_ps_wakeup(sc);
  503. mutex_lock(&sc->mutex);
  504. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  505. /* Reset SERDES registers */
  506. ath9k_hw_configpcipowersave(ah, false);
  507. /*
  508. * The basic interface to setting the hardware in a good
  509. * state is ``reset''. On return the hardware is known to
  510. * be powered up and with interrupts disabled. This must
  511. * be followed by initialization of the appropriate bits
  512. * and then setup of the interrupt mask.
  513. */
  514. spin_lock_bh(&sc->sc_pcu_lock);
  515. atomic_set(&ah->intr_ref_cnt, -1);
  516. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  517. if (r) {
  518. ath_err(common,
  519. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  520. r, curchan->center_freq);
  521. ah->reset_power_on = false;
  522. }
  523. /* Setup our intr mask. */
  524. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  525. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  526. ATH9K_INT_GLOBAL;
  527. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  528. ah->imask |= ATH9K_INT_RXHP |
  529. ATH9K_INT_RXLP |
  530. ATH9K_INT_BB_WATCHDOG;
  531. else
  532. ah->imask |= ATH9K_INT_RX;
  533. ah->imask |= ATH9K_INT_GTT;
  534. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  535. ah->imask |= ATH9K_INT_CST;
  536. ath_mci_enable(sc);
  537. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  538. sc->sc_ah->is_monitoring = false;
  539. if (!ath_complete_reset(sc, false))
  540. ah->reset_power_on = false;
  541. if (ah->led_pin >= 0) {
  542. ath9k_hw_cfg_output(ah, ah->led_pin,
  543. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  544. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  545. }
  546. /*
  547. * Reset key cache to sane defaults (all entries cleared) instead of
  548. * semi-random values after suspend/resume.
  549. */
  550. ath9k_cmn_init_crypto(sc->sc_ah);
  551. spin_unlock_bh(&sc->sc_pcu_lock);
  552. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  553. common->bus_ops->extn_synch_en(common);
  554. mutex_unlock(&sc->mutex);
  555. ath9k_ps_restore(sc);
  556. return 0;
  557. }
  558. static void ath9k_tx(struct ieee80211_hw *hw,
  559. struct ieee80211_tx_control *control,
  560. struct sk_buff *skb)
  561. {
  562. struct ath_softc *sc = hw->priv;
  563. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  564. struct ath_tx_control txctl;
  565. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  566. unsigned long flags;
  567. if (sc->ps_enabled) {
  568. /*
  569. * mac80211 does not set PM field for normal data frames, so we
  570. * need to update that based on the current PS mode.
  571. */
  572. if (ieee80211_is_data(hdr->frame_control) &&
  573. !ieee80211_is_nullfunc(hdr->frame_control) &&
  574. !ieee80211_has_pm(hdr->frame_control)) {
  575. ath_dbg(common, PS,
  576. "Add PM=1 for a TX frame while in PS mode\n");
  577. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  578. }
  579. }
  580. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  581. /*
  582. * We are using PS-Poll and mac80211 can request TX while in
  583. * power save mode. Need to wake up hardware for the TX to be
  584. * completed and if needed, also for RX of buffered frames.
  585. */
  586. ath9k_ps_wakeup(sc);
  587. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  588. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  589. ath9k_hw_setrxabort(sc->sc_ah, 0);
  590. if (ieee80211_is_pspoll(hdr->frame_control)) {
  591. ath_dbg(common, PS,
  592. "Sending PS-Poll to pick a buffered frame\n");
  593. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  594. } else {
  595. ath_dbg(common, PS, "Wake up to complete TX\n");
  596. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  597. }
  598. /*
  599. * The actual restore operation will happen only after
  600. * the ps_flags bit is cleared. We are just dropping
  601. * the ps_usecount here.
  602. */
  603. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  604. ath9k_ps_restore(sc);
  605. }
  606. /*
  607. * Cannot tx while the hardware is in full sleep, it first needs a full
  608. * chip reset to recover from that
  609. */
  610. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  611. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  612. goto exit;
  613. }
  614. memset(&txctl, 0, sizeof(struct ath_tx_control));
  615. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  616. txctl.sta = control->sta;
  617. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  618. if (ath_tx_start(hw, skb, &txctl) != 0) {
  619. ath_dbg(common, XMIT, "TX failed\n");
  620. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  621. goto exit;
  622. }
  623. return;
  624. exit:
  625. ieee80211_free_txskb(hw, skb);
  626. }
  627. static void ath9k_stop(struct ieee80211_hw *hw)
  628. {
  629. struct ath_softc *sc = hw->priv;
  630. struct ath_hw *ah = sc->sc_ah;
  631. struct ath_common *common = ath9k_hw_common(ah);
  632. bool prev_idle;
  633. mutex_lock(&sc->mutex);
  634. ath_cancel_work(sc);
  635. del_timer_sync(&sc->rx_poll_timer);
  636. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  637. ath_dbg(common, ANY, "Device not present\n");
  638. mutex_unlock(&sc->mutex);
  639. return;
  640. }
  641. /* Ensure HW is awake when we try to shut it down. */
  642. ath9k_ps_wakeup(sc);
  643. spin_lock_bh(&sc->sc_pcu_lock);
  644. /* prevent tasklets to enable interrupts once we disable them */
  645. ah->imask &= ~ATH9K_INT_GLOBAL;
  646. /* make sure h/w will not generate any interrupt
  647. * before setting the invalid flag. */
  648. ath9k_hw_disable_interrupts(ah);
  649. spin_unlock_bh(&sc->sc_pcu_lock);
  650. /* we can now sync irq and kill any running tasklets, since we already
  651. * disabled interrupts and not holding a spin lock */
  652. synchronize_irq(sc->irq);
  653. tasklet_kill(&sc->intr_tq);
  654. tasklet_kill(&sc->bcon_tasklet);
  655. prev_idle = sc->ps_idle;
  656. sc->ps_idle = true;
  657. spin_lock_bh(&sc->sc_pcu_lock);
  658. if (ah->led_pin >= 0) {
  659. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  660. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  661. }
  662. ath_prepare_reset(sc, false, true);
  663. if (sc->rx.frag) {
  664. dev_kfree_skb_any(sc->rx.frag);
  665. sc->rx.frag = NULL;
  666. }
  667. if (!ah->curchan)
  668. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  669. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  670. ath9k_hw_phy_disable(ah);
  671. ath9k_hw_configpcipowersave(ah, true);
  672. spin_unlock_bh(&sc->sc_pcu_lock);
  673. ath9k_ps_restore(sc);
  674. set_bit(SC_OP_INVALID, &sc->sc_flags);
  675. sc->ps_idle = prev_idle;
  676. mutex_unlock(&sc->mutex);
  677. ath_dbg(common, CONFIG, "Driver halt\n");
  678. }
  679. bool ath9k_uses_beacons(int type)
  680. {
  681. switch (type) {
  682. case NL80211_IFTYPE_AP:
  683. case NL80211_IFTYPE_ADHOC:
  684. case NL80211_IFTYPE_MESH_POINT:
  685. return true;
  686. default:
  687. return false;
  688. }
  689. }
  690. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  691. {
  692. struct ath9k_vif_iter_data *iter_data = data;
  693. int i;
  694. if (iter_data->hw_macaddr)
  695. for (i = 0; i < ETH_ALEN; i++)
  696. iter_data->mask[i] &=
  697. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  698. switch (vif->type) {
  699. case NL80211_IFTYPE_AP:
  700. iter_data->naps++;
  701. break;
  702. case NL80211_IFTYPE_STATION:
  703. iter_data->nstations++;
  704. break;
  705. case NL80211_IFTYPE_ADHOC:
  706. iter_data->nadhocs++;
  707. break;
  708. case NL80211_IFTYPE_MESH_POINT:
  709. iter_data->nmeshes++;
  710. break;
  711. case NL80211_IFTYPE_WDS:
  712. iter_data->nwds++;
  713. break;
  714. default:
  715. break;
  716. }
  717. }
  718. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  719. {
  720. struct ath_softc *sc = data;
  721. struct ath_vif *avp = (void *)vif->drv_priv;
  722. if (vif->type != NL80211_IFTYPE_STATION)
  723. return;
  724. if (avp->primary_sta_vif)
  725. ath9k_set_assoc_state(sc, vif);
  726. }
  727. /* Called with sc->mutex held. */
  728. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  729. struct ieee80211_vif *vif,
  730. struct ath9k_vif_iter_data *iter_data)
  731. {
  732. struct ath_softc *sc = hw->priv;
  733. struct ath_hw *ah = sc->sc_ah;
  734. struct ath_common *common = ath9k_hw_common(ah);
  735. /*
  736. * Use the hardware MAC address as reference, the hardware uses it
  737. * together with the BSSID mask when matching addresses.
  738. */
  739. memset(iter_data, 0, sizeof(*iter_data));
  740. iter_data->hw_macaddr = common->macaddr;
  741. memset(&iter_data->mask, 0xff, ETH_ALEN);
  742. if (vif)
  743. ath9k_vif_iter(iter_data, vif->addr, vif);
  744. /* Get list of all active MAC addresses */
  745. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  746. iter_data);
  747. }
  748. /* Called with sc->mutex held. */
  749. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  750. struct ieee80211_vif *vif)
  751. {
  752. struct ath_softc *sc = hw->priv;
  753. struct ath_hw *ah = sc->sc_ah;
  754. struct ath_common *common = ath9k_hw_common(ah);
  755. struct ath9k_vif_iter_data iter_data;
  756. enum nl80211_iftype old_opmode = ah->opmode;
  757. ath9k_calculate_iter_data(hw, vif, &iter_data);
  758. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  759. ath_hw_setbssidmask(common);
  760. if (iter_data.naps > 0) {
  761. ath9k_hw_set_tsfadjust(ah, true);
  762. ah->opmode = NL80211_IFTYPE_AP;
  763. } else {
  764. ath9k_hw_set_tsfadjust(ah, false);
  765. if (iter_data.nmeshes)
  766. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  767. else if (iter_data.nwds)
  768. ah->opmode = NL80211_IFTYPE_AP;
  769. else if (iter_data.nadhocs)
  770. ah->opmode = NL80211_IFTYPE_ADHOC;
  771. else
  772. ah->opmode = NL80211_IFTYPE_STATION;
  773. }
  774. ath9k_hw_setopmode(ah);
  775. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  776. ah->imask |= ATH9K_INT_TSFOOR;
  777. else
  778. ah->imask &= ~ATH9K_INT_TSFOOR;
  779. ath9k_hw_set_interrupts(ah);
  780. /*
  781. * If we are changing the opmode to STATION,
  782. * a beacon sync needs to be done.
  783. */
  784. if (ah->opmode == NL80211_IFTYPE_STATION &&
  785. old_opmode == NL80211_IFTYPE_AP &&
  786. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  787. ieee80211_iterate_active_interfaces_atomic(sc->hw,
  788. ath9k_sta_vif_iter, sc);
  789. }
  790. }
  791. static int ath9k_add_interface(struct ieee80211_hw *hw,
  792. struct ieee80211_vif *vif)
  793. {
  794. struct ath_softc *sc = hw->priv;
  795. struct ath_hw *ah = sc->sc_ah;
  796. struct ath_common *common = ath9k_hw_common(ah);
  797. mutex_lock(&sc->mutex);
  798. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  799. sc->nvifs++;
  800. ath9k_ps_wakeup(sc);
  801. ath9k_calculate_summary_state(hw, vif);
  802. ath9k_ps_restore(sc);
  803. if (ath9k_uses_beacons(vif->type))
  804. ath9k_beacon_assign_slot(sc, vif);
  805. mutex_unlock(&sc->mutex);
  806. return 0;
  807. }
  808. static int ath9k_change_interface(struct ieee80211_hw *hw,
  809. struct ieee80211_vif *vif,
  810. enum nl80211_iftype new_type,
  811. bool p2p)
  812. {
  813. struct ath_softc *sc = hw->priv;
  814. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  815. ath_dbg(common, CONFIG, "Change Interface\n");
  816. mutex_lock(&sc->mutex);
  817. if (ath9k_uses_beacons(vif->type))
  818. ath9k_beacon_remove_slot(sc, vif);
  819. vif->type = new_type;
  820. vif->p2p = p2p;
  821. ath9k_ps_wakeup(sc);
  822. ath9k_calculate_summary_state(hw, vif);
  823. ath9k_ps_restore(sc);
  824. if (ath9k_uses_beacons(vif->type))
  825. ath9k_beacon_assign_slot(sc, vif);
  826. mutex_unlock(&sc->mutex);
  827. return 0;
  828. }
  829. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  830. struct ieee80211_vif *vif)
  831. {
  832. struct ath_softc *sc = hw->priv;
  833. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  834. ath_dbg(common, CONFIG, "Detach Interface\n");
  835. mutex_lock(&sc->mutex);
  836. sc->nvifs--;
  837. if (ath9k_uses_beacons(vif->type))
  838. ath9k_beacon_remove_slot(sc, vif);
  839. ath9k_ps_wakeup(sc);
  840. ath9k_calculate_summary_state(hw, NULL);
  841. ath9k_ps_restore(sc);
  842. mutex_unlock(&sc->mutex);
  843. }
  844. static void ath9k_enable_ps(struct ath_softc *sc)
  845. {
  846. struct ath_hw *ah = sc->sc_ah;
  847. struct ath_common *common = ath9k_hw_common(ah);
  848. sc->ps_enabled = true;
  849. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  850. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  851. ah->imask |= ATH9K_INT_TIM_TIMER;
  852. ath9k_hw_set_interrupts(ah);
  853. }
  854. ath9k_hw_setrxabort(ah, 1);
  855. }
  856. ath_dbg(common, PS, "PowerSave enabled\n");
  857. }
  858. static void ath9k_disable_ps(struct ath_softc *sc)
  859. {
  860. struct ath_hw *ah = sc->sc_ah;
  861. struct ath_common *common = ath9k_hw_common(ah);
  862. sc->ps_enabled = false;
  863. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  864. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  865. ath9k_hw_setrxabort(ah, 0);
  866. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  867. PS_WAIT_FOR_CAB |
  868. PS_WAIT_FOR_PSPOLL_DATA |
  869. PS_WAIT_FOR_TX_ACK);
  870. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  871. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  872. ath9k_hw_set_interrupts(ah);
  873. }
  874. }
  875. ath_dbg(common, PS, "PowerSave disabled\n");
  876. }
  877. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  878. {
  879. struct ath_softc *sc = hw->priv;
  880. struct ath_hw *ah = sc->sc_ah;
  881. struct ath_common *common = ath9k_hw_common(ah);
  882. struct ieee80211_conf *conf = &hw->conf;
  883. bool reset_channel = false;
  884. ath9k_ps_wakeup(sc);
  885. mutex_lock(&sc->mutex);
  886. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  887. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  888. if (sc->ps_idle) {
  889. ath_cancel_work(sc);
  890. ath9k_stop_btcoex(sc);
  891. } else {
  892. ath9k_start_btcoex(sc);
  893. /*
  894. * The chip needs a reset to properly wake up from
  895. * full sleep
  896. */
  897. reset_channel = ah->chip_fullsleep;
  898. }
  899. }
  900. /*
  901. * We just prepare to enable PS. We have to wait until our AP has
  902. * ACK'd our null data frame to disable RX otherwise we'll ignore
  903. * those ACKs and end up retransmitting the same null data frames.
  904. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  905. */
  906. if (changed & IEEE80211_CONF_CHANGE_PS) {
  907. unsigned long flags;
  908. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  909. if (conf->flags & IEEE80211_CONF_PS)
  910. ath9k_enable_ps(sc);
  911. else
  912. ath9k_disable_ps(sc);
  913. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  914. }
  915. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  916. if (conf->flags & IEEE80211_CONF_MONITOR) {
  917. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  918. sc->sc_ah->is_monitoring = true;
  919. } else {
  920. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  921. sc->sc_ah->is_monitoring = false;
  922. }
  923. }
  924. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  925. struct ieee80211_channel *curchan = hw->conf.channel;
  926. int pos = curchan->hw_value;
  927. int old_pos = -1;
  928. unsigned long flags;
  929. if (ah->curchan)
  930. old_pos = ah->curchan - &ah->channels[0];
  931. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  932. curchan->center_freq, conf->channel_type);
  933. /* update survey stats for the old channel before switching */
  934. spin_lock_irqsave(&common->cc_lock, flags);
  935. ath_update_survey_stats(sc);
  936. spin_unlock_irqrestore(&common->cc_lock, flags);
  937. /*
  938. * Preserve the current channel values, before updating
  939. * the same channel
  940. */
  941. if (ah->curchan && (old_pos == pos))
  942. ath9k_hw_getnf(ah, ah->curchan);
  943. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  944. curchan, conf->channel_type);
  945. /*
  946. * If the operating channel changes, change the survey in-use flags
  947. * along with it.
  948. * Reset the survey data for the new channel, unless we're switching
  949. * back to the operating channel from an off-channel operation.
  950. */
  951. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  952. sc->cur_survey != &sc->survey[pos]) {
  953. if (sc->cur_survey)
  954. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  955. sc->cur_survey = &sc->survey[pos];
  956. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  957. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  958. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  959. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  960. }
  961. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  962. ath_err(common, "Unable to set channel\n");
  963. mutex_unlock(&sc->mutex);
  964. ath9k_ps_restore(sc);
  965. return -EINVAL;
  966. }
  967. /*
  968. * The most recent snapshot of channel->noisefloor for the old
  969. * channel is only available after the hardware reset. Copy it to
  970. * the survey stats now.
  971. */
  972. if (old_pos >= 0)
  973. ath_update_survey_nf(sc, old_pos);
  974. }
  975. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  976. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  977. sc->config.txpowlimit = 2 * conf->power_level;
  978. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  979. sc->config.txpowlimit, &sc->curtxpow);
  980. }
  981. mutex_unlock(&sc->mutex);
  982. ath9k_ps_restore(sc);
  983. return 0;
  984. }
  985. #define SUPPORTED_FILTERS \
  986. (FIF_PROMISC_IN_BSS | \
  987. FIF_ALLMULTI | \
  988. FIF_CONTROL | \
  989. FIF_PSPOLL | \
  990. FIF_OTHER_BSS | \
  991. FIF_BCN_PRBRESP_PROMISC | \
  992. FIF_PROBE_REQ | \
  993. FIF_FCSFAIL)
  994. /* FIXME: sc->sc_full_reset ? */
  995. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  996. unsigned int changed_flags,
  997. unsigned int *total_flags,
  998. u64 multicast)
  999. {
  1000. struct ath_softc *sc = hw->priv;
  1001. u32 rfilt;
  1002. changed_flags &= SUPPORTED_FILTERS;
  1003. *total_flags &= SUPPORTED_FILTERS;
  1004. sc->rx.rxfilter = *total_flags;
  1005. ath9k_ps_wakeup(sc);
  1006. rfilt = ath_calcrxfilter(sc);
  1007. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1008. ath9k_ps_restore(sc);
  1009. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1010. rfilt);
  1011. }
  1012. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1013. struct ieee80211_vif *vif,
  1014. struct ieee80211_sta *sta)
  1015. {
  1016. struct ath_softc *sc = hw->priv;
  1017. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1018. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1019. struct ieee80211_key_conf ps_key = { };
  1020. ath_node_attach(sc, sta, vif);
  1021. if (vif->type != NL80211_IFTYPE_AP &&
  1022. vif->type != NL80211_IFTYPE_AP_VLAN)
  1023. return 0;
  1024. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1025. return 0;
  1026. }
  1027. static void ath9k_del_ps_key(struct ath_softc *sc,
  1028. struct ieee80211_vif *vif,
  1029. struct ieee80211_sta *sta)
  1030. {
  1031. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1032. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1033. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1034. if (!an->ps_key)
  1035. return;
  1036. ath_key_delete(common, &ps_key);
  1037. }
  1038. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1039. struct ieee80211_vif *vif,
  1040. struct ieee80211_sta *sta)
  1041. {
  1042. struct ath_softc *sc = hw->priv;
  1043. ath9k_del_ps_key(sc, vif, sta);
  1044. ath_node_detach(sc, sta);
  1045. return 0;
  1046. }
  1047. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1048. struct ieee80211_vif *vif,
  1049. enum sta_notify_cmd cmd,
  1050. struct ieee80211_sta *sta)
  1051. {
  1052. struct ath_softc *sc = hw->priv;
  1053. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1054. if (!sta->ht_cap.ht_supported)
  1055. return;
  1056. switch (cmd) {
  1057. case STA_NOTIFY_SLEEP:
  1058. an->sleeping = true;
  1059. ath_tx_aggr_sleep(sta, sc, an);
  1060. break;
  1061. case STA_NOTIFY_AWAKE:
  1062. an->sleeping = false;
  1063. ath_tx_aggr_wakeup(sc, an);
  1064. break;
  1065. }
  1066. }
  1067. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1068. struct ieee80211_vif *vif, u16 queue,
  1069. const struct ieee80211_tx_queue_params *params)
  1070. {
  1071. struct ath_softc *sc = hw->priv;
  1072. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1073. struct ath_txq *txq;
  1074. struct ath9k_tx_queue_info qi;
  1075. int ret = 0;
  1076. if (queue >= WME_NUM_AC)
  1077. return 0;
  1078. txq = sc->tx.txq_map[queue];
  1079. ath9k_ps_wakeup(sc);
  1080. mutex_lock(&sc->mutex);
  1081. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1082. qi.tqi_aifs = params->aifs;
  1083. qi.tqi_cwmin = params->cw_min;
  1084. qi.tqi_cwmax = params->cw_max;
  1085. qi.tqi_burstTime = params->txop * 32;
  1086. ath_dbg(common, CONFIG,
  1087. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1088. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1089. params->cw_max, params->txop);
  1090. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1091. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1092. if (ret)
  1093. ath_err(common, "TXQ Update failed\n");
  1094. mutex_unlock(&sc->mutex);
  1095. ath9k_ps_restore(sc);
  1096. return ret;
  1097. }
  1098. static int ath9k_set_key(struct ieee80211_hw *hw,
  1099. enum set_key_cmd cmd,
  1100. struct ieee80211_vif *vif,
  1101. struct ieee80211_sta *sta,
  1102. struct ieee80211_key_conf *key)
  1103. {
  1104. struct ath_softc *sc = hw->priv;
  1105. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1106. int ret = 0;
  1107. if (ath9k_modparam_nohwcrypt)
  1108. return -ENOSPC;
  1109. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1110. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1111. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1112. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1113. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1114. /*
  1115. * For now, disable hw crypto for the RSN IBSS group keys. This
  1116. * could be optimized in the future to use a modified key cache
  1117. * design to support per-STA RX GTK, but until that gets
  1118. * implemented, use of software crypto for group addressed
  1119. * frames is a acceptable to allow RSN IBSS to be used.
  1120. */
  1121. return -EOPNOTSUPP;
  1122. }
  1123. mutex_lock(&sc->mutex);
  1124. ath9k_ps_wakeup(sc);
  1125. ath_dbg(common, CONFIG, "Set HW Key\n");
  1126. switch (cmd) {
  1127. case SET_KEY:
  1128. if (sta)
  1129. ath9k_del_ps_key(sc, vif, sta);
  1130. ret = ath_key_config(common, vif, sta, key);
  1131. if (ret >= 0) {
  1132. key->hw_key_idx = ret;
  1133. /* push IV and Michael MIC generation to stack */
  1134. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1135. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1136. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1137. if (sc->sc_ah->sw_mgmt_crypto &&
  1138. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1139. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1140. ret = 0;
  1141. }
  1142. break;
  1143. case DISABLE_KEY:
  1144. ath_key_delete(common, key);
  1145. break;
  1146. default:
  1147. ret = -EINVAL;
  1148. }
  1149. ath9k_ps_restore(sc);
  1150. mutex_unlock(&sc->mutex);
  1151. return ret;
  1152. }
  1153. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1154. struct ieee80211_vif *vif)
  1155. {
  1156. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1157. struct ath_vif *avp = (void *)vif->drv_priv;
  1158. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1159. unsigned long flags;
  1160. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1161. avp->primary_sta_vif = true;
  1162. /*
  1163. * Set the AID, BSSID and do beacon-sync only when
  1164. * the HW opmode is STATION.
  1165. *
  1166. * But the primary bit is set above in any case.
  1167. */
  1168. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1169. return;
  1170. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1171. common->curaid = bss_conf->aid;
  1172. ath9k_hw_write_associd(sc->sc_ah);
  1173. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1174. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1175. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1176. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1177. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1178. ath_dbg(common, CONFIG,
  1179. "Primary Station interface: %pM, BSSID: %pM\n",
  1180. vif->addr, common->curbssid);
  1181. }
  1182. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1183. {
  1184. struct ath_softc *sc = data;
  1185. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1186. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1187. return;
  1188. if (bss_conf->assoc)
  1189. ath9k_set_assoc_state(sc, vif);
  1190. }
  1191. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1192. struct ieee80211_vif *vif,
  1193. struct ieee80211_bss_conf *bss_conf,
  1194. u32 changed)
  1195. {
  1196. #define CHECK_ANI \
  1197. (BSS_CHANGED_ASSOC | \
  1198. BSS_CHANGED_IBSS | \
  1199. BSS_CHANGED_BEACON_ENABLED)
  1200. struct ath_softc *sc = hw->priv;
  1201. struct ath_hw *ah = sc->sc_ah;
  1202. struct ath_common *common = ath9k_hw_common(ah);
  1203. struct ath_vif *avp = (void *)vif->drv_priv;
  1204. int slottime;
  1205. ath9k_ps_wakeup(sc);
  1206. mutex_lock(&sc->mutex);
  1207. if (changed & BSS_CHANGED_ASSOC) {
  1208. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1209. bss_conf->bssid, bss_conf->assoc);
  1210. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1211. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1212. avp->primary_sta_vif = false;
  1213. if (ah->opmode == NL80211_IFTYPE_STATION)
  1214. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1215. }
  1216. ieee80211_iterate_active_interfaces_atomic(sc->hw,
  1217. ath9k_bss_assoc_iter, sc);
  1218. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1219. ah->opmode == NL80211_IFTYPE_STATION) {
  1220. memset(common->curbssid, 0, ETH_ALEN);
  1221. common->curaid = 0;
  1222. ath9k_hw_write_associd(sc->sc_ah);
  1223. }
  1224. }
  1225. if (changed & BSS_CHANGED_IBSS) {
  1226. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1227. common->curaid = bss_conf->aid;
  1228. ath9k_hw_write_associd(sc->sc_ah);
  1229. }
  1230. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1231. (changed & BSS_CHANGED_BEACON_INT)) {
  1232. if (ah->opmode == NL80211_IFTYPE_AP &&
  1233. bss_conf->enable_beacon)
  1234. ath9k_set_tsfadjust(sc, vif);
  1235. if (ath9k_allow_beacon_config(sc, vif))
  1236. ath9k_beacon_config(sc, vif, changed);
  1237. }
  1238. if (changed & BSS_CHANGED_ERP_SLOT) {
  1239. if (bss_conf->use_short_slot)
  1240. slottime = 9;
  1241. else
  1242. slottime = 20;
  1243. if (vif->type == NL80211_IFTYPE_AP) {
  1244. /*
  1245. * Defer update, so that connected stations can adjust
  1246. * their settings at the same time.
  1247. * See beacon.c for more details
  1248. */
  1249. sc->beacon.slottime = slottime;
  1250. sc->beacon.updateslot = UPDATE;
  1251. } else {
  1252. ah->slottime = slottime;
  1253. ath9k_hw_init_global_settings(ah);
  1254. }
  1255. }
  1256. if (changed & CHECK_ANI)
  1257. ath_check_ani(sc);
  1258. mutex_unlock(&sc->mutex);
  1259. ath9k_ps_restore(sc);
  1260. #undef CHECK_ANI
  1261. }
  1262. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1263. {
  1264. struct ath_softc *sc = hw->priv;
  1265. u64 tsf;
  1266. mutex_lock(&sc->mutex);
  1267. ath9k_ps_wakeup(sc);
  1268. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1269. ath9k_ps_restore(sc);
  1270. mutex_unlock(&sc->mutex);
  1271. return tsf;
  1272. }
  1273. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1274. struct ieee80211_vif *vif,
  1275. u64 tsf)
  1276. {
  1277. struct ath_softc *sc = hw->priv;
  1278. mutex_lock(&sc->mutex);
  1279. ath9k_ps_wakeup(sc);
  1280. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1281. ath9k_ps_restore(sc);
  1282. mutex_unlock(&sc->mutex);
  1283. }
  1284. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1285. {
  1286. struct ath_softc *sc = hw->priv;
  1287. mutex_lock(&sc->mutex);
  1288. ath9k_ps_wakeup(sc);
  1289. ath9k_hw_reset_tsf(sc->sc_ah);
  1290. ath9k_ps_restore(sc);
  1291. mutex_unlock(&sc->mutex);
  1292. }
  1293. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1294. struct ieee80211_vif *vif,
  1295. enum ieee80211_ampdu_mlme_action action,
  1296. struct ieee80211_sta *sta,
  1297. u16 tid, u16 *ssn, u8 buf_size)
  1298. {
  1299. struct ath_softc *sc = hw->priv;
  1300. int ret = 0;
  1301. local_bh_disable();
  1302. switch (action) {
  1303. case IEEE80211_AMPDU_RX_START:
  1304. break;
  1305. case IEEE80211_AMPDU_RX_STOP:
  1306. break;
  1307. case IEEE80211_AMPDU_TX_START:
  1308. ath9k_ps_wakeup(sc);
  1309. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1310. if (!ret)
  1311. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1312. ath9k_ps_restore(sc);
  1313. break;
  1314. case IEEE80211_AMPDU_TX_STOP:
  1315. ath9k_ps_wakeup(sc);
  1316. ath_tx_aggr_stop(sc, sta, tid);
  1317. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1318. ath9k_ps_restore(sc);
  1319. break;
  1320. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1321. ath9k_ps_wakeup(sc);
  1322. ath_tx_aggr_resume(sc, sta, tid);
  1323. ath9k_ps_restore(sc);
  1324. break;
  1325. default:
  1326. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1327. }
  1328. local_bh_enable();
  1329. return ret;
  1330. }
  1331. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1332. struct survey_info *survey)
  1333. {
  1334. struct ath_softc *sc = hw->priv;
  1335. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1336. struct ieee80211_supported_band *sband;
  1337. struct ieee80211_channel *chan;
  1338. unsigned long flags;
  1339. int pos;
  1340. spin_lock_irqsave(&common->cc_lock, flags);
  1341. if (idx == 0)
  1342. ath_update_survey_stats(sc);
  1343. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1344. if (sband && idx >= sband->n_channels) {
  1345. idx -= sband->n_channels;
  1346. sband = NULL;
  1347. }
  1348. if (!sband)
  1349. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1350. if (!sband || idx >= sband->n_channels) {
  1351. spin_unlock_irqrestore(&common->cc_lock, flags);
  1352. return -ENOENT;
  1353. }
  1354. chan = &sband->channels[idx];
  1355. pos = chan->hw_value;
  1356. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1357. survey->channel = chan;
  1358. spin_unlock_irqrestore(&common->cc_lock, flags);
  1359. return 0;
  1360. }
  1361. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1362. {
  1363. struct ath_softc *sc = hw->priv;
  1364. struct ath_hw *ah = sc->sc_ah;
  1365. mutex_lock(&sc->mutex);
  1366. ah->coverage_class = coverage_class;
  1367. ath9k_ps_wakeup(sc);
  1368. ath9k_hw_init_global_settings(ah);
  1369. ath9k_ps_restore(sc);
  1370. mutex_unlock(&sc->mutex);
  1371. }
  1372. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1373. {
  1374. struct ath_softc *sc = hw->priv;
  1375. struct ath_hw *ah = sc->sc_ah;
  1376. struct ath_common *common = ath9k_hw_common(ah);
  1377. int timeout = 200; /* ms */
  1378. int i, j;
  1379. bool drain_txq;
  1380. mutex_lock(&sc->mutex);
  1381. cancel_delayed_work_sync(&sc->tx_complete_work);
  1382. if (ah->ah_flags & AH_UNPLUGGED) {
  1383. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1384. mutex_unlock(&sc->mutex);
  1385. return;
  1386. }
  1387. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1388. ath_dbg(common, ANY, "Device not present\n");
  1389. mutex_unlock(&sc->mutex);
  1390. return;
  1391. }
  1392. for (j = 0; j < timeout; j++) {
  1393. bool npend = false;
  1394. if (j)
  1395. usleep_range(1000, 2000);
  1396. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1397. if (!ATH_TXQ_SETUP(sc, i))
  1398. continue;
  1399. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1400. if (npend)
  1401. break;
  1402. }
  1403. if (!npend)
  1404. break;
  1405. }
  1406. if (drop) {
  1407. ath9k_ps_wakeup(sc);
  1408. spin_lock_bh(&sc->sc_pcu_lock);
  1409. drain_txq = ath_drain_all_txq(sc, false);
  1410. spin_unlock_bh(&sc->sc_pcu_lock);
  1411. if (!drain_txq)
  1412. ath_reset(sc, false);
  1413. ath9k_ps_restore(sc);
  1414. ieee80211_wake_queues(hw);
  1415. }
  1416. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1417. mutex_unlock(&sc->mutex);
  1418. }
  1419. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1420. {
  1421. struct ath_softc *sc = hw->priv;
  1422. int i;
  1423. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1424. if (!ATH_TXQ_SETUP(sc, i))
  1425. continue;
  1426. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1427. return true;
  1428. }
  1429. return false;
  1430. }
  1431. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1432. {
  1433. struct ath_softc *sc = hw->priv;
  1434. struct ath_hw *ah = sc->sc_ah;
  1435. struct ieee80211_vif *vif;
  1436. struct ath_vif *avp;
  1437. struct ath_buf *bf;
  1438. struct ath_tx_status ts;
  1439. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1440. int status;
  1441. vif = sc->beacon.bslot[0];
  1442. if (!vif)
  1443. return 0;
  1444. if (!vif->bss_conf.enable_beacon)
  1445. return 0;
  1446. avp = (void *)vif->drv_priv;
  1447. if (!sc->beacon.tx_processed && !edma) {
  1448. tasklet_disable(&sc->bcon_tasklet);
  1449. bf = avp->av_bcbuf;
  1450. if (!bf || !bf->bf_mpdu)
  1451. goto skip;
  1452. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1453. if (status == -EINPROGRESS)
  1454. goto skip;
  1455. sc->beacon.tx_processed = true;
  1456. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1457. skip:
  1458. tasklet_enable(&sc->bcon_tasklet);
  1459. }
  1460. return sc->beacon.tx_last;
  1461. }
  1462. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1463. struct ieee80211_low_level_stats *stats)
  1464. {
  1465. struct ath_softc *sc = hw->priv;
  1466. struct ath_hw *ah = sc->sc_ah;
  1467. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1468. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1469. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1470. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1471. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1472. return 0;
  1473. }
  1474. static u32 fill_chainmask(u32 cap, u32 new)
  1475. {
  1476. u32 filled = 0;
  1477. int i;
  1478. for (i = 0; cap && new; i++, cap >>= 1) {
  1479. if (!(cap & BIT(0)))
  1480. continue;
  1481. if (new & BIT(0))
  1482. filled |= BIT(i);
  1483. new >>= 1;
  1484. }
  1485. return filled;
  1486. }
  1487. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1488. {
  1489. switch (val & 0x7) {
  1490. case 0x1:
  1491. case 0x3:
  1492. case 0x7:
  1493. return true;
  1494. case 0x2:
  1495. return (ah->caps.rx_chainmask == 1);
  1496. default:
  1497. return false;
  1498. }
  1499. }
  1500. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1501. {
  1502. struct ath_softc *sc = hw->priv;
  1503. struct ath_hw *ah = sc->sc_ah;
  1504. if (ah->caps.rx_chainmask != 1)
  1505. rx_ant |= tx_ant;
  1506. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1507. return -EINVAL;
  1508. sc->ant_rx = rx_ant;
  1509. sc->ant_tx = tx_ant;
  1510. if (ah->caps.rx_chainmask == 1)
  1511. return 0;
  1512. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1513. if (AR_SREV_9100(ah))
  1514. ah->rxchainmask = 0x7;
  1515. else
  1516. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1517. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1518. ath9k_reload_chainmask_settings(sc);
  1519. return 0;
  1520. }
  1521. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1522. {
  1523. struct ath_softc *sc = hw->priv;
  1524. *tx_ant = sc->ant_tx;
  1525. *rx_ant = sc->ant_rx;
  1526. return 0;
  1527. }
  1528. #ifdef CONFIG_ATH9K_DEBUGFS
  1529. /* Ethtool support for get-stats */
  1530. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1531. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1532. "tx_pkts_nic",
  1533. "tx_bytes_nic",
  1534. "rx_pkts_nic",
  1535. "rx_bytes_nic",
  1536. AMKSTR(d_tx_pkts),
  1537. AMKSTR(d_tx_bytes),
  1538. AMKSTR(d_tx_mpdus_queued),
  1539. AMKSTR(d_tx_mpdus_completed),
  1540. AMKSTR(d_tx_mpdu_xretries),
  1541. AMKSTR(d_tx_aggregates),
  1542. AMKSTR(d_tx_ampdus_queued_hw),
  1543. AMKSTR(d_tx_ampdus_queued_sw),
  1544. AMKSTR(d_tx_ampdus_completed),
  1545. AMKSTR(d_tx_ampdu_retries),
  1546. AMKSTR(d_tx_ampdu_xretries),
  1547. AMKSTR(d_tx_fifo_underrun),
  1548. AMKSTR(d_tx_op_exceeded),
  1549. AMKSTR(d_tx_timer_expiry),
  1550. AMKSTR(d_tx_desc_cfg_err),
  1551. AMKSTR(d_tx_data_underrun),
  1552. AMKSTR(d_tx_delim_underrun),
  1553. "d_rx_decrypt_crc_err",
  1554. "d_rx_phy_err",
  1555. "d_rx_mic_err",
  1556. "d_rx_pre_delim_crc_err",
  1557. "d_rx_post_delim_crc_err",
  1558. "d_rx_decrypt_busy_err",
  1559. "d_rx_phyerr_radar",
  1560. "d_rx_phyerr_ofdm_timing",
  1561. "d_rx_phyerr_cck_timing",
  1562. };
  1563. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1564. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1565. struct ieee80211_vif *vif,
  1566. u32 sset, u8 *data)
  1567. {
  1568. if (sset == ETH_SS_STATS)
  1569. memcpy(data, *ath9k_gstrings_stats,
  1570. sizeof(ath9k_gstrings_stats));
  1571. }
  1572. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1573. struct ieee80211_vif *vif, int sset)
  1574. {
  1575. if (sset == ETH_SS_STATS)
  1576. return ATH9K_SSTATS_LEN;
  1577. return 0;
  1578. }
  1579. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1580. #define AWDATA(elem) \
  1581. do { \
  1582. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1583. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1584. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1585. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1586. } while (0)
  1587. #define AWDATA_RX(elem) \
  1588. do { \
  1589. data[i++] = sc->debug.stats.rxstats.elem; \
  1590. } while (0)
  1591. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1592. struct ieee80211_vif *vif,
  1593. struct ethtool_stats *stats, u64 *data)
  1594. {
  1595. struct ath_softc *sc = hw->priv;
  1596. int i = 0;
  1597. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1598. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1599. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1600. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1601. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1602. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1603. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1604. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1605. AWDATA_RX(rx_pkts_all);
  1606. AWDATA_RX(rx_bytes_all);
  1607. AWDATA(tx_pkts_all);
  1608. AWDATA(tx_bytes_all);
  1609. AWDATA(queued);
  1610. AWDATA(completed);
  1611. AWDATA(xretries);
  1612. AWDATA(a_aggr);
  1613. AWDATA(a_queued_hw);
  1614. AWDATA(a_queued_sw);
  1615. AWDATA(a_completed);
  1616. AWDATA(a_retries);
  1617. AWDATA(a_xretries);
  1618. AWDATA(fifo_underrun);
  1619. AWDATA(xtxop);
  1620. AWDATA(timer_exp);
  1621. AWDATA(desc_cfg_err);
  1622. AWDATA(data_underrun);
  1623. AWDATA(delim_underrun);
  1624. AWDATA_RX(decrypt_crc_err);
  1625. AWDATA_RX(phy_err);
  1626. AWDATA_RX(mic_err);
  1627. AWDATA_RX(pre_delim_crc_err);
  1628. AWDATA_RX(post_delim_crc_err);
  1629. AWDATA_RX(decrypt_busy_err);
  1630. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1631. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1632. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1633. WARN_ON(i != ATH9K_SSTATS_LEN);
  1634. }
  1635. /* End of ethtool get-stats functions */
  1636. #endif
  1637. #ifdef CONFIG_PM_SLEEP
  1638. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1639. struct cfg80211_wowlan *wowlan,
  1640. u32 *wow_triggers)
  1641. {
  1642. if (wowlan->disconnect)
  1643. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1644. AH_WOW_BEACON_MISS;
  1645. if (wowlan->magic_pkt)
  1646. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1647. if (wowlan->n_patterns)
  1648. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1649. sc->wow_enabled = *wow_triggers;
  1650. }
  1651. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1652. {
  1653. struct ath_hw *ah = sc->sc_ah;
  1654. struct ath_common *common = ath9k_hw_common(ah);
  1655. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1656. int pattern_count = 0;
  1657. int i, byte_cnt;
  1658. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1659. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1660. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1661. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1662. /*
  1663. * Create Dissassociate / Deauthenticate packet filter
  1664. *
  1665. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1666. * +--------------+----------+---------+--------+--------+----
  1667. * + Frame Control+ Duration + DA + SA + BSSID +
  1668. * +--------------+----------+---------+--------+--------+----
  1669. *
  1670. * The above is the management frame format for disassociate/
  1671. * deauthenticate pattern, from this we need to match the first byte
  1672. * of 'Frame Control' and DA, SA, and BSSID fields
  1673. * (skipping 2nd byte of FC and Duration feild.
  1674. *
  1675. * Disassociate pattern
  1676. * --------------------
  1677. * Frame control = 00 00 1010
  1678. * DA, SA, BSSID = x:x:x:x:x:x
  1679. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1680. * | x:x:x:x:x:x -- 22 bytes
  1681. *
  1682. * Deauthenticate pattern
  1683. * ----------------------
  1684. * Frame control = 00 00 1100
  1685. * DA, SA, BSSID = x:x:x:x:x:x
  1686. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1687. * | x:x:x:x:x:x -- 22 bytes
  1688. */
  1689. /* Create Disassociate Pattern first */
  1690. byte_cnt = 0;
  1691. /* Fill out the mask with all FF's */
  1692. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1693. dis_deauth_mask[i] = 0xff;
  1694. /* copy the first byte of frame control field */
  1695. dis_deauth_pattern[byte_cnt] = 0xa0;
  1696. byte_cnt++;
  1697. /* skip 2nd byte of frame control and Duration field */
  1698. byte_cnt += 3;
  1699. /*
  1700. * need not match the destination mac address, it can be a broadcast
  1701. * mac address or an unicast to this station
  1702. */
  1703. byte_cnt += 6;
  1704. /* copy the source mac address */
  1705. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1706. byte_cnt += 6;
  1707. /* copy the bssid, its same as the source mac address */
  1708. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1709. /* Create Disassociate pattern mask */
  1710. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1711. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1712. /*
  1713. * for AR9280, because of hardware limitation, the
  1714. * first 4 bytes have to be matched for all patterns.
  1715. * the mask for disassociation and de-auth pattern
  1716. * matching need to enable the first 4 bytes.
  1717. * also the duration field needs to be filled.
  1718. */
  1719. dis_deauth_mask[0] = 0xf0;
  1720. /*
  1721. * fill in duration field
  1722. FIXME: what is the exact value ?
  1723. */
  1724. dis_deauth_pattern[2] = 0xff;
  1725. dis_deauth_pattern[3] = 0xff;
  1726. } else {
  1727. dis_deauth_mask[0] = 0xfe;
  1728. }
  1729. dis_deauth_mask[1] = 0x03;
  1730. dis_deauth_mask[2] = 0xc0;
  1731. } else {
  1732. dis_deauth_mask[0] = 0xef;
  1733. dis_deauth_mask[1] = 0x3f;
  1734. dis_deauth_mask[2] = 0x00;
  1735. dis_deauth_mask[3] = 0xfc;
  1736. }
  1737. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1738. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1739. pattern_count, byte_cnt);
  1740. pattern_count++;
  1741. /*
  1742. * for de-authenticate pattern, only the first byte of the frame
  1743. * control field gets changed from 0xA0 to 0xC0
  1744. */
  1745. dis_deauth_pattern[0] = 0xC0;
  1746. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1747. pattern_count, byte_cnt);
  1748. }
  1749. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1750. struct cfg80211_wowlan *wowlan)
  1751. {
  1752. struct ath_hw *ah = sc->sc_ah;
  1753. struct ath9k_wow_pattern *wow_pattern = NULL;
  1754. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1755. int mask_len;
  1756. s8 i = 0;
  1757. if (!wowlan->n_patterns)
  1758. return;
  1759. /*
  1760. * Add the new user configured patterns
  1761. */
  1762. for (i = 0; i < wowlan->n_patterns; i++) {
  1763. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1764. if (!wow_pattern)
  1765. return;
  1766. /*
  1767. * TODO: convert the generic user space pattern to
  1768. * appropriate chip specific/802.11 pattern.
  1769. */
  1770. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1771. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1772. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1773. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1774. patterns[i].pattern_len);
  1775. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1776. wow_pattern->pattern_len = patterns[i].pattern_len;
  1777. /*
  1778. * just need to take care of deauth and disssoc pattern,
  1779. * make sure we don't overwrite them.
  1780. */
  1781. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1782. wow_pattern->mask_bytes,
  1783. i + 2,
  1784. wow_pattern->pattern_len);
  1785. kfree(wow_pattern);
  1786. }
  1787. }
  1788. static int ath9k_suspend(struct ieee80211_hw *hw,
  1789. struct cfg80211_wowlan *wowlan)
  1790. {
  1791. struct ath_softc *sc = hw->priv;
  1792. struct ath_hw *ah = sc->sc_ah;
  1793. struct ath_common *common = ath9k_hw_common(ah);
  1794. u32 wow_triggers_enabled = 0;
  1795. int ret = 0;
  1796. mutex_lock(&sc->mutex);
  1797. ath_cancel_work(sc);
  1798. ath_stop_ani(sc);
  1799. del_timer_sync(&sc->rx_poll_timer);
  1800. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1801. ath_dbg(common, ANY, "Device not present\n");
  1802. ret = -EINVAL;
  1803. goto fail_wow;
  1804. }
  1805. if (WARN_ON(!wowlan)) {
  1806. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1807. ret = -EINVAL;
  1808. goto fail_wow;
  1809. }
  1810. if (!device_can_wakeup(sc->dev)) {
  1811. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1812. ret = 1;
  1813. goto fail_wow;
  1814. }
  1815. /*
  1816. * none of the sta vifs are associated
  1817. * and we are not currently handling multivif
  1818. * cases, for instance we have to seperately
  1819. * configure 'keep alive frame' for each
  1820. * STA.
  1821. */
  1822. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1823. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1824. ret = 1;
  1825. goto fail_wow;
  1826. }
  1827. if (sc->nvifs > 1) {
  1828. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1829. ret = 1;
  1830. goto fail_wow;
  1831. }
  1832. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1833. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1834. wow_triggers_enabled);
  1835. ath9k_ps_wakeup(sc);
  1836. ath9k_stop_btcoex(sc);
  1837. /*
  1838. * Enable wake up on recieving disassoc/deauth
  1839. * frame by default.
  1840. */
  1841. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1842. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1843. ath9k_wow_add_pattern(sc, wowlan);
  1844. spin_lock_bh(&sc->sc_pcu_lock);
  1845. /*
  1846. * To avoid false wake, we enable beacon miss interrupt only
  1847. * when we go to sleep. We save the current interrupt mask
  1848. * so we can restore it after the system wakes up
  1849. */
  1850. sc->wow_intr_before_sleep = ah->imask;
  1851. ah->imask &= ~ATH9K_INT_GLOBAL;
  1852. ath9k_hw_disable_interrupts(ah);
  1853. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1854. ath9k_hw_set_interrupts(ah);
  1855. ath9k_hw_enable_interrupts(ah);
  1856. spin_unlock_bh(&sc->sc_pcu_lock);
  1857. /*
  1858. * we can now sync irq and kill any running tasklets, since we already
  1859. * disabled interrupts and not holding a spin lock
  1860. */
  1861. synchronize_irq(sc->irq);
  1862. tasklet_kill(&sc->intr_tq);
  1863. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1864. ath9k_ps_restore(sc);
  1865. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1866. atomic_inc(&sc->wow_sleep_proc_intr);
  1867. fail_wow:
  1868. mutex_unlock(&sc->mutex);
  1869. return ret;
  1870. }
  1871. static int ath9k_resume(struct ieee80211_hw *hw)
  1872. {
  1873. struct ath_softc *sc = hw->priv;
  1874. struct ath_hw *ah = sc->sc_ah;
  1875. struct ath_common *common = ath9k_hw_common(ah);
  1876. u32 wow_status;
  1877. mutex_lock(&sc->mutex);
  1878. ath9k_ps_wakeup(sc);
  1879. spin_lock_bh(&sc->sc_pcu_lock);
  1880. ath9k_hw_disable_interrupts(ah);
  1881. ah->imask = sc->wow_intr_before_sleep;
  1882. ath9k_hw_set_interrupts(ah);
  1883. ath9k_hw_enable_interrupts(ah);
  1884. spin_unlock_bh(&sc->sc_pcu_lock);
  1885. wow_status = ath9k_hw_wow_wakeup(ah);
  1886. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1887. /*
  1888. * some devices may not pick beacon miss
  1889. * as the reason they woke up so we add
  1890. * that here for that shortcoming.
  1891. */
  1892. wow_status |= AH_WOW_BEACON_MISS;
  1893. atomic_dec(&sc->wow_got_bmiss_intr);
  1894. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1895. }
  1896. atomic_dec(&sc->wow_sleep_proc_intr);
  1897. if (wow_status) {
  1898. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1899. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1900. }
  1901. ath_restart_work(sc);
  1902. ath9k_start_btcoex(sc);
  1903. ath9k_ps_restore(sc);
  1904. mutex_unlock(&sc->mutex);
  1905. return 0;
  1906. }
  1907. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1908. {
  1909. struct ath_softc *sc = hw->priv;
  1910. mutex_lock(&sc->mutex);
  1911. device_init_wakeup(sc->dev, 1);
  1912. device_set_wakeup_enable(sc->dev, enabled);
  1913. mutex_unlock(&sc->mutex);
  1914. }
  1915. #endif
  1916. struct ieee80211_ops ath9k_ops = {
  1917. .tx = ath9k_tx,
  1918. .start = ath9k_start,
  1919. .stop = ath9k_stop,
  1920. .add_interface = ath9k_add_interface,
  1921. .change_interface = ath9k_change_interface,
  1922. .remove_interface = ath9k_remove_interface,
  1923. .config = ath9k_config,
  1924. .configure_filter = ath9k_configure_filter,
  1925. .sta_add = ath9k_sta_add,
  1926. .sta_remove = ath9k_sta_remove,
  1927. .sta_notify = ath9k_sta_notify,
  1928. .conf_tx = ath9k_conf_tx,
  1929. .bss_info_changed = ath9k_bss_info_changed,
  1930. .set_key = ath9k_set_key,
  1931. .get_tsf = ath9k_get_tsf,
  1932. .set_tsf = ath9k_set_tsf,
  1933. .reset_tsf = ath9k_reset_tsf,
  1934. .ampdu_action = ath9k_ampdu_action,
  1935. .get_survey = ath9k_get_survey,
  1936. .rfkill_poll = ath9k_rfkill_poll_state,
  1937. .set_coverage_class = ath9k_set_coverage_class,
  1938. .flush = ath9k_flush,
  1939. .tx_frames_pending = ath9k_tx_frames_pending,
  1940. .tx_last_beacon = ath9k_tx_last_beacon,
  1941. .get_stats = ath9k_get_stats,
  1942. .set_antenna = ath9k_set_antenna,
  1943. .get_antenna = ath9k_get_antenna,
  1944. #ifdef CONFIG_PM_SLEEP
  1945. .suspend = ath9k_suspend,
  1946. .resume = ath9k_resume,
  1947. .set_wakeup = ath9k_set_wakeup,
  1948. #endif
  1949. #ifdef CONFIG_ATH9K_DEBUGFS
  1950. .get_et_sset_count = ath9k_get_et_sset_count,
  1951. .get_et_stats = ath9k_get_et_stats,
  1952. .get_et_strings = ath9k_get_et_strings,
  1953. #endif
  1954. };