siena_sriov.c 45 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2010-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/pci.h>
  10. #include <linux/module.h>
  11. #include "net_driver.h"
  12. #include "efx.h"
  13. #include "nic.h"
  14. #include "io.h"
  15. #include "mcdi.h"
  16. #include "filter.h"
  17. #include "mcdi_pcol.h"
  18. #include "regs.h"
  19. #include "vfdi.h"
  20. /* Number of longs required to track all the VIs in a VF */
  21. #define VI_MASK_LENGTH BITS_TO_LONGS(1 << EFX_VI_SCALE_MAX)
  22. /* Maximum number of RX queues supported */
  23. #define VF_MAX_RX_QUEUES 63
  24. /**
  25. * enum efx_vf_tx_filter_mode - TX MAC filtering behaviour
  26. * @VF_TX_FILTER_OFF: Disabled
  27. * @VF_TX_FILTER_AUTO: Enabled if MAC address assigned to VF and only
  28. * 2 TX queues allowed per VF.
  29. * @VF_TX_FILTER_ON: Enabled
  30. */
  31. enum efx_vf_tx_filter_mode {
  32. VF_TX_FILTER_OFF,
  33. VF_TX_FILTER_AUTO,
  34. VF_TX_FILTER_ON,
  35. };
  36. /**
  37. * struct efx_vf - Back-end resource and protocol state for a PCI VF
  38. * @efx: The Efx NIC owning this VF
  39. * @pci_rid: The PCI requester ID for this VF
  40. * @pci_name: The PCI name (formatted address) of this VF
  41. * @index: Index of VF within its port and PF.
  42. * @req: VFDI incoming request work item. Incoming USR_EV events are received
  43. * by the NAPI handler, but must be handled by executing MCDI requests
  44. * inside a work item.
  45. * @req_addr: VFDI incoming request DMA address (in VF's PCI address space).
  46. * @req_type: Expected next incoming (from VF) %VFDI_EV_TYPE member.
  47. * @req_seqno: Expected next incoming (from VF) %VFDI_EV_SEQ member.
  48. * @msg_seqno: Next %VFDI_EV_SEQ member to reply to VF. Protected by
  49. * @status_lock
  50. * @busy: VFDI request queued to be processed or being processed. Receiving
  51. * a VFDI request when @busy is set is an error condition.
  52. * @buf: Incoming VFDI requests are DMA from the VF into this buffer.
  53. * @buftbl_base: Buffer table entries for this VF start at this index.
  54. * @rx_filtering: Receive filtering has been requested by the VF driver.
  55. * @rx_filter_flags: The flags sent in the %VFDI_OP_INSERT_FILTER request.
  56. * @rx_filter_qid: VF relative qid for RX filter requested by VF.
  57. * @rx_filter_id: Receive MAC filter ID. Only one filter per VF is supported.
  58. * @tx_filter_mode: Transmit MAC filtering mode.
  59. * @tx_filter_id: Transmit MAC filter ID.
  60. * @addr: The MAC address and outer vlan tag of the VF.
  61. * @status_addr: VF DMA address of page for &struct vfdi_status updates.
  62. * @status_lock: Mutex protecting @msg_seqno, @status_addr, @addr,
  63. * @peer_page_addrs and @peer_page_count from simultaneous
  64. * updates by the VM and consumption by
  65. * efx_sriov_update_vf_addr()
  66. * @peer_page_addrs: Pointer to an array of guest pages for local addresses.
  67. * @peer_page_count: Number of entries in @peer_page_count.
  68. * @evq0_addrs: Array of guest pages backing evq0.
  69. * @evq0_count: Number of entries in @evq0_addrs.
  70. * @flush_waitq: wait queue used by %VFDI_OP_FINI_ALL_QUEUES handler
  71. * to wait for flush completions.
  72. * @txq_lock: Mutex for TX queue allocation.
  73. * @txq_mask: Mask of initialized transmit queues.
  74. * @txq_count: Number of initialized transmit queues.
  75. * @rxq_mask: Mask of initialized receive queues.
  76. * @rxq_count: Number of initialized receive queues.
  77. * @rxq_retry_mask: Mask or receive queues that need to be flushed again
  78. * due to flush failure.
  79. * @rxq_retry_count: Number of receive queues in @rxq_retry_mask.
  80. * @reset_work: Work item to schedule a VF reset.
  81. */
  82. struct efx_vf {
  83. struct efx_nic *efx;
  84. unsigned int pci_rid;
  85. char pci_name[13]; /* dddd:bb:dd.f */
  86. unsigned int index;
  87. struct work_struct req;
  88. u64 req_addr;
  89. int req_type;
  90. unsigned req_seqno;
  91. unsigned msg_seqno;
  92. bool busy;
  93. struct efx_buffer buf;
  94. unsigned buftbl_base;
  95. bool rx_filtering;
  96. enum efx_filter_flags rx_filter_flags;
  97. unsigned rx_filter_qid;
  98. int rx_filter_id;
  99. enum efx_vf_tx_filter_mode tx_filter_mode;
  100. int tx_filter_id;
  101. struct vfdi_endpoint addr;
  102. u64 status_addr;
  103. struct mutex status_lock;
  104. u64 *peer_page_addrs;
  105. unsigned peer_page_count;
  106. u64 evq0_addrs[EFX_MAX_VF_EVQ_SIZE * sizeof(efx_qword_t) /
  107. EFX_BUF_SIZE];
  108. unsigned evq0_count;
  109. wait_queue_head_t flush_waitq;
  110. struct mutex txq_lock;
  111. unsigned long txq_mask[VI_MASK_LENGTH];
  112. unsigned txq_count;
  113. unsigned long rxq_mask[VI_MASK_LENGTH];
  114. unsigned rxq_count;
  115. unsigned long rxq_retry_mask[VI_MASK_LENGTH];
  116. atomic_t rxq_retry_count;
  117. struct work_struct reset_work;
  118. };
  119. struct efx_memcpy_req {
  120. unsigned int from_rid;
  121. void *from_buf;
  122. u64 from_addr;
  123. unsigned int to_rid;
  124. u64 to_addr;
  125. unsigned length;
  126. };
  127. /**
  128. * struct efx_local_addr - A MAC address on the vswitch without a VF.
  129. *
  130. * Siena does not have a switch, so VFs can't transmit data to each
  131. * other. Instead the VFs must be made aware of the local addresses
  132. * on the vswitch, so that they can arrange for an alternative
  133. * software datapath to be used.
  134. *
  135. * @link: List head for insertion into efx->local_addr_list.
  136. * @addr: Ethernet address
  137. */
  138. struct efx_local_addr {
  139. struct list_head link;
  140. u8 addr[ETH_ALEN];
  141. };
  142. /**
  143. * struct efx_endpoint_page - Page of vfdi_endpoint structures
  144. *
  145. * @link: List head for insertion into efx->local_page_list.
  146. * @ptr: Pointer to page.
  147. * @addr: DMA address of page.
  148. */
  149. struct efx_endpoint_page {
  150. struct list_head link;
  151. void *ptr;
  152. dma_addr_t addr;
  153. };
  154. /* Buffer table entries are reserved txq0,rxq0,evq0,txq1,rxq1,evq1 */
  155. #define EFX_BUFTBL_TXQ_BASE(_vf, _qid) \
  156. ((_vf)->buftbl_base + EFX_VF_BUFTBL_PER_VI * (_qid))
  157. #define EFX_BUFTBL_RXQ_BASE(_vf, _qid) \
  158. (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
  159. (EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
  160. #define EFX_BUFTBL_EVQ_BASE(_vf, _qid) \
  161. (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
  162. (2 * EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
  163. #define EFX_FIELD_MASK(_field) \
  164. ((1 << _field ## _WIDTH) - 1)
  165. /* VFs can only use this many transmit channels */
  166. static unsigned int vf_max_tx_channels = 2;
  167. module_param(vf_max_tx_channels, uint, 0444);
  168. MODULE_PARM_DESC(vf_max_tx_channels,
  169. "Limit the number of TX channels VFs can use");
  170. static int max_vfs = -1;
  171. module_param(max_vfs, int, 0444);
  172. MODULE_PARM_DESC(max_vfs,
  173. "Reduce the number of VFs initialized by the driver");
  174. /* Workqueue used by VFDI communication. We can't use the global
  175. * workqueue because it may be running the VF driver's probe()
  176. * routine, which will be blocked there waiting for a VFDI response.
  177. */
  178. static struct workqueue_struct *vfdi_workqueue;
  179. static unsigned abs_index(struct efx_vf *vf, unsigned index)
  180. {
  181. return EFX_VI_BASE + vf->index * efx_vf_size(vf->efx) + index;
  182. }
  183. static int efx_sriov_cmd(struct efx_nic *efx, bool enable,
  184. unsigned *vi_scale_out, unsigned *vf_total_out)
  185. {
  186. u8 inbuf[MC_CMD_SRIOV_IN_LEN];
  187. u8 outbuf[MC_CMD_SRIOV_OUT_LEN];
  188. unsigned vi_scale, vf_total;
  189. size_t outlen;
  190. int rc;
  191. MCDI_SET_DWORD(inbuf, SRIOV_IN_ENABLE, enable ? 1 : 0);
  192. MCDI_SET_DWORD(inbuf, SRIOV_IN_VI_BASE, EFX_VI_BASE);
  193. MCDI_SET_DWORD(inbuf, SRIOV_IN_VF_COUNT, efx->vf_count);
  194. rc = efx_mcdi_rpc(efx, MC_CMD_SRIOV, inbuf, MC_CMD_SRIOV_IN_LEN,
  195. outbuf, MC_CMD_SRIOV_OUT_LEN, &outlen);
  196. if (rc)
  197. return rc;
  198. if (outlen < MC_CMD_SRIOV_OUT_LEN)
  199. return -EIO;
  200. vf_total = MCDI_DWORD(outbuf, SRIOV_OUT_VF_TOTAL);
  201. vi_scale = MCDI_DWORD(outbuf, SRIOV_OUT_VI_SCALE);
  202. if (vi_scale > EFX_VI_SCALE_MAX)
  203. return -EOPNOTSUPP;
  204. if (vi_scale_out)
  205. *vi_scale_out = vi_scale;
  206. if (vf_total_out)
  207. *vf_total_out = vf_total;
  208. return 0;
  209. }
  210. static void efx_sriov_usrev(struct efx_nic *efx, bool enabled)
  211. {
  212. efx_oword_t reg;
  213. EFX_POPULATE_OWORD_2(reg,
  214. FRF_CZ_USREV_DIS, enabled ? 0 : 1,
  215. FRF_CZ_DFLT_EVQ, efx->vfdi_channel->channel);
  216. efx_writeo(efx, &reg, FR_CZ_USR_EV_CFG);
  217. }
  218. static int efx_sriov_memcpy(struct efx_nic *efx, struct efx_memcpy_req *req,
  219. unsigned int count)
  220. {
  221. u8 *inbuf, *record;
  222. unsigned int used;
  223. u32 from_rid, from_hi, from_lo;
  224. int rc;
  225. mb(); /* Finish writing source/reading dest before DMA starts */
  226. used = MC_CMD_MEMCPY_IN_LEN(count);
  227. if (WARN_ON(used > MCDI_CTL_SDU_LEN_MAX))
  228. return -ENOBUFS;
  229. /* Allocate room for the largest request */
  230. inbuf = kzalloc(MCDI_CTL_SDU_LEN_MAX, GFP_KERNEL);
  231. if (inbuf == NULL)
  232. return -ENOMEM;
  233. record = inbuf;
  234. MCDI_SET_DWORD(record, MEMCPY_IN_RECORD, count);
  235. while (count-- > 0) {
  236. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_RID,
  237. req->to_rid);
  238. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO,
  239. (u32)req->to_addr);
  240. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI,
  241. (u32)(req->to_addr >> 32));
  242. if (req->from_buf == NULL) {
  243. from_rid = req->from_rid;
  244. from_lo = (u32)req->from_addr;
  245. from_hi = (u32)(req->from_addr >> 32);
  246. } else {
  247. if (WARN_ON(used + req->length > MCDI_CTL_SDU_LEN_MAX)) {
  248. rc = -ENOBUFS;
  249. goto out;
  250. }
  251. from_rid = MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE;
  252. from_lo = used;
  253. from_hi = 0;
  254. memcpy(inbuf + used, req->from_buf, req->length);
  255. used += req->length;
  256. }
  257. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_RID, from_rid);
  258. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO,
  259. from_lo);
  260. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI,
  261. from_hi);
  262. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_LENGTH,
  263. req->length);
  264. ++req;
  265. record += MC_CMD_MEMCPY_IN_RECORD_LEN;
  266. }
  267. rc = efx_mcdi_rpc(efx, MC_CMD_MEMCPY, inbuf, used, NULL, 0, NULL);
  268. out:
  269. kfree(inbuf);
  270. mb(); /* Don't write source/read dest before DMA is complete */
  271. return rc;
  272. }
  273. /* The TX filter is entirely controlled by this driver, and is modified
  274. * underneath the feet of the VF
  275. */
  276. static void efx_sriov_reset_tx_filter(struct efx_vf *vf)
  277. {
  278. struct efx_nic *efx = vf->efx;
  279. struct efx_filter_spec filter;
  280. u16 vlan;
  281. int rc;
  282. if (vf->tx_filter_id != -1) {
  283. efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
  284. vf->tx_filter_id);
  285. netif_dbg(efx, hw, efx->net_dev, "Removed vf %s tx filter %d\n",
  286. vf->pci_name, vf->tx_filter_id);
  287. vf->tx_filter_id = -1;
  288. }
  289. if (is_zero_ether_addr(vf->addr.mac_addr))
  290. return;
  291. /* Turn on TX filtering automatically if not explicitly
  292. * enabled or disabled.
  293. */
  294. if (vf->tx_filter_mode == VF_TX_FILTER_AUTO && vf_max_tx_channels <= 2)
  295. vf->tx_filter_mode = VF_TX_FILTER_ON;
  296. vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
  297. efx_filter_init_tx(&filter, abs_index(vf, 0));
  298. rc = efx_filter_set_eth_local(&filter,
  299. vlan ? vlan : EFX_FILTER_VID_UNSPEC,
  300. vf->addr.mac_addr);
  301. BUG_ON(rc);
  302. rc = efx_filter_insert_filter(efx, &filter, true);
  303. if (rc < 0) {
  304. netif_warn(efx, hw, efx->net_dev,
  305. "Unable to migrate tx filter for vf %s\n",
  306. vf->pci_name);
  307. } else {
  308. netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s tx filter %d\n",
  309. vf->pci_name, rc);
  310. vf->tx_filter_id = rc;
  311. }
  312. }
  313. /* The RX filter is managed here on behalf of the VF driver */
  314. static void efx_sriov_reset_rx_filter(struct efx_vf *vf)
  315. {
  316. struct efx_nic *efx = vf->efx;
  317. struct efx_filter_spec filter;
  318. u16 vlan;
  319. int rc;
  320. if (vf->rx_filter_id != -1) {
  321. efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
  322. vf->rx_filter_id);
  323. netif_dbg(efx, hw, efx->net_dev, "Removed vf %s rx filter %d\n",
  324. vf->pci_name, vf->rx_filter_id);
  325. vf->rx_filter_id = -1;
  326. }
  327. if (!vf->rx_filtering || is_zero_ether_addr(vf->addr.mac_addr))
  328. return;
  329. vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
  330. efx_filter_init_rx(&filter, EFX_FILTER_PRI_REQUIRED,
  331. vf->rx_filter_flags,
  332. abs_index(vf, vf->rx_filter_qid));
  333. rc = efx_filter_set_eth_local(&filter,
  334. vlan ? vlan : EFX_FILTER_VID_UNSPEC,
  335. vf->addr.mac_addr);
  336. BUG_ON(rc);
  337. rc = efx_filter_insert_filter(efx, &filter, true);
  338. if (rc < 0) {
  339. netif_warn(efx, hw, efx->net_dev,
  340. "Unable to insert rx filter for vf %s\n",
  341. vf->pci_name);
  342. } else {
  343. netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s rx filter %d\n",
  344. vf->pci_name, rc);
  345. vf->rx_filter_id = rc;
  346. }
  347. }
  348. static void __efx_sriov_update_vf_addr(struct efx_vf *vf)
  349. {
  350. efx_sriov_reset_tx_filter(vf);
  351. efx_sriov_reset_rx_filter(vf);
  352. queue_work(vfdi_workqueue, &vf->efx->peer_work);
  353. }
  354. /* Push the peer list to this VF. The caller must hold status_lock to interlock
  355. * with VFDI requests, and they must be serialised against manipulation of
  356. * local_page_list, either by acquiring local_lock or by running from
  357. * efx_sriov_peer_work()
  358. */
  359. static void __efx_sriov_push_vf_status(struct efx_vf *vf)
  360. {
  361. struct efx_nic *efx = vf->efx;
  362. struct vfdi_status *status = efx->vfdi_status.addr;
  363. struct efx_memcpy_req copy[4];
  364. struct efx_endpoint_page *epp;
  365. unsigned int pos, count;
  366. unsigned data_offset;
  367. efx_qword_t event;
  368. WARN_ON(!mutex_is_locked(&vf->status_lock));
  369. WARN_ON(!vf->status_addr);
  370. status->local = vf->addr;
  371. status->generation_end = ++status->generation_start;
  372. memset(copy, '\0', sizeof(copy));
  373. /* Write generation_start */
  374. copy[0].from_buf = &status->generation_start;
  375. copy[0].to_rid = vf->pci_rid;
  376. copy[0].to_addr = vf->status_addr + offsetof(struct vfdi_status,
  377. generation_start);
  378. copy[0].length = sizeof(status->generation_start);
  379. /* DMA the rest of the structure (excluding the generations). This
  380. * assumes that the non-generation portion of vfdi_status is in
  381. * one chunk starting at the version member.
  382. */
  383. data_offset = offsetof(struct vfdi_status, version);
  384. copy[1].from_rid = efx->pci_dev->devfn;
  385. copy[1].from_addr = efx->vfdi_status.dma_addr + data_offset;
  386. copy[1].to_rid = vf->pci_rid;
  387. copy[1].to_addr = vf->status_addr + data_offset;
  388. copy[1].length = status->length - data_offset;
  389. /* Copy the peer pages */
  390. pos = 2;
  391. count = 0;
  392. list_for_each_entry(epp, &efx->local_page_list, link) {
  393. if (count == vf->peer_page_count) {
  394. /* The VF driver will know they need to provide more
  395. * pages because peer_addr_count is too large.
  396. */
  397. break;
  398. }
  399. copy[pos].from_buf = NULL;
  400. copy[pos].from_rid = efx->pci_dev->devfn;
  401. copy[pos].from_addr = epp->addr;
  402. copy[pos].to_rid = vf->pci_rid;
  403. copy[pos].to_addr = vf->peer_page_addrs[count];
  404. copy[pos].length = EFX_PAGE_SIZE;
  405. if (++pos == ARRAY_SIZE(copy)) {
  406. efx_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
  407. pos = 0;
  408. }
  409. ++count;
  410. }
  411. /* Write generation_end */
  412. copy[pos].from_buf = &status->generation_end;
  413. copy[pos].to_rid = vf->pci_rid;
  414. copy[pos].to_addr = vf->status_addr + offsetof(struct vfdi_status,
  415. generation_end);
  416. copy[pos].length = sizeof(status->generation_end);
  417. efx_sriov_memcpy(efx, copy, pos + 1);
  418. /* Notify the guest */
  419. EFX_POPULATE_QWORD_3(event,
  420. FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
  421. VFDI_EV_SEQ, (vf->msg_seqno & 0xff),
  422. VFDI_EV_TYPE, VFDI_EV_TYPE_STATUS);
  423. ++vf->msg_seqno;
  424. efx_generate_event(efx, EFX_VI_BASE + vf->index * efx_vf_size(efx),
  425. &event);
  426. }
  427. static void efx_sriov_bufs(struct efx_nic *efx, unsigned offset,
  428. u64 *addr, unsigned count)
  429. {
  430. efx_qword_t buf;
  431. unsigned pos;
  432. for (pos = 0; pos < count; ++pos) {
  433. EFX_POPULATE_QWORD_3(buf,
  434. FRF_AZ_BUF_ADR_REGION, 0,
  435. FRF_AZ_BUF_ADR_FBUF,
  436. addr ? addr[pos] >> 12 : 0,
  437. FRF_AZ_BUF_OWNER_ID_FBUF, 0);
  438. efx_sram_writeq(efx, efx->membase + FR_BZ_BUF_FULL_TBL,
  439. &buf, offset + pos);
  440. }
  441. }
  442. static bool bad_vf_index(struct efx_nic *efx, unsigned index)
  443. {
  444. return index >= efx_vf_size(efx);
  445. }
  446. static bool bad_buf_count(unsigned buf_count, unsigned max_entry_count)
  447. {
  448. unsigned max_buf_count = max_entry_count *
  449. sizeof(efx_qword_t) / EFX_BUF_SIZE;
  450. return ((buf_count & (buf_count - 1)) || buf_count > max_buf_count);
  451. }
  452. /* Check that VI specified by per-port index belongs to a VF.
  453. * Optionally set VF index and VI index within the VF.
  454. */
  455. static bool map_vi_index(struct efx_nic *efx, unsigned abs_index,
  456. struct efx_vf **vf_out, unsigned *rel_index_out)
  457. {
  458. unsigned vf_i;
  459. if (abs_index < EFX_VI_BASE)
  460. return true;
  461. vf_i = (abs_index - EFX_VI_BASE) / efx_vf_size(efx);
  462. if (vf_i >= efx->vf_init_count)
  463. return true;
  464. if (vf_out)
  465. *vf_out = efx->vf + vf_i;
  466. if (rel_index_out)
  467. *rel_index_out = abs_index % efx_vf_size(efx);
  468. return false;
  469. }
  470. static int efx_vfdi_init_evq(struct efx_vf *vf)
  471. {
  472. struct efx_nic *efx = vf->efx;
  473. struct vfdi_req *req = vf->buf.addr;
  474. unsigned vf_evq = req->u.init_evq.index;
  475. unsigned buf_count = req->u.init_evq.buf_count;
  476. unsigned abs_evq = abs_index(vf, vf_evq);
  477. unsigned buftbl = EFX_BUFTBL_EVQ_BASE(vf, vf_evq);
  478. efx_oword_t reg;
  479. if (bad_vf_index(efx, vf_evq) ||
  480. bad_buf_count(buf_count, EFX_MAX_VF_EVQ_SIZE)) {
  481. if (net_ratelimit())
  482. netif_err(efx, hw, efx->net_dev,
  483. "ERROR: Invalid INIT_EVQ from %s: evq %d bufs %d\n",
  484. vf->pci_name, vf_evq, buf_count);
  485. return VFDI_RC_EINVAL;
  486. }
  487. efx_sriov_bufs(efx, buftbl, req->u.init_evq.addr, buf_count);
  488. EFX_POPULATE_OWORD_3(reg,
  489. FRF_CZ_TIMER_Q_EN, 1,
  490. FRF_CZ_HOST_NOTIFY_MODE, 0,
  491. FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
  492. efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
  493. EFX_POPULATE_OWORD_3(reg,
  494. FRF_AZ_EVQ_EN, 1,
  495. FRF_AZ_EVQ_SIZE, __ffs(buf_count),
  496. FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
  497. efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
  498. if (vf_evq == 0) {
  499. memcpy(vf->evq0_addrs, req->u.init_evq.addr,
  500. buf_count * sizeof(u64));
  501. vf->evq0_count = buf_count;
  502. }
  503. return VFDI_RC_SUCCESS;
  504. }
  505. static int efx_vfdi_init_rxq(struct efx_vf *vf)
  506. {
  507. struct efx_nic *efx = vf->efx;
  508. struct vfdi_req *req = vf->buf.addr;
  509. unsigned vf_rxq = req->u.init_rxq.index;
  510. unsigned vf_evq = req->u.init_rxq.evq;
  511. unsigned buf_count = req->u.init_rxq.buf_count;
  512. unsigned buftbl = EFX_BUFTBL_RXQ_BASE(vf, vf_rxq);
  513. unsigned label;
  514. efx_oword_t reg;
  515. if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_rxq) ||
  516. vf_rxq >= VF_MAX_RX_QUEUES ||
  517. bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
  518. if (net_ratelimit())
  519. netif_err(efx, hw, efx->net_dev,
  520. "ERROR: Invalid INIT_RXQ from %s: rxq %d evq %d "
  521. "buf_count %d\n", vf->pci_name, vf_rxq,
  522. vf_evq, buf_count);
  523. return VFDI_RC_EINVAL;
  524. }
  525. if (__test_and_set_bit(req->u.init_rxq.index, vf->rxq_mask))
  526. ++vf->rxq_count;
  527. efx_sriov_bufs(efx, buftbl, req->u.init_rxq.addr, buf_count);
  528. label = req->u.init_rxq.label & EFX_FIELD_MASK(FRF_AZ_RX_DESCQ_LABEL);
  529. EFX_POPULATE_OWORD_6(reg,
  530. FRF_AZ_RX_DESCQ_BUF_BASE_ID, buftbl,
  531. FRF_AZ_RX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
  532. FRF_AZ_RX_DESCQ_LABEL, label,
  533. FRF_AZ_RX_DESCQ_SIZE, __ffs(buf_count),
  534. FRF_AZ_RX_DESCQ_JUMBO,
  535. !!(req->u.init_rxq.flags &
  536. VFDI_RXQ_FLAG_SCATTER_EN),
  537. FRF_AZ_RX_DESCQ_EN, 1);
  538. efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
  539. abs_index(vf, vf_rxq));
  540. return VFDI_RC_SUCCESS;
  541. }
  542. static int efx_vfdi_init_txq(struct efx_vf *vf)
  543. {
  544. struct efx_nic *efx = vf->efx;
  545. struct vfdi_req *req = vf->buf.addr;
  546. unsigned vf_txq = req->u.init_txq.index;
  547. unsigned vf_evq = req->u.init_txq.evq;
  548. unsigned buf_count = req->u.init_txq.buf_count;
  549. unsigned buftbl = EFX_BUFTBL_TXQ_BASE(vf, vf_txq);
  550. unsigned label, eth_filt_en;
  551. efx_oword_t reg;
  552. if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_txq) ||
  553. vf_txq >= vf_max_tx_channels ||
  554. bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
  555. if (net_ratelimit())
  556. netif_err(efx, hw, efx->net_dev,
  557. "ERROR: Invalid INIT_TXQ from %s: txq %d evq %d "
  558. "buf_count %d\n", vf->pci_name, vf_txq,
  559. vf_evq, buf_count);
  560. return VFDI_RC_EINVAL;
  561. }
  562. mutex_lock(&vf->txq_lock);
  563. if (__test_and_set_bit(req->u.init_txq.index, vf->txq_mask))
  564. ++vf->txq_count;
  565. mutex_unlock(&vf->txq_lock);
  566. efx_sriov_bufs(efx, buftbl, req->u.init_txq.addr, buf_count);
  567. eth_filt_en = vf->tx_filter_mode == VF_TX_FILTER_ON;
  568. label = req->u.init_txq.label & EFX_FIELD_MASK(FRF_AZ_TX_DESCQ_LABEL);
  569. EFX_POPULATE_OWORD_8(reg,
  570. FRF_CZ_TX_DPT_Q_MASK_WIDTH, min(efx->vi_scale, 1U),
  571. FRF_CZ_TX_DPT_ETH_FILT_EN, eth_filt_en,
  572. FRF_AZ_TX_DESCQ_EN, 1,
  573. FRF_AZ_TX_DESCQ_BUF_BASE_ID, buftbl,
  574. FRF_AZ_TX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
  575. FRF_AZ_TX_DESCQ_LABEL, label,
  576. FRF_AZ_TX_DESCQ_SIZE, __ffs(buf_count),
  577. FRF_BZ_TX_NON_IP_DROP_DIS, 1);
  578. efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
  579. abs_index(vf, vf_txq));
  580. return VFDI_RC_SUCCESS;
  581. }
  582. /* Returns true when efx_vfdi_fini_all_queues should wake */
  583. static bool efx_vfdi_flush_wake(struct efx_vf *vf)
  584. {
  585. /* Ensure that all updates are visible to efx_vfdi_fini_all_queues() */
  586. smp_mb();
  587. return (!vf->txq_count && !vf->rxq_count) ||
  588. atomic_read(&vf->rxq_retry_count);
  589. }
  590. static void efx_vfdi_flush_clear(struct efx_vf *vf)
  591. {
  592. memset(vf->txq_mask, 0, sizeof(vf->txq_mask));
  593. vf->txq_count = 0;
  594. memset(vf->rxq_mask, 0, sizeof(vf->rxq_mask));
  595. vf->rxq_count = 0;
  596. memset(vf->rxq_retry_mask, 0, sizeof(vf->rxq_retry_mask));
  597. atomic_set(&vf->rxq_retry_count, 0);
  598. }
  599. static int efx_vfdi_fini_all_queues(struct efx_vf *vf)
  600. {
  601. struct efx_nic *efx = vf->efx;
  602. efx_oword_t reg;
  603. unsigned count = efx_vf_size(efx);
  604. unsigned vf_offset = EFX_VI_BASE + vf->index * efx_vf_size(efx);
  605. unsigned timeout = HZ;
  606. unsigned index, rxqs_count;
  607. __le32 *rxqs;
  608. int rc;
  609. BUILD_BUG_ON(VF_MAX_RX_QUEUES >
  610. MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
  611. rxqs = kmalloc(count * sizeof(*rxqs), GFP_KERNEL);
  612. if (rxqs == NULL)
  613. return VFDI_RC_ENOMEM;
  614. rtnl_lock();
  615. if (efx->fc_disable++ == 0)
  616. efx_mcdi_set_mac(efx);
  617. rtnl_unlock();
  618. /* Flush all the initialized queues */
  619. rxqs_count = 0;
  620. for (index = 0; index < count; ++index) {
  621. if (test_bit(index, vf->txq_mask)) {
  622. EFX_POPULATE_OWORD_2(reg,
  623. FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
  624. FRF_AZ_TX_FLUSH_DESCQ,
  625. vf_offset + index);
  626. efx_writeo(efx, &reg, FR_AZ_TX_FLUSH_DESCQ);
  627. }
  628. if (test_bit(index, vf->rxq_mask))
  629. rxqs[rxqs_count++] = cpu_to_le32(vf_offset + index);
  630. }
  631. atomic_set(&vf->rxq_retry_count, 0);
  632. while (timeout && (vf->rxq_count || vf->txq_count)) {
  633. rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, (u8 *)rxqs,
  634. rxqs_count * sizeof(*rxqs), NULL, 0, NULL);
  635. WARN_ON(rc < 0);
  636. timeout = wait_event_timeout(vf->flush_waitq,
  637. efx_vfdi_flush_wake(vf),
  638. timeout);
  639. rxqs_count = 0;
  640. for (index = 0; index < count; ++index) {
  641. if (test_and_clear_bit(index, vf->rxq_retry_mask)) {
  642. atomic_dec(&vf->rxq_retry_count);
  643. rxqs[rxqs_count++] =
  644. cpu_to_le32(vf_offset + index);
  645. }
  646. }
  647. }
  648. rtnl_lock();
  649. if (--efx->fc_disable == 0)
  650. efx_mcdi_set_mac(efx);
  651. rtnl_unlock();
  652. /* Irrespective of success/failure, fini the queues */
  653. EFX_ZERO_OWORD(reg);
  654. for (index = 0; index < count; ++index) {
  655. efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
  656. vf_offset + index);
  657. efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
  658. vf_offset + index);
  659. efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL,
  660. vf_offset + index);
  661. efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL,
  662. vf_offset + index);
  663. }
  664. efx_sriov_bufs(efx, vf->buftbl_base, NULL,
  665. EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx));
  666. kfree(rxqs);
  667. efx_vfdi_flush_clear(vf);
  668. vf->evq0_count = 0;
  669. return timeout ? 0 : VFDI_RC_ETIMEDOUT;
  670. }
  671. static int efx_vfdi_insert_filter(struct efx_vf *vf)
  672. {
  673. struct efx_nic *efx = vf->efx;
  674. struct vfdi_req *req = vf->buf.addr;
  675. unsigned vf_rxq = req->u.mac_filter.rxq;
  676. unsigned flags;
  677. if (bad_vf_index(efx, vf_rxq) || vf->rx_filtering) {
  678. if (net_ratelimit())
  679. netif_err(efx, hw, efx->net_dev,
  680. "ERROR: Invalid INSERT_FILTER from %s: rxq %d "
  681. "flags 0x%x\n", vf->pci_name, vf_rxq,
  682. req->u.mac_filter.flags);
  683. return VFDI_RC_EINVAL;
  684. }
  685. flags = 0;
  686. if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_RSS)
  687. flags |= EFX_FILTER_FLAG_RX_RSS;
  688. if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_SCATTER)
  689. flags |= EFX_FILTER_FLAG_RX_SCATTER;
  690. vf->rx_filter_flags = flags;
  691. vf->rx_filter_qid = vf_rxq;
  692. vf->rx_filtering = true;
  693. efx_sriov_reset_rx_filter(vf);
  694. queue_work(vfdi_workqueue, &efx->peer_work);
  695. return VFDI_RC_SUCCESS;
  696. }
  697. static int efx_vfdi_remove_all_filters(struct efx_vf *vf)
  698. {
  699. vf->rx_filtering = false;
  700. efx_sriov_reset_rx_filter(vf);
  701. queue_work(vfdi_workqueue, &vf->efx->peer_work);
  702. return VFDI_RC_SUCCESS;
  703. }
  704. static int efx_vfdi_set_status_page(struct efx_vf *vf)
  705. {
  706. struct efx_nic *efx = vf->efx;
  707. struct vfdi_req *req = vf->buf.addr;
  708. u64 page_count = req->u.set_status_page.peer_page_count;
  709. u64 max_page_count =
  710. (EFX_PAGE_SIZE -
  711. offsetof(struct vfdi_req, u.set_status_page.peer_page_addr[0]))
  712. / sizeof(req->u.set_status_page.peer_page_addr[0]);
  713. if (!req->u.set_status_page.dma_addr || page_count > max_page_count) {
  714. if (net_ratelimit())
  715. netif_err(efx, hw, efx->net_dev,
  716. "ERROR: Invalid SET_STATUS_PAGE from %s\n",
  717. vf->pci_name);
  718. return VFDI_RC_EINVAL;
  719. }
  720. mutex_lock(&efx->local_lock);
  721. mutex_lock(&vf->status_lock);
  722. vf->status_addr = req->u.set_status_page.dma_addr;
  723. kfree(vf->peer_page_addrs);
  724. vf->peer_page_addrs = NULL;
  725. vf->peer_page_count = 0;
  726. if (page_count) {
  727. vf->peer_page_addrs = kcalloc(page_count, sizeof(u64),
  728. GFP_KERNEL);
  729. if (vf->peer_page_addrs) {
  730. memcpy(vf->peer_page_addrs,
  731. req->u.set_status_page.peer_page_addr,
  732. page_count * sizeof(u64));
  733. vf->peer_page_count = page_count;
  734. }
  735. }
  736. __efx_sriov_push_vf_status(vf);
  737. mutex_unlock(&vf->status_lock);
  738. mutex_unlock(&efx->local_lock);
  739. return VFDI_RC_SUCCESS;
  740. }
  741. static int efx_vfdi_clear_status_page(struct efx_vf *vf)
  742. {
  743. mutex_lock(&vf->status_lock);
  744. vf->status_addr = 0;
  745. mutex_unlock(&vf->status_lock);
  746. return VFDI_RC_SUCCESS;
  747. }
  748. typedef int (*efx_vfdi_op_t)(struct efx_vf *vf);
  749. static const efx_vfdi_op_t vfdi_ops[VFDI_OP_LIMIT] = {
  750. [VFDI_OP_INIT_EVQ] = efx_vfdi_init_evq,
  751. [VFDI_OP_INIT_TXQ] = efx_vfdi_init_txq,
  752. [VFDI_OP_INIT_RXQ] = efx_vfdi_init_rxq,
  753. [VFDI_OP_FINI_ALL_QUEUES] = efx_vfdi_fini_all_queues,
  754. [VFDI_OP_INSERT_FILTER] = efx_vfdi_insert_filter,
  755. [VFDI_OP_REMOVE_ALL_FILTERS] = efx_vfdi_remove_all_filters,
  756. [VFDI_OP_SET_STATUS_PAGE] = efx_vfdi_set_status_page,
  757. [VFDI_OP_CLEAR_STATUS_PAGE] = efx_vfdi_clear_status_page,
  758. };
  759. static void efx_sriov_vfdi(struct work_struct *work)
  760. {
  761. struct efx_vf *vf = container_of(work, struct efx_vf, req);
  762. struct efx_nic *efx = vf->efx;
  763. struct vfdi_req *req = vf->buf.addr;
  764. struct efx_memcpy_req copy[2];
  765. int rc;
  766. /* Copy this page into the local address space */
  767. memset(copy, '\0', sizeof(copy));
  768. copy[0].from_rid = vf->pci_rid;
  769. copy[0].from_addr = vf->req_addr;
  770. copy[0].to_rid = efx->pci_dev->devfn;
  771. copy[0].to_addr = vf->buf.dma_addr;
  772. copy[0].length = EFX_PAGE_SIZE;
  773. rc = efx_sriov_memcpy(efx, copy, 1);
  774. if (rc) {
  775. /* If we can't get the request, we can't reply to the caller */
  776. if (net_ratelimit())
  777. netif_err(efx, hw, efx->net_dev,
  778. "ERROR: Unable to fetch VFDI request from %s rc %d\n",
  779. vf->pci_name, -rc);
  780. vf->busy = false;
  781. return;
  782. }
  783. if (req->op < VFDI_OP_LIMIT && vfdi_ops[req->op] != NULL) {
  784. rc = vfdi_ops[req->op](vf);
  785. if (rc == 0) {
  786. netif_dbg(efx, hw, efx->net_dev,
  787. "vfdi request %d from %s ok\n",
  788. req->op, vf->pci_name);
  789. }
  790. } else {
  791. netif_dbg(efx, hw, efx->net_dev,
  792. "ERROR: Unrecognised request %d from VF %s addr "
  793. "%llx\n", req->op, vf->pci_name,
  794. (unsigned long long)vf->req_addr);
  795. rc = VFDI_RC_EOPNOTSUPP;
  796. }
  797. /* Allow subsequent VF requests */
  798. vf->busy = false;
  799. smp_wmb();
  800. /* Respond to the request */
  801. req->rc = rc;
  802. req->op = VFDI_OP_RESPONSE;
  803. memset(copy, '\0', sizeof(copy));
  804. copy[0].from_buf = &req->rc;
  805. copy[0].to_rid = vf->pci_rid;
  806. copy[0].to_addr = vf->req_addr + offsetof(struct vfdi_req, rc);
  807. copy[0].length = sizeof(req->rc);
  808. copy[1].from_buf = &req->op;
  809. copy[1].to_rid = vf->pci_rid;
  810. copy[1].to_addr = vf->req_addr + offsetof(struct vfdi_req, op);
  811. copy[1].length = sizeof(req->op);
  812. (void) efx_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
  813. }
  814. /* After a reset the event queues inside the guests no longer exist. Fill the
  815. * event ring in guest memory with VFDI reset events, then (re-initialise) the
  816. * event queue to raise an interrupt. The guest driver will then recover.
  817. */
  818. static void efx_sriov_reset_vf(struct efx_vf *vf, struct efx_buffer *buffer)
  819. {
  820. struct efx_nic *efx = vf->efx;
  821. struct efx_memcpy_req copy_req[4];
  822. efx_qword_t event;
  823. unsigned int pos, count, k, buftbl, abs_evq;
  824. efx_oword_t reg;
  825. efx_dword_t ptr;
  826. int rc;
  827. BUG_ON(buffer->len != EFX_PAGE_SIZE);
  828. if (!vf->evq0_count)
  829. return;
  830. BUG_ON(vf->evq0_count & (vf->evq0_count - 1));
  831. mutex_lock(&vf->status_lock);
  832. EFX_POPULATE_QWORD_3(event,
  833. FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
  834. VFDI_EV_SEQ, vf->msg_seqno,
  835. VFDI_EV_TYPE, VFDI_EV_TYPE_RESET);
  836. vf->msg_seqno++;
  837. for (pos = 0; pos < EFX_PAGE_SIZE; pos += sizeof(event))
  838. memcpy(buffer->addr + pos, &event, sizeof(event));
  839. for (pos = 0; pos < vf->evq0_count; pos += count) {
  840. count = min_t(unsigned, vf->evq0_count - pos,
  841. ARRAY_SIZE(copy_req));
  842. for (k = 0; k < count; k++) {
  843. copy_req[k].from_buf = NULL;
  844. copy_req[k].from_rid = efx->pci_dev->devfn;
  845. copy_req[k].from_addr = buffer->dma_addr;
  846. copy_req[k].to_rid = vf->pci_rid;
  847. copy_req[k].to_addr = vf->evq0_addrs[pos + k];
  848. copy_req[k].length = EFX_PAGE_SIZE;
  849. }
  850. rc = efx_sriov_memcpy(efx, copy_req, count);
  851. if (rc) {
  852. if (net_ratelimit())
  853. netif_err(efx, hw, efx->net_dev,
  854. "ERROR: Unable to notify %s of reset"
  855. ": %d\n", vf->pci_name, -rc);
  856. break;
  857. }
  858. }
  859. /* Reinitialise, arm and trigger evq0 */
  860. abs_evq = abs_index(vf, 0);
  861. buftbl = EFX_BUFTBL_EVQ_BASE(vf, 0);
  862. efx_sriov_bufs(efx, buftbl, vf->evq0_addrs, vf->evq0_count);
  863. EFX_POPULATE_OWORD_3(reg,
  864. FRF_CZ_TIMER_Q_EN, 1,
  865. FRF_CZ_HOST_NOTIFY_MODE, 0,
  866. FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
  867. efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
  868. EFX_POPULATE_OWORD_3(reg,
  869. FRF_AZ_EVQ_EN, 1,
  870. FRF_AZ_EVQ_SIZE, __ffs(vf->evq0_count),
  871. FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
  872. efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
  873. EFX_POPULATE_DWORD_1(ptr, FRF_AZ_EVQ_RPTR, 0);
  874. efx_writed_table(efx, &ptr, FR_BZ_EVQ_RPTR, abs_evq);
  875. mutex_unlock(&vf->status_lock);
  876. }
  877. static void efx_sriov_reset_vf_work(struct work_struct *work)
  878. {
  879. struct efx_vf *vf = container_of(work, struct efx_vf, req);
  880. struct efx_nic *efx = vf->efx;
  881. struct efx_buffer buf;
  882. if (!efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE)) {
  883. efx_sriov_reset_vf(vf, &buf);
  884. efx_nic_free_buffer(efx, &buf);
  885. }
  886. }
  887. static void efx_sriov_handle_no_channel(struct efx_nic *efx)
  888. {
  889. netif_err(efx, drv, efx->net_dev,
  890. "ERROR: IOV requires MSI-X and 1 additional interrupt"
  891. "vector. IOV disabled\n");
  892. efx->vf_count = 0;
  893. }
  894. static int efx_sriov_probe_channel(struct efx_channel *channel)
  895. {
  896. channel->efx->vfdi_channel = channel;
  897. return 0;
  898. }
  899. static void
  900. efx_sriov_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
  901. {
  902. snprintf(buf, len, "%s-iov", channel->efx->name);
  903. }
  904. static const struct efx_channel_type efx_sriov_channel_type = {
  905. .handle_no_channel = efx_sriov_handle_no_channel,
  906. .pre_probe = efx_sriov_probe_channel,
  907. .post_remove = efx_channel_dummy_op_void,
  908. .get_name = efx_sriov_get_channel_name,
  909. /* no copy operation; channel must not be reallocated */
  910. .keep_eventq = true,
  911. };
  912. void efx_sriov_probe(struct efx_nic *efx)
  913. {
  914. unsigned count;
  915. if (!max_vfs)
  916. return;
  917. if (efx_sriov_cmd(efx, false, &efx->vi_scale, &count))
  918. return;
  919. if (count > 0 && count > max_vfs)
  920. count = max_vfs;
  921. /* efx_nic_dimension_resources() will reduce vf_count as appopriate */
  922. efx->vf_count = count;
  923. efx->extra_channel_type[EFX_EXTRA_CHANNEL_IOV] = &efx_sriov_channel_type;
  924. }
  925. /* Copy the list of individual addresses into the vfdi_status.peers
  926. * array and auxillary pages, protected by %local_lock. Drop that lock
  927. * and then broadcast the address list to every VF.
  928. */
  929. static void efx_sriov_peer_work(struct work_struct *data)
  930. {
  931. struct efx_nic *efx = container_of(data, struct efx_nic, peer_work);
  932. struct vfdi_status *vfdi_status = efx->vfdi_status.addr;
  933. struct efx_vf *vf;
  934. struct efx_local_addr *local_addr;
  935. struct vfdi_endpoint *peer;
  936. struct efx_endpoint_page *epp;
  937. struct list_head pages;
  938. unsigned int peer_space;
  939. unsigned int peer_count;
  940. unsigned int pos;
  941. mutex_lock(&efx->local_lock);
  942. /* Move the existing peer pages off %local_page_list */
  943. INIT_LIST_HEAD(&pages);
  944. list_splice_tail_init(&efx->local_page_list, &pages);
  945. /* Populate the VF addresses starting from entry 1 (entry 0 is
  946. * the PF address)
  947. */
  948. peer = vfdi_status->peers + 1;
  949. peer_space = ARRAY_SIZE(vfdi_status->peers) - 1;
  950. peer_count = 1;
  951. for (pos = 0; pos < efx->vf_count; ++pos) {
  952. vf = efx->vf + pos;
  953. mutex_lock(&vf->status_lock);
  954. if (vf->rx_filtering && !is_zero_ether_addr(vf->addr.mac_addr)) {
  955. *peer++ = vf->addr;
  956. ++peer_count;
  957. --peer_space;
  958. BUG_ON(peer_space == 0);
  959. }
  960. mutex_unlock(&vf->status_lock);
  961. }
  962. /* Fill the remaining addresses */
  963. list_for_each_entry(local_addr, &efx->local_addr_list, link) {
  964. memcpy(peer->mac_addr, local_addr->addr, ETH_ALEN);
  965. peer->tci = 0;
  966. ++peer;
  967. ++peer_count;
  968. if (--peer_space == 0) {
  969. if (list_empty(&pages)) {
  970. epp = kmalloc(sizeof(*epp), GFP_KERNEL);
  971. if (!epp)
  972. break;
  973. epp->ptr = dma_alloc_coherent(
  974. &efx->pci_dev->dev, EFX_PAGE_SIZE,
  975. &epp->addr, GFP_KERNEL);
  976. if (!epp->ptr) {
  977. kfree(epp);
  978. break;
  979. }
  980. } else {
  981. epp = list_first_entry(
  982. &pages, struct efx_endpoint_page, link);
  983. list_del(&epp->link);
  984. }
  985. list_add_tail(&epp->link, &efx->local_page_list);
  986. peer = (struct vfdi_endpoint *)epp->ptr;
  987. peer_space = EFX_PAGE_SIZE / sizeof(struct vfdi_endpoint);
  988. }
  989. }
  990. vfdi_status->peer_count = peer_count;
  991. mutex_unlock(&efx->local_lock);
  992. /* Free any now unused endpoint pages */
  993. while (!list_empty(&pages)) {
  994. epp = list_first_entry(
  995. &pages, struct efx_endpoint_page, link);
  996. list_del(&epp->link);
  997. dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
  998. epp->ptr, epp->addr);
  999. kfree(epp);
  1000. }
  1001. /* Finally, push the pages */
  1002. for (pos = 0; pos < efx->vf_count; ++pos) {
  1003. vf = efx->vf + pos;
  1004. mutex_lock(&vf->status_lock);
  1005. if (vf->status_addr)
  1006. __efx_sriov_push_vf_status(vf);
  1007. mutex_unlock(&vf->status_lock);
  1008. }
  1009. }
  1010. static void efx_sriov_free_local(struct efx_nic *efx)
  1011. {
  1012. struct efx_local_addr *local_addr;
  1013. struct efx_endpoint_page *epp;
  1014. while (!list_empty(&efx->local_addr_list)) {
  1015. local_addr = list_first_entry(&efx->local_addr_list,
  1016. struct efx_local_addr, link);
  1017. list_del(&local_addr->link);
  1018. kfree(local_addr);
  1019. }
  1020. while (!list_empty(&efx->local_page_list)) {
  1021. epp = list_first_entry(&efx->local_page_list,
  1022. struct efx_endpoint_page, link);
  1023. list_del(&epp->link);
  1024. dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
  1025. epp->ptr, epp->addr);
  1026. kfree(epp);
  1027. }
  1028. }
  1029. static int efx_sriov_vf_alloc(struct efx_nic *efx)
  1030. {
  1031. unsigned index;
  1032. struct efx_vf *vf;
  1033. efx->vf = kzalloc(sizeof(struct efx_vf) * efx->vf_count, GFP_KERNEL);
  1034. if (!efx->vf)
  1035. return -ENOMEM;
  1036. for (index = 0; index < efx->vf_count; ++index) {
  1037. vf = efx->vf + index;
  1038. vf->efx = efx;
  1039. vf->index = index;
  1040. vf->rx_filter_id = -1;
  1041. vf->tx_filter_mode = VF_TX_FILTER_AUTO;
  1042. vf->tx_filter_id = -1;
  1043. INIT_WORK(&vf->req, efx_sriov_vfdi);
  1044. INIT_WORK(&vf->reset_work, efx_sriov_reset_vf_work);
  1045. init_waitqueue_head(&vf->flush_waitq);
  1046. mutex_init(&vf->status_lock);
  1047. mutex_init(&vf->txq_lock);
  1048. }
  1049. return 0;
  1050. }
  1051. static void efx_sriov_vfs_fini(struct efx_nic *efx)
  1052. {
  1053. struct efx_vf *vf;
  1054. unsigned int pos;
  1055. for (pos = 0; pos < efx->vf_count; ++pos) {
  1056. vf = efx->vf + pos;
  1057. efx_nic_free_buffer(efx, &vf->buf);
  1058. kfree(vf->peer_page_addrs);
  1059. vf->peer_page_addrs = NULL;
  1060. vf->peer_page_count = 0;
  1061. vf->evq0_count = 0;
  1062. }
  1063. }
  1064. static int efx_sriov_vfs_init(struct efx_nic *efx)
  1065. {
  1066. struct pci_dev *pci_dev = efx->pci_dev;
  1067. unsigned index, devfn, sriov, buftbl_base;
  1068. u16 offset, stride;
  1069. struct efx_vf *vf;
  1070. int rc;
  1071. sriov = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_SRIOV);
  1072. if (!sriov)
  1073. return -ENOENT;
  1074. pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_OFFSET, &offset);
  1075. pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_STRIDE, &stride);
  1076. buftbl_base = efx->vf_buftbl_base;
  1077. devfn = pci_dev->devfn + offset;
  1078. for (index = 0; index < efx->vf_count; ++index) {
  1079. vf = efx->vf + index;
  1080. /* Reserve buffer entries */
  1081. vf->buftbl_base = buftbl_base;
  1082. buftbl_base += EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx);
  1083. vf->pci_rid = devfn;
  1084. snprintf(vf->pci_name, sizeof(vf->pci_name),
  1085. "%04x:%02x:%02x.%d",
  1086. pci_domain_nr(pci_dev->bus), pci_dev->bus->number,
  1087. PCI_SLOT(devfn), PCI_FUNC(devfn));
  1088. rc = efx_nic_alloc_buffer(efx, &vf->buf, EFX_PAGE_SIZE);
  1089. if (rc)
  1090. goto fail;
  1091. devfn += stride;
  1092. }
  1093. return 0;
  1094. fail:
  1095. efx_sriov_vfs_fini(efx);
  1096. return rc;
  1097. }
  1098. int efx_sriov_init(struct efx_nic *efx)
  1099. {
  1100. struct net_device *net_dev = efx->net_dev;
  1101. struct vfdi_status *vfdi_status;
  1102. int rc;
  1103. /* Ensure there's room for vf_channel */
  1104. BUILD_BUG_ON(EFX_MAX_CHANNELS + 1 >= EFX_VI_BASE);
  1105. /* Ensure that VI_BASE is aligned on VI_SCALE */
  1106. BUILD_BUG_ON(EFX_VI_BASE & ((1 << EFX_VI_SCALE_MAX) - 1));
  1107. if (efx->vf_count == 0)
  1108. return 0;
  1109. rc = efx_sriov_cmd(efx, true, NULL, NULL);
  1110. if (rc)
  1111. goto fail_cmd;
  1112. rc = efx_nic_alloc_buffer(efx, &efx->vfdi_status, sizeof(*vfdi_status));
  1113. if (rc)
  1114. goto fail_status;
  1115. vfdi_status = efx->vfdi_status.addr;
  1116. memset(vfdi_status, 0, sizeof(*vfdi_status));
  1117. vfdi_status->version = 1;
  1118. vfdi_status->length = sizeof(*vfdi_status);
  1119. vfdi_status->max_tx_channels = vf_max_tx_channels;
  1120. vfdi_status->vi_scale = efx->vi_scale;
  1121. vfdi_status->rss_rxq_count = efx->rss_spread;
  1122. vfdi_status->peer_count = 1 + efx->vf_count;
  1123. vfdi_status->timer_quantum_ns = efx->timer_quantum_ns;
  1124. rc = efx_sriov_vf_alloc(efx);
  1125. if (rc)
  1126. goto fail_alloc;
  1127. mutex_init(&efx->local_lock);
  1128. INIT_WORK(&efx->peer_work, efx_sriov_peer_work);
  1129. INIT_LIST_HEAD(&efx->local_addr_list);
  1130. INIT_LIST_HEAD(&efx->local_page_list);
  1131. rc = efx_sriov_vfs_init(efx);
  1132. if (rc)
  1133. goto fail_vfs;
  1134. rtnl_lock();
  1135. memcpy(vfdi_status->peers[0].mac_addr,
  1136. net_dev->dev_addr, ETH_ALEN);
  1137. efx->vf_init_count = efx->vf_count;
  1138. rtnl_unlock();
  1139. efx_sriov_usrev(efx, true);
  1140. /* At this point we must be ready to accept VFDI requests */
  1141. rc = pci_enable_sriov(efx->pci_dev, efx->vf_count);
  1142. if (rc)
  1143. goto fail_pci;
  1144. netif_info(efx, probe, net_dev,
  1145. "enabled SR-IOV for %d VFs, %d VI per VF\n",
  1146. efx->vf_count, efx_vf_size(efx));
  1147. return 0;
  1148. fail_pci:
  1149. efx_sriov_usrev(efx, false);
  1150. rtnl_lock();
  1151. efx->vf_init_count = 0;
  1152. rtnl_unlock();
  1153. efx_sriov_vfs_fini(efx);
  1154. fail_vfs:
  1155. cancel_work_sync(&efx->peer_work);
  1156. efx_sriov_free_local(efx);
  1157. kfree(efx->vf);
  1158. fail_alloc:
  1159. efx_nic_free_buffer(efx, &efx->vfdi_status);
  1160. fail_status:
  1161. efx_sriov_cmd(efx, false, NULL, NULL);
  1162. fail_cmd:
  1163. return rc;
  1164. }
  1165. void efx_sriov_fini(struct efx_nic *efx)
  1166. {
  1167. struct efx_vf *vf;
  1168. unsigned int pos;
  1169. if (efx->vf_init_count == 0)
  1170. return;
  1171. /* Disable all interfaces to reconfiguration */
  1172. BUG_ON(efx->vfdi_channel->enabled);
  1173. efx_sriov_usrev(efx, false);
  1174. rtnl_lock();
  1175. efx->vf_init_count = 0;
  1176. rtnl_unlock();
  1177. /* Flush all reconfiguration work */
  1178. for (pos = 0; pos < efx->vf_count; ++pos) {
  1179. vf = efx->vf + pos;
  1180. cancel_work_sync(&vf->req);
  1181. cancel_work_sync(&vf->reset_work);
  1182. }
  1183. cancel_work_sync(&efx->peer_work);
  1184. pci_disable_sriov(efx->pci_dev);
  1185. /* Tear down back-end state */
  1186. efx_sriov_vfs_fini(efx);
  1187. efx_sriov_free_local(efx);
  1188. kfree(efx->vf);
  1189. efx_nic_free_buffer(efx, &efx->vfdi_status);
  1190. efx_sriov_cmd(efx, false, NULL, NULL);
  1191. }
  1192. void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event)
  1193. {
  1194. struct efx_nic *efx = channel->efx;
  1195. struct efx_vf *vf;
  1196. unsigned qid, seq, type, data;
  1197. qid = EFX_QWORD_FIELD(*event, FSF_CZ_USER_QID);
  1198. /* USR_EV_REG_VALUE is dword0, so access the VFDI_EV fields directly */
  1199. BUILD_BUG_ON(FSF_CZ_USER_EV_REG_VALUE_LBN != 0);
  1200. seq = EFX_QWORD_FIELD(*event, VFDI_EV_SEQ);
  1201. type = EFX_QWORD_FIELD(*event, VFDI_EV_TYPE);
  1202. data = EFX_QWORD_FIELD(*event, VFDI_EV_DATA);
  1203. netif_vdbg(efx, hw, efx->net_dev,
  1204. "USR_EV event from qid %d seq 0x%x type %d data 0x%x\n",
  1205. qid, seq, type, data);
  1206. if (map_vi_index(efx, qid, &vf, NULL))
  1207. return;
  1208. if (vf->busy)
  1209. goto error;
  1210. if (type == VFDI_EV_TYPE_REQ_WORD0) {
  1211. /* Resynchronise */
  1212. vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
  1213. vf->req_seqno = seq + 1;
  1214. vf->req_addr = 0;
  1215. } else if (seq != (vf->req_seqno++ & 0xff) || type != vf->req_type)
  1216. goto error;
  1217. switch (vf->req_type) {
  1218. case VFDI_EV_TYPE_REQ_WORD0:
  1219. case VFDI_EV_TYPE_REQ_WORD1:
  1220. case VFDI_EV_TYPE_REQ_WORD2:
  1221. vf->req_addr |= (u64)data << (vf->req_type << 4);
  1222. ++vf->req_type;
  1223. return;
  1224. case VFDI_EV_TYPE_REQ_WORD3:
  1225. vf->req_addr |= (u64)data << 48;
  1226. vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
  1227. vf->busy = true;
  1228. queue_work(vfdi_workqueue, &vf->req);
  1229. return;
  1230. }
  1231. error:
  1232. if (net_ratelimit())
  1233. netif_err(efx, hw, efx->net_dev,
  1234. "ERROR: Screaming VFDI request from %s\n",
  1235. vf->pci_name);
  1236. /* Reset the request and sequence number */
  1237. vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
  1238. vf->req_seqno = seq + 1;
  1239. }
  1240. void efx_sriov_flr(struct efx_nic *efx, unsigned vf_i)
  1241. {
  1242. struct efx_vf *vf;
  1243. if (vf_i > efx->vf_init_count)
  1244. return;
  1245. vf = efx->vf + vf_i;
  1246. netif_info(efx, hw, efx->net_dev,
  1247. "FLR on VF %s\n", vf->pci_name);
  1248. vf->status_addr = 0;
  1249. efx_vfdi_remove_all_filters(vf);
  1250. efx_vfdi_flush_clear(vf);
  1251. vf->evq0_count = 0;
  1252. }
  1253. void efx_sriov_mac_address_changed(struct efx_nic *efx)
  1254. {
  1255. struct vfdi_status *vfdi_status = efx->vfdi_status.addr;
  1256. if (!efx->vf_init_count)
  1257. return;
  1258. memcpy(vfdi_status->peers[0].mac_addr,
  1259. efx->net_dev->dev_addr, ETH_ALEN);
  1260. queue_work(vfdi_workqueue, &efx->peer_work);
  1261. }
  1262. void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
  1263. {
  1264. struct efx_vf *vf;
  1265. unsigned queue, qid;
  1266. queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
  1267. if (map_vi_index(efx, queue, &vf, &qid))
  1268. return;
  1269. /* Ignore flush completions triggered by an FLR */
  1270. if (!test_bit(qid, vf->txq_mask))
  1271. return;
  1272. __clear_bit(qid, vf->txq_mask);
  1273. --vf->txq_count;
  1274. if (efx_vfdi_flush_wake(vf))
  1275. wake_up(&vf->flush_waitq);
  1276. }
  1277. void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
  1278. {
  1279. struct efx_vf *vf;
  1280. unsigned ev_failed, queue, qid;
  1281. queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
  1282. ev_failed = EFX_QWORD_FIELD(*event,
  1283. FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
  1284. if (map_vi_index(efx, queue, &vf, &qid))
  1285. return;
  1286. if (!test_bit(qid, vf->rxq_mask))
  1287. return;
  1288. if (ev_failed) {
  1289. set_bit(qid, vf->rxq_retry_mask);
  1290. atomic_inc(&vf->rxq_retry_count);
  1291. } else {
  1292. __clear_bit(qid, vf->rxq_mask);
  1293. --vf->rxq_count;
  1294. }
  1295. if (efx_vfdi_flush_wake(vf))
  1296. wake_up(&vf->flush_waitq);
  1297. }
  1298. /* Called from napi. Schedule the reset work item */
  1299. void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq)
  1300. {
  1301. struct efx_vf *vf;
  1302. unsigned int rel;
  1303. if (map_vi_index(efx, dmaq, &vf, &rel))
  1304. return;
  1305. if (net_ratelimit())
  1306. netif_err(efx, hw, efx->net_dev,
  1307. "VF %d DMA Q %d reports descriptor fetch error.\n",
  1308. vf->index, rel);
  1309. queue_work(vfdi_workqueue, &vf->reset_work);
  1310. }
  1311. /* Reset all VFs */
  1312. void efx_sriov_reset(struct efx_nic *efx)
  1313. {
  1314. unsigned int vf_i;
  1315. struct efx_buffer buf;
  1316. struct efx_vf *vf;
  1317. ASSERT_RTNL();
  1318. if (efx->vf_init_count == 0)
  1319. return;
  1320. efx_sriov_usrev(efx, true);
  1321. (void)efx_sriov_cmd(efx, true, NULL, NULL);
  1322. if (efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE))
  1323. return;
  1324. for (vf_i = 0; vf_i < efx->vf_init_count; ++vf_i) {
  1325. vf = efx->vf + vf_i;
  1326. efx_sriov_reset_vf(vf, &buf);
  1327. }
  1328. efx_nic_free_buffer(efx, &buf);
  1329. }
  1330. int efx_init_sriov(void)
  1331. {
  1332. /* A single threaded workqueue is sufficient. efx_sriov_vfdi() and
  1333. * efx_sriov_peer_work() spend almost all their time sleeping for
  1334. * MCDI to complete anyway
  1335. */
  1336. vfdi_workqueue = create_singlethread_workqueue("sfc_vfdi");
  1337. if (!vfdi_workqueue)
  1338. return -ENOMEM;
  1339. return 0;
  1340. }
  1341. void efx_fini_sriov(void)
  1342. {
  1343. destroy_workqueue(vfdi_workqueue);
  1344. }
  1345. int efx_sriov_set_vf_mac(struct net_device *net_dev, int vf_i, u8 *mac)
  1346. {
  1347. struct efx_nic *efx = netdev_priv(net_dev);
  1348. struct efx_vf *vf;
  1349. if (vf_i >= efx->vf_init_count)
  1350. return -EINVAL;
  1351. vf = efx->vf + vf_i;
  1352. mutex_lock(&vf->status_lock);
  1353. memcpy(vf->addr.mac_addr, mac, ETH_ALEN);
  1354. __efx_sriov_update_vf_addr(vf);
  1355. mutex_unlock(&vf->status_lock);
  1356. return 0;
  1357. }
  1358. int efx_sriov_set_vf_vlan(struct net_device *net_dev, int vf_i,
  1359. u16 vlan, u8 qos)
  1360. {
  1361. struct efx_nic *efx = netdev_priv(net_dev);
  1362. struct efx_vf *vf;
  1363. u16 tci;
  1364. if (vf_i >= efx->vf_init_count)
  1365. return -EINVAL;
  1366. vf = efx->vf + vf_i;
  1367. mutex_lock(&vf->status_lock);
  1368. tci = (vlan & VLAN_VID_MASK) | ((qos & 0x7) << VLAN_PRIO_SHIFT);
  1369. vf->addr.tci = htons(tci);
  1370. __efx_sriov_update_vf_addr(vf);
  1371. mutex_unlock(&vf->status_lock);
  1372. return 0;
  1373. }
  1374. int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf_i,
  1375. bool spoofchk)
  1376. {
  1377. struct efx_nic *efx = netdev_priv(net_dev);
  1378. struct efx_vf *vf;
  1379. int rc;
  1380. if (vf_i >= efx->vf_init_count)
  1381. return -EINVAL;
  1382. vf = efx->vf + vf_i;
  1383. mutex_lock(&vf->txq_lock);
  1384. if (vf->txq_count == 0) {
  1385. vf->tx_filter_mode =
  1386. spoofchk ? VF_TX_FILTER_ON : VF_TX_FILTER_OFF;
  1387. rc = 0;
  1388. } else {
  1389. /* This cannot be changed while TX queues are running */
  1390. rc = -EBUSY;
  1391. }
  1392. mutex_unlock(&vf->txq_lock);
  1393. return rc;
  1394. }
  1395. int efx_sriov_get_vf_config(struct net_device *net_dev, int vf_i,
  1396. struct ifla_vf_info *ivi)
  1397. {
  1398. struct efx_nic *efx = netdev_priv(net_dev);
  1399. struct efx_vf *vf;
  1400. u16 tci;
  1401. if (vf_i >= efx->vf_init_count)
  1402. return -EINVAL;
  1403. vf = efx->vf + vf_i;
  1404. ivi->vf = vf_i;
  1405. memcpy(ivi->mac, vf->addr.mac_addr, ETH_ALEN);
  1406. ivi->tx_rate = 0;
  1407. tci = ntohs(vf->addr.tci);
  1408. ivi->vlan = tci & VLAN_VID_MASK;
  1409. ivi->qos = (tci >> VLAN_PRIO_SHIFT) & 0x7;
  1410. ivi->spoofchk = vf->tx_filter_mode == VF_TX_FILTER_ON;
  1411. return 0;
  1412. }