r8169.c 168 KB

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  1. /*
  2. * r8169.c: RealTek 8169/8168/8101 ethernet driver.
  3. *
  4. * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
  5. * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
  6. * Copyright (c) a lot of people too. Please respect their work.
  7. *
  8. * See MAINTAINERS file for support contact information.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/pci.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/delay.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/mii.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/crc32.h>
  20. #include <linux/in.h>
  21. #include <linux/ip.h>
  22. #include <linux/tcp.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/firmware.h>
  28. #include <linux/pci-aspm.h>
  29. #include <linux/prefetch.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #define RTL8169_VERSION "2.3LK-NAPI"
  33. #define MODULENAME "r8169"
  34. #define PFX MODULENAME ": "
  35. #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
  36. #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
  37. #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
  38. #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
  39. #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
  40. #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
  41. #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
  42. #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
  43. #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
  44. #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
  45. #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
  46. #define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw"
  47. #ifdef RTL8169_DEBUG
  48. #define assert(expr) \
  49. if (!(expr)) { \
  50. printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  51. #expr,__FILE__,__func__,__LINE__); \
  52. }
  53. #define dprintk(fmt, args...) \
  54. do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  55. #else
  56. #define assert(expr) do {} while (0)
  57. #define dprintk(fmt, args...) do {} while (0)
  58. #endif /* RTL8169_DEBUG */
  59. #define R8169_MSG_DEFAULT \
  60. (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61. #define TX_SLOTS_AVAIL(tp) \
  62. (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  63. /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  64. #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  65. (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  66. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  67. The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  68. static const int multicast_filter_limit = 32;
  69. #define MAX_READ_REQUEST_SHIFT 12
  70. #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
  71. #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
  72. #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
  73. #define R8169_REGS_SIZE 256
  74. #define R8169_NAPI_WEIGHT 64
  75. #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
  76. #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
  77. #define RX_BUF_SIZE 1536 /* Rx Buffer size */
  78. #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
  79. #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
  80. #define RTL8169_TX_TIMEOUT (6*HZ)
  81. #define RTL8169_PHY_TIMEOUT (10*HZ)
  82. #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
  83. #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
  84. #define RTL_EEPROM_SIG_ADDR 0x0000
  85. /* write/read MMIO register */
  86. #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
  87. #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
  88. #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
  89. #define RTL_R8(reg) readb (ioaddr + (reg))
  90. #define RTL_R16(reg) readw (ioaddr + (reg))
  91. #define RTL_R32(reg) readl (ioaddr + (reg))
  92. enum mac_version {
  93. RTL_GIGA_MAC_VER_01 = 0,
  94. RTL_GIGA_MAC_VER_02,
  95. RTL_GIGA_MAC_VER_03,
  96. RTL_GIGA_MAC_VER_04,
  97. RTL_GIGA_MAC_VER_05,
  98. RTL_GIGA_MAC_VER_06,
  99. RTL_GIGA_MAC_VER_07,
  100. RTL_GIGA_MAC_VER_08,
  101. RTL_GIGA_MAC_VER_09,
  102. RTL_GIGA_MAC_VER_10,
  103. RTL_GIGA_MAC_VER_11,
  104. RTL_GIGA_MAC_VER_12,
  105. RTL_GIGA_MAC_VER_13,
  106. RTL_GIGA_MAC_VER_14,
  107. RTL_GIGA_MAC_VER_15,
  108. RTL_GIGA_MAC_VER_16,
  109. RTL_GIGA_MAC_VER_17,
  110. RTL_GIGA_MAC_VER_18,
  111. RTL_GIGA_MAC_VER_19,
  112. RTL_GIGA_MAC_VER_20,
  113. RTL_GIGA_MAC_VER_21,
  114. RTL_GIGA_MAC_VER_22,
  115. RTL_GIGA_MAC_VER_23,
  116. RTL_GIGA_MAC_VER_24,
  117. RTL_GIGA_MAC_VER_25,
  118. RTL_GIGA_MAC_VER_26,
  119. RTL_GIGA_MAC_VER_27,
  120. RTL_GIGA_MAC_VER_28,
  121. RTL_GIGA_MAC_VER_29,
  122. RTL_GIGA_MAC_VER_30,
  123. RTL_GIGA_MAC_VER_31,
  124. RTL_GIGA_MAC_VER_32,
  125. RTL_GIGA_MAC_VER_33,
  126. RTL_GIGA_MAC_VER_34,
  127. RTL_GIGA_MAC_VER_35,
  128. RTL_GIGA_MAC_VER_36,
  129. RTL_GIGA_MAC_VER_37,
  130. RTL_GIGA_MAC_VER_38,
  131. RTL_GIGA_MAC_VER_39,
  132. RTL_GIGA_MAC_VER_40,
  133. RTL_GIGA_MAC_VER_41,
  134. RTL_GIGA_MAC_NONE = 0xff,
  135. };
  136. enum rtl_tx_desc_version {
  137. RTL_TD_0 = 0,
  138. RTL_TD_1 = 1,
  139. };
  140. #define JUMBO_1K ETH_DATA_LEN
  141. #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
  142. #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
  143. #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
  144. #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
  145. #define _R(NAME,TD,FW,SZ,B) { \
  146. .name = NAME, \
  147. .txd_version = TD, \
  148. .fw_name = FW, \
  149. .jumbo_max = SZ, \
  150. .jumbo_tx_csum = B \
  151. }
  152. static const struct {
  153. const char *name;
  154. enum rtl_tx_desc_version txd_version;
  155. const char *fw_name;
  156. u16 jumbo_max;
  157. bool jumbo_tx_csum;
  158. } rtl_chip_infos[] = {
  159. /* PCI devices. */
  160. [RTL_GIGA_MAC_VER_01] =
  161. _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
  162. [RTL_GIGA_MAC_VER_02] =
  163. _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
  164. [RTL_GIGA_MAC_VER_03] =
  165. _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
  166. [RTL_GIGA_MAC_VER_04] =
  167. _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
  168. [RTL_GIGA_MAC_VER_05] =
  169. _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
  170. [RTL_GIGA_MAC_VER_06] =
  171. _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
  172. /* PCI-E devices. */
  173. [RTL_GIGA_MAC_VER_07] =
  174. _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
  175. [RTL_GIGA_MAC_VER_08] =
  176. _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
  177. [RTL_GIGA_MAC_VER_09] =
  178. _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
  179. [RTL_GIGA_MAC_VER_10] =
  180. _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
  181. [RTL_GIGA_MAC_VER_11] =
  182. _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
  183. [RTL_GIGA_MAC_VER_12] =
  184. _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
  185. [RTL_GIGA_MAC_VER_13] =
  186. _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
  187. [RTL_GIGA_MAC_VER_14] =
  188. _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
  189. [RTL_GIGA_MAC_VER_15] =
  190. _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
  191. [RTL_GIGA_MAC_VER_16] =
  192. _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
  193. [RTL_GIGA_MAC_VER_17] =
  194. _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
  195. [RTL_GIGA_MAC_VER_18] =
  196. _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
  197. [RTL_GIGA_MAC_VER_19] =
  198. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  199. [RTL_GIGA_MAC_VER_20] =
  200. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  201. [RTL_GIGA_MAC_VER_21] =
  202. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  203. [RTL_GIGA_MAC_VER_22] =
  204. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  205. [RTL_GIGA_MAC_VER_23] =
  206. _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
  207. [RTL_GIGA_MAC_VER_24] =
  208. _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
  209. [RTL_GIGA_MAC_VER_25] =
  210. _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
  211. JUMBO_9K, false),
  212. [RTL_GIGA_MAC_VER_26] =
  213. _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
  214. JUMBO_9K, false),
  215. [RTL_GIGA_MAC_VER_27] =
  216. _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
  217. [RTL_GIGA_MAC_VER_28] =
  218. _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
  219. [RTL_GIGA_MAC_VER_29] =
  220. _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
  221. JUMBO_1K, true),
  222. [RTL_GIGA_MAC_VER_30] =
  223. _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
  224. JUMBO_1K, true),
  225. [RTL_GIGA_MAC_VER_31] =
  226. _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
  227. [RTL_GIGA_MAC_VER_32] =
  228. _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
  229. JUMBO_9K, false),
  230. [RTL_GIGA_MAC_VER_33] =
  231. _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
  232. JUMBO_9K, false),
  233. [RTL_GIGA_MAC_VER_34] =
  234. _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
  235. JUMBO_9K, false),
  236. [RTL_GIGA_MAC_VER_35] =
  237. _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
  238. JUMBO_9K, false),
  239. [RTL_GIGA_MAC_VER_36] =
  240. _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
  241. JUMBO_9K, false),
  242. [RTL_GIGA_MAC_VER_37] =
  243. _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
  244. JUMBO_1K, true),
  245. [RTL_GIGA_MAC_VER_38] =
  246. _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
  247. JUMBO_9K, false),
  248. [RTL_GIGA_MAC_VER_39] =
  249. _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
  250. JUMBO_1K, true),
  251. [RTL_GIGA_MAC_VER_40] =
  252. _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1,
  253. JUMBO_9K, false),
  254. [RTL_GIGA_MAC_VER_41] =
  255. _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
  256. };
  257. #undef _R
  258. enum cfg_version {
  259. RTL_CFG_0 = 0x00,
  260. RTL_CFG_1,
  261. RTL_CFG_2
  262. };
  263. static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
  264. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
  265. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
  266. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
  267. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
  268. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
  269. { PCI_VENDOR_ID_DLINK, 0x4300,
  270. PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
  271. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
  272. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
  273. { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
  274. { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
  275. { PCI_VENDOR_ID_LINKSYS, 0x1032,
  276. PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
  277. { 0x0001, 0x8168,
  278. PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
  279. {0,},
  280. };
  281. MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
  282. static int rx_buf_sz = 16383;
  283. static int use_dac;
  284. static struct {
  285. u32 msg_enable;
  286. } debug = { -1 };
  287. enum rtl_registers {
  288. MAC0 = 0, /* Ethernet hardware address. */
  289. MAC4 = 4,
  290. MAR0 = 8, /* Multicast filter. */
  291. CounterAddrLow = 0x10,
  292. CounterAddrHigh = 0x14,
  293. TxDescStartAddrLow = 0x20,
  294. TxDescStartAddrHigh = 0x24,
  295. TxHDescStartAddrLow = 0x28,
  296. TxHDescStartAddrHigh = 0x2c,
  297. FLASH = 0x30,
  298. ERSR = 0x36,
  299. ChipCmd = 0x37,
  300. TxPoll = 0x38,
  301. IntrMask = 0x3c,
  302. IntrStatus = 0x3e,
  303. TxConfig = 0x40,
  304. #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
  305. #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
  306. RxConfig = 0x44,
  307. #define RX128_INT_EN (1 << 15) /* 8111c and later */
  308. #define RX_MULTI_EN (1 << 14) /* 8111c only */
  309. #define RXCFG_FIFO_SHIFT 13
  310. /* No threshold before first PCI xfer */
  311. #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
  312. #define RXCFG_DMA_SHIFT 8
  313. /* Unlimited maximum PCI burst. */
  314. #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
  315. RxMissed = 0x4c,
  316. Cfg9346 = 0x50,
  317. Config0 = 0x51,
  318. Config1 = 0x52,
  319. Config2 = 0x53,
  320. #define PME_SIGNAL (1 << 5) /* 8168c and later */
  321. Config3 = 0x54,
  322. Config4 = 0x55,
  323. Config5 = 0x56,
  324. MultiIntr = 0x5c,
  325. PHYAR = 0x60,
  326. PHYstatus = 0x6c,
  327. RxMaxSize = 0xda,
  328. CPlusCmd = 0xe0,
  329. IntrMitigate = 0xe2,
  330. RxDescAddrLow = 0xe4,
  331. RxDescAddrHigh = 0xe8,
  332. EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
  333. #define NoEarlyTx 0x3f /* Max value : no early transmit. */
  334. MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
  335. #define TxPacketMax (8064 >> 7)
  336. #define EarlySize 0x27
  337. FuncEvent = 0xf0,
  338. FuncEventMask = 0xf4,
  339. FuncPresetState = 0xf8,
  340. FuncForceEvent = 0xfc,
  341. };
  342. enum rtl8110_registers {
  343. TBICSR = 0x64,
  344. TBI_ANAR = 0x68,
  345. TBI_LPAR = 0x6a,
  346. };
  347. enum rtl8168_8101_registers {
  348. CSIDR = 0x64,
  349. CSIAR = 0x68,
  350. #define CSIAR_FLAG 0x80000000
  351. #define CSIAR_WRITE_CMD 0x80000000
  352. #define CSIAR_BYTE_ENABLE 0x0f
  353. #define CSIAR_BYTE_ENABLE_SHIFT 12
  354. #define CSIAR_ADDR_MASK 0x0fff
  355. #define CSIAR_FUNC_CARD 0x00000000
  356. #define CSIAR_FUNC_SDIO 0x00010000
  357. #define CSIAR_FUNC_NIC 0x00020000
  358. PMCH = 0x6f,
  359. EPHYAR = 0x80,
  360. #define EPHYAR_FLAG 0x80000000
  361. #define EPHYAR_WRITE_CMD 0x80000000
  362. #define EPHYAR_REG_MASK 0x1f
  363. #define EPHYAR_REG_SHIFT 16
  364. #define EPHYAR_DATA_MASK 0xffff
  365. DLLPR = 0xd0,
  366. #define PFM_EN (1 << 6)
  367. DBG_REG = 0xd1,
  368. #define FIX_NAK_1 (1 << 4)
  369. #define FIX_NAK_2 (1 << 3)
  370. TWSI = 0xd2,
  371. MCU = 0xd3,
  372. #define NOW_IS_OOB (1 << 7)
  373. #define TX_EMPTY (1 << 5)
  374. #define RX_EMPTY (1 << 4)
  375. #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
  376. #define EN_NDP (1 << 3)
  377. #define EN_OOB_RESET (1 << 2)
  378. #define LINK_LIST_RDY (1 << 1)
  379. EFUSEAR = 0xdc,
  380. #define EFUSEAR_FLAG 0x80000000
  381. #define EFUSEAR_WRITE_CMD 0x80000000
  382. #define EFUSEAR_READ_CMD 0x00000000
  383. #define EFUSEAR_REG_MASK 0x03ff
  384. #define EFUSEAR_REG_SHIFT 8
  385. #define EFUSEAR_DATA_MASK 0xff
  386. };
  387. enum rtl8168_registers {
  388. LED_FREQ = 0x1a,
  389. EEE_LED = 0x1b,
  390. ERIDR = 0x70,
  391. ERIAR = 0x74,
  392. #define ERIAR_FLAG 0x80000000
  393. #define ERIAR_WRITE_CMD 0x80000000
  394. #define ERIAR_READ_CMD 0x00000000
  395. #define ERIAR_ADDR_BYTE_ALIGN 4
  396. #define ERIAR_TYPE_SHIFT 16
  397. #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
  398. #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
  399. #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
  400. #define ERIAR_MASK_SHIFT 12
  401. #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
  402. #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
  403. #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
  404. #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
  405. EPHY_RXER_NUM = 0x7c,
  406. OCPDR = 0xb0, /* OCP GPHY access */
  407. #define OCPDR_WRITE_CMD 0x80000000
  408. #define OCPDR_READ_CMD 0x00000000
  409. #define OCPDR_REG_MASK 0x7f
  410. #define OCPDR_GPHY_REG_SHIFT 16
  411. #define OCPDR_DATA_MASK 0xffff
  412. OCPAR = 0xb4,
  413. #define OCPAR_FLAG 0x80000000
  414. #define OCPAR_GPHY_WRITE_CMD 0x8000f060
  415. #define OCPAR_GPHY_READ_CMD 0x0000f060
  416. GPHY_OCP = 0xb8,
  417. RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
  418. MISC = 0xf0, /* 8168e only. */
  419. #define TXPLA_RST (1 << 29)
  420. #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
  421. #define PWM_EN (1 << 22)
  422. #define RXDV_GATED_EN (1 << 19)
  423. #define EARLY_TALLY_EN (1 << 16)
  424. };
  425. enum rtl_register_content {
  426. /* InterruptStatusBits */
  427. SYSErr = 0x8000,
  428. PCSTimeout = 0x4000,
  429. SWInt = 0x0100,
  430. TxDescUnavail = 0x0080,
  431. RxFIFOOver = 0x0040,
  432. LinkChg = 0x0020,
  433. RxOverflow = 0x0010,
  434. TxErr = 0x0008,
  435. TxOK = 0x0004,
  436. RxErr = 0x0002,
  437. RxOK = 0x0001,
  438. /* RxStatusDesc */
  439. RxBOVF = (1 << 24),
  440. RxFOVF = (1 << 23),
  441. RxRWT = (1 << 22),
  442. RxRES = (1 << 21),
  443. RxRUNT = (1 << 20),
  444. RxCRC = (1 << 19),
  445. /* ChipCmdBits */
  446. StopReq = 0x80,
  447. CmdReset = 0x10,
  448. CmdRxEnb = 0x08,
  449. CmdTxEnb = 0x04,
  450. RxBufEmpty = 0x01,
  451. /* TXPoll register p.5 */
  452. HPQ = 0x80, /* Poll cmd on the high prio queue */
  453. NPQ = 0x40, /* Poll cmd on the low prio queue */
  454. FSWInt = 0x01, /* Forced software interrupt */
  455. /* Cfg9346Bits */
  456. Cfg9346_Lock = 0x00,
  457. Cfg9346_Unlock = 0xc0,
  458. /* rx_mode_bits */
  459. AcceptErr = 0x20,
  460. AcceptRunt = 0x10,
  461. AcceptBroadcast = 0x08,
  462. AcceptMulticast = 0x04,
  463. AcceptMyPhys = 0x02,
  464. AcceptAllPhys = 0x01,
  465. #define RX_CONFIG_ACCEPT_MASK 0x3f
  466. /* TxConfigBits */
  467. TxInterFrameGapShift = 24,
  468. TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
  469. /* Config1 register p.24 */
  470. LEDS1 = (1 << 7),
  471. LEDS0 = (1 << 6),
  472. Speed_down = (1 << 4),
  473. MEMMAP = (1 << 3),
  474. IOMAP = (1 << 2),
  475. VPD = (1 << 1),
  476. PMEnable = (1 << 0), /* Power Management Enable */
  477. /* Config2 register p. 25 */
  478. MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
  479. PCI_Clock_66MHz = 0x01,
  480. PCI_Clock_33MHz = 0x00,
  481. /* Config3 register p.25 */
  482. MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
  483. LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
  484. Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
  485. Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
  486. /* Config4 register */
  487. Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
  488. /* Config5 register p.27 */
  489. BWF = (1 << 6), /* Accept Broadcast wakeup frame */
  490. MWF = (1 << 5), /* Accept Multicast wakeup frame */
  491. UWF = (1 << 4), /* Accept Unicast wakeup frame */
  492. Spi_en = (1 << 3),
  493. LanWake = (1 << 1), /* LanWake enable/disable */
  494. PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
  495. /* TBICSR p.28 */
  496. TBIReset = 0x80000000,
  497. TBILoopback = 0x40000000,
  498. TBINwEnable = 0x20000000,
  499. TBINwRestart = 0x10000000,
  500. TBILinkOk = 0x02000000,
  501. TBINwComplete = 0x01000000,
  502. /* CPlusCmd p.31 */
  503. EnableBist = (1 << 15), // 8168 8101
  504. Mac_dbgo_oe = (1 << 14), // 8168 8101
  505. Normal_mode = (1 << 13), // unused
  506. Force_half_dup = (1 << 12), // 8168 8101
  507. Force_rxflow_en = (1 << 11), // 8168 8101
  508. Force_txflow_en = (1 << 10), // 8168 8101
  509. Cxpl_dbg_sel = (1 << 9), // 8168 8101
  510. ASF = (1 << 8), // 8168 8101
  511. PktCntrDisable = (1 << 7), // 8168 8101
  512. Mac_dbgo_sel = 0x001c, // 8168
  513. RxVlan = (1 << 6),
  514. RxChkSum = (1 << 5),
  515. PCIDAC = (1 << 4),
  516. PCIMulRW = (1 << 3),
  517. INTT_0 = 0x0000, // 8168
  518. INTT_1 = 0x0001, // 8168
  519. INTT_2 = 0x0002, // 8168
  520. INTT_3 = 0x0003, // 8168
  521. /* rtl8169_PHYstatus */
  522. TBI_Enable = 0x80,
  523. TxFlowCtrl = 0x40,
  524. RxFlowCtrl = 0x20,
  525. _1000bpsF = 0x10,
  526. _100bps = 0x08,
  527. _10bps = 0x04,
  528. LinkStatus = 0x02,
  529. FullDup = 0x01,
  530. /* _TBICSRBit */
  531. TBILinkOK = 0x02000000,
  532. /* DumpCounterCommand */
  533. CounterDump = 0x8,
  534. };
  535. enum rtl_desc_bit {
  536. /* First doubleword. */
  537. DescOwn = (1 << 31), /* Descriptor is owned by NIC */
  538. RingEnd = (1 << 30), /* End of descriptor ring */
  539. FirstFrag = (1 << 29), /* First segment of a packet */
  540. LastFrag = (1 << 28), /* Final segment of a packet */
  541. };
  542. /* Generic case. */
  543. enum rtl_tx_desc_bit {
  544. /* First doubleword. */
  545. TD_LSO = (1 << 27), /* Large Send Offload */
  546. #define TD_MSS_MAX 0x07ffu /* MSS value */
  547. /* Second doubleword. */
  548. TxVlanTag = (1 << 17), /* Add VLAN tag */
  549. };
  550. /* 8169, 8168b and 810x except 8102e. */
  551. enum rtl_tx_desc_bit_0 {
  552. /* First doubleword. */
  553. #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
  554. TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
  555. TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
  556. TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
  557. };
  558. /* 8102e, 8168c and beyond. */
  559. enum rtl_tx_desc_bit_1 {
  560. /* Second doubleword. */
  561. #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
  562. TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
  563. TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
  564. TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
  565. };
  566. static const struct rtl_tx_desc_info {
  567. struct {
  568. u32 udp;
  569. u32 tcp;
  570. } checksum;
  571. u16 mss_shift;
  572. u16 opts_offset;
  573. } tx_desc_info [] = {
  574. [RTL_TD_0] = {
  575. .checksum = {
  576. .udp = TD0_IP_CS | TD0_UDP_CS,
  577. .tcp = TD0_IP_CS | TD0_TCP_CS
  578. },
  579. .mss_shift = TD0_MSS_SHIFT,
  580. .opts_offset = 0
  581. },
  582. [RTL_TD_1] = {
  583. .checksum = {
  584. .udp = TD1_IP_CS | TD1_UDP_CS,
  585. .tcp = TD1_IP_CS | TD1_TCP_CS
  586. },
  587. .mss_shift = TD1_MSS_SHIFT,
  588. .opts_offset = 1
  589. }
  590. };
  591. enum rtl_rx_desc_bit {
  592. /* Rx private */
  593. PID1 = (1 << 18), /* Protocol ID bit 1/2 */
  594. PID0 = (1 << 17), /* Protocol ID bit 2/2 */
  595. #define RxProtoUDP (PID1)
  596. #define RxProtoTCP (PID0)
  597. #define RxProtoIP (PID1 | PID0)
  598. #define RxProtoMask RxProtoIP
  599. IPFail = (1 << 16), /* IP checksum failed */
  600. UDPFail = (1 << 15), /* UDP/IP checksum failed */
  601. TCPFail = (1 << 14), /* TCP/IP checksum failed */
  602. RxVlanTag = (1 << 16), /* VLAN tag available */
  603. };
  604. #define RsvdMask 0x3fffc000
  605. struct TxDesc {
  606. __le32 opts1;
  607. __le32 opts2;
  608. __le64 addr;
  609. };
  610. struct RxDesc {
  611. __le32 opts1;
  612. __le32 opts2;
  613. __le64 addr;
  614. };
  615. struct ring_info {
  616. struct sk_buff *skb;
  617. u32 len;
  618. u8 __pad[sizeof(void *) - sizeof(u32)];
  619. };
  620. enum features {
  621. RTL_FEATURE_WOL = (1 << 0),
  622. RTL_FEATURE_MSI = (1 << 1),
  623. RTL_FEATURE_GMII = (1 << 2),
  624. };
  625. struct rtl8169_counters {
  626. __le64 tx_packets;
  627. __le64 rx_packets;
  628. __le64 tx_errors;
  629. __le32 rx_errors;
  630. __le16 rx_missed;
  631. __le16 align_errors;
  632. __le32 tx_one_collision;
  633. __le32 tx_multi_collision;
  634. __le64 rx_unicast;
  635. __le64 rx_broadcast;
  636. __le32 rx_multicast;
  637. __le16 tx_aborted;
  638. __le16 tx_underun;
  639. };
  640. enum rtl_flag {
  641. RTL_FLAG_TASK_ENABLED,
  642. RTL_FLAG_TASK_SLOW_PENDING,
  643. RTL_FLAG_TASK_RESET_PENDING,
  644. RTL_FLAG_TASK_PHY_PENDING,
  645. RTL_FLAG_MAX
  646. };
  647. struct rtl8169_stats {
  648. u64 packets;
  649. u64 bytes;
  650. struct u64_stats_sync syncp;
  651. };
  652. struct rtl8169_private {
  653. void __iomem *mmio_addr; /* memory map physical address */
  654. struct pci_dev *pci_dev;
  655. struct net_device *dev;
  656. struct napi_struct napi;
  657. u32 msg_enable;
  658. u16 txd_version;
  659. u16 mac_version;
  660. u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
  661. u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
  662. u32 dirty_rx;
  663. u32 dirty_tx;
  664. struct rtl8169_stats rx_stats;
  665. struct rtl8169_stats tx_stats;
  666. struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
  667. struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
  668. dma_addr_t TxPhyAddr;
  669. dma_addr_t RxPhyAddr;
  670. void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
  671. struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
  672. struct timer_list timer;
  673. u16 cp_cmd;
  674. u16 event_slow;
  675. struct mdio_ops {
  676. void (*write)(struct rtl8169_private *, int, int);
  677. int (*read)(struct rtl8169_private *, int);
  678. } mdio_ops;
  679. struct pll_power_ops {
  680. void (*down)(struct rtl8169_private *);
  681. void (*up)(struct rtl8169_private *);
  682. } pll_power_ops;
  683. struct jumbo_ops {
  684. void (*enable)(struct rtl8169_private *);
  685. void (*disable)(struct rtl8169_private *);
  686. } jumbo_ops;
  687. struct csi_ops {
  688. void (*write)(struct rtl8169_private *, int, int);
  689. u32 (*read)(struct rtl8169_private *, int);
  690. } csi_ops;
  691. int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
  692. int (*get_settings)(struct net_device *, struct ethtool_cmd *);
  693. void (*phy_reset_enable)(struct rtl8169_private *tp);
  694. void (*hw_start)(struct net_device *);
  695. unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
  696. unsigned int (*link_ok)(void __iomem *);
  697. int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
  698. struct {
  699. DECLARE_BITMAP(flags, RTL_FLAG_MAX);
  700. struct mutex mutex;
  701. struct work_struct work;
  702. } wk;
  703. unsigned features;
  704. struct mii_if_info mii;
  705. struct rtl8169_counters counters;
  706. u32 saved_wolopts;
  707. u32 opts1_mask;
  708. struct rtl_fw {
  709. const struct firmware *fw;
  710. #define RTL_VER_SIZE 32
  711. char version[RTL_VER_SIZE];
  712. struct rtl_fw_phy_action {
  713. __le32 *code;
  714. size_t size;
  715. } phy_action;
  716. } *rtl_fw;
  717. #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
  718. u32 ocp_base;
  719. };
  720. MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
  721. MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
  722. module_param(use_dac, int, 0);
  723. MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
  724. module_param_named(debug, debug.msg_enable, int, 0);
  725. MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
  726. MODULE_LICENSE("GPL");
  727. MODULE_VERSION(RTL8169_VERSION);
  728. MODULE_FIRMWARE(FIRMWARE_8168D_1);
  729. MODULE_FIRMWARE(FIRMWARE_8168D_2);
  730. MODULE_FIRMWARE(FIRMWARE_8168E_1);
  731. MODULE_FIRMWARE(FIRMWARE_8168E_2);
  732. MODULE_FIRMWARE(FIRMWARE_8168E_3);
  733. MODULE_FIRMWARE(FIRMWARE_8105E_1);
  734. MODULE_FIRMWARE(FIRMWARE_8168F_1);
  735. MODULE_FIRMWARE(FIRMWARE_8168F_2);
  736. MODULE_FIRMWARE(FIRMWARE_8402_1);
  737. MODULE_FIRMWARE(FIRMWARE_8411_1);
  738. MODULE_FIRMWARE(FIRMWARE_8106E_1);
  739. MODULE_FIRMWARE(FIRMWARE_8168G_1);
  740. static void rtl_lock_work(struct rtl8169_private *tp)
  741. {
  742. mutex_lock(&tp->wk.mutex);
  743. }
  744. static void rtl_unlock_work(struct rtl8169_private *tp)
  745. {
  746. mutex_unlock(&tp->wk.mutex);
  747. }
  748. static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
  749. {
  750. pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
  751. PCI_EXP_DEVCTL_READRQ, force);
  752. }
  753. struct rtl_cond {
  754. bool (*check)(struct rtl8169_private *);
  755. const char *msg;
  756. };
  757. static void rtl_udelay(unsigned int d)
  758. {
  759. udelay(d);
  760. }
  761. static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
  762. void (*delay)(unsigned int), unsigned int d, int n,
  763. bool high)
  764. {
  765. int i;
  766. for (i = 0; i < n; i++) {
  767. delay(d);
  768. if (c->check(tp) == high)
  769. return true;
  770. }
  771. netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
  772. c->msg, !high, n, d);
  773. return false;
  774. }
  775. static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
  776. const struct rtl_cond *c,
  777. unsigned int d, int n)
  778. {
  779. return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
  780. }
  781. static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
  782. const struct rtl_cond *c,
  783. unsigned int d, int n)
  784. {
  785. return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
  786. }
  787. static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
  788. const struct rtl_cond *c,
  789. unsigned int d, int n)
  790. {
  791. return rtl_loop_wait(tp, c, msleep, d, n, true);
  792. }
  793. static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
  794. const struct rtl_cond *c,
  795. unsigned int d, int n)
  796. {
  797. return rtl_loop_wait(tp, c, msleep, d, n, false);
  798. }
  799. #define DECLARE_RTL_COND(name) \
  800. static bool name ## _check(struct rtl8169_private *); \
  801. \
  802. static const struct rtl_cond name = { \
  803. .check = name ## _check, \
  804. .msg = #name \
  805. }; \
  806. \
  807. static bool name ## _check(struct rtl8169_private *tp)
  808. DECLARE_RTL_COND(rtl_ocpar_cond)
  809. {
  810. void __iomem *ioaddr = tp->mmio_addr;
  811. return RTL_R32(OCPAR) & OCPAR_FLAG;
  812. }
  813. static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
  814. {
  815. void __iomem *ioaddr = tp->mmio_addr;
  816. RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
  817. return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
  818. RTL_R32(OCPDR) : ~0;
  819. }
  820. static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
  821. {
  822. void __iomem *ioaddr = tp->mmio_addr;
  823. RTL_W32(OCPDR, data);
  824. RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
  825. rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
  826. }
  827. DECLARE_RTL_COND(rtl_eriar_cond)
  828. {
  829. void __iomem *ioaddr = tp->mmio_addr;
  830. return RTL_R32(ERIAR) & ERIAR_FLAG;
  831. }
  832. static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
  833. {
  834. void __iomem *ioaddr = tp->mmio_addr;
  835. RTL_W8(ERIDR, cmd);
  836. RTL_W32(ERIAR, 0x800010e8);
  837. msleep(2);
  838. if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
  839. return;
  840. ocp_write(tp, 0x1, 0x30, 0x00000001);
  841. }
  842. #define OOB_CMD_RESET 0x00
  843. #define OOB_CMD_DRIVER_START 0x05
  844. #define OOB_CMD_DRIVER_STOP 0x06
  845. static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
  846. {
  847. return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
  848. }
  849. DECLARE_RTL_COND(rtl_ocp_read_cond)
  850. {
  851. u16 reg;
  852. reg = rtl8168_get_ocp_reg(tp);
  853. return ocp_read(tp, 0x0f, reg) & 0x00000800;
  854. }
  855. static void rtl8168_driver_start(struct rtl8169_private *tp)
  856. {
  857. rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
  858. rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
  859. }
  860. static void rtl8168_driver_stop(struct rtl8169_private *tp)
  861. {
  862. rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
  863. rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
  864. }
  865. static int r8168dp_check_dash(struct rtl8169_private *tp)
  866. {
  867. u16 reg = rtl8168_get_ocp_reg(tp);
  868. return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
  869. }
  870. static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
  871. {
  872. if (reg & 0xffff0001) {
  873. netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
  874. return true;
  875. }
  876. return false;
  877. }
  878. DECLARE_RTL_COND(rtl_ocp_gphy_cond)
  879. {
  880. void __iomem *ioaddr = tp->mmio_addr;
  881. return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
  882. }
  883. static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
  884. {
  885. void __iomem *ioaddr = tp->mmio_addr;
  886. if (rtl_ocp_reg_failure(tp, reg))
  887. return;
  888. RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
  889. rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
  890. }
  891. static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
  892. {
  893. void __iomem *ioaddr = tp->mmio_addr;
  894. if (rtl_ocp_reg_failure(tp, reg))
  895. return 0;
  896. RTL_W32(GPHY_OCP, reg << 15);
  897. return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
  898. (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
  899. }
  900. static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
  901. {
  902. int val;
  903. val = r8168_phy_ocp_read(tp, reg);
  904. r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
  905. }
  906. static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
  907. {
  908. void __iomem *ioaddr = tp->mmio_addr;
  909. if (rtl_ocp_reg_failure(tp, reg))
  910. return;
  911. RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
  912. }
  913. static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
  914. {
  915. void __iomem *ioaddr = tp->mmio_addr;
  916. if (rtl_ocp_reg_failure(tp, reg))
  917. return 0;
  918. RTL_W32(OCPDR, reg << 15);
  919. return RTL_R32(OCPDR);
  920. }
  921. #define OCP_STD_PHY_BASE 0xa400
  922. static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
  923. {
  924. if (reg == 0x1f) {
  925. tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
  926. return;
  927. }
  928. if (tp->ocp_base != OCP_STD_PHY_BASE)
  929. reg -= 0x10;
  930. r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
  931. }
  932. static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
  933. {
  934. if (tp->ocp_base != OCP_STD_PHY_BASE)
  935. reg -= 0x10;
  936. return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
  937. }
  938. DECLARE_RTL_COND(rtl_phyar_cond)
  939. {
  940. void __iomem *ioaddr = tp->mmio_addr;
  941. return RTL_R32(PHYAR) & 0x80000000;
  942. }
  943. static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
  944. {
  945. void __iomem *ioaddr = tp->mmio_addr;
  946. RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
  947. rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
  948. /*
  949. * According to hardware specs a 20us delay is required after write
  950. * complete indication, but before sending next command.
  951. */
  952. udelay(20);
  953. }
  954. static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
  955. {
  956. void __iomem *ioaddr = tp->mmio_addr;
  957. int value;
  958. RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
  959. value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
  960. RTL_R32(PHYAR) & 0xffff : ~0;
  961. /*
  962. * According to hardware specs a 20us delay is required after read
  963. * complete indication, but before sending next command.
  964. */
  965. udelay(20);
  966. return value;
  967. }
  968. static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
  969. {
  970. void __iomem *ioaddr = tp->mmio_addr;
  971. RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
  972. RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
  973. RTL_W32(EPHY_RXER_NUM, 0);
  974. rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
  975. }
  976. static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
  977. {
  978. r8168dp_1_mdio_access(tp, reg,
  979. OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
  980. }
  981. static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
  982. {
  983. void __iomem *ioaddr = tp->mmio_addr;
  984. r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
  985. mdelay(1);
  986. RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
  987. RTL_W32(EPHY_RXER_NUM, 0);
  988. return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
  989. RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
  990. }
  991. #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
  992. static void r8168dp_2_mdio_start(void __iomem *ioaddr)
  993. {
  994. RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
  995. }
  996. static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
  997. {
  998. RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
  999. }
  1000. static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
  1001. {
  1002. void __iomem *ioaddr = tp->mmio_addr;
  1003. r8168dp_2_mdio_start(ioaddr);
  1004. r8169_mdio_write(tp, reg, value);
  1005. r8168dp_2_mdio_stop(ioaddr);
  1006. }
  1007. static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
  1008. {
  1009. void __iomem *ioaddr = tp->mmio_addr;
  1010. int value;
  1011. r8168dp_2_mdio_start(ioaddr);
  1012. value = r8169_mdio_read(tp, reg);
  1013. r8168dp_2_mdio_stop(ioaddr);
  1014. return value;
  1015. }
  1016. static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
  1017. {
  1018. tp->mdio_ops.write(tp, location, val);
  1019. }
  1020. static int rtl_readphy(struct rtl8169_private *tp, int location)
  1021. {
  1022. return tp->mdio_ops.read(tp, location);
  1023. }
  1024. static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
  1025. {
  1026. rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
  1027. }
  1028. static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
  1029. {
  1030. int val;
  1031. val = rtl_readphy(tp, reg_addr);
  1032. rtl_writephy(tp, reg_addr, (val | p) & ~m);
  1033. }
  1034. static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
  1035. int val)
  1036. {
  1037. struct rtl8169_private *tp = netdev_priv(dev);
  1038. rtl_writephy(tp, location, val);
  1039. }
  1040. static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
  1041. {
  1042. struct rtl8169_private *tp = netdev_priv(dev);
  1043. return rtl_readphy(tp, location);
  1044. }
  1045. DECLARE_RTL_COND(rtl_ephyar_cond)
  1046. {
  1047. void __iomem *ioaddr = tp->mmio_addr;
  1048. return RTL_R32(EPHYAR) & EPHYAR_FLAG;
  1049. }
  1050. static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
  1051. {
  1052. void __iomem *ioaddr = tp->mmio_addr;
  1053. RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
  1054. (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
  1055. rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
  1056. udelay(10);
  1057. }
  1058. static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
  1059. {
  1060. void __iomem *ioaddr = tp->mmio_addr;
  1061. RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
  1062. return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
  1063. RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
  1064. }
  1065. static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
  1066. u32 val, int type)
  1067. {
  1068. void __iomem *ioaddr = tp->mmio_addr;
  1069. BUG_ON((addr & 3) || (mask == 0));
  1070. RTL_W32(ERIDR, val);
  1071. RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
  1072. rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
  1073. }
  1074. static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
  1075. {
  1076. void __iomem *ioaddr = tp->mmio_addr;
  1077. RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
  1078. return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
  1079. RTL_R32(ERIDR) : ~0;
  1080. }
  1081. static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
  1082. u32 m, int type)
  1083. {
  1084. u32 val;
  1085. val = rtl_eri_read(tp, addr, type);
  1086. rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
  1087. }
  1088. struct exgmac_reg {
  1089. u16 addr;
  1090. u16 mask;
  1091. u32 val;
  1092. };
  1093. static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
  1094. const struct exgmac_reg *r, int len)
  1095. {
  1096. while (len-- > 0) {
  1097. rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
  1098. r++;
  1099. }
  1100. }
  1101. DECLARE_RTL_COND(rtl_efusear_cond)
  1102. {
  1103. void __iomem *ioaddr = tp->mmio_addr;
  1104. return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
  1105. }
  1106. static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
  1107. {
  1108. void __iomem *ioaddr = tp->mmio_addr;
  1109. RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
  1110. return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
  1111. RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
  1112. }
  1113. static u16 rtl_get_events(struct rtl8169_private *tp)
  1114. {
  1115. void __iomem *ioaddr = tp->mmio_addr;
  1116. return RTL_R16(IntrStatus);
  1117. }
  1118. static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
  1119. {
  1120. void __iomem *ioaddr = tp->mmio_addr;
  1121. RTL_W16(IntrStatus, bits);
  1122. mmiowb();
  1123. }
  1124. static void rtl_irq_disable(struct rtl8169_private *tp)
  1125. {
  1126. void __iomem *ioaddr = tp->mmio_addr;
  1127. RTL_W16(IntrMask, 0);
  1128. mmiowb();
  1129. }
  1130. static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
  1131. {
  1132. void __iomem *ioaddr = tp->mmio_addr;
  1133. RTL_W16(IntrMask, bits);
  1134. }
  1135. #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
  1136. #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
  1137. #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
  1138. static void rtl_irq_enable_all(struct rtl8169_private *tp)
  1139. {
  1140. rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
  1141. }
  1142. static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
  1143. {
  1144. void __iomem *ioaddr = tp->mmio_addr;
  1145. rtl_irq_disable(tp);
  1146. rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
  1147. RTL_R8(ChipCmd);
  1148. }
  1149. static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
  1150. {
  1151. void __iomem *ioaddr = tp->mmio_addr;
  1152. return RTL_R32(TBICSR) & TBIReset;
  1153. }
  1154. static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
  1155. {
  1156. return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
  1157. }
  1158. static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
  1159. {
  1160. return RTL_R32(TBICSR) & TBILinkOk;
  1161. }
  1162. static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
  1163. {
  1164. return RTL_R8(PHYstatus) & LinkStatus;
  1165. }
  1166. static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
  1167. {
  1168. void __iomem *ioaddr = tp->mmio_addr;
  1169. RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
  1170. }
  1171. static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
  1172. {
  1173. unsigned int val;
  1174. val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
  1175. rtl_writephy(tp, MII_BMCR, val & 0xffff);
  1176. }
  1177. static void rtl_link_chg_patch(struct rtl8169_private *tp)
  1178. {
  1179. void __iomem *ioaddr = tp->mmio_addr;
  1180. struct net_device *dev = tp->dev;
  1181. if (!netif_running(dev))
  1182. return;
  1183. if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
  1184. tp->mac_version == RTL_GIGA_MAC_VER_38) {
  1185. if (RTL_R8(PHYstatus) & _1000bpsF) {
  1186. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
  1187. ERIAR_EXGMAC);
  1188. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
  1189. ERIAR_EXGMAC);
  1190. } else if (RTL_R8(PHYstatus) & _100bps) {
  1191. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
  1192. ERIAR_EXGMAC);
  1193. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
  1194. ERIAR_EXGMAC);
  1195. } else {
  1196. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
  1197. ERIAR_EXGMAC);
  1198. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
  1199. ERIAR_EXGMAC);
  1200. }
  1201. /* Reset packet filter */
  1202. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
  1203. ERIAR_EXGMAC);
  1204. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
  1205. ERIAR_EXGMAC);
  1206. } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
  1207. tp->mac_version == RTL_GIGA_MAC_VER_36) {
  1208. if (RTL_R8(PHYstatus) & _1000bpsF) {
  1209. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
  1210. ERIAR_EXGMAC);
  1211. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
  1212. ERIAR_EXGMAC);
  1213. } else {
  1214. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
  1215. ERIAR_EXGMAC);
  1216. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
  1217. ERIAR_EXGMAC);
  1218. }
  1219. } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
  1220. if (RTL_R8(PHYstatus) & _10bps) {
  1221. rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
  1222. ERIAR_EXGMAC);
  1223. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
  1224. ERIAR_EXGMAC);
  1225. } else {
  1226. rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
  1227. ERIAR_EXGMAC);
  1228. }
  1229. }
  1230. }
  1231. static void __rtl8169_check_link_status(struct net_device *dev,
  1232. struct rtl8169_private *tp,
  1233. void __iomem *ioaddr, bool pm)
  1234. {
  1235. if (tp->link_ok(ioaddr)) {
  1236. rtl_link_chg_patch(tp);
  1237. /* This is to cancel a scheduled suspend if there's one. */
  1238. if (pm)
  1239. pm_request_resume(&tp->pci_dev->dev);
  1240. netif_carrier_on(dev);
  1241. if (net_ratelimit())
  1242. netif_info(tp, ifup, dev, "link up\n");
  1243. } else {
  1244. netif_carrier_off(dev);
  1245. netif_info(tp, ifdown, dev, "link down\n");
  1246. if (pm)
  1247. pm_schedule_suspend(&tp->pci_dev->dev, 5000);
  1248. }
  1249. }
  1250. static void rtl8169_check_link_status(struct net_device *dev,
  1251. struct rtl8169_private *tp,
  1252. void __iomem *ioaddr)
  1253. {
  1254. __rtl8169_check_link_status(dev, tp, ioaddr, false);
  1255. }
  1256. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1257. static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
  1258. {
  1259. void __iomem *ioaddr = tp->mmio_addr;
  1260. u8 options;
  1261. u32 wolopts = 0;
  1262. options = RTL_R8(Config1);
  1263. if (!(options & PMEnable))
  1264. return 0;
  1265. options = RTL_R8(Config3);
  1266. if (options & LinkUp)
  1267. wolopts |= WAKE_PHY;
  1268. if (options & MagicPacket)
  1269. wolopts |= WAKE_MAGIC;
  1270. options = RTL_R8(Config5);
  1271. if (options & UWF)
  1272. wolopts |= WAKE_UCAST;
  1273. if (options & BWF)
  1274. wolopts |= WAKE_BCAST;
  1275. if (options & MWF)
  1276. wolopts |= WAKE_MCAST;
  1277. return wolopts;
  1278. }
  1279. static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1280. {
  1281. struct rtl8169_private *tp = netdev_priv(dev);
  1282. rtl_lock_work(tp);
  1283. wol->supported = WAKE_ANY;
  1284. wol->wolopts = __rtl8169_get_wol(tp);
  1285. rtl_unlock_work(tp);
  1286. }
  1287. static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
  1288. {
  1289. void __iomem *ioaddr = tp->mmio_addr;
  1290. unsigned int i;
  1291. static const struct {
  1292. u32 opt;
  1293. u16 reg;
  1294. u8 mask;
  1295. } cfg[] = {
  1296. { WAKE_PHY, Config3, LinkUp },
  1297. { WAKE_MAGIC, Config3, MagicPacket },
  1298. { WAKE_UCAST, Config5, UWF },
  1299. { WAKE_BCAST, Config5, BWF },
  1300. { WAKE_MCAST, Config5, MWF },
  1301. { WAKE_ANY, Config5, LanWake }
  1302. };
  1303. u8 options;
  1304. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1305. for (i = 0; i < ARRAY_SIZE(cfg); i++) {
  1306. options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
  1307. if (wolopts & cfg[i].opt)
  1308. options |= cfg[i].mask;
  1309. RTL_W8(cfg[i].reg, options);
  1310. }
  1311. switch (tp->mac_version) {
  1312. case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
  1313. options = RTL_R8(Config1) & ~PMEnable;
  1314. if (wolopts)
  1315. options |= PMEnable;
  1316. RTL_W8(Config1, options);
  1317. break;
  1318. default:
  1319. options = RTL_R8(Config2) & ~PME_SIGNAL;
  1320. if (wolopts)
  1321. options |= PME_SIGNAL;
  1322. RTL_W8(Config2, options);
  1323. break;
  1324. }
  1325. RTL_W8(Cfg9346, Cfg9346_Lock);
  1326. }
  1327. static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1328. {
  1329. struct rtl8169_private *tp = netdev_priv(dev);
  1330. rtl_lock_work(tp);
  1331. if (wol->wolopts)
  1332. tp->features |= RTL_FEATURE_WOL;
  1333. else
  1334. tp->features &= ~RTL_FEATURE_WOL;
  1335. __rtl8169_set_wol(tp, wol->wolopts);
  1336. rtl_unlock_work(tp);
  1337. device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
  1338. return 0;
  1339. }
  1340. static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
  1341. {
  1342. return rtl_chip_infos[tp->mac_version].fw_name;
  1343. }
  1344. static void rtl8169_get_drvinfo(struct net_device *dev,
  1345. struct ethtool_drvinfo *info)
  1346. {
  1347. struct rtl8169_private *tp = netdev_priv(dev);
  1348. struct rtl_fw *rtl_fw = tp->rtl_fw;
  1349. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  1350. strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
  1351. strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
  1352. BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
  1353. if (!IS_ERR_OR_NULL(rtl_fw))
  1354. strlcpy(info->fw_version, rtl_fw->version,
  1355. sizeof(info->fw_version));
  1356. }
  1357. static int rtl8169_get_regs_len(struct net_device *dev)
  1358. {
  1359. return R8169_REGS_SIZE;
  1360. }
  1361. static int rtl8169_set_speed_tbi(struct net_device *dev,
  1362. u8 autoneg, u16 speed, u8 duplex, u32 ignored)
  1363. {
  1364. struct rtl8169_private *tp = netdev_priv(dev);
  1365. void __iomem *ioaddr = tp->mmio_addr;
  1366. int ret = 0;
  1367. u32 reg;
  1368. reg = RTL_R32(TBICSR);
  1369. if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
  1370. (duplex == DUPLEX_FULL)) {
  1371. RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
  1372. } else if (autoneg == AUTONEG_ENABLE)
  1373. RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
  1374. else {
  1375. netif_warn(tp, link, dev,
  1376. "incorrect speed setting refused in TBI mode\n");
  1377. ret = -EOPNOTSUPP;
  1378. }
  1379. return ret;
  1380. }
  1381. static int rtl8169_set_speed_xmii(struct net_device *dev,
  1382. u8 autoneg, u16 speed, u8 duplex, u32 adv)
  1383. {
  1384. struct rtl8169_private *tp = netdev_priv(dev);
  1385. int giga_ctrl, bmcr;
  1386. int rc = -EINVAL;
  1387. rtl_writephy(tp, 0x1f, 0x0000);
  1388. if (autoneg == AUTONEG_ENABLE) {
  1389. int auto_nego;
  1390. auto_nego = rtl_readphy(tp, MII_ADVERTISE);
  1391. auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1392. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1393. if (adv & ADVERTISED_10baseT_Half)
  1394. auto_nego |= ADVERTISE_10HALF;
  1395. if (adv & ADVERTISED_10baseT_Full)
  1396. auto_nego |= ADVERTISE_10FULL;
  1397. if (adv & ADVERTISED_100baseT_Half)
  1398. auto_nego |= ADVERTISE_100HALF;
  1399. if (adv & ADVERTISED_100baseT_Full)
  1400. auto_nego |= ADVERTISE_100FULL;
  1401. auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1402. giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
  1403. giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  1404. /* The 8100e/8101e/8102e do Fast Ethernet only. */
  1405. if (tp->mii.supports_gmii) {
  1406. if (adv & ADVERTISED_1000baseT_Half)
  1407. giga_ctrl |= ADVERTISE_1000HALF;
  1408. if (adv & ADVERTISED_1000baseT_Full)
  1409. giga_ctrl |= ADVERTISE_1000FULL;
  1410. } else if (adv & (ADVERTISED_1000baseT_Half |
  1411. ADVERTISED_1000baseT_Full)) {
  1412. netif_info(tp, link, dev,
  1413. "PHY does not support 1000Mbps\n");
  1414. goto out;
  1415. }
  1416. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  1417. rtl_writephy(tp, MII_ADVERTISE, auto_nego);
  1418. rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
  1419. } else {
  1420. giga_ctrl = 0;
  1421. if (speed == SPEED_10)
  1422. bmcr = 0;
  1423. else if (speed == SPEED_100)
  1424. bmcr = BMCR_SPEED100;
  1425. else
  1426. goto out;
  1427. if (duplex == DUPLEX_FULL)
  1428. bmcr |= BMCR_FULLDPLX;
  1429. }
  1430. rtl_writephy(tp, MII_BMCR, bmcr);
  1431. if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  1432. tp->mac_version == RTL_GIGA_MAC_VER_03) {
  1433. if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
  1434. rtl_writephy(tp, 0x17, 0x2138);
  1435. rtl_writephy(tp, 0x0e, 0x0260);
  1436. } else {
  1437. rtl_writephy(tp, 0x17, 0x2108);
  1438. rtl_writephy(tp, 0x0e, 0x0000);
  1439. }
  1440. }
  1441. rc = 0;
  1442. out:
  1443. return rc;
  1444. }
  1445. static int rtl8169_set_speed(struct net_device *dev,
  1446. u8 autoneg, u16 speed, u8 duplex, u32 advertising)
  1447. {
  1448. struct rtl8169_private *tp = netdev_priv(dev);
  1449. int ret;
  1450. ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
  1451. if (ret < 0)
  1452. goto out;
  1453. if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
  1454. (advertising & ADVERTISED_1000baseT_Full)) {
  1455. mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
  1456. }
  1457. out:
  1458. return ret;
  1459. }
  1460. static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1461. {
  1462. struct rtl8169_private *tp = netdev_priv(dev);
  1463. int ret;
  1464. del_timer_sync(&tp->timer);
  1465. rtl_lock_work(tp);
  1466. ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
  1467. cmd->duplex, cmd->advertising);
  1468. rtl_unlock_work(tp);
  1469. return ret;
  1470. }
  1471. static netdev_features_t rtl8169_fix_features(struct net_device *dev,
  1472. netdev_features_t features)
  1473. {
  1474. struct rtl8169_private *tp = netdev_priv(dev);
  1475. if (dev->mtu > TD_MSS_MAX)
  1476. features &= ~NETIF_F_ALL_TSO;
  1477. if (dev->mtu > JUMBO_1K &&
  1478. !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
  1479. features &= ~NETIF_F_IP_CSUM;
  1480. return features;
  1481. }
  1482. static void __rtl8169_set_features(struct net_device *dev,
  1483. netdev_features_t features)
  1484. {
  1485. struct rtl8169_private *tp = netdev_priv(dev);
  1486. netdev_features_t changed = features ^ dev->features;
  1487. void __iomem *ioaddr = tp->mmio_addr;
  1488. if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
  1489. return;
  1490. if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
  1491. if (features & NETIF_F_RXCSUM)
  1492. tp->cp_cmd |= RxChkSum;
  1493. else
  1494. tp->cp_cmd &= ~RxChkSum;
  1495. if (dev->features & NETIF_F_HW_VLAN_RX)
  1496. tp->cp_cmd |= RxVlan;
  1497. else
  1498. tp->cp_cmd &= ~RxVlan;
  1499. RTL_W16(CPlusCmd, tp->cp_cmd);
  1500. RTL_R16(CPlusCmd);
  1501. }
  1502. if (changed & NETIF_F_RXALL) {
  1503. int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
  1504. if (features & NETIF_F_RXALL)
  1505. tmp |= (AcceptErr | AcceptRunt);
  1506. RTL_W32(RxConfig, tmp);
  1507. }
  1508. }
  1509. static int rtl8169_set_features(struct net_device *dev,
  1510. netdev_features_t features)
  1511. {
  1512. struct rtl8169_private *tp = netdev_priv(dev);
  1513. rtl_lock_work(tp);
  1514. __rtl8169_set_features(dev, features);
  1515. rtl_unlock_work(tp);
  1516. return 0;
  1517. }
  1518. static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
  1519. struct sk_buff *skb)
  1520. {
  1521. return (vlan_tx_tag_present(skb)) ?
  1522. TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
  1523. }
  1524. static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
  1525. {
  1526. u32 opts2 = le32_to_cpu(desc->opts2);
  1527. if (opts2 & RxVlanTag)
  1528. __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
  1529. desc->opts2 = 0;
  1530. }
  1531. static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
  1532. {
  1533. struct rtl8169_private *tp = netdev_priv(dev);
  1534. void __iomem *ioaddr = tp->mmio_addr;
  1535. u32 status;
  1536. cmd->supported =
  1537. SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1538. cmd->port = PORT_FIBRE;
  1539. cmd->transceiver = XCVR_INTERNAL;
  1540. status = RTL_R32(TBICSR);
  1541. cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
  1542. cmd->autoneg = !!(status & TBINwEnable);
  1543. ethtool_cmd_speed_set(cmd, SPEED_1000);
  1544. cmd->duplex = DUPLEX_FULL; /* Always set */
  1545. return 0;
  1546. }
  1547. static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
  1548. {
  1549. struct rtl8169_private *tp = netdev_priv(dev);
  1550. return mii_ethtool_gset(&tp->mii, cmd);
  1551. }
  1552. static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1553. {
  1554. struct rtl8169_private *tp = netdev_priv(dev);
  1555. int rc;
  1556. rtl_lock_work(tp);
  1557. rc = tp->get_settings(dev, cmd);
  1558. rtl_unlock_work(tp);
  1559. return rc;
  1560. }
  1561. static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  1562. void *p)
  1563. {
  1564. struct rtl8169_private *tp = netdev_priv(dev);
  1565. if (regs->len > R8169_REGS_SIZE)
  1566. regs->len = R8169_REGS_SIZE;
  1567. rtl_lock_work(tp);
  1568. memcpy_fromio(p, tp->mmio_addr, regs->len);
  1569. rtl_unlock_work(tp);
  1570. }
  1571. static u32 rtl8169_get_msglevel(struct net_device *dev)
  1572. {
  1573. struct rtl8169_private *tp = netdev_priv(dev);
  1574. return tp->msg_enable;
  1575. }
  1576. static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
  1577. {
  1578. struct rtl8169_private *tp = netdev_priv(dev);
  1579. tp->msg_enable = value;
  1580. }
  1581. static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
  1582. "tx_packets",
  1583. "rx_packets",
  1584. "tx_errors",
  1585. "rx_errors",
  1586. "rx_missed",
  1587. "align_errors",
  1588. "tx_single_collisions",
  1589. "tx_multi_collisions",
  1590. "unicast",
  1591. "broadcast",
  1592. "multicast",
  1593. "tx_aborted",
  1594. "tx_underrun",
  1595. };
  1596. static int rtl8169_get_sset_count(struct net_device *dev, int sset)
  1597. {
  1598. switch (sset) {
  1599. case ETH_SS_STATS:
  1600. return ARRAY_SIZE(rtl8169_gstrings);
  1601. default:
  1602. return -EOPNOTSUPP;
  1603. }
  1604. }
  1605. DECLARE_RTL_COND(rtl_counters_cond)
  1606. {
  1607. void __iomem *ioaddr = tp->mmio_addr;
  1608. return RTL_R32(CounterAddrLow) & CounterDump;
  1609. }
  1610. static void rtl8169_update_counters(struct net_device *dev)
  1611. {
  1612. struct rtl8169_private *tp = netdev_priv(dev);
  1613. void __iomem *ioaddr = tp->mmio_addr;
  1614. struct device *d = &tp->pci_dev->dev;
  1615. struct rtl8169_counters *counters;
  1616. dma_addr_t paddr;
  1617. u32 cmd;
  1618. /*
  1619. * Some chips are unable to dump tally counters when the receiver
  1620. * is disabled.
  1621. */
  1622. if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
  1623. return;
  1624. counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
  1625. if (!counters)
  1626. return;
  1627. RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
  1628. cmd = (u64)paddr & DMA_BIT_MASK(32);
  1629. RTL_W32(CounterAddrLow, cmd);
  1630. RTL_W32(CounterAddrLow, cmd | CounterDump);
  1631. if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
  1632. memcpy(&tp->counters, counters, sizeof(*counters));
  1633. RTL_W32(CounterAddrLow, 0);
  1634. RTL_W32(CounterAddrHigh, 0);
  1635. dma_free_coherent(d, sizeof(*counters), counters, paddr);
  1636. }
  1637. static void rtl8169_get_ethtool_stats(struct net_device *dev,
  1638. struct ethtool_stats *stats, u64 *data)
  1639. {
  1640. struct rtl8169_private *tp = netdev_priv(dev);
  1641. ASSERT_RTNL();
  1642. rtl8169_update_counters(dev);
  1643. data[0] = le64_to_cpu(tp->counters.tx_packets);
  1644. data[1] = le64_to_cpu(tp->counters.rx_packets);
  1645. data[2] = le64_to_cpu(tp->counters.tx_errors);
  1646. data[3] = le32_to_cpu(tp->counters.rx_errors);
  1647. data[4] = le16_to_cpu(tp->counters.rx_missed);
  1648. data[5] = le16_to_cpu(tp->counters.align_errors);
  1649. data[6] = le32_to_cpu(tp->counters.tx_one_collision);
  1650. data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
  1651. data[8] = le64_to_cpu(tp->counters.rx_unicast);
  1652. data[9] = le64_to_cpu(tp->counters.rx_broadcast);
  1653. data[10] = le32_to_cpu(tp->counters.rx_multicast);
  1654. data[11] = le16_to_cpu(tp->counters.tx_aborted);
  1655. data[12] = le16_to_cpu(tp->counters.tx_underun);
  1656. }
  1657. static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  1658. {
  1659. switch(stringset) {
  1660. case ETH_SS_STATS:
  1661. memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
  1662. break;
  1663. }
  1664. }
  1665. static const struct ethtool_ops rtl8169_ethtool_ops = {
  1666. .get_drvinfo = rtl8169_get_drvinfo,
  1667. .get_regs_len = rtl8169_get_regs_len,
  1668. .get_link = ethtool_op_get_link,
  1669. .get_settings = rtl8169_get_settings,
  1670. .set_settings = rtl8169_set_settings,
  1671. .get_msglevel = rtl8169_get_msglevel,
  1672. .set_msglevel = rtl8169_set_msglevel,
  1673. .get_regs = rtl8169_get_regs,
  1674. .get_wol = rtl8169_get_wol,
  1675. .set_wol = rtl8169_set_wol,
  1676. .get_strings = rtl8169_get_strings,
  1677. .get_sset_count = rtl8169_get_sset_count,
  1678. .get_ethtool_stats = rtl8169_get_ethtool_stats,
  1679. .get_ts_info = ethtool_op_get_ts_info,
  1680. };
  1681. static void rtl8169_get_mac_version(struct rtl8169_private *tp,
  1682. struct net_device *dev, u8 default_version)
  1683. {
  1684. void __iomem *ioaddr = tp->mmio_addr;
  1685. /*
  1686. * The driver currently handles the 8168Bf and the 8168Be identically
  1687. * but they can be identified more specifically through the test below
  1688. * if needed:
  1689. *
  1690. * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
  1691. *
  1692. * Same thing for the 8101Eb and the 8101Ec:
  1693. *
  1694. * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
  1695. */
  1696. static const struct rtl_mac_info {
  1697. u32 mask;
  1698. u32 val;
  1699. int mac_version;
  1700. } mac_info[] = {
  1701. /* 8168G family. */
  1702. { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
  1703. { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
  1704. /* 8168F family. */
  1705. { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
  1706. { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
  1707. { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
  1708. /* 8168E family. */
  1709. { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
  1710. { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
  1711. { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
  1712. { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
  1713. /* 8168D family. */
  1714. { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
  1715. { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
  1716. { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
  1717. /* 8168DP family. */
  1718. { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
  1719. { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
  1720. { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
  1721. /* 8168C family. */
  1722. { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
  1723. { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
  1724. { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
  1725. { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
  1726. { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
  1727. { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
  1728. { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
  1729. { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
  1730. { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
  1731. /* 8168B family. */
  1732. { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
  1733. { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
  1734. { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
  1735. { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
  1736. /* 8101 family. */
  1737. { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
  1738. { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
  1739. { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
  1740. { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
  1741. { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
  1742. { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
  1743. { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
  1744. { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
  1745. { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
  1746. { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
  1747. { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
  1748. { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
  1749. { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
  1750. { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
  1751. { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
  1752. { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
  1753. { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
  1754. { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
  1755. { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
  1756. /* FIXME: where did these entries come from ? -- FR */
  1757. { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
  1758. { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
  1759. /* 8110 family. */
  1760. { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
  1761. { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
  1762. { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
  1763. { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
  1764. { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
  1765. { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
  1766. /* Catch-all */
  1767. { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
  1768. };
  1769. const struct rtl_mac_info *p = mac_info;
  1770. u32 reg;
  1771. reg = RTL_R32(TxConfig);
  1772. while ((reg & p->mask) != p->val)
  1773. p++;
  1774. tp->mac_version = p->mac_version;
  1775. if (tp->mac_version == RTL_GIGA_MAC_NONE) {
  1776. netif_notice(tp, probe, dev,
  1777. "unknown MAC, using family default\n");
  1778. tp->mac_version = default_version;
  1779. }
  1780. }
  1781. static void rtl8169_print_mac_version(struct rtl8169_private *tp)
  1782. {
  1783. dprintk("mac_version = 0x%02x\n", tp->mac_version);
  1784. }
  1785. struct phy_reg {
  1786. u16 reg;
  1787. u16 val;
  1788. };
  1789. static void rtl_writephy_batch(struct rtl8169_private *tp,
  1790. const struct phy_reg *regs, int len)
  1791. {
  1792. while (len-- > 0) {
  1793. rtl_writephy(tp, regs->reg, regs->val);
  1794. regs++;
  1795. }
  1796. }
  1797. #define PHY_READ 0x00000000
  1798. #define PHY_DATA_OR 0x10000000
  1799. #define PHY_DATA_AND 0x20000000
  1800. #define PHY_BJMPN 0x30000000
  1801. #define PHY_READ_EFUSE 0x40000000
  1802. #define PHY_READ_MAC_BYTE 0x50000000
  1803. #define PHY_WRITE_MAC_BYTE 0x60000000
  1804. #define PHY_CLEAR_READCOUNT 0x70000000
  1805. #define PHY_WRITE 0x80000000
  1806. #define PHY_READCOUNT_EQ_SKIP 0x90000000
  1807. #define PHY_COMP_EQ_SKIPN 0xa0000000
  1808. #define PHY_COMP_NEQ_SKIPN 0xb0000000
  1809. #define PHY_WRITE_PREVIOUS 0xc0000000
  1810. #define PHY_SKIPN 0xd0000000
  1811. #define PHY_DELAY_MS 0xe0000000
  1812. #define PHY_WRITE_ERI_WORD 0xf0000000
  1813. struct fw_info {
  1814. u32 magic;
  1815. char version[RTL_VER_SIZE];
  1816. __le32 fw_start;
  1817. __le32 fw_len;
  1818. u8 chksum;
  1819. } __packed;
  1820. #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
  1821. static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
  1822. {
  1823. const struct firmware *fw = rtl_fw->fw;
  1824. struct fw_info *fw_info = (struct fw_info *)fw->data;
  1825. struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
  1826. char *version = rtl_fw->version;
  1827. bool rc = false;
  1828. if (fw->size < FW_OPCODE_SIZE)
  1829. goto out;
  1830. if (!fw_info->magic) {
  1831. size_t i, size, start;
  1832. u8 checksum = 0;
  1833. if (fw->size < sizeof(*fw_info))
  1834. goto out;
  1835. for (i = 0; i < fw->size; i++)
  1836. checksum += fw->data[i];
  1837. if (checksum != 0)
  1838. goto out;
  1839. start = le32_to_cpu(fw_info->fw_start);
  1840. if (start > fw->size)
  1841. goto out;
  1842. size = le32_to_cpu(fw_info->fw_len);
  1843. if (size > (fw->size - start) / FW_OPCODE_SIZE)
  1844. goto out;
  1845. memcpy(version, fw_info->version, RTL_VER_SIZE);
  1846. pa->code = (__le32 *)(fw->data + start);
  1847. pa->size = size;
  1848. } else {
  1849. if (fw->size % FW_OPCODE_SIZE)
  1850. goto out;
  1851. strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
  1852. pa->code = (__le32 *)fw->data;
  1853. pa->size = fw->size / FW_OPCODE_SIZE;
  1854. }
  1855. version[RTL_VER_SIZE - 1] = 0;
  1856. rc = true;
  1857. out:
  1858. return rc;
  1859. }
  1860. static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
  1861. struct rtl_fw_phy_action *pa)
  1862. {
  1863. bool rc = false;
  1864. size_t index;
  1865. for (index = 0; index < pa->size; index++) {
  1866. u32 action = le32_to_cpu(pa->code[index]);
  1867. u32 regno = (action & 0x0fff0000) >> 16;
  1868. switch(action & 0xf0000000) {
  1869. case PHY_READ:
  1870. case PHY_DATA_OR:
  1871. case PHY_DATA_AND:
  1872. case PHY_READ_EFUSE:
  1873. case PHY_CLEAR_READCOUNT:
  1874. case PHY_WRITE:
  1875. case PHY_WRITE_PREVIOUS:
  1876. case PHY_DELAY_MS:
  1877. break;
  1878. case PHY_BJMPN:
  1879. if (regno > index) {
  1880. netif_err(tp, ifup, tp->dev,
  1881. "Out of range of firmware\n");
  1882. goto out;
  1883. }
  1884. break;
  1885. case PHY_READCOUNT_EQ_SKIP:
  1886. if (index + 2 >= pa->size) {
  1887. netif_err(tp, ifup, tp->dev,
  1888. "Out of range of firmware\n");
  1889. goto out;
  1890. }
  1891. break;
  1892. case PHY_COMP_EQ_SKIPN:
  1893. case PHY_COMP_NEQ_SKIPN:
  1894. case PHY_SKIPN:
  1895. if (index + 1 + regno >= pa->size) {
  1896. netif_err(tp, ifup, tp->dev,
  1897. "Out of range of firmware\n");
  1898. goto out;
  1899. }
  1900. break;
  1901. case PHY_READ_MAC_BYTE:
  1902. case PHY_WRITE_MAC_BYTE:
  1903. case PHY_WRITE_ERI_WORD:
  1904. default:
  1905. netif_err(tp, ifup, tp->dev,
  1906. "Invalid action 0x%08x\n", action);
  1907. goto out;
  1908. }
  1909. }
  1910. rc = true;
  1911. out:
  1912. return rc;
  1913. }
  1914. static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
  1915. {
  1916. struct net_device *dev = tp->dev;
  1917. int rc = -EINVAL;
  1918. if (!rtl_fw_format_ok(tp, rtl_fw)) {
  1919. netif_err(tp, ifup, dev, "invalid firwmare\n");
  1920. goto out;
  1921. }
  1922. if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
  1923. rc = 0;
  1924. out:
  1925. return rc;
  1926. }
  1927. static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
  1928. {
  1929. struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
  1930. u32 predata, count;
  1931. size_t index;
  1932. predata = count = 0;
  1933. for (index = 0; index < pa->size; ) {
  1934. u32 action = le32_to_cpu(pa->code[index]);
  1935. u32 data = action & 0x0000ffff;
  1936. u32 regno = (action & 0x0fff0000) >> 16;
  1937. if (!action)
  1938. break;
  1939. switch(action & 0xf0000000) {
  1940. case PHY_READ:
  1941. predata = rtl_readphy(tp, regno);
  1942. count++;
  1943. index++;
  1944. break;
  1945. case PHY_DATA_OR:
  1946. predata |= data;
  1947. index++;
  1948. break;
  1949. case PHY_DATA_AND:
  1950. predata &= data;
  1951. index++;
  1952. break;
  1953. case PHY_BJMPN:
  1954. index -= regno;
  1955. break;
  1956. case PHY_READ_EFUSE:
  1957. predata = rtl8168d_efuse_read(tp, regno);
  1958. index++;
  1959. break;
  1960. case PHY_CLEAR_READCOUNT:
  1961. count = 0;
  1962. index++;
  1963. break;
  1964. case PHY_WRITE:
  1965. rtl_writephy(tp, regno, data);
  1966. index++;
  1967. break;
  1968. case PHY_READCOUNT_EQ_SKIP:
  1969. index += (count == data) ? 2 : 1;
  1970. break;
  1971. case PHY_COMP_EQ_SKIPN:
  1972. if (predata == data)
  1973. index += regno;
  1974. index++;
  1975. break;
  1976. case PHY_COMP_NEQ_SKIPN:
  1977. if (predata != data)
  1978. index += regno;
  1979. index++;
  1980. break;
  1981. case PHY_WRITE_PREVIOUS:
  1982. rtl_writephy(tp, regno, predata);
  1983. index++;
  1984. break;
  1985. case PHY_SKIPN:
  1986. index += regno + 1;
  1987. break;
  1988. case PHY_DELAY_MS:
  1989. mdelay(data);
  1990. index++;
  1991. break;
  1992. case PHY_READ_MAC_BYTE:
  1993. case PHY_WRITE_MAC_BYTE:
  1994. case PHY_WRITE_ERI_WORD:
  1995. default:
  1996. BUG();
  1997. }
  1998. }
  1999. }
  2000. static void rtl_release_firmware(struct rtl8169_private *tp)
  2001. {
  2002. if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
  2003. release_firmware(tp->rtl_fw->fw);
  2004. kfree(tp->rtl_fw);
  2005. }
  2006. tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
  2007. }
  2008. static void rtl_apply_firmware(struct rtl8169_private *tp)
  2009. {
  2010. struct rtl_fw *rtl_fw = tp->rtl_fw;
  2011. /* TODO: release firmware once rtl_phy_write_fw signals failures. */
  2012. if (!IS_ERR_OR_NULL(rtl_fw))
  2013. rtl_phy_write_fw(tp, rtl_fw);
  2014. }
  2015. static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
  2016. {
  2017. if (rtl_readphy(tp, reg) != val)
  2018. netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
  2019. else
  2020. rtl_apply_firmware(tp);
  2021. }
  2022. static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
  2023. {
  2024. static const struct phy_reg phy_reg_init[] = {
  2025. { 0x1f, 0x0001 },
  2026. { 0x06, 0x006e },
  2027. { 0x08, 0x0708 },
  2028. { 0x15, 0x4000 },
  2029. { 0x18, 0x65c7 },
  2030. { 0x1f, 0x0001 },
  2031. { 0x03, 0x00a1 },
  2032. { 0x02, 0x0008 },
  2033. { 0x01, 0x0120 },
  2034. { 0x00, 0x1000 },
  2035. { 0x04, 0x0800 },
  2036. { 0x04, 0x0000 },
  2037. { 0x03, 0xff41 },
  2038. { 0x02, 0xdf60 },
  2039. { 0x01, 0x0140 },
  2040. { 0x00, 0x0077 },
  2041. { 0x04, 0x7800 },
  2042. { 0x04, 0x7000 },
  2043. { 0x03, 0x802f },
  2044. { 0x02, 0x4f02 },
  2045. { 0x01, 0x0409 },
  2046. { 0x00, 0xf0f9 },
  2047. { 0x04, 0x9800 },
  2048. { 0x04, 0x9000 },
  2049. { 0x03, 0xdf01 },
  2050. { 0x02, 0xdf20 },
  2051. { 0x01, 0xff95 },
  2052. { 0x00, 0xba00 },
  2053. { 0x04, 0xa800 },
  2054. { 0x04, 0xa000 },
  2055. { 0x03, 0xff41 },
  2056. { 0x02, 0xdf20 },
  2057. { 0x01, 0x0140 },
  2058. { 0x00, 0x00bb },
  2059. { 0x04, 0xb800 },
  2060. { 0x04, 0xb000 },
  2061. { 0x03, 0xdf41 },
  2062. { 0x02, 0xdc60 },
  2063. { 0x01, 0x6340 },
  2064. { 0x00, 0x007d },
  2065. { 0x04, 0xd800 },
  2066. { 0x04, 0xd000 },
  2067. { 0x03, 0xdf01 },
  2068. { 0x02, 0xdf20 },
  2069. { 0x01, 0x100a },
  2070. { 0x00, 0xa0ff },
  2071. { 0x04, 0xf800 },
  2072. { 0x04, 0xf000 },
  2073. { 0x1f, 0x0000 },
  2074. { 0x0b, 0x0000 },
  2075. { 0x00, 0x9200 }
  2076. };
  2077. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2078. }
  2079. static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
  2080. {
  2081. static const struct phy_reg phy_reg_init[] = {
  2082. { 0x1f, 0x0002 },
  2083. { 0x01, 0x90d0 },
  2084. { 0x1f, 0x0000 }
  2085. };
  2086. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2087. }
  2088. static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
  2089. {
  2090. struct pci_dev *pdev = tp->pci_dev;
  2091. if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
  2092. (pdev->subsystem_device != 0xe000))
  2093. return;
  2094. rtl_writephy(tp, 0x1f, 0x0001);
  2095. rtl_writephy(tp, 0x10, 0xf01b);
  2096. rtl_writephy(tp, 0x1f, 0x0000);
  2097. }
  2098. static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
  2099. {
  2100. static const struct phy_reg phy_reg_init[] = {
  2101. { 0x1f, 0x0001 },
  2102. { 0x04, 0x0000 },
  2103. { 0x03, 0x00a1 },
  2104. { 0x02, 0x0008 },
  2105. { 0x01, 0x0120 },
  2106. { 0x00, 0x1000 },
  2107. { 0x04, 0x0800 },
  2108. { 0x04, 0x9000 },
  2109. { 0x03, 0x802f },
  2110. { 0x02, 0x4f02 },
  2111. { 0x01, 0x0409 },
  2112. { 0x00, 0xf099 },
  2113. { 0x04, 0x9800 },
  2114. { 0x04, 0xa000 },
  2115. { 0x03, 0xdf01 },
  2116. { 0x02, 0xdf20 },
  2117. { 0x01, 0xff95 },
  2118. { 0x00, 0xba00 },
  2119. { 0x04, 0xa800 },
  2120. { 0x04, 0xf000 },
  2121. { 0x03, 0xdf01 },
  2122. { 0x02, 0xdf20 },
  2123. { 0x01, 0x101a },
  2124. { 0x00, 0xa0ff },
  2125. { 0x04, 0xf800 },
  2126. { 0x04, 0x0000 },
  2127. { 0x1f, 0x0000 },
  2128. { 0x1f, 0x0001 },
  2129. { 0x10, 0xf41b },
  2130. { 0x14, 0xfb54 },
  2131. { 0x18, 0xf5c7 },
  2132. { 0x1f, 0x0000 },
  2133. { 0x1f, 0x0001 },
  2134. { 0x17, 0x0cc0 },
  2135. { 0x1f, 0x0000 }
  2136. };
  2137. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2138. rtl8169scd_hw_phy_config_quirk(tp);
  2139. }
  2140. static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
  2141. {
  2142. static const struct phy_reg phy_reg_init[] = {
  2143. { 0x1f, 0x0001 },
  2144. { 0x04, 0x0000 },
  2145. { 0x03, 0x00a1 },
  2146. { 0x02, 0x0008 },
  2147. { 0x01, 0x0120 },
  2148. { 0x00, 0x1000 },
  2149. { 0x04, 0x0800 },
  2150. { 0x04, 0x9000 },
  2151. { 0x03, 0x802f },
  2152. { 0x02, 0x4f02 },
  2153. { 0x01, 0x0409 },
  2154. { 0x00, 0xf099 },
  2155. { 0x04, 0x9800 },
  2156. { 0x04, 0xa000 },
  2157. { 0x03, 0xdf01 },
  2158. { 0x02, 0xdf20 },
  2159. { 0x01, 0xff95 },
  2160. { 0x00, 0xba00 },
  2161. { 0x04, 0xa800 },
  2162. { 0x04, 0xf000 },
  2163. { 0x03, 0xdf01 },
  2164. { 0x02, 0xdf20 },
  2165. { 0x01, 0x101a },
  2166. { 0x00, 0xa0ff },
  2167. { 0x04, 0xf800 },
  2168. { 0x04, 0x0000 },
  2169. { 0x1f, 0x0000 },
  2170. { 0x1f, 0x0001 },
  2171. { 0x0b, 0x8480 },
  2172. { 0x1f, 0x0000 },
  2173. { 0x1f, 0x0001 },
  2174. { 0x18, 0x67c7 },
  2175. { 0x04, 0x2000 },
  2176. { 0x03, 0x002f },
  2177. { 0x02, 0x4360 },
  2178. { 0x01, 0x0109 },
  2179. { 0x00, 0x3022 },
  2180. { 0x04, 0x2800 },
  2181. { 0x1f, 0x0000 },
  2182. { 0x1f, 0x0001 },
  2183. { 0x17, 0x0cc0 },
  2184. { 0x1f, 0x0000 }
  2185. };
  2186. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2187. }
  2188. static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
  2189. {
  2190. static const struct phy_reg phy_reg_init[] = {
  2191. { 0x10, 0xf41b },
  2192. { 0x1f, 0x0000 }
  2193. };
  2194. rtl_writephy(tp, 0x1f, 0x0001);
  2195. rtl_patchphy(tp, 0x16, 1 << 0);
  2196. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2197. }
  2198. static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
  2199. {
  2200. static const struct phy_reg phy_reg_init[] = {
  2201. { 0x1f, 0x0001 },
  2202. { 0x10, 0xf41b },
  2203. { 0x1f, 0x0000 }
  2204. };
  2205. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2206. }
  2207. static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
  2208. {
  2209. static const struct phy_reg phy_reg_init[] = {
  2210. { 0x1f, 0x0000 },
  2211. { 0x1d, 0x0f00 },
  2212. { 0x1f, 0x0002 },
  2213. { 0x0c, 0x1ec8 },
  2214. { 0x1f, 0x0000 }
  2215. };
  2216. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2217. }
  2218. static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
  2219. {
  2220. static const struct phy_reg phy_reg_init[] = {
  2221. { 0x1f, 0x0001 },
  2222. { 0x1d, 0x3d98 },
  2223. { 0x1f, 0x0000 }
  2224. };
  2225. rtl_writephy(tp, 0x1f, 0x0000);
  2226. rtl_patchphy(tp, 0x14, 1 << 5);
  2227. rtl_patchphy(tp, 0x0d, 1 << 5);
  2228. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2229. }
  2230. static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
  2231. {
  2232. static const struct phy_reg phy_reg_init[] = {
  2233. { 0x1f, 0x0001 },
  2234. { 0x12, 0x2300 },
  2235. { 0x1f, 0x0002 },
  2236. { 0x00, 0x88d4 },
  2237. { 0x01, 0x82b1 },
  2238. { 0x03, 0x7002 },
  2239. { 0x08, 0x9e30 },
  2240. { 0x09, 0x01f0 },
  2241. { 0x0a, 0x5500 },
  2242. { 0x0c, 0x00c8 },
  2243. { 0x1f, 0x0003 },
  2244. { 0x12, 0xc096 },
  2245. { 0x16, 0x000a },
  2246. { 0x1f, 0x0000 },
  2247. { 0x1f, 0x0000 },
  2248. { 0x09, 0x2000 },
  2249. { 0x09, 0x0000 }
  2250. };
  2251. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2252. rtl_patchphy(tp, 0x14, 1 << 5);
  2253. rtl_patchphy(tp, 0x0d, 1 << 5);
  2254. rtl_writephy(tp, 0x1f, 0x0000);
  2255. }
  2256. static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
  2257. {
  2258. static const struct phy_reg phy_reg_init[] = {
  2259. { 0x1f, 0x0001 },
  2260. { 0x12, 0x2300 },
  2261. { 0x03, 0x802f },
  2262. { 0x02, 0x4f02 },
  2263. { 0x01, 0x0409 },
  2264. { 0x00, 0xf099 },
  2265. { 0x04, 0x9800 },
  2266. { 0x04, 0x9000 },
  2267. { 0x1d, 0x3d98 },
  2268. { 0x1f, 0x0002 },
  2269. { 0x0c, 0x7eb8 },
  2270. { 0x06, 0x0761 },
  2271. { 0x1f, 0x0003 },
  2272. { 0x16, 0x0f0a },
  2273. { 0x1f, 0x0000 }
  2274. };
  2275. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2276. rtl_patchphy(tp, 0x16, 1 << 0);
  2277. rtl_patchphy(tp, 0x14, 1 << 5);
  2278. rtl_patchphy(tp, 0x0d, 1 << 5);
  2279. rtl_writephy(tp, 0x1f, 0x0000);
  2280. }
  2281. static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
  2282. {
  2283. static const struct phy_reg phy_reg_init[] = {
  2284. { 0x1f, 0x0001 },
  2285. { 0x12, 0x2300 },
  2286. { 0x1d, 0x3d98 },
  2287. { 0x1f, 0x0002 },
  2288. { 0x0c, 0x7eb8 },
  2289. { 0x06, 0x5461 },
  2290. { 0x1f, 0x0003 },
  2291. { 0x16, 0x0f0a },
  2292. { 0x1f, 0x0000 }
  2293. };
  2294. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2295. rtl_patchphy(tp, 0x16, 1 << 0);
  2296. rtl_patchphy(tp, 0x14, 1 << 5);
  2297. rtl_patchphy(tp, 0x0d, 1 << 5);
  2298. rtl_writephy(tp, 0x1f, 0x0000);
  2299. }
  2300. static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
  2301. {
  2302. rtl8168c_3_hw_phy_config(tp);
  2303. }
  2304. static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
  2305. {
  2306. static const struct phy_reg phy_reg_init_0[] = {
  2307. /* Channel Estimation */
  2308. { 0x1f, 0x0001 },
  2309. { 0x06, 0x4064 },
  2310. { 0x07, 0x2863 },
  2311. { 0x08, 0x059c },
  2312. { 0x09, 0x26b4 },
  2313. { 0x0a, 0x6a19 },
  2314. { 0x0b, 0xdcc8 },
  2315. { 0x10, 0xf06d },
  2316. { 0x14, 0x7f68 },
  2317. { 0x18, 0x7fd9 },
  2318. { 0x1c, 0xf0ff },
  2319. { 0x1d, 0x3d9c },
  2320. { 0x1f, 0x0003 },
  2321. { 0x12, 0xf49f },
  2322. { 0x13, 0x070b },
  2323. { 0x1a, 0x05ad },
  2324. { 0x14, 0x94c0 },
  2325. /*
  2326. * Tx Error Issue
  2327. * Enhance line driver power
  2328. */
  2329. { 0x1f, 0x0002 },
  2330. { 0x06, 0x5561 },
  2331. { 0x1f, 0x0005 },
  2332. { 0x05, 0x8332 },
  2333. { 0x06, 0x5561 },
  2334. /*
  2335. * Can not link to 1Gbps with bad cable
  2336. * Decrease SNR threshold form 21.07dB to 19.04dB
  2337. */
  2338. { 0x1f, 0x0001 },
  2339. { 0x17, 0x0cc0 },
  2340. { 0x1f, 0x0000 },
  2341. { 0x0d, 0xf880 }
  2342. };
  2343. rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
  2344. /*
  2345. * Rx Error Issue
  2346. * Fine Tune Switching regulator parameter
  2347. */
  2348. rtl_writephy(tp, 0x1f, 0x0002);
  2349. rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
  2350. rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
  2351. if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
  2352. static const struct phy_reg phy_reg_init[] = {
  2353. { 0x1f, 0x0002 },
  2354. { 0x05, 0x669a },
  2355. { 0x1f, 0x0005 },
  2356. { 0x05, 0x8330 },
  2357. { 0x06, 0x669a },
  2358. { 0x1f, 0x0002 }
  2359. };
  2360. int val;
  2361. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2362. val = rtl_readphy(tp, 0x0d);
  2363. if ((val & 0x00ff) != 0x006c) {
  2364. static const u32 set[] = {
  2365. 0x0065, 0x0066, 0x0067, 0x0068,
  2366. 0x0069, 0x006a, 0x006b, 0x006c
  2367. };
  2368. int i;
  2369. rtl_writephy(tp, 0x1f, 0x0002);
  2370. val &= 0xff00;
  2371. for (i = 0; i < ARRAY_SIZE(set); i++)
  2372. rtl_writephy(tp, 0x0d, val | set[i]);
  2373. }
  2374. } else {
  2375. static const struct phy_reg phy_reg_init[] = {
  2376. { 0x1f, 0x0002 },
  2377. { 0x05, 0x6662 },
  2378. { 0x1f, 0x0005 },
  2379. { 0x05, 0x8330 },
  2380. { 0x06, 0x6662 }
  2381. };
  2382. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2383. }
  2384. /* RSET couple improve */
  2385. rtl_writephy(tp, 0x1f, 0x0002);
  2386. rtl_patchphy(tp, 0x0d, 0x0300);
  2387. rtl_patchphy(tp, 0x0f, 0x0010);
  2388. /* Fine tune PLL performance */
  2389. rtl_writephy(tp, 0x1f, 0x0002);
  2390. rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
  2391. rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
  2392. rtl_writephy(tp, 0x1f, 0x0005);
  2393. rtl_writephy(tp, 0x05, 0x001b);
  2394. rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
  2395. rtl_writephy(tp, 0x1f, 0x0000);
  2396. }
  2397. static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
  2398. {
  2399. static const struct phy_reg phy_reg_init_0[] = {
  2400. /* Channel Estimation */
  2401. { 0x1f, 0x0001 },
  2402. { 0x06, 0x4064 },
  2403. { 0x07, 0x2863 },
  2404. { 0x08, 0x059c },
  2405. { 0x09, 0x26b4 },
  2406. { 0x0a, 0x6a19 },
  2407. { 0x0b, 0xdcc8 },
  2408. { 0x10, 0xf06d },
  2409. { 0x14, 0x7f68 },
  2410. { 0x18, 0x7fd9 },
  2411. { 0x1c, 0xf0ff },
  2412. { 0x1d, 0x3d9c },
  2413. { 0x1f, 0x0003 },
  2414. { 0x12, 0xf49f },
  2415. { 0x13, 0x070b },
  2416. { 0x1a, 0x05ad },
  2417. { 0x14, 0x94c0 },
  2418. /*
  2419. * Tx Error Issue
  2420. * Enhance line driver power
  2421. */
  2422. { 0x1f, 0x0002 },
  2423. { 0x06, 0x5561 },
  2424. { 0x1f, 0x0005 },
  2425. { 0x05, 0x8332 },
  2426. { 0x06, 0x5561 },
  2427. /*
  2428. * Can not link to 1Gbps with bad cable
  2429. * Decrease SNR threshold form 21.07dB to 19.04dB
  2430. */
  2431. { 0x1f, 0x0001 },
  2432. { 0x17, 0x0cc0 },
  2433. { 0x1f, 0x0000 },
  2434. { 0x0d, 0xf880 }
  2435. };
  2436. rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
  2437. if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
  2438. static const struct phy_reg phy_reg_init[] = {
  2439. { 0x1f, 0x0002 },
  2440. { 0x05, 0x669a },
  2441. { 0x1f, 0x0005 },
  2442. { 0x05, 0x8330 },
  2443. { 0x06, 0x669a },
  2444. { 0x1f, 0x0002 }
  2445. };
  2446. int val;
  2447. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2448. val = rtl_readphy(tp, 0x0d);
  2449. if ((val & 0x00ff) != 0x006c) {
  2450. static const u32 set[] = {
  2451. 0x0065, 0x0066, 0x0067, 0x0068,
  2452. 0x0069, 0x006a, 0x006b, 0x006c
  2453. };
  2454. int i;
  2455. rtl_writephy(tp, 0x1f, 0x0002);
  2456. val &= 0xff00;
  2457. for (i = 0; i < ARRAY_SIZE(set); i++)
  2458. rtl_writephy(tp, 0x0d, val | set[i]);
  2459. }
  2460. } else {
  2461. static const struct phy_reg phy_reg_init[] = {
  2462. { 0x1f, 0x0002 },
  2463. { 0x05, 0x2642 },
  2464. { 0x1f, 0x0005 },
  2465. { 0x05, 0x8330 },
  2466. { 0x06, 0x2642 }
  2467. };
  2468. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2469. }
  2470. /* Fine tune PLL performance */
  2471. rtl_writephy(tp, 0x1f, 0x0002);
  2472. rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
  2473. rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
  2474. /* Switching regulator Slew rate */
  2475. rtl_writephy(tp, 0x1f, 0x0002);
  2476. rtl_patchphy(tp, 0x0f, 0x0017);
  2477. rtl_writephy(tp, 0x1f, 0x0005);
  2478. rtl_writephy(tp, 0x05, 0x001b);
  2479. rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
  2480. rtl_writephy(tp, 0x1f, 0x0000);
  2481. }
  2482. static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
  2483. {
  2484. static const struct phy_reg phy_reg_init[] = {
  2485. { 0x1f, 0x0002 },
  2486. { 0x10, 0x0008 },
  2487. { 0x0d, 0x006c },
  2488. { 0x1f, 0x0000 },
  2489. { 0x0d, 0xf880 },
  2490. { 0x1f, 0x0001 },
  2491. { 0x17, 0x0cc0 },
  2492. { 0x1f, 0x0001 },
  2493. { 0x0b, 0xa4d8 },
  2494. { 0x09, 0x281c },
  2495. { 0x07, 0x2883 },
  2496. { 0x0a, 0x6b35 },
  2497. { 0x1d, 0x3da4 },
  2498. { 0x1c, 0xeffd },
  2499. { 0x14, 0x7f52 },
  2500. { 0x18, 0x7fc6 },
  2501. { 0x08, 0x0601 },
  2502. { 0x06, 0x4063 },
  2503. { 0x10, 0xf074 },
  2504. { 0x1f, 0x0003 },
  2505. { 0x13, 0x0789 },
  2506. { 0x12, 0xf4bd },
  2507. { 0x1a, 0x04fd },
  2508. { 0x14, 0x84b0 },
  2509. { 0x1f, 0x0000 },
  2510. { 0x00, 0x9200 },
  2511. { 0x1f, 0x0005 },
  2512. { 0x01, 0x0340 },
  2513. { 0x1f, 0x0001 },
  2514. { 0x04, 0x4000 },
  2515. { 0x03, 0x1d21 },
  2516. { 0x02, 0x0c32 },
  2517. { 0x01, 0x0200 },
  2518. { 0x00, 0x5554 },
  2519. { 0x04, 0x4800 },
  2520. { 0x04, 0x4000 },
  2521. { 0x04, 0xf000 },
  2522. { 0x03, 0xdf01 },
  2523. { 0x02, 0xdf20 },
  2524. { 0x01, 0x101a },
  2525. { 0x00, 0xa0ff },
  2526. { 0x04, 0xf800 },
  2527. { 0x04, 0xf000 },
  2528. { 0x1f, 0x0000 },
  2529. { 0x1f, 0x0007 },
  2530. { 0x1e, 0x0023 },
  2531. { 0x16, 0x0000 },
  2532. { 0x1f, 0x0000 }
  2533. };
  2534. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2535. }
  2536. static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
  2537. {
  2538. static const struct phy_reg phy_reg_init[] = {
  2539. { 0x1f, 0x0001 },
  2540. { 0x17, 0x0cc0 },
  2541. { 0x1f, 0x0007 },
  2542. { 0x1e, 0x002d },
  2543. { 0x18, 0x0040 },
  2544. { 0x1f, 0x0000 }
  2545. };
  2546. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2547. rtl_patchphy(tp, 0x0d, 1 << 5);
  2548. }
  2549. static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
  2550. {
  2551. static const struct phy_reg phy_reg_init[] = {
  2552. /* Enable Delay cap */
  2553. { 0x1f, 0x0005 },
  2554. { 0x05, 0x8b80 },
  2555. { 0x06, 0xc896 },
  2556. { 0x1f, 0x0000 },
  2557. /* Channel estimation fine tune */
  2558. { 0x1f, 0x0001 },
  2559. { 0x0b, 0x6c20 },
  2560. { 0x07, 0x2872 },
  2561. { 0x1c, 0xefff },
  2562. { 0x1f, 0x0003 },
  2563. { 0x14, 0x6420 },
  2564. { 0x1f, 0x0000 },
  2565. /* Update PFM & 10M TX idle timer */
  2566. { 0x1f, 0x0007 },
  2567. { 0x1e, 0x002f },
  2568. { 0x15, 0x1919 },
  2569. { 0x1f, 0x0000 },
  2570. { 0x1f, 0x0007 },
  2571. { 0x1e, 0x00ac },
  2572. { 0x18, 0x0006 },
  2573. { 0x1f, 0x0000 }
  2574. };
  2575. rtl_apply_firmware(tp);
  2576. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2577. /* DCO enable for 10M IDLE Power */
  2578. rtl_writephy(tp, 0x1f, 0x0007);
  2579. rtl_writephy(tp, 0x1e, 0x0023);
  2580. rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
  2581. rtl_writephy(tp, 0x1f, 0x0000);
  2582. /* For impedance matching */
  2583. rtl_writephy(tp, 0x1f, 0x0002);
  2584. rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
  2585. rtl_writephy(tp, 0x1f, 0x0000);
  2586. /* PHY auto speed down */
  2587. rtl_writephy(tp, 0x1f, 0x0007);
  2588. rtl_writephy(tp, 0x1e, 0x002d);
  2589. rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
  2590. rtl_writephy(tp, 0x1f, 0x0000);
  2591. rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
  2592. rtl_writephy(tp, 0x1f, 0x0005);
  2593. rtl_writephy(tp, 0x05, 0x8b86);
  2594. rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
  2595. rtl_writephy(tp, 0x1f, 0x0000);
  2596. rtl_writephy(tp, 0x1f, 0x0005);
  2597. rtl_writephy(tp, 0x05, 0x8b85);
  2598. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
  2599. rtl_writephy(tp, 0x1f, 0x0007);
  2600. rtl_writephy(tp, 0x1e, 0x0020);
  2601. rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
  2602. rtl_writephy(tp, 0x1f, 0x0006);
  2603. rtl_writephy(tp, 0x00, 0x5a00);
  2604. rtl_writephy(tp, 0x1f, 0x0000);
  2605. rtl_writephy(tp, 0x0d, 0x0007);
  2606. rtl_writephy(tp, 0x0e, 0x003c);
  2607. rtl_writephy(tp, 0x0d, 0x4007);
  2608. rtl_writephy(tp, 0x0e, 0x0000);
  2609. rtl_writephy(tp, 0x0d, 0x0000);
  2610. }
  2611. static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
  2612. {
  2613. static const struct phy_reg phy_reg_init[] = {
  2614. /* Enable Delay cap */
  2615. { 0x1f, 0x0004 },
  2616. { 0x1f, 0x0007 },
  2617. { 0x1e, 0x00ac },
  2618. { 0x18, 0x0006 },
  2619. { 0x1f, 0x0002 },
  2620. { 0x1f, 0x0000 },
  2621. { 0x1f, 0x0000 },
  2622. /* Channel estimation fine tune */
  2623. { 0x1f, 0x0003 },
  2624. { 0x09, 0xa20f },
  2625. { 0x1f, 0x0000 },
  2626. { 0x1f, 0x0000 },
  2627. /* Green Setting */
  2628. { 0x1f, 0x0005 },
  2629. { 0x05, 0x8b5b },
  2630. { 0x06, 0x9222 },
  2631. { 0x05, 0x8b6d },
  2632. { 0x06, 0x8000 },
  2633. { 0x05, 0x8b76 },
  2634. { 0x06, 0x8000 },
  2635. { 0x1f, 0x0000 }
  2636. };
  2637. rtl_apply_firmware(tp);
  2638. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2639. /* For 4-corner performance improve */
  2640. rtl_writephy(tp, 0x1f, 0x0005);
  2641. rtl_writephy(tp, 0x05, 0x8b80);
  2642. rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
  2643. rtl_writephy(tp, 0x1f, 0x0000);
  2644. /* PHY auto speed down */
  2645. rtl_writephy(tp, 0x1f, 0x0004);
  2646. rtl_writephy(tp, 0x1f, 0x0007);
  2647. rtl_writephy(tp, 0x1e, 0x002d);
  2648. rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
  2649. rtl_writephy(tp, 0x1f, 0x0002);
  2650. rtl_writephy(tp, 0x1f, 0x0000);
  2651. rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
  2652. /* improve 10M EEE waveform */
  2653. rtl_writephy(tp, 0x1f, 0x0005);
  2654. rtl_writephy(tp, 0x05, 0x8b86);
  2655. rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
  2656. rtl_writephy(tp, 0x1f, 0x0000);
  2657. /* Improve 2-pair detection performance */
  2658. rtl_writephy(tp, 0x1f, 0x0005);
  2659. rtl_writephy(tp, 0x05, 0x8b85);
  2660. rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
  2661. rtl_writephy(tp, 0x1f, 0x0000);
  2662. /* EEE setting */
  2663. rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
  2664. rtl_writephy(tp, 0x1f, 0x0005);
  2665. rtl_writephy(tp, 0x05, 0x8b85);
  2666. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
  2667. rtl_writephy(tp, 0x1f, 0x0004);
  2668. rtl_writephy(tp, 0x1f, 0x0007);
  2669. rtl_writephy(tp, 0x1e, 0x0020);
  2670. rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
  2671. rtl_writephy(tp, 0x1f, 0x0002);
  2672. rtl_writephy(tp, 0x1f, 0x0000);
  2673. rtl_writephy(tp, 0x0d, 0x0007);
  2674. rtl_writephy(tp, 0x0e, 0x003c);
  2675. rtl_writephy(tp, 0x0d, 0x4007);
  2676. rtl_writephy(tp, 0x0e, 0x0000);
  2677. rtl_writephy(tp, 0x0d, 0x0000);
  2678. /* Green feature */
  2679. rtl_writephy(tp, 0x1f, 0x0003);
  2680. rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
  2681. rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
  2682. rtl_writephy(tp, 0x1f, 0x0000);
  2683. }
  2684. static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
  2685. {
  2686. /* For 4-corner performance improve */
  2687. rtl_writephy(tp, 0x1f, 0x0005);
  2688. rtl_writephy(tp, 0x05, 0x8b80);
  2689. rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
  2690. rtl_writephy(tp, 0x1f, 0x0000);
  2691. /* PHY auto speed down */
  2692. rtl_writephy(tp, 0x1f, 0x0007);
  2693. rtl_writephy(tp, 0x1e, 0x002d);
  2694. rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
  2695. rtl_writephy(tp, 0x1f, 0x0000);
  2696. rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
  2697. /* Improve 10M EEE waveform */
  2698. rtl_writephy(tp, 0x1f, 0x0005);
  2699. rtl_writephy(tp, 0x05, 0x8b86);
  2700. rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
  2701. rtl_writephy(tp, 0x1f, 0x0000);
  2702. }
  2703. static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
  2704. {
  2705. static const struct phy_reg phy_reg_init[] = {
  2706. /* Channel estimation fine tune */
  2707. { 0x1f, 0x0003 },
  2708. { 0x09, 0xa20f },
  2709. { 0x1f, 0x0000 },
  2710. /* Modify green table for giga & fnet */
  2711. { 0x1f, 0x0005 },
  2712. { 0x05, 0x8b55 },
  2713. { 0x06, 0x0000 },
  2714. { 0x05, 0x8b5e },
  2715. { 0x06, 0x0000 },
  2716. { 0x05, 0x8b67 },
  2717. { 0x06, 0x0000 },
  2718. { 0x05, 0x8b70 },
  2719. { 0x06, 0x0000 },
  2720. { 0x1f, 0x0000 },
  2721. { 0x1f, 0x0007 },
  2722. { 0x1e, 0x0078 },
  2723. { 0x17, 0x0000 },
  2724. { 0x19, 0x00fb },
  2725. { 0x1f, 0x0000 },
  2726. /* Modify green table for 10M */
  2727. { 0x1f, 0x0005 },
  2728. { 0x05, 0x8b79 },
  2729. { 0x06, 0xaa00 },
  2730. { 0x1f, 0x0000 },
  2731. /* Disable hiimpedance detection (RTCT) */
  2732. { 0x1f, 0x0003 },
  2733. { 0x01, 0x328a },
  2734. { 0x1f, 0x0000 }
  2735. };
  2736. rtl_apply_firmware(tp);
  2737. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2738. rtl8168f_hw_phy_config(tp);
  2739. /* Improve 2-pair detection performance */
  2740. rtl_writephy(tp, 0x1f, 0x0005);
  2741. rtl_writephy(tp, 0x05, 0x8b85);
  2742. rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
  2743. rtl_writephy(tp, 0x1f, 0x0000);
  2744. }
  2745. static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
  2746. {
  2747. rtl_apply_firmware(tp);
  2748. rtl8168f_hw_phy_config(tp);
  2749. }
  2750. static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
  2751. {
  2752. static const struct phy_reg phy_reg_init[] = {
  2753. /* Channel estimation fine tune */
  2754. { 0x1f, 0x0003 },
  2755. { 0x09, 0xa20f },
  2756. { 0x1f, 0x0000 },
  2757. /* Modify green table for giga & fnet */
  2758. { 0x1f, 0x0005 },
  2759. { 0x05, 0x8b55 },
  2760. { 0x06, 0x0000 },
  2761. { 0x05, 0x8b5e },
  2762. { 0x06, 0x0000 },
  2763. { 0x05, 0x8b67 },
  2764. { 0x06, 0x0000 },
  2765. { 0x05, 0x8b70 },
  2766. { 0x06, 0x0000 },
  2767. { 0x1f, 0x0000 },
  2768. { 0x1f, 0x0007 },
  2769. { 0x1e, 0x0078 },
  2770. { 0x17, 0x0000 },
  2771. { 0x19, 0x00aa },
  2772. { 0x1f, 0x0000 },
  2773. /* Modify green table for 10M */
  2774. { 0x1f, 0x0005 },
  2775. { 0x05, 0x8b79 },
  2776. { 0x06, 0xaa00 },
  2777. { 0x1f, 0x0000 },
  2778. /* Disable hiimpedance detection (RTCT) */
  2779. { 0x1f, 0x0003 },
  2780. { 0x01, 0x328a },
  2781. { 0x1f, 0x0000 }
  2782. };
  2783. rtl_apply_firmware(tp);
  2784. rtl8168f_hw_phy_config(tp);
  2785. /* Improve 2-pair detection performance */
  2786. rtl_writephy(tp, 0x1f, 0x0005);
  2787. rtl_writephy(tp, 0x05, 0x8b85);
  2788. rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
  2789. rtl_writephy(tp, 0x1f, 0x0000);
  2790. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2791. /* Modify green table for giga */
  2792. rtl_writephy(tp, 0x1f, 0x0005);
  2793. rtl_writephy(tp, 0x05, 0x8b54);
  2794. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
  2795. rtl_writephy(tp, 0x05, 0x8b5d);
  2796. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
  2797. rtl_writephy(tp, 0x05, 0x8a7c);
  2798. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
  2799. rtl_writephy(tp, 0x05, 0x8a7f);
  2800. rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
  2801. rtl_writephy(tp, 0x05, 0x8a82);
  2802. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
  2803. rtl_writephy(tp, 0x05, 0x8a85);
  2804. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
  2805. rtl_writephy(tp, 0x05, 0x8a88);
  2806. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
  2807. rtl_writephy(tp, 0x1f, 0x0000);
  2808. /* uc same-seed solution */
  2809. rtl_writephy(tp, 0x1f, 0x0005);
  2810. rtl_writephy(tp, 0x05, 0x8b85);
  2811. rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
  2812. rtl_writephy(tp, 0x1f, 0x0000);
  2813. /* eee setting */
  2814. rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
  2815. rtl_writephy(tp, 0x1f, 0x0005);
  2816. rtl_writephy(tp, 0x05, 0x8b85);
  2817. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
  2818. rtl_writephy(tp, 0x1f, 0x0004);
  2819. rtl_writephy(tp, 0x1f, 0x0007);
  2820. rtl_writephy(tp, 0x1e, 0x0020);
  2821. rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
  2822. rtl_writephy(tp, 0x1f, 0x0000);
  2823. rtl_writephy(tp, 0x0d, 0x0007);
  2824. rtl_writephy(tp, 0x0e, 0x003c);
  2825. rtl_writephy(tp, 0x0d, 0x4007);
  2826. rtl_writephy(tp, 0x0e, 0x0000);
  2827. rtl_writephy(tp, 0x0d, 0x0000);
  2828. /* Green feature */
  2829. rtl_writephy(tp, 0x1f, 0x0003);
  2830. rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
  2831. rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
  2832. rtl_writephy(tp, 0x1f, 0x0000);
  2833. }
  2834. static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
  2835. {
  2836. static const u16 mac_ocp_patch[] = {
  2837. 0xe008, 0xe01b, 0xe01d, 0xe01f,
  2838. 0xe021, 0xe023, 0xe025, 0xe027,
  2839. 0x49d2, 0xf10d, 0x766c, 0x49e2,
  2840. 0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
  2841. 0x77c0, 0x4870, 0x9fc0, 0x1ea0,
  2842. 0xc707, 0x8ee1, 0x9d6c, 0xc603,
  2843. 0xbe00, 0xb416, 0x0076, 0xe86c,
  2844. 0xc602, 0xbe00, 0x0000, 0xc602,
  2845. 0xbe00, 0x0000, 0xc602, 0xbe00,
  2846. 0x0000, 0xc602, 0xbe00, 0x0000,
  2847. 0xc602, 0xbe00, 0x0000, 0xc602,
  2848. 0xbe00, 0x0000, 0xc602, 0xbe00,
  2849. 0x0000, 0x0000, 0x0000, 0x0000
  2850. };
  2851. u32 i;
  2852. /* Patch code for GPHY reset */
  2853. for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
  2854. r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
  2855. r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
  2856. r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
  2857. rtl_apply_firmware(tp);
  2858. if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
  2859. rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
  2860. else
  2861. rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
  2862. if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
  2863. rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
  2864. else
  2865. rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
  2866. rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
  2867. rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
  2868. r8168_phy_ocp_write(tp, 0xa436, 0x8012);
  2869. rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
  2870. rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
  2871. }
  2872. static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
  2873. {
  2874. static const struct phy_reg phy_reg_init[] = {
  2875. { 0x1f, 0x0003 },
  2876. { 0x08, 0x441d },
  2877. { 0x01, 0x9100 },
  2878. { 0x1f, 0x0000 }
  2879. };
  2880. rtl_writephy(tp, 0x1f, 0x0000);
  2881. rtl_patchphy(tp, 0x11, 1 << 12);
  2882. rtl_patchphy(tp, 0x19, 1 << 13);
  2883. rtl_patchphy(tp, 0x10, 1 << 15);
  2884. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2885. }
  2886. static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
  2887. {
  2888. static const struct phy_reg phy_reg_init[] = {
  2889. { 0x1f, 0x0005 },
  2890. { 0x1a, 0x0000 },
  2891. { 0x1f, 0x0000 },
  2892. { 0x1f, 0x0004 },
  2893. { 0x1c, 0x0000 },
  2894. { 0x1f, 0x0000 },
  2895. { 0x1f, 0x0001 },
  2896. { 0x15, 0x7701 },
  2897. { 0x1f, 0x0000 }
  2898. };
  2899. /* Disable ALDPS before ram code */
  2900. rtl_writephy(tp, 0x1f, 0x0000);
  2901. rtl_writephy(tp, 0x18, 0x0310);
  2902. msleep(100);
  2903. rtl_apply_firmware(tp);
  2904. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2905. }
  2906. static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
  2907. {
  2908. /* Disable ALDPS before setting firmware */
  2909. rtl_writephy(tp, 0x1f, 0x0000);
  2910. rtl_writephy(tp, 0x18, 0x0310);
  2911. msleep(20);
  2912. rtl_apply_firmware(tp);
  2913. /* EEE setting */
  2914. rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  2915. rtl_writephy(tp, 0x1f, 0x0004);
  2916. rtl_writephy(tp, 0x10, 0x401f);
  2917. rtl_writephy(tp, 0x19, 0x7030);
  2918. rtl_writephy(tp, 0x1f, 0x0000);
  2919. }
  2920. static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
  2921. {
  2922. static const struct phy_reg phy_reg_init[] = {
  2923. { 0x1f, 0x0004 },
  2924. { 0x10, 0xc07f },
  2925. { 0x19, 0x7030 },
  2926. { 0x1f, 0x0000 }
  2927. };
  2928. /* Disable ALDPS before ram code */
  2929. rtl_writephy(tp, 0x1f, 0x0000);
  2930. rtl_writephy(tp, 0x18, 0x0310);
  2931. msleep(100);
  2932. rtl_apply_firmware(tp);
  2933. rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  2934. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2935. rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  2936. }
  2937. static void rtl_hw_phy_config(struct net_device *dev)
  2938. {
  2939. struct rtl8169_private *tp = netdev_priv(dev);
  2940. rtl8169_print_mac_version(tp);
  2941. switch (tp->mac_version) {
  2942. case RTL_GIGA_MAC_VER_01:
  2943. break;
  2944. case RTL_GIGA_MAC_VER_02:
  2945. case RTL_GIGA_MAC_VER_03:
  2946. rtl8169s_hw_phy_config(tp);
  2947. break;
  2948. case RTL_GIGA_MAC_VER_04:
  2949. rtl8169sb_hw_phy_config(tp);
  2950. break;
  2951. case RTL_GIGA_MAC_VER_05:
  2952. rtl8169scd_hw_phy_config(tp);
  2953. break;
  2954. case RTL_GIGA_MAC_VER_06:
  2955. rtl8169sce_hw_phy_config(tp);
  2956. break;
  2957. case RTL_GIGA_MAC_VER_07:
  2958. case RTL_GIGA_MAC_VER_08:
  2959. case RTL_GIGA_MAC_VER_09:
  2960. rtl8102e_hw_phy_config(tp);
  2961. break;
  2962. case RTL_GIGA_MAC_VER_11:
  2963. rtl8168bb_hw_phy_config(tp);
  2964. break;
  2965. case RTL_GIGA_MAC_VER_12:
  2966. rtl8168bef_hw_phy_config(tp);
  2967. break;
  2968. case RTL_GIGA_MAC_VER_17:
  2969. rtl8168bef_hw_phy_config(tp);
  2970. break;
  2971. case RTL_GIGA_MAC_VER_18:
  2972. rtl8168cp_1_hw_phy_config(tp);
  2973. break;
  2974. case RTL_GIGA_MAC_VER_19:
  2975. rtl8168c_1_hw_phy_config(tp);
  2976. break;
  2977. case RTL_GIGA_MAC_VER_20:
  2978. rtl8168c_2_hw_phy_config(tp);
  2979. break;
  2980. case RTL_GIGA_MAC_VER_21:
  2981. rtl8168c_3_hw_phy_config(tp);
  2982. break;
  2983. case RTL_GIGA_MAC_VER_22:
  2984. rtl8168c_4_hw_phy_config(tp);
  2985. break;
  2986. case RTL_GIGA_MAC_VER_23:
  2987. case RTL_GIGA_MAC_VER_24:
  2988. rtl8168cp_2_hw_phy_config(tp);
  2989. break;
  2990. case RTL_GIGA_MAC_VER_25:
  2991. rtl8168d_1_hw_phy_config(tp);
  2992. break;
  2993. case RTL_GIGA_MAC_VER_26:
  2994. rtl8168d_2_hw_phy_config(tp);
  2995. break;
  2996. case RTL_GIGA_MAC_VER_27:
  2997. rtl8168d_3_hw_phy_config(tp);
  2998. break;
  2999. case RTL_GIGA_MAC_VER_28:
  3000. rtl8168d_4_hw_phy_config(tp);
  3001. break;
  3002. case RTL_GIGA_MAC_VER_29:
  3003. case RTL_GIGA_MAC_VER_30:
  3004. rtl8105e_hw_phy_config(tp);
  3005. break;
  3006. case RTL_GIGA_MAC_VER_31:
  3007. /* None. */
  3008. break;
  3009. case RTL_GIGA_MAC_VER_32:
  3010. case RTL_GIGA_MAC_VER_33:
  3011. rtl8168e_1_hw_phy_config(tp);
  3012. break;
  3013. case RTL_GIGA_MAC_VER_34:
  3014. rtl8168e_2_hw_phy_config(tp);
  3015. break;
  3016. case RTL_GIGA_MAC_VER_35:
  3017. rtl8168f_1_hw_phy_config(tp);
  3018. break;
  3019. case RTL_GIGA_MAC_VER_36:
  3020. rtl8168f_2_hw_phy_config(tp);
  3021. break;
  3022. case RTL_GIGA_MAC_VER_37:
  3023. rtl8402_hw_phy_config(tp);
  3024. break;
  3025. case RTL_GIGA_MAC_VER_38:
  3026. rtl8411_hw_phy_config(tp);
  3027. break;
  3028. case RTL_GIGA_MAC_VER_39:
  3029. rtl8106e_hw_phy_config(tp);
  3030. break;
  3031. case RTL_GIGA_MAC_VER_40:
  3032. rtl8168g_1_hw_phy_config(tp);
  3033. break;
  3034. case RTL_GIGA_MAC_VER_41:
  3035. default:
  3036. break;
  3037. }
  3038. }
  3039. static void rtl_phy_work(struct rtl8169_private *tp)
  3040. {
  3041. struct timer_list *timer = &tp->timer;
  3042. void __iomem *ioaddr = tp->mmio_addr;
  3043. unsigned long timeout = RTL8169_PHY_TIMEOUT;
  3044. assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
  3045. if (tp->phy_reset_pending(tp)) {
  3046. /*
  3047. * A busy loop could burn quite a few cycles on nowadays CPU.
  3048. * Let's delay the execution of the timer for a few ticks.
  3049. */
  3050. timeout = HZ/10;
  3051. goto out_mod_timer;
  3052. }
  3053. if (tp->link_ok(ioaddr))
  3054. return;
  3055. netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
  3056. tp->phy_reset_enable(tp);
  3057. out_mod_timer:
  3058. mod_timer(timer, jiffies + timeout);
  3059. }
  3060. static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
  3061. {
  3062. if (!test_and_set_bit(flag, tp->wk.flags))
  3063. schedule_work(&tp->wk.work);
  3064. }
  3065. static void rtl8169_phy_timer(unsigned long __opaque)
  3066. {
  3067. struct net_device *dev = (struct net_device *)__opaque;
  3068. struct rtl8169_private *tp = netdev_priv(dev);
  3069. rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
  3070. }
  3071. static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
  3072. void __iomem *ioaddr)
  3073. {
  3074. iounmap(ioaddr);
  3075. pci_release_regions(pdev);
  3076. pci_clear_mwi(pdev);
  3077. pci_disable_device(pdev);
  3078. free_netdev(dev);
  3079. }
  3080. DECLARE_RTL_COND(rtl_phy_reset_cond)
  3081. {
  3082. return tp->phy_reset_pending(tp);
  3083. }
  3084. static void rtl8169_phy_reset(struct net_device *dev,
  3085. struct rtl8169_private *tp)
  3086. {
  3087. tp->phy_reset_enable(tp);
  3088. rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
  3089. }
  3090. static bool rtl_tbi_enabled(struct rtl8169_private *tp)
  3091. {
  3092. void __iomem *ioaddr = tp->mmio_addr;
  3093. return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
  3094. (RTL_R8(PHYstatus) & TBI_Enable);
  3095. }
  3096. static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
  3097. {
  3098. void __iomem *ioaddr = tp->mmio_addr;
  3099. rtl_hw_phy_config(dev);
  3100. if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
  3101. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  3102. RTL_W8(0x82, 0x01);
  3103. }
  3104. pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
  3105. if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
  3106. pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
  3107. if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
  3108. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  3109. RTL_W8(0x82, 0x01);
  3110. dprintk("Set PHY Reg 0x0bh = 0x00h\n");
  3111. rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
  3112. }
  3113. rtl8169_phy_reset(dev, tp);
  3114. rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
  3115. ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3116. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  3117. (tp->mii.supports_gmii ?
  3118. ADVERTISED_1000baseT_Half |
  3119. ADVERTISED_1000baseT_Full : 0));
  3120. if (rtl_tbi_enabled(tp))
  3121. netif_info(tp, link, dev, "TBI auto-negotiating\n");
  3122. }
  3123. static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
  3124. {
  3125. void __iomem *ioaddr = tp->mmio_addr;
  3126. u32 high;
  3127. u32 low;
  3128. low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
  3129. high = addr[4] | (addr[5] << 8);
  3130. rtl_lock_work(tp);
  3131. RTL_W8(Cfg9346, Cfg9346_Unlock);
  3132. RTL_W32(MAC4, high);
  3133. RTL_R32(MAC4);
  3134. RTL_W32(MAC0, low);
  3135. RTL_R32(MAC0);
  3136. if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
  3137. const struct exgmac_reg e[] = {
  3138. { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
  3139. { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
  3140. { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
  3141. { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
  3142. low >> 16 },
  3143. };
  3144. rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
  3145. }
  3146. RTL_W8(Cfg9346, Cfg9346_Lock);
  3147. rtl_unlock_work(tp);
  3148. }
  3149. static int rtl_set_mac_address(struct net_device *dev, void *p)
  3150. {
  3151. struct rtl8169_private *tp = netdev_priv(dev);
  3152. struct sockaddr *addr = p;
  3153. if (!is_valid_ether_addr(addr->sa_data))
  3154. return -EADDRNOTAVAIL;
  3155. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  3156. rtl_rar_set(tp, dev->dev_addr);
  3157. return 0;
  3158. }
  3159. static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3160. {
  3161. struct rtl8169_private *tp = netdev_priv(dev);
  3162. struct mii_ioctl_data *data = if_mii(ifr);
  3163. return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
  3164. }
  3165. static int rtl_xmii_ioctl(struct rtl8169_private *tp,
  3166. struct mii_ioctl_data *data, int cmd)
  3167. {
  3168. switch (cmd) {
  3169. case SIOCGMIIPHY:
  3170. data->phy_id = 32; /* Internal PHY */
  3171. return 0;
  3172. case SIOCGMIIREG:
  3173. data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
  3174. return 0;
  3175. case SIOCSMIIREG:
  3176. rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
  3177. return 0;
  3178. }
  3179. return -EOPNOTSUPP;
  3180. }
  3181. static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
  3182. {
  3183. return -EOPNOTSUPP;
  3184. }
  3185. static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
  3186. {
  3187. if (tp->features & RTL_FEATURE_MSI) {
  3188. pci_disable_msi(pdev);
  3189. tp->features &= ~RTL_FEATURE_MSI;
  3190. }
  3191. }
  3192. static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
  3193. {
  3194. struct mdio_ops *ops = &tp->mdio_ops;
  3195. switch (tp->mac_version) {
  3196. case RTL_GIGA_MAC_VER_27:
  3197. ops->write = r8168dp_1_mdio_write;
  3198. ops->read = r8168dp_1_mdio_read;
  3199. break;
  3200. case RTL_GIGA_MAC_VER_28:
  3201. case RTL_GIGA_MAC_VER_31:
  3202. ops->write = r8168dp_2_mdio_write;
  3203. ops->read = r8168dp_2_mdio_read;
  3204. break;
  3205. case RTL_GIGA_MAC_VER_40:
  3206. case RTL_GIGA_MAC_VER_41:
  3207. ops->write = r8168g_mdio_write;
  3208. ops->read = r8168g_mdio_read;
  3209. break;
  3210. default:
  3211. ops->write = r8169_mdio_write;
  3212. ops->read = r8169_mdio_read;
  3213. break;
  3214. }
  3215. }
  3216. static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
  3217. {
  3218. void __iomem *ioaddr = tp->mmio_addr;
  3219. switch (tp->mac_version) {
  3220. case RTL_GIGA_MAC_VER_25:
  3221. case RTL_GIGA_MAC_VER_26:
  3222. case RTL_GIGA_MAC_VER_29:
  3223. case RTL_GIGA_MAC_VER_30:
  3224. case RTL_GIGA_MAC_VER_32:
  3225. case RTL_GIGA_MAC_VER_33:
  3226. case RTL_GIGA_MAC_VER_34:
  3227. case RTL_GIGA_MAC_VER_37:
  3228. case RTL_GIGA_MAC_VER_38:
  3229. case RTL_GIGA_MAC_VER_39:
  3230. case RTL_GIGA_MAC_VER_40:
  3231. case RTL_GIGA_MAC_VER_41:
  3232. RTL_W32(RxConfig, RTL_R32(RxConfig) |
  3233. AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
  3234. break;
  3235. default:
  3236. break;
  3237. }
  3238. }
  3239. static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
  3240. {
  3241. if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
  3242. return false;
  3243. rtl_writephy(tp, 0x1f, 0x0000);
  3244. rtl_writephy(tp, MII_BMCR, 0x0000);
  3245. rtl_wol_suspend_quirk(tp);
  3246. return true;
  3247. }
  3248. static void r810x_phy_power_down(struct rtl8169_private *tp)
  3249. {
  3250. rtl_writephy(tp, 0x1f, 0x0000);
  3251. rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
  3252. }
  3253. static void r810x_phy_power_up(struct rtl8169_private *tp)
  3254. {
  3255. rtl_writephy(tp, 0x1f, 0x0000);
  3256. rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
  3257. }
  3258. static void r810x_pll_power_down(struct rtl8169_private *tp)
  3259. {
  3260. void __iomem *ioaddr = tp->mmio_addr;
  3261. if (rtl_wol_pll_power_down(tp))
  3262. return;
  3263. r810x_phy_power_down(tp);
  3264. switch (tp->mac_version) {
  3265. case RTL_GIGA_MAC_VER_07:
  3266. case RTL_GIGA_MAC_VER_08:
  3267. case RTL_GIGA_MAC_VER_09:
  3268. case RTL_GIGA_MAC_VER_10:
  3269. case RTL_GIGA_MAC_VER_13:
  3270. case RTL_GIGA_MAC_VER_16:
  3271. break;
  3272. default:
  3273. RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
  3274. break;
  3275. }
  3276. }
  3277. static void r810x_pll_power_up(struct rtl8169_private *tp)
  3278. {
  3279. void __iomem *ioaddr = tp->mmio_addr;
  3280. r810x_phy_power_up(tp);
  3281. switch (tp->mac_version) {
  3282. case RTL_GIGA_MAC_VER_07:
  3283. case RTL_GIGA_MAC_VER_08:
  3284. case RTL_GIGA_MAC_VER_09:
  3285. case RTL_GIGA_MAC_VER_10:
  3286. case RTL_GIGA_MAC_VER_13:
  3287. case RTL_GIGA_MAC_VER_16:
  3288. break;
  3289. default:
  3290. RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
  3291. break;
  3292. }
  3293. }
  3294. static void r8168_phy_power_up(struct rtl8169_private *tp)
  3295. {
  3296. rtl_writephy(tp, 0x1f, 0x0000);
  3297. switch (tp->mac_version) {
  3298. case RTL_GIGA_MAC_VER_11:
  3299. case RTL_GIGA_MAC_VER_12:
  3300. case RTL_GIGA_MAC_VER_17:
  3301. case RTL_GIGA_MAC_VER_18:
  3302. case RTL_GIGA_MAC_VER_19:
  3303. case RTL_GIGA_MAC_VER_20:
  3304. case RTL_GIGA_MAC_VER_21:
  3305. case RTL_GIGA_MAC_VER_22:
  3306. case RTL_GIGA_MAC_VER_23:
  3307. case RTL_GIGA_MAC_VER_24:
  3308. case RTL_GIGA_MAC_VER_25:
  3309. case RTL_GIGA_MAC_VER_26:
  3310. case RTL_GIGA_MAC_VER_27:
  3311. case RTL_GIGA_MAC_VER_28:
  3312. case RTL_GIGA_MAC_VER_31:
  3313. rtl_writephy(tp, 0x0e, 0x0000);
  3314. break;
  3315. default:
  3316. break;
  3317. }
  3318. rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
  3319. }
  3320. static void r8168_phy_power_down(struct rtl8169_private *tp)
  3321. {
  3322. rtl_writephy(tp, 0x1f, 0x0000);
  3323. switch (tp->mac_version) {
  3324. case RTL_GIGA_MAC_VER_32:
  3325. case RTL_GIGA_MAC_VER_33:
  3326. rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
  3327. break;
  3328. case RTL_GIGA_MAC_VER_11:
  3329. case RTL_GIGA_MAC_VER_12:
  3330. case RTL_GIGA_MAC_VER_17:
  3331. case RTL_GIGA_MAC_VER_18:
  3332. case RTL_GIGA_MAC_VER_19:
  3333. case RTL_GIGA_MAC_VER_20:
  3334. case RTL_GIGA_MAC_VER_21:
  3335. case RTL_GIGA_MAC_VER_22:
  3336. case RTL_GIGA_MAC_VER_23:
  3337. case RTL_GIGA_MAC_VER_24:
  3338. case RTL_GIGA_MAC_VER_25:
  3339. case RTL_GIGA_MAC_VER_26:
  3340. case RTL_GIGA_MAC_VER_27:
  3341. case RTL_GIGA_MAC_VER_28:
  3342. case RTL_GIGA_MAC_VER_31:
  3343. rtl_writephy(tp, 0x0e, 0x0200);
  3344. default:
  3345. rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
  3346. break;
  3347. }
  3348. }
  3349. static void r8168_pll_power_down(struct rtl8169_private *tp)
  3350. {
  3351. void __iomem *ioaddr = tp->mmio_addr;
  3352. if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  3353. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  3354. tp->mac_version == RTL_GIGA_MAC_VER_31) &&
  3355. r8168dp_check_dash(tp)) {
  3356. return;
  3357. }
  3358. if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
  3359. tp->mac_version == RTL_GIGA_MAC_VER_24) &&
  3360. (RTL_R16(CPlusCmd) & ASF)) {
  3361. return;
  3362. }
  3363. if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
  3364. tp->mac_version == RTL_GIGA_MAC_VER_33)
  3365. rtl_ephy_write(tp, 0x19, 0xff64);
  3366. if (rtl_wol_pll_power_down(tp))
  3367. return;
  3368. r8168_phy_power_down(tp);
  3369. switch (tp->mac_version) {
  3370. case RTL_GIGA_MAC_VER_25:
  3371. case RTL_GIGA_MAC_VER_26:
  3372. case RTL_GIGA_MAC_VER_27:
  3373. case RTL_GIGA_MAC_VER_28:
  3374. case RTL_GIGA_MAC_VER_31:
  3375. case RTL_GIGA_MAC_VER_32:
  3376. case RTL_GIGA_MAC_VER_33:
  3377. RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
  3378. break;
  3379. }
  3380. }
  3381. static void r8168_pll_power_up(struct rtl8169_private *tp)
  3382. {
  3383. void __iomem *ioaddr = tp->mmio_addr;
  3384. switch (tp->mac_version) {
  3385. case RTL_GIGA_MAC_VER_25:
  3386. case RTL_GIGA_MAC_VER_26:
  3387. case RTL_GIGA_MAC_VER_27:
  3388. case RTL_GIGA_MAC_VER_28:
  3389. case RTL_GIGA_MAC_VER_31:
  3390. case RTL_GIGA_MAC_VER_32:
  3391. case RTL_GIGA_MAC_VER_33:
  3392. RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
  3393. break;
  3394. }
  3395. r8168_phy_power_up(tp);
  3396. }
  3397. static void rtl_generic_op(struct rtl8169_private *tp,
  3398. void (*op)(struct rtl8169_private *))
  3399. {
  3400. if (op)
  3401. op(tp);
  3402. }
  3403. static void rtl_pll_power_down(struct rtl8169_private *tp)
  3404. {
  3405. rtl_generic_op(tp, tp->pll_power_ops.down);
  3406. }
  3407. static void rtl_pll_power_up(struct rtl8169_private *tp)
  3408. {
  3409. rtl_generic_op(tp, tp->pll_power_ops.up);
  3410. }
  3411. static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
  3412. {
  3413. struct pll_power_ops *ops = &tp->pll_power_ops;
  3414. switch (tp->mac_version) {
  3415. case RTL_GIGA_MAC_VER_07:
  3416. case RTL_GIGA_MAC_VER_08:
  3417. case RTL_GIGA_MAC_VER_09:
  3418. case RTL_GIGA_MAC_VER_10:
  3419. case RTL_GIGA_MAC_VER_16:
  3420. case RTL_GIGA_MAC_VER_29:
  3421. case RTL_GIGA_MAC_VER_30:
  3422. case RTL_GIGA_MAC_VER_37:
  3423. case RTL_GIGA_MAC_VER_39:
  3424. ops->down = r810x_pll_power_down;
  3425. ops->up = r810x_pll_power_up;
  3426. break;
  3427. case RTL_GIGA_MAC_VER_11:
  3428. case RTL_GIGA_MAC_VER_12:
  3429. case RTL_GIGA_MAC_VER_17:
  3430. case RTL_GIGA_MAC_VER_18:
  3431. case RTL_GIGA_MAC_VER_19:
  3432. case RTL_GIGA_MAC_VER_20:
  3433. case RTL_GIGA_MAC_VER_21:
  3434. case RTL_GIGA_MAC_VER_22:
  3435. case RTL_GIGA_MAC_VER_23:
  3436. case RTL_GIGA_MAC_VER_24:
  3437. case RTL_GIGA_MAC_VER_25:
  3438. case RTL_GIGA_MAC_VER_26:
  3439. case RTL_GIGA_MAC_VER_27:
  3440. case RTL_GIGA_MAC_VER_28:
  3441. case RTL_GIGA_MAC_VER_31:
  3442. case RTL_GIGA_MAC_VER_32:
  3443. case RTL_GIGA_MAC_VER_33:
  3444. case RTL_GIGA_MAC_VER_34:
  3445. case RTL_GIGA_MAC_VER_35:
  3446. case RTL_GIGA_MAC_VER_36:
  3447. case RTL_GIGA_MAC_VER_38:
  3448. case RTL_GIGA_MAC_VER_40:
  3449. case RTL_GIGA_MAC_VER_41:
  3450. ops->down = r8168_pll_power_down;
  3451. ops->up = r8168_pll_power_up;
  3452. break;
  3453. default:
  3454. ops->down = NULL;
  3455. ops->up = NULL;
  3456. break;
  3457. }
  3458. }
  3459. static void rtl_init_rxcfg(struct rtl8169_private *tp)
  3460. {
  3461. void __iomem *ioaddr = tp->mmio_addr;
  3462. switch (tp->mac_version) {
  3463. case RTL_GIGA_MAC_VER_01:
  3464. case RTL_GIGA_MAC_VER_02:
  3465. case RTL_GIGA_MAC_VER_03:
  3466. case RTL_GIGA_MAC_VER_04:
  3467. case RTL_GIGA_MAC_VER_05:
  3468. case RTL_GIGA_MAC_VER_06:
  3469. case RTL_GIGA_MAC_VER_10:
  3470. case RTL_GIGA_MAC_VER_11:
  3471. case RTL_GIGA_MAC_VER_12:
  3472. case RTL_GIGA_MAC_VER_13:
  3473. case RTL_GIGA_MAC_VER_14:
  3474. case RTL_GIGA_MAC_VER_15:
  3475. case RTL_GIGA_MAC_VER_16:
  3476. case RTL_GIGA_MAC_VER_17:
  3477. RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
  3478. break;
  3479. case RTL_GIGA_MAC_VER_18:
  3480. case RTL_GIGA_MAC_VER_19:
  3481. case RTL_GIGA_MAC_VER_20:
  3482. case RTL_GIGA_MAC_VER_21:
  3483. case RTL_GIGA_MAC_VER_22:
  3484. case RTL_GIGA_MAC_VER_23:
  3485. case RTL_GIGA_MAC_VER_24:
  3486. case RTL_GIGA_MAC_VER_34:
  3487. RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
  3488. break;
  3489. default:
  3490. RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
  3491. break;
  3492. }
  3493. }
  3494. static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
  3495. {
  3496. tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
  3497. }
  3498. static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
  3499. {
  3500. void __iomem *ioaddr = tp->mmio_addr;
  3501. RTL_W8(Cfg9346, Cfg9346_Unlock);
  3502. rtl_generic_op(tp, tp->jumbo_ops.enable);
  3503. RTL_W8(Cfg9346, Cfg9346_Lock);
  3504. }
  3505. static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
  3506. {
  3507. void __iomem *ioaddr = tp->mmio_addr;
  3508. RTL_W8(Cfg9346, Cfg9346_Unlock);
  3509. rtl_generic_op(tp, tp->jumbo_ops.disable);
  3510. RTL_W8(Cfg9346, Cfg9346_Lock);
  3511. }
  3512. static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
  3513. {
  3514. void __iomem *ioaddr = tp->mmio_addr;
  3515. RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
  3516. RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
  3517. rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
  3518. }
  3519. static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
  3520. {
  3521. void __iomem *ioaddr = tp->mmio_addr;
  3522. RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
  3523. RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
  3524. rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
  3525. }
  3526. static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
  3527. {
  3528. void __iomem *ioaddr = tp->mmio_addr;
  3529. RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
  3530. }
  3531. static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
  3532. {
  3533. void __iomem *ioaddr = tp->mmio_addr;
  3534. RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
  3535. }
  3536. static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
  3537. {
  3538. void __iomem *ioaddr = tp->mmio_addr;
  3539. RTL_W8(MaxTxPacketSize, 0x3f);
  3540. RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
  3541. RTL_W8(Config4, RTL_R8(Config4) | 0x01);
  3542. rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
  3543. }
  3544. static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
  3545. {
  3546. void __iomem *ioaddr = tp->mmio_addr;
  3547. RTL_W8(MaxTxPacketSize, 0x0c);
  3548. RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
  3549. RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
  3550. rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
  3551. }
  3552. static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
  3553. {
  3554. rtl_tx_performance_tweak(tp->pci_dev,
  3555. (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
  3556. }
  3557. static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
  3558. {
  3559. rtl_tx_performance_tweak(tp->pci_dev,
  3560. (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
  3561. }
  3562. static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
  3563. {
  3564. void __iomem *ioaddr = tp->mmio_addr;
  3565. r8168b_0_hw_jumbo_enable(tp);
  3566. RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
  3567. }
  3568. static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
  3569. {
  3570. void __iomem *ioaddr = tp->mmio_addr;
  3571. r8168b_0_hw_jumbo_disable(tp);
  3572. RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
  3573. }
  3574. static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
  3575. {
  3576. struct jumbo_ops *ops = &tp->jumbo_ops;
  3577. switch (tp->mac_version) {
  3578. case RTL_GIGA_MAC_VER_11:
  3579. ops->disable = r8168b_0_hw_jumbo_disable;
  3580. ops->enable = r8168b_0_hw_jumbo_enable;
  3581. break;
  3582. case RTL_GIGA_MAC_VER_12:
  3583. case RTL_GIGA_MAC_VER_17:
  3584. ops->disable = r8168b_1_hw_jumbo_disable;
  3585. ops->enable = r8168b_1_hw_jumbo_enable;
  3586. break;
  3587. case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
  3588. case RTL_GIGA_MAC_VER_19:
  3589. case RTL_GIGA_MAC_VER_20:
  3590. case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
  3591. case RTL_GIGA_MAC_VER_22:
  3592. case RTL_GIGA_MAC_VER_23:
  3593. case RTL_GIGA_MAC_VER_24:
  3594. case RTL_GIGA_MAC_VER_25:
  3595. case RTL_GIGA_MAC_VER_26:
  3596. ops->disable = r8168c_hw_jumbo_disable;
  3597. ops->enable = r8168c_hw_jumbo_enable;
  3598. break;
  3599. case RTL_GIGA_MAC_VER_27:
  3600. case RTL_GIGA_MAC_VER_28:
  3601. ops->disable = r8168dp_hw_jumbo_disable;
  3602. ops->enable = r8168dp_hw_jumbo_enable;
  3603. break;
  3604. case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
  3605. case RTL_GIGA_MAC_VER_32:
  3606. case RTL_GIGA_MAC_VER_33:
  3607. case RTL_GIGA_MAC_VER_34:
  3608. ops->disable = r8168e_hw_jumbo_disable;
  3609. ops->enable = r8168e_hw_jumbo_enable;
  3610. break;
  3611. /*
  3612. * No action needed for jumbo frames with 8169.
  3613. * No jumbo for 810x at all.
  3614. */
  3615. case RTL_GIGA_MAC_VER_40:
  3616. case RTL_GIGA_MAC_VER_41:
  3617. default:
  3618. ops->disable = NULL;
  3619. ops->enable = NULL;
  3620. break;
  3621. }
  3622. }
  3623. DECLARE_RTL_COND(rtl_chipcmd_cond)
  3624. {
  3625. void __iomem *ioaddr = tp->mmio_addr;
  3626. return RTL_R8(ChipCmd) & CmdReset;
  3627. }
  3628. static void rtl_hw_reset(struct rtl8169_private *tp)
  3629. {
  3630. void __iomem *ioaddr = tp->mmio_addr;
  3631. RTL_W8(ChipCmd, CmdReset);
  3632. rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
  3633. }
  3634. static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
  3635. {
  3636. struct rtl_fw *rtl_fw;
  3637. const char *name;
  3638. int rc = -ENOMEM;
  3639. name = rtl_lookup_firmware_name(tp);
  3640. if (!name)
  3641. goto out_no_firmware;
  3642. rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
  3643. if (!rtl_fw)
  3644. goto err_warn;
  3645. rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
  3646. if (rc < 0)
  3647. goto err_free;
  3648. rc = rtl_check_firmware(tp, rtl_fw);
  3649. if (rc < 0)
  3650. goto err_release_firmware;
  3651. tp->rtl_fw = rtl_fw;
  3652. out:
  3653. return;
  3654. err_release_firmware:
  3655. release_firmware(rtl_fw->fw);
  3656. err_free:
  3657. kfree(rtl_fw);
  3658. err_warn:
  3659. netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
  3660. name, rc);
  3661. out_no_firmware:
  3662. tp->rtl_fw = NULL;
  3663. goto out;
  3664. }
  3665. static void rtl_request_firmware(struct rtl8169_private *tp)
  3666. {
  3667. if (IS_ERR(tp->rtl_fw))
  3668. rtl_request_uncached_firmware(tp);
  3669. }
  3670. static void rtl_rx_close(struct rtl8169_private *tp)
  3671. {
  3672. void __iomem *ioaddr = tp->mmio_addr;
  3673. RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
  3674. }
  3675. DECLARE_RTL_COND(rtl_npq_cond)
  3676. {
  3677. void __iomem *ioaddr = tp->mmio_addr;
  3678. return RTL_R8(TxPoll) & NPQ;
  3679. }
  3680. DECLARE_RTL_COND(rtl_txcfg_empty_cond)
  3681. {
  3682. void __iomem *ioaddr = tp->mmio_addr;
  3683. return RTL_R32(TxConfig) & TXCFG_EMPTY;
  3684. }
  3685. static void rtl8169_hw_reset(struct rtl8169_private *tp)
  3686. {
  3687. void __iomem *ioaddr = tp->mmio_addr;
  3688. /* Disable interrupts */
  3689. rtl8169_irq_mask_and_ack(tp);
  3690. rtl_rx_close(tp);
  3691. if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  3692. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  3693. tp->mac_version == RTL_GIGA_MAC_VER_31) {
  3694. rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
  3695. } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
  3696. tp->mac_version == RTL_GIGA_MAC_VER_35 ||
  3697. tp->mac_version == RTL_GIGA_MAC_VER_36 ||
  3698. tp->mac_version == RTL_GIGA_MAC_VER_37 ||
  3699. tp->mac_version == RTL_GIGA_MAC_VER_40 ||
  3700. tp->mac_version == RTL_GIGA_MAC_VER_41 ||
  3701. tp->mac_version == RTL_GIGA_MAC_VER_38) {
  3702. RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
  3703. rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
  3704. } else {
  3705. RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
  3706. udelay(100);
  3707. }
  3708. rtl_hw_reset(tp);
  3709. }
  3710. static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
  3711. {
  3712. void __iomem *ioaddr = tp->mmio_addr;
  3713. /* Set DMA burst size and Interframe Gap Time */
  3714. RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
  3715. (InterFrameGap << TxInterFrameGapShift));
  3716. }
  3717. static void rtl_hw_start(struct net_device *dev)
  3718. {
  3719. struct rtl8169_private *tp = netdev_priv(dev);
  3720. tp->hw_start(dev);
  3721. rtl_irq_enable_all(tp);
  3722. }
  3723. static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
  3724. void __iomem *ioaddr)
  3725. {
  3726. /*
  3727. * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
  3728. * register to be written before TxDescAddrLow to work.
  3729. * Switching from MMIO to I/O access fixes the issue as well.
  3730. */
  3731. RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
  3732. RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
  3733. RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
  3734. RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
  3735. }
  3736. static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
  3737. {
  3738. u16 cmd;
  3739. cmd = RTL_R16(CPlusCmd);
  3740. RTL_W16(CPlusCmd, cmd);
  3741. return cmd;
  3742. }
  3743. static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
  3744. {
  3745. /* Low hurts. Let's disable the filtering. */
  3746. RTL_W16(RxMaxSize, rx_buf_sz + 1);
  3747. }
  3748. static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
  3749. {
  3750. static const struct rtl_cfg2_info {
  3751. u32 mac_version;
  3752. u32 clk;
  3753. u32 val;
  3754. } cfg2_info [] = {
  3755. { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
  3756. { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
  3757. { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
  3758. { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
  3759. };
  3760. const struct rtl_cfg2_info *p = cfg2_info;
  3761. unsigned int i;
  3762. u32 clk;
  3763. clk = RTL_R8(Config2) & PCI_Clock_66MHz;
  3764. for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
  3765. if ((p->mac_version == mac_version) && (p->clk == clk)) {
  3766. RTL_W32(0x7c, p->val);
  3767. break;
  3768. }
  3769. }
  3770. }
  3771. static void rtl_set_rx_mode(struct net_device *dev)
  3772. {
  3773. struct rtl8169_private *tp = netdev_priv(dev);
  3774. void __iomem *ioaddr = tp->mmio_addr;
  3775. u32 mc_filter[2]; /* Multicast hash filter */
  3776. int rx_mode;
  3777. u32 tmp = 0;
  3778. if (dev->flags & IFF_PROMISC) {
  3779. /* Unconditionally log net taps. */
  3780. netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
  3781. rx_mode =
  3782. AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
  3783. AcceptAllPhys;
  3784. mc_filter[1] = mc_filter[0] = 0xffffffff;
  3785. } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
  3786. (dev->flags & IFF_ALLMULTI)) {
  3787. /* Too many to filter perfectly -- accept all multicasts. */
  3788. rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  3789. mc_filter[1] = mc_filter[0] = 0xffffffff;
  3790. } else {
  3791. struct netdev_hw_addr *ha;
  3792. rx_mode = AcceptBroadcast | AcceptMyPhys;
  3793. mc_filter[1] = mc_filter[0] = 0;
  3794. netdev_for_each_mc_addr(ha, dev) {
  3795. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  3796. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  3797. rx_mode |= AcceptMulticast;
  3798. }
  3799. }
  3800. if (dev->features & NETIF_F_RXALL)
  3801. rx_mode |= (AcceptErr | AcceptRunt);
  3802. tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
  3803. if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
  3804. u32 data = mc_filter[0];
  3805. mc_filter[0] = swab32(mc_filter[1]);
  3806. mc_filter[1] = swab32(data);
  3807. }
  3808. if (tp->mac_version == RTL_GIGA_MAC_VER_35)
  3809. mc_filter[1] = mc_filter[0] = 0xffffffff;
  3810. RTL_W32(MAR0 + 4, mc_filter[1]);
  3811. RTL_W32(MAR0 + 0, mc_filter[0]);
  3812. RTL_W32(RxConfig, tmp);
  3813. }
  3814. static void rtl_hw_start_8169(struct net_device *dev)
  3815. {
  3816. struct rtl8169_private *tp = netdev_priv(dev);
  3817. void __iomem *ioaddr = tp->mmio_addr;
  3818. struct pci_dev *pdev = tp->pci_dev;
  3819. if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
  3820. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
  3821. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
  3822. }
  3823. RTL_W8(Cfg9346, Cfg9346_Unlock);
  3824. if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
  3825. tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  3826. tp->mac_version == RTL_GIGA_MAC_VER_03 ||
  3827. tp->mac_version == RTL_GIGA_MAC_VER_04)
  3828. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  3829. rtl_init_rxcfg(tp);
  3830. RTL_W8(EarlyTxThres, NoEarlyTx);
  3831. rtl_set_rx_max_size(ioaddr, rx_buf_sz);
  3832. if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
  3833. tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  3834. tp->mac_version == RTL_GIGA_MAC_VER_03 ||
  3835. tp->mac_version == RTL_GIGA_MAC_VER_04)
  3836. rtl_set_rx_tx_config_registers(tp);
  3837. tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
  3838. if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  3839. tp->mac_version == RTL_GIGA_MAC_VER_03) {
  3840. dprintk("Set MAC Reg C+CR Offset 0xE0. "
  3841. "Bit-3 and bit-14 MUST be 1\n");
  3842. tp->cp_cmd |= (1 << 14);
  3843. }
  3844. RTL_W16(CPlusCmd, tp->cp_cmd);
  3845. rtl8169_set_magic_reg(ioaddr, tp->mac_version);
  3846. /*
  3847. * Undocumented corner. Supposedly:
  3848. * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
  3849. */
  3850. RTL_W16(IntrMitigate, 0x0000);
  3851. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  3852. if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
  3853. tp->mac_version != RTL_GIGA_MAC_VER_02 &&
  3854. tp->mac_version != RTL_GIGA_MAC_VER_03 &&
  3855. tp->mac_version != RTL_GIGA_MAC_VER_04) {
  3856. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  3857. rtl_set_rx_tx_config_registers(tp);
  3858. }
  3859. RTL_W8(Cfg9346, Cfg9346_Lock);
  3860. /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
  3861. RTL_R8(IntrMask);
  3862. RTL_W32(RxMissed, 0);
  3863. rtl_set_rx_mode(dev);
  3864. /* no early-rx interrupts */
  3865. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  3866. }
  3867. static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
  3868. {
  3869. if (tp->csi_ops.write)
  3870. tp->csi_ops.write(tp, addr, value);
  3871. }
  3872. static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
  3873. {
  3874. return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
  3875. }
  3876. static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
  3877. {
  3878. u32 csi;
  3879. csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
  3880. rtl_csi_write(tp, 0x070c, csi | bits);
  3881. }
  3882. static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
  3883. {
  3884. rtl_csi_access_enable(tp, 0x17000000);
  3885. }
  3886. static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
  3887. {
  3888. rtl_csi_access_enable(tp, 0x27000000);
  3889. }
  3890. DECLARE_RTL_COND(rtl_csiar_cond)
  3891. {
  3892. void __iomem *ioaddr = tp->mmio_addr;
  3893. return RTL_R32(CSIAR) & CSIAR_FLAG;
  3894. }
  3895. static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
  3896. {
  3897. void __iomem *ioaddr = tp->mmio_addr;
  3898. RTL_W32(CSIDR, value);
  3899. RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
  3900. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  3901. rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
  3902. }
  3903. static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
  3904. {
  3905. void __iomem *ioaddr = tp->mmio_addr;
  3906. RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
  3907. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  3908. return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
  3909. RTL_R32(CSIDR) : ~0;
  3910. }
  3911. static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
  3912. {
  3913. void __iomem *ioaddr = tp->mmio_addr;
  3914. RTL_W32(CSIDR, value);
  3915. RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
  3916. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
  3917. CSIAR_FUNC_NIC);
  3918. rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
  3919. }
  3920. static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
  3921. {
  3922. void __iomem *ioaddr = tp->mmio_addr;
  3923. RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
  3924. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  3925. return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
  3926. RTL_R32(CSIDR) : ~0;
  3927. }
  3928. static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
  3929. {
  3930. struct csi_ops *ops = &tp->csi_ops;
  3931. switch (tp->mac_version) {
  3932. case RTL_GIGA_MAC_VER_01:
  3933. case RTL_GIGA_MAC_VER_02:
  3934. case RTL_GIGA_MAC_VER_03:
  3935. case RTL_GIGA_MAC_VER_04:
  3936. case RTL_GIGA_MAC_VER_05:
  3937. case RTL_GIGA_MAC_VER_06:
  3938. case RTL_GIGA_MAC_VER_10:
  3939. case RTL_GIGA_MAC_VER_11:
  3940. case RTL_GIGA_MAC_VER_12:
  3941. case RTL_GIGA_MAC_VER_13:
  3942. case RTL_GIGA_MAC_VER_14:
  3943. case RTL_GIGA_MAC_VER_15:
  3944. case RTL_GIGA_MAC_VER_16:
  3945. case RTL_GIGA_MAC_VER_17:
  3946. ops->write = NULL;
  3947. ops->read = NULL;
  3948. break;
  3949. case RTL_GIGA_MAC_VER_37:
  3950. case RTL_GIGA_MAC_VER_38:
  3951. ops->write = r8402_csi_write;
  3952. ops->read = r8402_csi_read;
  3953. break;
  3954. default:
  3955. ops->write = r8169_csi_write;
  3956. ops->read = r8169_csi_read;
  3957. break;
  3958. }
  3959. }
  3960. struct ephy_info {
  3961. unsigned int offset;
  3962. u16 mask;
  3963. u16 bits;
  3964. };
  3965. static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
  3966. int len)
  3967. {
  3968. u16 w;
  3969. while (len-- > 0) {
  3970. w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
  3971. rtl_ephy_write(tp, e->offset, w);
  3972. e++;
  3973. }
  3974. }
  3975. static void rtl_disable_clock_request(struct pci_dev *pdev)
  3976. {
  3977. pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
  3978. PCI_EXP_LNKCTL_CLKREQ_EN);
  3979. }
  3980. static void rtl_enable_clock_request(struct pci_dev *pdev)
  3981. {
  3982. pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
  3983. PCI_EXP_LNKCTL_CLKREQ_EN);
  3984. }
  3985. #define R8168_CPCMD_QUIRK_MASK (\
  3986. EnableBist | \
  3987. Mac_dbgo_oe | \
  3988. Force_half_dup | \
  3989. Force_rxflow_en | \
  3990. Force_txflow_en | \
  3991. Cxpl_dbg_sel | \
  3992. ASF | \
  3993. PktCntrDisable | \
  3994. Mac_dbgo_sel)
  3995. static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
  3996. {
  3997. void __iomem *ioaddr = tp->mmio_addr;
  3998. struct pci_dev *pdev = tp->pci_dev;
  3999. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4000. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4001. rtl_tx_performance_tweak(pdev,
  4002. (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
  4003. }
  4004. static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
  4005. {
  4006. void __iomem *ioaddr = tp->mmio_addr;
  4007. rtl_hw_start_8168bb(tp);
  4008. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4009. RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
  4010. }
  4011. static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
  4012. {
  4013. void __iomem *ioaddr = tp->mmio_addr;
  4014. struct pci_dev *pdev = tp->pci_dev;
  4015. RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
  4016. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4017. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4018. rtl_disable_clock_request(pdev);
  4019. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4020. }
  4021. static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
  4022. {
  4023. static const struct ephy_info e_info_8168cp[] = {
  4024. { 0x01, 0, 0x0001 },
  4025. { 0x02, 0x0800, 0x1000 },
  4026. { 0x03, 0, 0x0042 },
  4027. { 0x06, 0x0080, 0x0000 },
  4028. { 0x07, 0, 0x2000 }
  4029. };
  4030. rtl_csi_access_enable_2(tp);
  4031. rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
  4032. __rtl_hw_start_8168cp(tp);
  4033. }
  4034. static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
  4035. {
  4036. void __iomem *ioaddr = tp->mmio_addr;
  4037. struct pci_dev *pdev = tp->pci_dev;
  4038. rtl_csi_access_enable_2(tp);
  4039. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4040. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4041. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4042. }
  4043. static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
  4044. {
  4045. void __iomem *ioaddr = tp->mmio_addr;
  4046. struct pci_dev *pdev = tp->pci_dev;
  4047. rtl_csi_access_enable_2(tp);
  4048. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4049. /* Magic. */
  4050. RTL_W8(DBG_REG, 0x20);
  4051. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4052. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4053. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4054. }
  4055. static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
  4056. {
  4057. void __iomem *ioaddr = tp->mmio_addr;
  4058. static const struct ephy_info e_info_8168c_1[] = {
  4059. { 0x02, 0x0800, 0x1000 },
  4060. { 0x03, 0, 0x0002 },
  4061. { 0x06, 0x0080, 0x0000 }
  4062. };
  4063. rtl_csi_access_enable_2(tp);
  4064. RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
  4065. rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
  4066. __rtl_hw_start_8168cp(tp);
  4067. }
  4068. static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
  4069. {
  4070. static const struct ephy_info e_info_8168c_2[] = {
  4071. { 0x01, 0, 0x0001 },
  4072. { 0x03, 0x0400, 0x0220 }
  4073. };
  4074. rtl_csi_access_enable_2(tp);
  4075. rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
  4076. __rtl_hw_start_8168cp(tp);
  4077. }
  4078. static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
  4079. {
  4080. rtl_hw_start_8168c_2(tp);
  4081. }
  4082. static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
  4083. {
  4084. rtl_csi_access_enable_2(tp);
  4085. __rtl_hw_start_8168cp(tp);
  4086. }
  4087. static void rtl_hw_start_8168d(struct rtl8169_private *tp)
  4088. {
  4089. void __iomem *ioaddr = tp->mmio_addr;
  4090. struct pci_dev *pdev = tp->pci_dev;
  4091. rtl_csi_access_enable_2(tp);
  4092. rtl_disable_clock_request(pdev);
  4093. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4094. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4095. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4096. }
  4097. static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
  4098. {
  4099. void __iomem *ioaddr = tp->mmio_addr;
  4100. struct pci_dev *pdev = tp->pci_dev;
  4101. rtl_csi_access_enable_1(tp);
  4102. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4103. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4104. rtl_disable_clock_request(pdev);
  4105. }
  4106. static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
  4107. {
  4108. void __iomem *ioaddr = tp->mmio_addr;
  4109. struct pci_dev *pdev = tp->pci_dev;
  4110. static const struct ephy_info e_info_8168d_4[] = {
  4111. { 0x0b, ~0, 0x48 },
  4112. { 0x19, 0x20, 0x50 },
  4113. { 0x0c, ~0, 0x20 }
  4114. };
  4115. int i;
  4116. rtl_csi_access_enable_1(tp);
  4117. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4118. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4119. for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
  4120. const struct ephy_info *e = e_info_8168d_4 + i;
  4121. u16 w;
  4122. w = rtl_ephy_read(tp, e->offset);
  4123. rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
  4124. }
  4125. rtl_enable_clock_request(pdev);
  4126. }
  4127. static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
  4128. {
  4129. void __iomem *ioaddr = tp->mmio_addr;
  4130. struct pci_dev *pdev = tp->pci_dev;
  4131. static const struct ephy_info e_info_8168e_1[] = {
  4132. { 0x00, 0x0200, 0x0100 },
  4133. { 0x00, 0x0000, 0x0004 },
  4134. { 0x06, 0x0002, 0x0001 },
  4135. { 0x06, 0x0000, 0x0030 },
  4136. { 0x07, 0x0000, 0x2000 },
  4137. { 0x00, 0x0000, 0x0020 },
  4138. { 0x03, 0x5800, 0x2000 },
  4139. { 0x03, 0x0000, 0x0001 },
  4140. { 0x01, 0x0800, 0x1000 },
  4141. { 0x07, 0x0000, 0x4000 },
  4142. { 0x1e, 0x0000, 0x2000 },
  4143. { 0x19, 0xffff, 0xfe6c },
  4144. { 0x0a, 0x0000, 0x0040 }
  4145. };
  4146. rtl_csi_access_enable_2(tp);
  4147. rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
  4148. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4149. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4150. rtl_disable_clock_request(pdev);
  4151. /* Reset tx FIFO pointer */
  4152. RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
  4153. RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
  4154. RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
  4155. }
  4156. static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
  4157. {
  4158. void __iomem *ioaddr = tp->mmio_addr;
  4159. struct pci_dev *pdev = tp->pci_dev;
  4160. static const struct ephy_info e_info_8168e_2[] = {
  4161. { 0x09, 0x0000, 0x0080 },
  4162. { 0x19, 0x0000, 0x0224 }
  4163. };
  4164. rtl_csi_access_enable_1(tp);
  4165. rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
  4166. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4167. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4168. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4169. rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
  4170. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  4171. rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
  4172. rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
  4173. rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
  4174. rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
  4175. RTL_W8(MaxTxPacketSize, EarlySize);
  4176. rtl_disable_clock_request(pdev);
  4177. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  4178. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  4179. /* Adjust EEE LED frequency */
  4180. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  4181. RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
  4182. RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
  4183. RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
  4184. }
  4185. static void rtl_hw_start_8168f(struct rtl8169_private *tp)
  4186. {
  4187. void __iomem *ioaddr = tp->mmio_addr;
  4188. struct pci_dev *pdev = tp->pci_dev;
  4189. rtl_csi_access_enable_2(tp);
  4190. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4191. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4192. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4193. rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
  4194. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  4195. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  4196. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  4197. rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
  4198. rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
  4199. rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
  4200. rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
  4201. RTL_W8(MaxTxPacketSize, EarlySize);
  4202. rtl_disable_clock_request(pdev);
  4203. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  4204. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  4205. RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
  4206. RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
  4207. RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
  4208. }
  4209. static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
  4210. {
  4211. void __iomem *ioaddr = tp->mmio_addr;
  4212. static const struct ephy_info e_info_8168f_1[] = {
  4213. { 0x06, 0x00c0, 0x0020 },
  4214. { 0x08, 0x0001, 0x0002 },
  4215. { 0x09, 0x0000, 0x0080 },
  4216. { 0x19, 0x0000, 0x0224 }
  4217. };
  4218. rtl_hw_start_8168f(tp);
  4219. rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
  4220. rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
  4221. /* Adjust EEE LED frequency */
  4222. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  4223. }
  4224. static void rtl_hw_start_8411(struct rtl8169_private *tp)
  4225. {
  4226. static const struct ephy_info e_info_8168f_1[] = {
  4227. { 0x06, 0x00c0, 0x0020 },
  4228. { 0x0f, 0xffff, 0x5200 },
  4229. { 0x1e, 0x0000, 0x4000 },
  4230. { 0x19, 0x0000, 0x0224 }
  4231. };
  4232. rtl_hw_start_8168f(tp);
  4233. rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
  4234. rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
  4235. }
  4236. static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
  4237. {
  4238. void __iomem *ioaddr = tp->mmio_addr;
  4239. struct pci_dev *pdev = tp->pci_dev;
  4240. rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
  4241. rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
  4242. rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
  4243. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  4244. rtl_csi_access_enable_1(tp);
  4245. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4246. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  4247. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  4248. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  4249. RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
  4250. RTL_W8(MaxTxPacketSize, EarlySize);
  4251. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4252. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4253. /* Adjust EEE LED frequency */
  4254. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  4255. rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
  4256. }
  4257. static void rtl_hw_start_8168(struct net_device *dev)
  4258. {
  4259. struct rtl8169_private *tp = netdev_priv(dev);
  4260. void __iomem *ioaddr = tp->mmio_addr;
  4261. RTL_W8(Cfg9346, Cfg9346_Unlock);
  4262. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4263. rtl_set_rx_max_size(ioaddr, rx_buf_sz);
  4264. tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
  4265. RTL_W16(CPlusCmd, tp->cp_cmd);
  4266. RTL_W16(IntrMitigate, 0x5151);
  4267. /* Work around for RxFIFO overflow. */
  4268. if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
  4269. tp->event_slow |= RxFIFOOver | PCSTimeout;
  4270. tp->event_slow &= ~RxOverflow;
  4271. }
  4272. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  4273. rtl_set_rx_mode(dev);
  4274. RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
  4275. (InterFrameGap << TxInterFrameGapShift));
  4276. RTL_R8(IntrMask);
  4277. switch (tp->mac_version) {
  4278. case RTL_GIGA_MAC_VER_11:
  4279. rtl_hw_start_8168bb(tp);
  4280. break;
  4281. case RTL_GIGA_MAC_VER_12:
  4282. case RTL_GIGA_MAC_VER_17:
  4283. rtl_hw_start_8168bef(tp);
  4284. break;
  4285. case RTL_GIGA_MAC_VER_18:
  4286. rtl_hw_start_8168cp_1(tp);
  4287. break;
  4288. case RTL_GIGA_MAC_VER_19:
  4289. rtl_hw_start_8168c_1(tp);
  4290. break;
  4291. case RTL_GIGA_MAC_VER_20:
  4292. rtl_hw_start_8168c_2(tp);
  4293. break;
  4294. case RTL_GIGA_MAC_VER_21:
  4295. rtl_hw_start_8168c_3(tp);
  4296. break;
  4297. case RTL_GIGA_MAC_VER_22:
  4298. rtl_hw_start_8168c_4(tp);
  4299. break;
  4300. case RTL_GIGA_MAC_VER_23:
  4301. rtl_hw_start_8168cp_2(tp);
  4302. break;
  4303. case RTL_GIGA_MAC_VER_24:
  4304. rtl_hw_start_8168cp_3(tp);
  4305. break;
  4306. case RTL_GIGA_MAC_VER_25:
  4307. case RTL_GIGA_MAC_VER_26:
  4308. case RTL_GIGA_MAC_VER_27:
  4309. rtl_hw_start_8168d(tp);
  4310. break;
  4311. case RTL_GIGA_MAC_VER_28:
  4312. rtl_hw_start_8168d_4(tp);
  4313. break;
  4314. case RTL_GIGA_MAC_VER_31:
  4315. rtl_hw_start_8168dp(tp);
  4316. break;
  4317. case RTL_GIGA_MAC_VER_32:
  4318. case RTL_GIGA_MAC_VER_33:
  4319. rtl_hw_start_8168e_1(tp);
  4320. break;
  4321. case RTL_GIGA_MAC_VER_34:
  4322. rtl_hw_start_8168e_2(tp);
  4323. break;
  4324. case RTL_GIGA_MAC_VER_35:
  4325. case RTL_GIGA_MAC_VER_36:
  4326. rtl_hw_start_8168f_1(tp);
  4327. break;
  4328. case RTL_GIGA_MAC_VER_38:
  4329. rtl_hw_start_8411(tp);
  4330. break;
  4331. case RTL_GIGA_MAC_VER_40:
  4332. case RTL_GIGA_MAC_VER_41:
  4333. rtl_hw_start_8168g_1(tp);
  4334. break;
  4335. default:
  4336. printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
  4337. dev->name, tp->mac_version);
  4338. break;
  4339. }
  4340. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  4341. RTL_W8(Cfg9346, Cfg9346_Lock);
  4342. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  4343. }
  4344. #define R810X_CPCMD_QUIRK_MASK (\
  4345. EnableBist | \
  4346. Mac_dbgo_oe | \
  4347. Force_half_dup | \
  4348. Force_rxflow_en | \
  4349. Force_txflow_en | \
  4350. Cxpl_dbg_sel | \
  4351. ASF | \
  4352. PktCntrDisable | \
  4353. Mac_dbgo_sel)
  4354. static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
  4355. {
  4356. void __iomem *ioaddr = tp->mmio_addr;
  4357. struct pci_dev *pdev = tp->pci_dev;
  4358. static const struct ephy_info e_info_8102e_1[] = {
  4359. { 0x01, 0, 0x6e65 },
  4360. { 0x02, 0, 0x091f },
  4361. { 0x03, 0, 0xc2f9 },
  4362. { 0x06, 0, 0xafb5 },
  4363. { 0x07, 0, 0x0e00 },
  4364. { 0x19, 0, 0xec80 },
  4365. { 0x01, 0, 0x2e65 },
  4366. { 0x01, 0, 0x6e65 }
  4367. };
  4368. u8 cfg1;
  4369. rtl_csi_access_enable_2(tp);
  4370. RTL_W8(DBG_REG, FIX_NAK_1);
  4371. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4372. RTL_W8(Config1,
  4373. LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
  4374. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4375. cfg1 = RTL_R8(Config1);
  4376. if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
  4377. RTL_W8(Config1, cfg1 & ~LEDS0);
  4378. rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
  4379. }
  4380. static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
  4381. {
  4382. void __iomem *ioaddr = tp->mmio_addr;
  4383. struct pci_dev *pdev = tp->pci_dev;
  4384. rtl_csi_access_enable_2(tp);
  4385. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4386. RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
  4387. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4388. }
  4389. static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
  4390. {
  4391. rtl_hw_start_8102e_2(tp);
  4392. rtl_ephy_write(tp, 0x03, 0xc2f9);
  4393. }
  4394. static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
  4395. {
  4396. void __iomem *ioaddr = tp->mmio_addr;
  4397. static const struct ephy_info e_info_8105e_1[] = {
  4398. { 0x07, 0, 0x4000 },
  4399. { 0x19, 0, 0x0200 },
  4400. { 0x19, 0, 0x0020 },
  4401. { 0x1e, 0, 0x2000 },
  4402. { 0x03, 0, 0x0001 },
  4403. { 0x19, 0, 0x0100 },
  4404. { 0x19, 0, 0x0004 },
  4405. { 0x0a, 0, 0x0020 }
  4406. };
  4407. /* Force LAN exit from ASPM if Rx/Tx are not idle */
  4408. RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
  4409. /* Disable Early Tally Counter */
  4410. RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
  4411. RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
  4412. RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
  4413. rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
  4414. }
  4415. static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
  4416. {
  4417. rtl_hw_start_8105e_1(tp);
  4418. rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
  4419. }
  4420. static void rtl_hw_start_8402(struct rtl8169_private *tp)
  4421. {
  4422. void __iomem *ioaddr = tp->mmio_addr;
  4423. static const struct ephy_info e_info_8402[] = {
  4424. { 0x19, 0xffff, 0xff64 },
  4425. { 0x1e, 0, 0x4000 }
  4426. };
  4427. rtl_csi_access_enable_2(tp);
  4428. /* Force LAN exit from ASPM if Rx/Tx are not idle */
  4429. RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
  4430. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  4431. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  4432. rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
  4433. rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4434. rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
  4435. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
  4436. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  4437. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  4438. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4439. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4440. rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
  4441. }
  4442. static void rtl_hw_start_8106(struct rtl8169_private *tp)
  4443. {
  4444. void __iomem *ioaddr = tp->mmio_addr;
  4445. /* Force LAN exit from ASPM if Rx/Tx are not idle */
  4446. RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
  4447. RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
  4448. RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
  4449. RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
  4450. }
  4451. static void rtl_hw_start_8101(struct net_device *dev)
  4452. {
  4453. struct rtl8169_private *tp = netdev_priv(dev);
  4454. void __iomem *ioaddr = tp->mmio_addr;
  4455. struct pci_dev *pdev = tp->pci_dev;
  4456. if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
  4457. tp->event_slow &= ~RxFIFOOver;
  4458. if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
  4459. tp->mac_version == RTL_GIGA_MAC_VER_16)
  4460. pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
  4461. PCI_EXP_DEVCTL_NOSNOOP_EN);
  4462. RTL_W8(Cfg9346, Cfg9346_Unlock);
  4463. switch (tp->mac_version) {
  4464. case RTL_GIGA_MAC_VER_07:
  4465. rtl_hw_start_8102e_1(tp);
  4466. break;
  4467. case RTL_GIGA_MAC_VER_08:
  4468. rtl_hw_start_8102e_3(tp);
  4469. break;
  4470. case RTL_GIGA_MAC_VER_09:
  4471. rtl_hw_start_8102e_2(tp);
  4472. break;
  4473. case RTL_GIGA_MAC_VER_29:
  4474. rtl_hw_start_8105e_1(tp);
  4475. break;
  4476. case RTL_GIGA_MAC_VER_30:
  4477. rtl_hw_start_8105e_2(tp);
  4478. break;
  4479. case RTL_GIGA_MAC_VER_37:
  4480. rtl_hw_start_8402(tp);
  4481. break;
  4482. case RTL_GIGA_MAC_VER_39:
  4483. rtl_hw_start_8106(tp);
  4484. break;
  4485. }
  4486. RTL_W8(Cfg9346, Cfg9346_Lock);
  4487. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4488. rtl_set_rx_max_size(ioaddr, rx_buf_sz);
  4489. tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
  4490. RTL_W16(CPlusCmd, tp->cp_cmd);
  4491. RTL_W16(IntrMitigate, 0x0000);
  4492. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  4493. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  4494. rtl_set_rx_tx_config_registers(tp);
  4495. RTL_R8(IntrMask);
  4496. rtl_set_rx_mode(dev);
  4497. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
  4498. }
  4499. static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
  4500. {
  4501. struct rtl8169_private *tp = netdev_priv(dev);
  4502. if (new_mtu < ETH_ZLEN ||
  4503. new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
  4504. return -EINVAL;
  4505. if (new_mtu > ETH_DATA_LEN)
  4506. rtl_hw_jumbo_enable(tp);
  4507. else
  4508. rtl_hw_jumbo_disable(tp);
  4509. dev->mtu = new_mtu;
  4510. netdev_update_features(dev);
  4511. return 0;
  4512. }
  4513. static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
  4514. {
  4515. desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
  4516. desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
  4517. }
  4518. static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
  4519. void **data_buff, struct RxDesc *desc)
  4520. {
  4521. dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
  4522. DMA_FROM_DEVICE);
  4523. kfree(*data_buff);
  4524. *data_buff = NULL;
  4525. rtl8169_make_unusable_by_asic(desc);
  4526. }
  4527. static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
  4528. {
  4529. u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
  4530. desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
  4531. }
  4532. static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
  4533. u32 rx_buf_sz)
  4534. {
  4535. desc->addr = cpu_to_le64(mapping);
  4536. wmb();
  4537. rtl8169_mark_to_asic(desc, rx_buf_sz);
  4538. }
  4539. static inline void *rtl8169_align(void *data)
  4540. {
  4541. return (void *)ALIGN((long)data, 16);
  4542. }
  4543. static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
  4544. struct RxDesc *desc)
  4545. {
  4546. void *data;
  4547. dma_addr_t mapping;
  4548. struct device *d = &tp->pci_dev->dev;
  4549. struct net_device *dev = tp->dev;
  4550. int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
  4551. data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  4552. if (!data)
  4553. return NULL;
  4554. if (rtl8169_align(data) != data) {
  4555. kfree(data);
  4556. data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
  4557. if (!data)
  4558. return NULL;
  4559. }
  4560. mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
  4561. DMA_FROM_DEVICE);
  4562. if (unlikely(dma_mapping_error(d, mapping))) {
  4563. if (net_ratelimit())
  4564. netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
  4565. goto err_out;
  4566. }
  4567. rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
  4568. return data;
  4569. err_out:
  4570. kfree(data);
  4571. return NULL;
  4572. }
  4573. static void rtl8169_rx_clear(struct rtl8169_private *tp)
  4574. {
  4575. unsigned int i;
  4576. for (i = 0; i < NUM_RX_DESC; i++) {
  4577. if (tp->Rx_databuff[i]) {
  4578. rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
  4579. tp->RxDescArray + i);
  4580. }
  4581. }
  4582. }
  4583. static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
  4584. {
  4585. desc->opts1 |= cpu_to_le32(RingEnd);
  4586. }
  4587. static int rtl8169_rx_fill(struct rtl8169_private *tp)
  4588. {
  4589. unsigned int i;
  4590. for (i = 0; i < NUM_RX_DESC; i++) {
  4591. void *data;
  4592. if (tp->Rx_databuff[i])
  4593. continue;
  4594. data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
  4595. if (!data) {
  4596. rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
  4597. goto err_out;
  4598. }
  4599. tp->Rx_databuff[i] = data;
  4600. }
  4601. rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
  4602. return 0;
  4603. err_out:
  4604. rtl8169_rx_clear(tp);
  4605. return -ENOMEM;
  4606. }
  4607. static int rtl8169_init_ring(struct net_device *dev)
  4608. {
  4609. struct rtl8169_private *tp = netdev_priv(dev);
  4610. rtl8169_init_ring_indexes(tp);
  4611. memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
  4612. memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
  4613. return rtl8169_rx_fill(tp);
  4614. }
  4615. static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
  4616. struct TxDesc *desc)
  4617. {
  4618. unsigned int len = tx_skb->len;
  4619. dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
  4620. desc->opts1 = 0x00;
  4621. desc->opts2 = 0x00;
  4622. desc->addr = 0x00;
  4623. tx_skb->len = 0;
  4624. }
  4625. static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
  4626. unsigned int n)
  4627. {
  4628. unsigned int i;
  4629. for (i = 0; i < n; i++) {
  4630. unsigned int entry = (start + i) % NUM_TX_DESC;
  4631. struct ring_info *tx_skb = tp->tx_skb + entry;
  4632. unsigned int len = tx_skb->len;
  4633. if (len) {
  4634. struct sk_buff *skb = tx_skb->skb;
  4635. rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
  4636. tp->TxDescArray + entry);
  4637. if (skb) {
  4638. tp->dev->stats.tx_dropped++;
  4639. dev_kfree_skb(skb);
  4640. tx_skb->skb = NULL;
  4641. }
  4642. }
  4643. }
  4644. }
  4645. static void rtl8169_tx_clear(struct rtl8169_private *tp)
  4646. {
  4647. rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
  4648. tp->cur_tx = tp->dirty_tx = 0;
  4649. }
  4650. static void rtl_reset_work(struct rtl8169_private *tp)
  4651. {
  4652. struct net_device *dev = tp->dev;
  4653. int i;
  4654. napi_disable(&tp->napi);
  4655. netif_stop_queue(dev);
  4656. synchronize_sched();
  4657. rtl8169_hw_reset(tp);
  4658. for (i = 0; i < NUM_RX_DESC; i++)
  4659. rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
  4660. rtl8169_tx_clear(tp);
  4661. rtl8169_init_ring_indexes(tp);
  4662. napi_enable(&tp->napi);
  4663. rtl_hw_start(dev);
  4664. netif_wake_queue(dev);
  4665. rtl8169_check_link_status(dev, tp, tp->mmio_addr);
  4666. }
  4667. static void rtl8169_tx_timeout(struct net_device *dev)
  4668. {
  4669. struct rtl8169_private *tp = netdev_priv(dev);
  4670. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  4671. }
  4672. static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
  4673. u32 *opts)
  4674. {
  4675. struct skb_shared_info *info = skb_shinfo(skb);
  4676. unsigned int cur_frag, entry;
  4677. struct TxDesc * uninitialized_var(txd);
  4678. struct device *d = &tp->pci_dev->dev;
  4679. entry = tp->cur_tx;
  4680. for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
  4681. const skb_frag_t *frag = info->frags + cur_frag;
  4682. dma_addr_t mapping;
  4683. u32 status, len;
  4684. void *addr;
  4685. entry = (entry + 1) % NUM_TX_DESC;
  4686. txd = tp->TxDescArray + entry;
  4687. len = skb_frag_size(frag);
  4688. addr = skb_frag_address(frag);
  4689. mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
  4690. if (unlikely(dma_mapping_error(d, mapping))) {
  4691. if (net_ratelimit())
  4692. netif_err(tp, drv, tp->dev,
  4693. "Failed to map TX fragments DMA!\n");
  4694. goto err_out;
  4695. }
  4696. /* Anti gcc 2.95.3 bugware (sic) */
  4697. status = opts[0] | len |
  4698. (RingEnd * !((entry + 1) % NUM_TX_DESC));
  4699. txd->opts1 = cpu_to_le32(status);
  4700. txd->opts2 = cpu_to_le32(opts[1]);
  4701. txd->addr = cpu_to_le64(mapping);
  4702. tp->tx_skb[entry].len = len;
  4703. }
  4704. if (cur_frag) {
  4705. tp->tx_skb[entry].skb = skb;
  4706. txd->opts1 |= cpu_to_le32(LastFrag);
  4707. }
  4708. return cur_frag;
  4709. err_out:
  4710. rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
  4711. return -EIO;
  4712. }
  4713. static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
  4714. struct sk_buff *skb, u32 *opts)
  4715. {
  4716. const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
  4717. u32 mss = skb_shinfo(skb)->gso_size;
  4718. int offset = info->opts_offset;
  4719. if (mss) {
  4720. opts[0] |= TD_LSO;
  4721. opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
  4722. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  4723. const struct iphdr *ip = ip_hdr(skb);
  4724. if (ip->protocol == IPPROTO_TCP)
  4725. opts[offset] |= info->checksum.tcp;
  4726. else if (ip->protocol == IPPROTO_UDP)
  4727. opts[offset] |= info->checksum.udp;
  4728. else
  4729. WARN_ON_ONCE(1);
  4730. }
  4731. }
  4732. static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
  4733. struct net_device *dev)
  4734. {
  4735. struct rtl8169_private *tp = netdev_priv(dev);
  4736. unsigned int entry = tp->cur_tx % NUM_TX_DESC;
  4737. struct TxDesc *txd = tp->TxDescArray + entry;
  4738. void __iomem *ioaddr = tp->mmio_addr;
  4739. struct device *d = &tp->pci_dev->dev;
  4740. dma_addr_t mapping;
  4741. u32 status, len;
  4742. u32 opts[2];
  4743. int frags;
  4744. if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
  4745. netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
  4746. goto err_stop_0;
  4747. }
  4748. if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
  4749. goto err_stop_0;
  4750. len = skb_headlen(skb);
  4751. mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
  4752. if (unlikely(dma_mapping_error(d, mapping))) {
  4753. if (net_ratelimit())
  4754. netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
  4755. goto err_dma_0;
  4756. }
  4757. tp->tx_skb[entry].len = len;
  4758. txd->addr = cpu_to_le64(mapping);
  4759. opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
  4760. opts[0] = DescOwn;
  4761. rtl8169_tso_csum(tp, skb, opts);
  4762. frags = rtl8169_xmit_frags(tp, skb, opts);
  4763. if (frags < 0)
  4764. goto err_dma_1;
  4765. else if (frags)
  4766. opts[0] |= FirstFrag;
  4767. else {
  4768. opts[0] |= FirstFrag | LastFrag;
  4769. tp->tx_skb[entry].skb = skb;
  4770. }
  4771. txd->opts2 = cpu_to_le32(opts[1]);
  4772. skb_tx_timestamp(skb);
  4773. wmb();
  4774. /* Anti gcc 2.95.3 bugware (sic) */
  4775. status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
  4776. txd->opts1 = cpu_to_le32(status);
  4777. tp->cur_tx += frags + 1;
  4778. wmb();
  4779. RTL_W8(TxPoll, NPQ);
  4780. mmiowb();
  4781. if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
  4782. /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
  4783. * not miss a ring update when it notices a stopped queue.
  4784. */
  4785. smp_wmb();
  4786. netif_stop_queue(dev);
  4787. /* Sync with rtl_tx:
  4788. * - publish queue status and cur_tx ring index (write barrier)
  4789. * - refresh dirty_tx ring index (read barrier).
  4790. * May the current thread have a pessimistic view of the ring
  4791. * status and forget to wake up queue, a racing rtl_tx thread
  4792. * can't.
  4793. */
  4794. smp_mb();
  4795. if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
  4796. netif_wake_queue(dev);
  4797. }
  4798. return NETDEV_TX_OK;
  4799. err_dma_1:
  4800. rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
  4801. err_dma_0:
  4802. dev_kfree_skb(skb);
  4803. dev->stats.tx_dropped++;
  4804. return NETDEV_TX_OK;
  4805. err_stop_0:
  4806. netif_stop_queue(dev);
  4807. dev->stats.tx_dropped++;
  4808. return NETDEV_TX_BUSY;
  4809. }
  4810. static void rtl8169_pcierr_interrupt(struct net_device *dev)
  4811. {
  4812. struct rtl8169_private *tp = netdev_priv(dev);
  4813. struct pci_dev *pdev = tp->pci_dev;
  4814. u16 pci_status, pci_cmd;
  4815. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  4816. pci_read_config_word(pdev, PCI_STATUS, &pci_status);
  4817. netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
  4818. pci_cmd, pci_status);
  4819. /*
  4820. * The recovery sequence below admits a very elaborated explanation:
  4821. * - it seems to work;
  4822. * - I did not see what else could be done;
  4823. * - it makes iop3xx happy.
  4824. *
  4825. * Feel free to adjust to your needs.
  4826. */
  4827. if (pdev->broken_parity_status)
  4828. pci_cmd &= ~PCI_COMMAND_PARITY;
  4829. else
  4830. pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
  4831. pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
  4832. pci_write_config_word(pdev, PCI_STATUS,
  4833. pci_status & (PCI_STATUS_DETECTED_PARITY |
  4834. PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
  4835. PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
  4836. /* The infamous DAC f*ckup only happens at boot time */
  4837. if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
  4838. void __iomem *ioaddr = tp->mmio_addr;
  4839. netif_info(tp, intr, dev, "disabling PCI DAC\n");
  4840. tp->cp_cmd &= ~PCIDAC;
  4841. RTL_W16(CPlusCmd, tp->cp_cmd);
  4842. dev->features &= ~NETIF_F_HIGHDMA;
  4843. }
  4844. rtl8169_hw_reset(tp);
  4845. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  4846. }
  4847. static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
  4848. {
  4849. unsigned int dirty_tx, tx_left;
  4850. dirty_tx = tp->dirty_tx;
  4851. smp_rmb();
  4852. tx_left = tp->cur_tx - dirty_tx;
  4853. while (tx_left > 0) {
  4854. unsigned int entry = dirty_tx % NUM_TX_DESC;
  4855. struct ring_info *tx_skb = tp->tx_skb + entry;
  4856. u32 status;
  4857. rmb();
  4858. status = le32_to_cpu(tp->TxDescArray[entry].opts1);
  4859. if (status & DescOwn)
  4860. break;
  4861. rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
  4862. tp->TxDescArray + entry);
  4863. if (status & LastFrag) {
  4864. u64_stats_update_begin(&tp->tx_stats.syncp);
  4865. tp->tx_stats.packets++;
  4866. tp->tx_stats.bytes += tx_skb->skb->len;
  4867. u64_stats_update_end(&tp->tx_stats.syncp);
  4868. dev_kfree_skb(tx_skb->skb);
  4869. tx_skb->skb = NULL;
  4870. }
  4871. dirty_tx++;
  4872. tx_left--;
  4873. }
  4874. if (tp->dirty_tx != dirty_tx) {
  4875. tp->dirty_tx = dirty_tx;
  4876. /* Sync with rtl8169_start_xmit:
  4877. * - publish dirty_tx ring index (write barrier)
  4878. * - refresh cur_tx ring index and queue status (read barrier)
  4879. * May the current thread miss the stopped queue condition,
  4880. * a racing xmit thread can only have a right view of the
  4881. * ring status.
  4882. */
  4883. smp_mb();
  4884. if (netif_queue_stopped(dev) &&
  4885. TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
  4886. netif_wake_queue(dev);
  4887. }
  4888. /*
  4889. * 8168 hack: TxPoll requests are lost when the Tx packets are
  4890. * too close. Let's kick an extra TxPoll request when a burst
  4891. * of start_xmit activity is detected (if it is not detected,
  4892. * it is slow enough). -- FR
  4893. */
  4894. if (tp->cur_tx != dirty_tx) {
  4895. void __iomem *ioaddr = tp->mmio_addr;
  4896. RTL_W8(TxPoll, NPQ);
  4897. }
  4898. }
  4899. }
  4900. static inline int rtl8169_fragmented_frame(u32 status)
  4901. {
  4902. return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
  4903. }
  4904. static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
  4905. {
  4906. u32 status = opts1 & RxProtoMask;
  4907. if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
  4908. ((status == RxProtoUDP) && !(opts1 & UDPFail)))
  4909. skb->ip_summed = CHECKSUM_UNNECESSARY;
  4910. else
  4911. skb_checksum_none_assert(skb);
  4912. }
  4913. static struct sk_buff *rtl8169_try_rx_copy(void *data,
  4914. struct rtl8169_private *tp,
  4915. int pkt_size,
  4916. dma_addr_t addr)
  4917. {
  4918. struct sk_buff *skb;
  4919. struct device *d = &tp->pci_dev->dev;
  4920. data = rtl8169_align(data);
  4921. dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
  4922. prefetch(data);
  4923. skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
  4924. if (skb)
  4925. memcpy(skb->data, data, pkt_size);
  4926. dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
  4927. return skb;
  4928. }
  4929. static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
  4930. {
  4931. unsigned int cur_rx, rx_left;
  4932. unsigned int count;
  4933. cur_rx = tp->cur_rx;
  4934. rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
  4935. rx_left = min(rx_left, budget);
  4936. for (; rx_left > 0; rx_left--, cur_rx++) {
  4937. unsigned int entry = cur_rx % NUM_RX_DESC;
  4938. struct RxDesc *desc = tp->RxDescArray + entry;
  4939. u32 status;
  4940. rmb();
  4941. status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
  4942. if (status & DescOwn)
  4943. break;
  4944. if (unlikely(status & RxRES)) {
  4945. netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
  4946. status);
  4947. dev->stats.rx_errors++;
  4948. if (status & (RxRWT | RxRUNT))
  4949. dev->stats.rx_length_errors++;
  4950. if (status & RxCRC)
  4951. dev->stats.rx_crc_errors++;
  4952. if (status & RxFOVF) {
  4953. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  4954. dev->stats.rx_fifo_errors++;
  4955. }
  4956. if ((status & (RxRUNT | RxCRC)) &&
  4957. !(status & (RxRWT | RxFOVF)) &&
  4958. (dev->features & NETIF_F_RXALL))
  4959. goto process_pkt;
  4960. rtl8169_mark_to_asic(desc, rx_buf_sz);
  4961. } else {
  4962. struct sk_buff *skb;
  4963. dma_addr_t addr;
  4964. int pkt_size;
  4965. process_pkt:
  4966. addr = le64_to_cpu(desc->addr);
  4967. if (likely(!(dev->features & NETIF_F_RXFCS)))
  4968. pkt_size = (status & 0x00003fff) - 4;
  4969. else
  4970. pkt_size = status & 0x00003fff;
  4971. /*
  4972. * The driver does not support incoming fragmented
  4973. * frames. They are seen as a symptom of over-mtu
  4974. * sized frames.
  4975. */
  4976. if (unlikely(rtl8169_fragmented_frame(status))) {
  4977. dev->stats.rx_dropped++;
  4978. dev->stats.rx_length_errors++;
  4979. rtl8169_mark_to_asic(desc, rx_buf_sz);
  4980. continue;
  4981. }
  4982. skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
  4983. tp, pkt_size, addr);
  4984. rtl8169_mark_to_asic(desc, rx_buf_sz);
  4985. if (!skb) {
  4986. dev->stats.rx_dropped++;
  4987. continue;
  4988. }
  4989. rtl8169_rx_csum(skb, status);
  4990. skb_put(skb, pkt_size);
  4991. skb->protocol = eth_type_trans(skb, dev);
  4992. rtl8169_rx_vlan_tag(desc, skb);
  4993. napi_gro_receive(&tp->napi, skb);
  4994. u64_stats_update_begin(&tp->rx_stats.syncp);
  4995. tp->rx_stats.packets++;
  4996. tp->rx_stats.bytes += pkt_size;
  4997. u64_stats_update_end(&tp->rx_stats.syncp);
  4998. }
  4999. /* Work around for AMD plateform. */
  5000. if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
  5001. (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
  5002. desc->opts2 = 0;
  5003. cur_rx++;
  5004. }
  5005. }
  5006. count = cur_rx - tp->cur_rx;
  5007. tp->cur_rx = cur_rx;
  5008. tp->dirty_rx += count;
  5009. return count;
  5010. }
  5011. static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
  5012. {
  5013. struct net_device *dev = dev_instance;
  5014. struct rtl8169_private *tp = netdev_priv(dev);
  5015. int handled = 0;
  5016. u16 status;
  5017. status = rtl_get_events(tp);
  5018. if (status && status != 0xffff) {
  5019. status &= RTL_EVENT_NAPI | tp->event_slow;
  5020. if (status) {
  5021. handled = 1;
  5022. rtl_irq_disable(tp);
  5023. napi_schedule(&tp->napi);
  5024. }
  5025. }
  5026. return IRQ_RETVAL(handled);
  5027. }
  5028. /*
  5029. * Workqueue context.
  5030. */
  5031. static void rtl_slow_event_work(struct rtl8169_private *tp)
  5032. {
  5033. struct net_device *dev = tp->dev;
  5034. u16 status;
  5035. status = rtl_get_events(tp) & tp->event_slow;
  5036. rtl_ack_events(tp, status);
  5037. if (unlikely(status & RxFIFOOver)) {
  5038. switch (tp->mac_version) {
  5039. /* Work around for rx fifo overflow */
  5040. case RTL_GIGA_MAC_VER_11:
  5041. netif_stop_queue(dev);
  5042. /* XXX - Hack alert. See rtl_task(). */
  5043. set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
  5044. default:
  5045. break;
  5046. }
  5047. }
  5048. if (unlikely(status & SYSErr))
  5049. rtl8169_pcierr_interrupt(dev);
  5050. if (status & LinkChg)
  5051. __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
  5052. rtl_irq_enable_all(tp);
  5053. }
  5054. static void rtl_task(struct work_struct *work)
  5055. {
  5056. static const struct {
  5057. int bitnr;
  5058. void (*action)(struct rtl8169_private *);
  5059. } rtl_work[] = {
  5060. /* XXX - keep rtl_slow_event_work() as first element. */
  5061. { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
  5062. { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
  5063. { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
  5064. };
  5065. struct rtl8169_private *tp =
  5066. container_of(work, struct rtl8169_private, wk.work);
  5067. struct net_device *dev = tp->dev;
  5068. int i;
  5069. rtl_lock_work(tp);
  5070. if (!netif_running(dev) ||
  5071. !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
  5072. goto out_unlock;
  5073. for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
  5074. bool pending;
  5075. pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
  5076. if (pending)
  5077. rtl_work[i].action(tp);
  5078. }
  5079. out_unlock:
  5080. rtl_unlock_work(tp);
  5081. }
  5082. static int rtl8169_poll(struct napi_struct *napi, int budget)
  5083. {
  5084. struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
  5085. struct net_device *dev = tp->dev;
  5086. u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
  5087. int work_done= 0;
  5088. u16 status;
  5089. status = rtl_get_events(tp);
  5090. rtl_ack_events(tp, status & ~tp->event_slow);
  5091. if (status & RTL_EVENT_NAPI_RX)
  5092. work_done = rtl_rx(dev, tp, (u32) budget);
  5093. if (status & RTL_EVENT_NAPI_TX)
  5094. rtl_tx(dev, tp);
  5095. if (status & tp->event_slow) {
  5096. enable_mask &= ~tp->event_slow;
  5097. rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
  5098. }
  5099. if (work_done < budget) {
  5100. napi_complete(napi);
  5101. rtl_irq_enable(tp, enable_mask);
  5102. mmiowb();
  5103. }
  5104. return work_done;
  5105. }
  5106. static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
  5107. {
  5108. struct rtl8169_private *tp = netdev_priv(dev);
  5109. if (tp->mac_version > RTL_GIGA_MAC_VER_06)
  5110. return;
  5111. dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
  5112. RTL_W32(RxMissed, 0);
  5113. }
  5114. static void rtl8169_down(struct net_device *dev)
  5115. {
  5116. struct rtl8169_private *tp = netdev_priv(dev);
  5117. void __iomem *ioaddr = tp->mmio_addr;
  5118. del_timer_sync(&tp->timer);
  5119. napi_disable(&tp->napi);
  5120. netif_stop_queue(dev);
  5121. rtl8169_hw_reset(tp);
  5122. /*
  5123. * At this point device interrupts can not be enabled in any function,
  5124. * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
  5125. * and napi is disabled (rtl8169_poll).
  5126. */
  5127. rtl8169_rx_missed(dev, ioaddr);
  5128. /* Give a racing hard_start_xmit a few cycles to complete. */
  5129. synchronize_sched();
  5130. rtl8169_tx_clear(tp);
  5131. rtl8169_rx_clear(tp);
  5132. rtl_pll_power_down(tp);
  5133. }
  5134. static int rtl8169_close(struct net_device *dev)
  5135. {
  5136. struct rtl8169_private *tp = netdev_priv(dev);
  5137. struct pci_dev *pdev = tp->pci_dev;
  5138. pm_runtime_get_sync(&pdev->dev);
  5139. /* Update counters before going down */
  5140. rtl8169_update_counters(dev);
  5141. rtl_lock_work(tp);
  5142. clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  5143. rtl8169_down(dev);
  5144. rtl_unlock_work(tp);
  5145. free_irq(pdev->irq, dev);
  5146. dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
  5147. tp->RxPhyAddr);
  5148. dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
  5149. tp->TxPhyAddr);
  5150. tp->TxDescArray = NULL;
  5151. tp->RxDescArray = NULL;
  5152. pm_runtime_put_sync(&pdev->dev);
  5153. return 0;
  5154. }
  5155. #ifdef CONFIG_NET_POLL_CONTROLLER
  5156. static void rtl8169_netpoll(struct net_device *dev)
  5157. {
  5158. struct rtl8169_private *tp = netdev_priv(dev);
  5159. rtl8169_interrupt(tp->pci_dev->irq, dev);
  5160. }
  5161. #endif
  5162. static int rtl_open(struct net_device *dev)
  5163. {
  5164. struct rtl8169_private *tp = netdev_priv(dev);
  5165. void __iomem *ioaddr = tp->mmio_addr;
  5166. struct pci_dev *pdev = tp->pci_dev;
  5167. int retval = -ENOMEM;
  5168. pm_runtime_get_sync(&pdev->dev);
  5169. /*
  5170. * Rx and Tx descriptors needs 256 bytes alignment.
  5171. * dma_alloc_coherent provides more.
  5172. */
  5173. tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
  5174. &tp->TxPhyAddr, GFP_KERNEL);
  5175. if (!tp->TxDescArray)
  5176. goto err_pm_runtime_put;
  5177. tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
  5178. &tp->RxPhyAddr, GFP_KERNEL);
  5179. if (!tp->RxDescArray)
  5180. goto err_free_tx_0;
  5181. retval = rtl8169_init_ring(dev);
  5182. if (retval < 0)
  5183. goto err_free_rx_1;
  5184. INIT_WORK(&tp->wk.work, rtl_task);
  5185. smp_mb();
  5186. rtl_request_firmware(tp);
  5187. retval = request_irq(pdev->irq, rtl8169_interrupt,
  5188. (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
  5189. dev->name, dev);
  5190. if (retval < 0)
  5191. goto err_release_fw_2;
  5192. rtl_lock_work(tp);
  5193. set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  5194. napi_enable(&tp->napi);
  5195. rtl8169_init_phy(dev, tp);
  5196. __rtl8169_set_features(dev, dev->features);
  5197. rtl_pll_power_up(tp);
  5198. rtl_hw_start(dev);
  5199. netif_start_queue(dev);
  5200. rtl_unlock_work(tp);
  5201. tp->saved_wolopts = 0;
  5202. pm_runtime_put_noidle(&pdev->dev);
  5203. rtl8169_check_link_status(dev, tp, ioaddr);
  5204. out:
  5205. return retval;
  5206. err_release_fw_2:
  5207. rtl_release_firmware(tp);
  5208. rtl8169_rx_clear(tp);
  5209. err_free_rx_1:
  5210. dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
  5211. tp->RxPhyAddr);
  5212. tp->RxDescArray = NULL;
  5213. err_free_tx_0:
  5214. dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
  5215. tp->TxPhyAddr);
  5216. tp->TxDescArray = NULL;
  5217. err_pm_runtime_put:
  5218. pm_runtime_put_noidle(&pdev->dev);
  5219. goto out;
  5220. }
  5221. static struct rtnl_link_stats64 *
  5222. rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
  5223. {
  5224. struct rtl8169_private *tp = netdev_priv(dev);
  5225. void __iomem *ioaddr = tp->mmio_addr;
  5226. unsigned int start;
  5227. if (netif_running(dev))
  5228. rtl8169_rx_missed(dev, ioaddr);
  5229. do {
  5230. start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
  5231. stats->rx_packets = tp->rx_stats.packets;
  5232. stats->rx_bytes = tp->rx_stats.bytes;
  5233. } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
  5234. do {
  5235. start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
  5236. stats->tx_packets = tp->tx_stats.packets;
  5237. stats->tx_bytes = tp->tx_stats.bytes;
  5238. } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
  5239. stats->rx_dropped = dev->stats.rx_dropped;
  5240. stats->tx_dropped = dev->stats.tx_dropped;
  5241. stats->rx_length_errors = dev->stats.rx_length_errors;
  5242. stats->rx_errors = dev->stats.rx_errors;
  5243. stats->rx_crc_errors = dev->stats.rx_crc_errors;
  5244. stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
  5245. stats->rx_missed_errors = dev->stats.rx_missed_errors;
  5246. return stats;
  5247. }
  5248. static void rtl8169_net_suspend(struct net_device *dev)
  5249. {
  5250. struct rtl8169_private *tp = netdev_priv(dev);
  5251. if (!netif_running(dev))
  5252. return;
  5253. netif_device_detach(dev);
  5254. netif_stop_queue(dev);
  5255. rtl_lock_work(tp);
  5256. napi_disable(&tp->napi);
  5257. clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  5258. rtl_unlock_work(tp);
  5259. rtl_pll_power_down(tp);
  5260. }
  5261. #ifdef CONFIG_PM
  5262. static int rtl8169_suspend(struct device *device)
  5263. {
  5264. struct pci_dev *pdev = to_pci_dev(device);
  5265. struct net_device *dev = pci_get_drvdata(pdev);
  5266. rtl8169_net_suspend(dev);
  5267. return 0;
  5268. }
  5269. static void __rtl8169_resume(struct net_device *dev)
  5270. {
  5271. struct rtl8169_private *tp = netdev_priv(dev);
  5272. netif_device_attach(dev);
  5273. rtl_pll_power_up(tp);
  5274. rtl_lock_work(tp);
  5275. napi_enable(&tp->napi);
  5276. set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  5277. rtl_unlock_work(tp);
  5278. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  5279. }
  5280. static int rtl8169_resume(struct device *device)
  5281. {
  5282. struct pci_dev *pdev = to_pci_dev(device);
  5283. struct net_device *dev = pci_get_drvdata(pdev);
  5284. struct rtl8169_private *tp = netdev_priv(dev);
  5285. rtl8169_init_phy(dev, tp);
  5286. if (netif_running(dev))
  5287. __rtl8169_resume(dev);
  5288. return 0;
  5289. }
  5290. static int rtl8169_runtime_suspend(struct device *device)
  5291. {
  5292. struct pci_dev *pdev = to_pci_dev(device);
  5293. struct net_device *dev = pci_get_drvdata(pdev);
  5294. struct rtl8169_private *tp = netdev_priv(dev);
  5295. if (!tp->TxDescArray)
  5296. return 0;
  5297. rtl_lock_work(tp);
  5298. tp->saved_wolopts = __rtl8169_get_wol(tp);
  5299. __rtl8169_set_wol(tp, WAKE_ANY);
  5300. rtl_unlock_work(tp);
  5301. rtl8169_net_suspend(dev);
  5302. return 0;
  5303. }
  5304. static int rtl8169_runtime_resume(struct device *device)
  5305. {
  5306. struct pci_dev *pdev = to_pci_dev(device);
  5307. struct net_device *dev = pci_get_drvdata(pdev);
  5308. struct rtl8169_private *tp = netdev_priv(dev);
  5309. if (!tp->TxDescArray)
  5310. return 0;
  5311. rtl_lock_work(tp);
  5312. __rtl8169_set_wol(tp, tp->saved_wolopts);
  5313. tp->saved_wolopts = 0;
  5314. rtl_unlock_work(tp);
  5315. rtl8169_init_phy(dev, tp);
  5316. __rtl8169_resume(dev);
  5317. return 0;
  5318. }
  5319. static int rtl8169_runtime_idle(struct device *device)
  5320. {
  5321. struct pci_dev *pdev = to_pci_dev(device);
  5322. struct net_device *dev = pci_get_drvdata(pdev);
  5323. struct rtl8169_private *tp = netdev_priv(dev);
  5324. return tp->TxDescArray ? -EBUSY : 0;
  5325. }
  5326. static const struct dev_pm_ops rtl8169_pm_ops = {
  5327. .suspend = rtl8169_suspend,
  5328. .resume = rtl8169_resume,
  5329. .freeze = rtl8169_suspend,
  5330. .thaw = rtl8169_resume,
  5331. .poweroff = rtl8169_suspend,
  5332. .restore = rtl8169_resume,
  5333. .runtime_suspend = rtl8169_runtime_suspend,
  5334. .runtime_resume = rtl8169_runtime_resume,
  5335. .runtime_idle = rtl8169_runtime_idle,
  5336. };
  5337. #define RTL8169_PM_OPS (&rtl8169_pm_ops)
  5338. #else /* !CONFIG_PM */
  5339. #define RTL8169_PM_OPS NULL
  5340. #endif /* !CONFIG_PM */
  5341. static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
  5342. {
  5343. void __iomem *ioaddr = tp->mmio_addr;
  5344. /* WoL fails with 8168b when the receiver is disabled. */
  5345. switch (tp->mac_version) {
  5346. case RTL_GIGA_MAC_VER_11:
  5347. case RTL_GIGA_MAC_VER_12:
  5348. case RTL_GIGA_MAC_VER_17:
  5349. pci_clear_master(tp->pci_dev);
  5350. RTL_W8(ChipCmd, CmdRxEnb);
  5351. /* PCI commit */
  5352. RTL_R8(ChipCmd);
  5353. break;
  5354. default:
  5355. break;
  5356. }
  5357. }
  5358. static void rtl_shutdown(struct pci_dev *pdev)
  5359. {
  5360. struct net_device *dev = pci_get_drvdata(pdev);
  5361. struct rtl8169_private *tp = netdev_priv(dev);
  5362. struct device *d = &pdev->dev;
  5363. pm_runtime_get_sync(d);
  5364. rtl8169_net_suspend(dev);
  5365. /* Restore original MAC address */
  5366. rtl_rar_set(tp, dev->perm_addr);
  5367. rtl8169_hw_reset(tp);
  5368. if (system_state == SYSTEM_POWER_OFF) {
  5369. if (__rtl8169_get_wol(tp) & WAKE_ANY) {
  5370. rtl_wol_suspend_quirk(tp);
  5371. rtl_wol_shutdown_quirk(tp);
  5372. }
  5373. pci_wake_from_d3(pdev, true);
  5374. pci_set_power_state(pdev, PCI_D3hot);
  5375. }
  5376. pm_runtime_put_noidle(d);
  5377. }
  5378. static void __devexit rtl_remove_one(struct pci_dev *pdev)
  5379. {
  5380. struct net_device *dev = pci_get_drvdata(pdev);
  5381. struct rtl8169_private *tp = netdev_priv(dev);
  5382. if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  5383. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  5384. tp->mac_version == RTL_GIGA_MAC_VER_31) {
  5385. rtl8168_driver_stop(tp);
  5386. }
  5387. cancel_work_sync(&tp->wk.work);
  5388. netif_napi_del(&tp->napi);
  5389. unregister_netdev(dev);
  5390. rtl_release_firmware(tp);
  5391. if (pci_dev_run_wake(pdev))
  5392. pm_runtime_get_noresume(&pdev->dev);
  5393. /* restore original MAC address */
  5394. rtl_rar_set(tp, dev->perm_addr);
  5395. rtl_disable_msi(pdev, tp);
  5396. rtl8169_release_board(pdev, dev, tp->mmio_addr);
  5397. pci_set_drvdata(pdev, NULL);
  5398. }
  5399. static const struct net_device_ops rtl_netdev_ops = {
  5400. .ndo_open = rtl_open,
  5401. .ndo_stop = rtl8169_close,
  5402. .ndo_get_stats64 = rtl8169_get_stats64,
  5403. .ndo_start_xmit = rtl8169_start_xmit,
  5404. .ndo_tx_timeout = rtl8169_tx_timeout,
  5405. .ndo_validate_addr = eth_validate_addr,
  5406. .ndo_change_mtu = rtl8169_change_mtu,
  5407. .ndo_fix_features = rtl8169_fix_features,
  5408. .ndo_set_features = rtl8169_set_features,
  5409. .ndo_set_mac_address = rtl_set_mac_address,
  5410. .ndo_do_ioctl = rtl8169_ioctl,
  5411. .ndo_set_rx_mode = rtl_set_rx_mode,
  5412. #ifdef CONFIG_NET_POLL_CONTROLLER
  5413. .ndo_poll_controller = rtl8169_netpoll,
  5414. #endif
  5415. };
  5416. static const struct rtl_cfg_info {
  5417. void (*hw_start)(struct net_device *);
  5418. unsigned int region;
  5419. unsigned int align;
  5420. u16 event_slow;
  5421. unsigned features;
  5422. u8 default_ver;
  5423. } rtl_cfg_infos [] = {
  5424. [RTL_CFG_0] = {
  5425. .hw_start = rtl_hw_start_8169,
  5426. .region = 1,
  5427. .align = 0,
  5428. .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
  5429. .features = RTL_FEATURE_GMII,
  5430. .default_ver = RTL_GIGA_MAC_VER_01,
  5431. },
  5432. [RTL_CFG_1] = {
  5433. .hw_start = rtl_hw_start_8168,
  5434. .region = 2,
  5435. .align = 8,
  5436. .event_slow = SYSErr | LinkChg | RxOverflow,
  5437. .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
  5438. .default_ver = RTL_GIGA_MAC_VER_11,
  5439. },
  5440. [RTL_CFG_2] = {
  5441. .hw_start = rtl_hw_start_8101,
  5442. .region = 2,
  5443. .align = 8,
  5444. .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
  5445. PCSTimeout,
  5446. .features = RTL_FEATURE_MSI,
  5447. .default_ver = RTL_GIGA_MAC_VER_13,
  5448. }
  5449. };
  5450. /* Cfg9346_Unlock assumed. */
  5451. static unsigned rtl_try_msi(struct rtl8169_private *tp,
  5452. const struct rtl_cfg_info *cfg)
  5453. {
  5454. void __iomem *ioaddr = tp->mmio_addr;
  5455. unsigned msi = 0;
  5456. u8 cfg2;
  5457. cfg2 = RTL_R8(Config2) & ~MSIEnable;
  5458. if (cfg->features & RTL_FEATURE_MSI) {
  5459. if (pci_enable_msi(tp->pci_dev)) {
  5460. netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
  5461. } else {
  5462. cfg2 |= MSIEnable;
  5463. msi = RTL_FEATURE_MSI;
  5464. }
  5465. }
  5466. if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
  5467. RTL_W8(Config2, cfg2);
  5468. return msi;
  5469. }
  5470. DECLARE_RTL_COND(rtl_link_list_ready_cond)
  5471. {
  5472. void __iomem *ioaddr = tp->mmio_addr;
  5473. return RTL_R8(MCU) & LINK_LIST_RDY;
  5474. }
  5475. DECLARE_RTL_COND(rtl_rxtx_empty_cond)
  5476. {
  5477. void __iomem *ioaddr = tp->mmio_addr;
  5478. return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
  5479. }
  5480. static void __devinit rtl_hw_init_8168g(struct rtl8169_private *tp)
  5481. {
  5482. void __iomem *ioaddr = tp->mmio_addr;
  5483. u32 data;
  5484. tp->ocp_base = OCP_STD_PHY_BASE;
  5485. RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
  5486. if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
  5487. return;
  5488. if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
  5489. return;
  5490. RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
  5491. msleep(1);
  5492. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  5493. data = r8168_mac_ocp_read(tp, 0xe8de);
  5494. data &= ~(1 << 14);
  5495. r8168_mac_ocp_write(tp, 0xe8de, data);
  5496. if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
  5497. return;
  5498. data = r8168_mac_ocp_read(tp, 0xe8de);
  5499. data |= (1 << 15);
  5500. r8168_mac_ocp_write(tp, 0xe8de, data);
  5501. if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
  5502. return;
  5503. }
  5504. static void __devinit rtl_hw_initialize(struct rtl8169_private *tp)
  5505. {
  5506. switch (tp->mac_version) {
  5507. case RTL_GIGA_MAC_VER_40:
  5508. case RTL_GIGA_MAC_VER_41:
  5509. rtl_hw_init_8168g(tp);
  5510. break;
  5511. default:
  5512. break;
  5513. }
  5514. }
  5515. static int __devinit
  5516. rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  5517. {
  5518. const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
  5519. const unsigned int region = cfg->region;
  5520. struct rtl8169_private *tp;
  5521. struct mii_if_info *mii;
  5522. struct net_device *dev;
  5523. void __iomem *ioaddr;
  5524. int chipset, i;
  5525. int rc;
  5526. if (netif_msg_drv(&debug)) {
  5527. printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
  5528. MODULENAME, RTL8169_VERSION);
  5529. }
  5530. dev = alloc_etherdev(sizeof (*tp));
  5531. if (!dev) {
  5532. rc = -ENOMEM;
  5533. goto out;
  5534. }
  5535. SET_NETDEV_DEV(dev, &pdev->dev);
  5536. dev->netdev_ops = &rtl_netdev_ops;
  5537. tp = netdev_priv(dev);
  5538. tp->dev = dev;
  5539. tp->pci_dev = pdev;
  5540. tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
  5541. mii = &tp->mii;
  5542. mii->dev = dev;
  5543. mii->mdio_read = rtl_mdio_read;
  5544. mii->mdio_write = rtl_mdio_write;
  5545. mii->phy_id_mask = 0x1f;
  5546. mii->reg_num_mask = 0x1f;
  5547. mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
  5548. /* disable ASPM completely as that cause random device stop working
  5549. * problems as well as full system hangs for some PCIe devices users */
  5550. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  5551. PCIE_LINK_STATE_CLKPM);
  5552. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  5553. rc = pci_enable_device(pdev);
  5554. if (rc < 0) {
  5555. netif_err(tp, probe, dev, "enable failure\n");
  5556. goto err_out_free_dev_1;
  5557. }
  5558. if (pci_set_mwi(pdev) < 0)
  5559. netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
  5560. /* make sure PCI base addr 1 is MMIO */
  5561. if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
  5562. netif_err(tp, probe, dev,
  5563. "region #%d not an MMIO resource, aborting\n",
  5564. region);
  5565. rc = -ENODEV;
  5566. goto err_out_mwi_2;
  5567. }
  5568. /* check for weird/broken PCI region reporting */
  5569. if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
  5570. netif_err(tp, probe, dev,
  5571. "Invalid PCI region size(s), aborting\n");
  5572. rc = -ENODEV;
  5573. goto err_out_mwi_2;
  5574. }
  5575. rc = pci_request_regions(pdev, MODULENAME);
  5576. if (rc < 0) {
  5577. netif_err(tp, probe, dev, "could not request regions\n");
  5578. goto err_out_mwi_2;
  5579. }
  5580. tp->cp_cmd = RxChkSum;
  5581. if ((sizeof(dma_addr_t) > 4) &&
  5582. !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
  5583. tp->cp_cmd |= PCIDAC;
  5584. dev->features |= NETIF_F_HIGHDMA;
  5585. } else {
  5586. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  5587. if (rc < 0) {
  5588. netif_err(tp, probe, dev, "DMA configuration failed\n");
  5589. goto err_out_free_res_3;
  5590. }
  5591. }
  5592. /* ioremap MMIO region */
  5593. ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
  5594. if (!ioaddr) {
  5595. netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
  5596. rc = -EIO;
  5597. goto err_out_free_res_3;
  5598. }
  5599. tp->mmio_addr = ioaddr;
  5600. if (!pci_is_pcie(pdev))
  5601. netif_info(tp, probe, dev, "not PCI Express\n");
  5602. /* Identify chip attached to board */
  5603. rtl8169_get_mac_version(tp, dev, cfg->default_ver);
  5604. rtl_init_rxcfg(tp);
  5605. rtl_irq_disable(tp);
  5606. rtl_hw_initialize(tp);
  5607. rtl_hw_reset(tp);
  5608. rtl_ack_events(tp, 0xffff);
  5609. pci_set_master(pdev);
  5610. /*
  5611. * Pretend we are using VLANs; This bypasses a nasty bug where
  5612. * Interrupts stop flowing on high load on 8110SCd controllers.
  5613. */
  5614. if (tp->mac_version == RTL_GIGA_MAC_VER_05)
  5615. tp->cp_cmd |= RxVlan;
  5616. rtl_init_mdio_ops(tp);
  5617. rtl_init_pll_power_ops(tp);
  5618. rtl_init_jumbo_ops(tp);
  5619. rtl_init_csi_ops(tp);
  5620. rtl8169_print_mac_version(tp);
  5621. chipset = tp->mac_version;
  5622. tp->txd_version = rtl_chip_infos[chipset].txd_version;
  5623. RTL_W8(Cfg9346, Cfg9346_Unlock);
  5624. RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
  5625. RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
  5626. if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
  5627. tp->features |= RTL_FEATURE_WOL;
  5628. if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
  5629. tp->features |= RTL_FEATURE_WOL;
  5630. tp->features |= rtl_try_msi(tp, cfg);
  5631. RTL_W8(Cfg9346, Cfg9346_Lock);
  5632. if (rtl_tbi_enabled(tp)) {
  5633. tp->set_speed = rtl8169_set_speed_tbi;
  5634. tp->get_settings = rtl8169_gset_tbi;
  5635. tp->phy_reset_enable = rtl8169_tbi_reset_enable;
  5636. tp->phy_reset_pending = rtl8169_tbi_reset_pending;
  5637. tp->link_ok = rtl8169_tbi_link_ok;
  5638. tp->do_ioctl = rtl_tbi_ioctl;
  5639. } else {
  5640. tp->set_speed = rtl8169_set_speed_xmii;
  5641. tp->get_settings = rtl8169_gset_xmii;
  5642. tp->phy_reset_enable = rtl8169_xmii_reset_enable;
  5643. tp->phy_reset_pending = rtl8169_xmii_reset_pending;
  5644. tp->link_ok = rtl8169_xmii_link_ok;
  5645. tp->do_ioctl = rtl_xmii_ioctl;
  5646. }
  5647. mutex_init(&tp->wk.mutex);
  5648. /* Get MAC address */
  5649. for (i = 0; i < ETH_ALEN; i++)
  5650. dev->dev_addr[i] = RTL_R8(MAC0 + i);
  5651. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  5652. SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
  5653. dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
  5654. netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
  5655. /* don't enable SG, IP_CSUM and TSO by default - it might not work
  5656. * properly for all devices */
  5657. dev->features |= NETIF_F_RXCSUM |
  5658. NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  5659. dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  5660. NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  5661. dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  5662. NETIF_F_HIGHDMA;
  5663. if (tp->mac_version == RTL_GIGA_MAC_VER_05)
  5664. /* 8110SCd requires hardware Rx VLAN - disallow toggling */
  5665. dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
  5666. dev->hw_features |= NETIF_F_RXALL;
  5667. dev->hw_features |= NETIF_F_RXFCS;
  5668. tp->hw_start = cfg->hw_start;
  5669. tp->event_slow = cfg->event_slow;
  5670. tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
  5671. ~(RxBOVF | RxFOVF) : ~0;
  5672. init_timer(&tp->timer);
  5673. tp->timer.data = (unsigned long) dev;
  5674. tp->timer.function = rtl8169_phy_timer;
  5675. tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
  5676. rc = register_netdev(dev);
  5677. if (rc < 0)
  5678. goto err_out_msi_4;
  5679. pci_set_drvdata(pdev, dev);
  5680. netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
  5681. rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
  5682. (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
  5683. if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
  5684. netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
  5685. "tx checksumming: %s]\n",
  5686. rtl_chip_infos[chipset].jumbo_max,
  5687. rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
  5688. }
  5689. if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  5690. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  5691. tp->mac_version == RTL_GIGA_MAC_VER_31) {
  5692. rtl8168_driver_start(tp);
  5693. }
  5694. device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
  5695. if (pci_dev_run_wake(pdev))
  5696. pm_runtime_put_noidle(&pdev->dev);
  5697. netif_carrier_off(dev);
  5698. out:
  5699. return rc;
  5700. err_out_msi_4:
  5701. netif_napi_del(&tp->napi);
  5702. rtl_disable_msi(pdev, tp);
  5703. iounmap(ioaddr);
  5704. err_out_free_res_3:
  5705. pci_release_regions(pdev);
  5706. err_out_mwi_2:
  5707. pci_clear_mwi(pdev);
  5708. pci_disable_device(pdev);
  5709. err_out_free_dev_1:
  5710. free_netdev(dev);
  5711. goto out;
  5712. }
  5713. static struct pci_driver rtl8169_pci_driver = {
  5714. .name = MODULENAME,
  5715. .id_table = rtl8169_pci_tbl,
  5716. .probe = rtl_init_one,
  5717. .remove = __devexit_p(rtl_remove_one),
  5718. .shutdown = rtl_shutdown,
  5719. .driver.pm = RTL8169_PM_OPS,
  5720. };
  5721. static int __init rtl8169_init_module(void)
  5722. {
  5723. return pci_register_driver(&rtl8169_pci_driver);
  5724. }
  5725. static void __exit rtl8169_cleanup_module(void)
  5726. {
  5727. pci_unregister_driver(&rtl8169_pci_driver);
  5728. }
  5729. module_init(rtl8169_init_module);
  5730. module_exit(rtl8169_cleanup_module);