cq.c 21 KB

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  1. /*
  2. * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/mlx4/cq.h>
  34. #include <linux/mlx4/qp.h>
  35. #include <linux/slab.h>
  36. #include "mlx4_ib.h"
  37. #include "user.h"
  38. static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
  39. {
  40. struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  41. ibcq->comp_handler(ibcq, ibcq->cq_context);
  42. }
  43. static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
  44. {
  45. struct ib_event event;
  46. struct ib_cq *ibcq;
  47. if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
  48. pr_warn("Unexpected event type %d "
  49. "on CQ %06x\n", type, cq->cqn);
  50. return;
  51. }
  52. ibcq = &to_mibcq(cq)->ibcq;
  53. if (ibcq->event_handler) {
  54. event.device = ibcq->device;
  55. event.event = IB_EVENT_CQ_ERR;
  56. event.element.cq = ibcq;
  57. ibcq->event_handler(&event, ibcq->cq_context);
  58. }
  59. }
  60. static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
  61. {
  62. return mlx4_buf_offset(&buf->buf, n * sizeof (struct mlx4_cqe));
  63. }
  64. static void *get_cqe(struct mlx4_ib_cq *cq, int n)
  65. {
  66. return get_cqe_from_buf(&cq->buf, n);
  67. }
  68. static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
  69. {
  70. struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  71. return (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
  72. !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
  73. }
  74. static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
  75. {
  76. return get_sw_cqe(cq, cq->mcq.cons_index);
  77. }
  78. int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
  79. {
  80. struct mlx4_ib_cq *mcq = to_mcq(cq);
  81. struct mlx4_ib_dev *dev = to_mdev(cq->device);
  82. return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
  83. }
  84. static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
  85. {
  86. int err;
  87. err = mlx4_buf_alloc(dev->dev, nent * sizeof(struct mlx4_cqe),
  88. PAGE_SIZE * 2, &buf->buf);
  89. if (err)
  90. goto out;
  91. err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
  92. &buf->mtt);
  93. if (err)
  94. goto err_buf;
  95. err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf);
  96. if (err)
  97. goto err_mtt;
  98. return 0;
  99. err_mtt:
  100. mlx4_mtt_cleanup(dev->dev, &buf->mtt);
  101. err_buf:
  102. mlx4_buf_free(dev->dev, nent * sizeof(struct mlx4_cqe),
  103. &buf->buf);
  104. out:
  105. return err;
  106. }
  107. static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
  108. {
  109. mlx4_buf_free(dev->dev, (cqe + 1) * sizeof(struct mlx4_cqe), &buf->buf);
  110. }
  111. static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
  112. struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
  113. u64 buf_addr, int cqe)
  114. {
  115. int err;
  116. *umem = ib_umem_get(context, buf_addr, cqe * sizeof (struct mlx4_cqe),
  117. IB_ACCESS_LOCAL_WRITE, 1);
  118. if (IS_ERR(*umem))
  119. return PTR_ERR(*umem);
  120. err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
  121. ilog2((*umem)->page_size), &buf->mtt);
  122. if (err)
  123. goto err_buf;
  124. err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
  125. if (err)
  126. goto err_mtt;
  127. return 0;
  128. err_mtt:
  129. mlx4_mtt_cleanup(dev->dev, &buf->mtt);
  130. err_buf:
  131. ib_umem_release(*umem);
  132. return err;
  133. }
  134. struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
  135. struct ib_ucontext *context,
  136. struct ib_udata *udata)
  137. {
  138. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  139. struct mlx4_ib_cq *cq;
  140. struct mlx4_uar *uar;
  141. int err;
  142. if (entries < 1 || entries > dev->dev->caps.max_cqes)
  143. return ERR_PTR(-EINVAL);
  144. cq = kmalloc(sizeof *cq, GFP_KERNEL);
  145. if (!cq)
  146. return ERR_PTR(-ENOMEM);
  147. entries = roundup_pow_of_two(entries + 1);
  148. cq->ibcq.cqe = entries - 1;
  149. mutex_init(&cq->resize_mutex);
  150. spin_lock_init(&cq->lock);
  151. cq->resize_buf = NULL;
  152. cq->resize_umem = NULL;
  153. if (context) {
  154. struct mlx4_ib_create_cq ucmd;
  155. if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
  156. err = -EFAULT;
  157. goto err_cq;
  158. }
  159. err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
  160. ucmd.buf_addr, entries);
  161. if (err)
  162. goto err_cq;
  163. err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
  164. &cq->db);
  165. if (err)
  166. goto err_mtt;
  167. uar = &to_mucontext(context)->uar;
  168. } else {
  169. err = mlx4_db_alloc(dev->dev, &cq->db, 1);
  170. if (err)
  171. goto err_cq;
  172. cq->mcq.set_ci_db = cq->db.db;
  173. cq->mcq.arm_db = cq->db.db + 1;
  174. *cq->mcq.set_ci_db = 0;
  175. *cq->mcq.arm_db = 0;
  176. err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
  177. if (err)
  178. goto err_db;
  179. uar = &dev->priv_uar;
  180. }
  181. if (dev->eq_table)
  182. vector = dev->eq_table[vector % ibdev->num_comp_vectors];
  183. err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
  184. cq->db.dma, &cq->mcq, vector, 0);
  185. if (err)
  186. goto err_dbmap;
  187. cq->mcq.comp = mlx4_ib_cq_comp;
  188. cq->mcq.event = mlx4_ib_cq_event;
  189. if (context)
  190. if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
  191. err = -EFAULT;
  192. goto err_dbmap;
  193. }
  194. return &cq->ibcq;
  195. err_dbmap:
  196. if (context)
  197. mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
  198. err_mtt:
  199. mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
  200. if (context)
  201. ib_umem_release(cq->umem);
  202. else
  203. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  204. err_db:
  205. if (!context)
  206. mlx4_db_free(dev->dev, &cq->db);
  207. err_cq:
  208. kfree(cq);
  209. return ERR_PTR(err);
  210. }
  211. static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
  212. int entries)
  213. {
  214. int err;
  215. if (cq->resize_buf)
  216. return -EBUSY;
  217. cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
  218. if (!cq->resize_buf)
  219. return -ENOMEM;
  220. err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
  221. if (err) {
  222. kfree(cq->resize_buf);
  223. cq->resize_buf = NULL;
  224. return err;
  225. }
  226. cq->resize_buf->cqe = entries - 1;
  227. return 0;
  228. }
  229. static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
  230. int entries, struct ib_udata *udata)
  231. {
  232. struct mlx4_ib_resize_cq ucmd;
  233. int err;
  234. if (cq->resize_umem)
  235. return -EBUSY;
  236. if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
  237. return -EFAULT;
  238. cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
  239. if (!cq->resize_buf)
  240. return -ENOMEM;
  241. err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
  242. &cq->resize_umem, ucmd.buf_addr, entries);
  243. if (err) {
  244. kfree(cq->resize_buf);
  245. cq->resize_buf = NULL;
  246. return err;
  247. }
  248. cq->resize_buf->cqe = entries - 1;
  249. return 0;
  250. }
  251. static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
  252. {
  253. u32 i;
  254. i = cq->mcq.cons_index;
  255. while (get_sw_cqe(cq, i & cq->ibcq.cqe))
  256. ++i;
  257. return i - cq->mcq.cons_index;
  258. }
  259. static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
  260. {
  261. struct mlx4_cqe *cqe, *new_cqe;
  262. int i;
  263. i = cq->mcq.cons_index;
  264. cqe = get_cqe(cq, i & cq->ibcq.cqe);
  265. while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
  266. new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
  267. (i + 1) & cq->resize_buf->cqe);
  268. memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), sizeof(struct mlx4_cqe));
  269. new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
  270. (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
  271. cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
  272. }
  273. ++cq->mcq.cons_index;
  274. }
  275. int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
  276. {
  277. struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
  278. struct mlx4_ib_cq *cq = to_mcq(ibcq);
  279. struct mlx4_mtt mtt;
  280. int outst_cqe;
  281. int err;
  282. mutex_lock(&cq->resize_mutex);
  283. if (entries < 1 || entries > dev->dev->caps.max_cqes) {
  284. err = -EINVAL;
  285. goto out;
  286. }
  287. entries = roundup_pow_of_two(entries + 1);
  288. if (entries == ibcq->cqe + 1) {
  289. err = 0;
  290. goto out;
  291. }
  292. if (ibcq->uobject) {
  293. err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
  294. if (err)
  295. goto out;
  296. } else {
  297. /* Can't be smaller than the number of outstanding CQEs */
  298. outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
  299. if (entries < outst_cqe + 1) {
  300. err = 0;
  301. goto out;
  302. }
  303. err = mlx4_alloc_resize_buf(dev, cq, entries);
  304. if (err)
  305. goto out;
  306. }
  307. mtt = cq->buf.mtt;
  308. err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
  309. if (err)
  310. goto err_buf;
  311. mlx4_mtt_cleanup(dev->dev, &mtt);
  312. if (ibcq->uobject) {
  313. cq->buf = cq->resize_buf->buf;
  314. cq->ibcq.cqe = cq->resize_buf->cqe;
  315. ib_umem_release(cq->umem);
  316. cq->umem = cq->resize_umem;
  317. kfree(cq->resize_buf);
  318. cq->resize_buf = NULL;
  319. cq->resize_umem = NULL;
  320. } else {
  321. struct mlx4_ib_cq_buf tmp_buf;
  322. int tmp_cqe = 0;
  323. spin_lock_irq(&cq->lock);
  324. if (cq->resize_buf) {
  325. mlx4_ib_cq_resize_copy_cqes(cq);
  326. tmp_buf = cq->buf;
  327. tmp_cqe = cq->ibcq.cqe;
  328. cq->buf = cq->resize_buf->buf;
  329. cq->ibcq.cqe = cq->resize_buf->cqe;
  330. kfree(cq->resize_buf);
  331. cq->resize_buf = NULL;
  332. }
  333. spin_unlock_irq(&cq->lock);
  334. if (tmp_cqe)
  335. mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
  336. }
  337. goto out;
  338. err_buf:
  339. mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
  340. if (!ibcq->uobject)
  341. mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
  342. cq->resize_buf->cqe);
  343. kfree(cq->resize_buf);
  344. cq->resize_buf = NULL;
  345. if (cq->resize_umem) {
  346. ib_umem_release(cq->resize_umem);
  347. cq->resize_umem = NULL;
  348. }
  349. out:
  350. mutex_unlock(&cq->resize_mutex);
  351. return err;
  352. }
  353. int mlx4_ib_destroy_cq(struct ib_cq *cq)
  354. {
  355. struct mlx4_ib_dev *dev = to_mdev(cq->device);
  356. struct mlx4_ib_cq *mcq = to_mcq(cq);
  357. mlx4_cq_free(dev->dev, &mcq->mcq);
  358. mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
  359. if (cq->uobject) {
  360. mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
  361. ib_umem_release(mcq->umem);
  362. } else {
  363. mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
  364. mlx4_db_free(dev->dev, &mcq->db);
  365. }
  366. kfree(mcq);
  367. return 0;
  368. }
  369. static void dump_cqe(void *cqe)
  370. {
  371. __be32 *buf = cqe;
  372. pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
  373. be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
  374. be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
  375. be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
  376. }
  377. static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
  378. struct ib_wc *wc)
  379. {
  380. if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
  381. pr_debug("local QP operation err "
  382. "(QPN %06x, WQE index %x, vendor syndrome %02x, "
  383. "opcode = %02x)\n",
  384. be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
  385. cqe->vendor_err_syndrome,
  386. cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
  387. dump_cqe(cqe);
  388. }
  389. switch (cqe->syndrome) {
  390. case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
  391. wc->status = IB_WC_LOC_LEN_ERR;
  392. break;
  393. case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
  394. wc->status = IB_WC_LOC_QP_OP_ERR;
  395. break;
  396. case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
  397. wc->status = IB_WC_LOC_PROT_ERR;
  398. break;
  399. case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
  400. wc->status = IB_WC_WR_FLUSH_ERR;
  401. break;
  402. case MLX4_CQE_SYNDROME_MW_BIND_ERR:
  403. wc->status = IB_WC_MW_BIND_ERR;
  404. break;
  405. case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
  406. wc->status = IB_WC_BAD_RESP_ERR;
  407. break;
  408. case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
  409. wc->status = IB_WC_LOC_ACCESS_ERR;
  410. break;
  411. case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
  412. wc->status = IB_WC_REM_INV_REQ_ERR;
  413. break;
  414. case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
  415. wc->status = IB_WC_REM_ACCESS_ERR;
  416. break;
  417. case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
  418. wc->status = IB_WC_REM_OP_ERR;
  419. break;
  420. case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
  421. wc->status = IB_WC_RETRY_EXC_ERR;
  422. break;
  423. case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
  424. wc->status = IB_WC_RNR_RETRY_EXC_ERR;
  425. break;
  426. case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
  427. wc->status = IB_WC_REM_ABORT_ERR;
  428. break;
  429. default:
  430. wc->status = IB_WC_GENERAL_ERR;
  431. break;
  432. }
  433. wc->vendor_err = cqe->vendor_err_syndrome;
  434. }
  435. static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
  436. {
  437. return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
  438. MLX4_CQE_STATUS_IPV4F |
  439. MLX4_CQE_STATUS_IPV4OPT |
  440. MLX4_CQE_STATUS_IPV6 |
  441. MLX4_CQE_STATUS_IPOK)) ==
  442. cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
  443. MLX4_CQE_STATUS_IPOK)) &&
  444. (status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
  445. MLX4_CQE_STATUS_TCP)) &&
  446. checksum == cpu_to_be16(0xffff);
  447. }
  448. static int use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
  449. unsigned tail, struct mlx4_cqe *cqe)
  450. {
  451. struct mlx4_ib_proxy_sqp_hdr *hdr;
  452. ib_dma_sync_single_for_cpu(qp->ibqp.device,
  453. qp->sqp_proxy_rcv[tail].map,
  454. sizeof (struct mlx4_ib_proxy_sqp_hdr),
  455. DMA_FROM_DEVICE);
  456. hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
  457. wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index);
  458. wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32);
  459. wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
  460. wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
  461. wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
  462. wc->dlid_path_bits = 0;
  463. return 0;
  464. }
  465. static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
  466. struct mlx4_ib_qp **cur_qp,
  467. struct ib_wc *wc)
  468. {
  469. struct mlx4_cqe *cqe;
  470. struct mlx4_qp *mqp;
  471. struct mlx4_ib_wq *wq;
  472. struct mlx4_ib_srq *srq;
  473. int is_send;
  474. int is_error;
  475. u32 g_mlpath_rqpn;
  476. u16 wqe_ctr;
  477. unsigned tail = 0;
  478. repoll:
  479. cqe = next_cqe_sw(cq);
  480. if (!cqe)
  481. return -EAGAIN;
  482. ++cq->mcq.cons_index;
  483. /*
  484. * Make sure we read CQ entry contents after we've checked the
  485. * ownership bit.
  486. */
  487. rmb();
  488. is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
  489. is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  490. MLX4_CQE_OPCODE_ERROR;
  491. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
  492. is_send)) {
  493. pr_warn("Completion for NOP opcode detected!\n");
  494. return -EINVAL;
  495. }
  496. /* Resize CQ in progress */
  497. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
  498. if (cq->resize_buf) {
  499. struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
  500. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  501. cq->buf = cq->resize_buf->buf;
  502. cq->ibcq.cqe = cq->resize_buf->cqe;
  503. kfree(cq->resize_buf);
  504. cq->resize_buf = NULL;
  505. }
  506. goto repoll;
  507. }
  508. if (!*cur_qp ||
  509. (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
  510. /*
  511. * We do not have to take the QP table lock here,
  512. * because CQs will be locked while QPs are removed
  513. * from the table.
  514. */
  515. mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
  516. be32_to_cpu(cqe->vlan_my_qpn));
  517. if (unlikely(!mqp)) {
  518. pr_warn("CQ %06x with entry for unknown QPN %06x\n",
  519. cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
  520. return -EINVAL;
  521. }
  522. *cur_qp = to_mibqp(mqp);
  523. }
  524. wc->qp = &(*cur_qp)->ibqp;
  525. if (is_send) {
  526. wq = &(*cur_qp)->sq;
  527. if (!(*cur_qp)->sq_signal_bits) {
  528. wqe_ctr = be16_to_cpu(cqe->wqe_index);
  529. wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
  530. }
  531. wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
  532. ++wq->tail;
  533. } else if ((*cur_qp)->ibqp.srq) {
  534. srq = to_msrq((*cur_qp)->ibqp.srq);
  535. wqe_ctr = be16_to_cpu(cqe->wqe_index);
  536. wc->wr_id = srq->wrid[wqe_ctr];
  537. mlx4_ib_free_srq_wqe(srq, wqe_ctr);
  538. } else {
  539. wq = &(*cur_qp)->rq;
  540. tail = wq->tail & (wq->wqe_cnt - 1);
  541. wc->wr_id = wq->wrid[tail];
  542. ++wq->tail;
  543. }
  544. if (unlikely(is_error)) {
  545. mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
  546. return 0;
  547. }
  548. wc->status = IB_WC_SUCCESS;
  549. if (is_send) {
  550. wc->wc_flags = 0;
  551. switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
  552. case MLX4_OPCODE_RDMA_WRITE_IMM:
  553. wc->wc_flags |= IB_WC_WITH_IMM;
  554. case MLX4_OPCODE_RDMA_WRITE:
  555. wc->opcode = IB_WC_RDMA_WRITE;
  556. break;
  557. case MLX4_OPCODE_SEND_IMM:
  558. wc->wc_flags |= IB_WC_WITH_IMM;
  559. case MLX4_OPCODE_SEND:
  560. case MLX4_OPCODE_SEND_INVAL:
  561. wc->opcode = IB_WC_SEND;
  562. break;
  563. case MLX4_OPCODE_RDMA_READ:
  564. wc->opcode = IB_WC_RDMA_READ;
  565. wc->byte_len = be32_to_cpu(cqe->byte_cnt);
  566. break;
  567. case MLX4_OPCODE_ATOMIC_CS:
  568. wc->opcode = IB_WC_COMP_SWAP;
  569. wc->byte_len = 8;
  570. break;
  571. case MLX4_OPCODE_ATOMIC_FA:
  572. wc->opcode = IB_WC_FETCH_ADD;
  573. wc->byte_len = 8;
  574. break;
  575. case MLX4_OPCODE_MASKED_ATOMIC_CS:
  576. wc->opcode = IB_WC_MASKED_COMP_SWAP;
  577. wc->byte_len = 8;
  578. break;
  579. case MLX4_OPCODE_MASKED_ATOMIC_FA:
  580. wc->opcode = IB_WC_MASKED_FETCH_ADD;
  581. wc->byte_len = 8;
  582. break;
  583. case MLX4_OPCODE_BIND_MW:
  584. wc->opcode = IB_WC_BIND_MW;
  585. break;
  586. case MLX4_OPCODE_LSO:
  587. wc->opcode = IB_WC_LSO;
  588. break;
  589. case MLX4_OPCODE_FMR:
  590. wc->opcode = IB_WC_FAST_REG_MR;
  591. break;
  592. case MLX4_OPCODE_LOCAL_INVAL:
  593. wc->opcode = IB_WC_LOCAL_INV;
  594. break;
  595. }
  596. } else {
  597. wc->byte_len = be32_to_cpu(cqe->byte_cnt);
  598. switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
  599. case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
  600. wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  601. wc->wc_flags = IB_WC_WITH_IMM;
  602. wc->ex.imm_data = cqe->immed_rss_invalid;
  603. break;
  604. case MLX4_RECV_OPCODE_SEND_INVAL:
  605. wc->opcode = IB_WC_RECV;
  606. wc->wc_flags = IB_WC_WITH_INVALIDATE;
  607. wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
  608. break;
  609. case MLX4_RECV_OPCODE_SEND:
  610. wc->opcode = IB_WC_RECV;
  611. wc->wc_flags = 0;
  612. break;
  613. case MLX4_RECV_OPCODE_SEND_IMM:
  614. wc->opcode = IB_WC_RECV;
  615. wc->wc_flags = IB_WC_WITH_IMM;
  616. wc->ex.imm_data = cqe->immed_rss_invalid;
  617. break;
  618. }
  619. if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
  620. if ((*cur_qp)->mlx4_ib_qp_type &
  621. (MLX4_IB_QPT_PROXY_SMI_OWNER |
  622. MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
  623. return use_tunnel_data(*cur_qp, cq, wc, tail, cqe);
  624. }
  625. wc->slid = be16_to_cpu(cqe->rlid);
  626. g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
  627. wc->src_qp = g_mlpath_rqpn & 0xffffff;
  628. wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
  629. wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
  630. wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
  631. wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status,
  632. cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
  633. if (rdma_port_get_link_layer(wc->qp->device,
  634. (*cur_qp)->port) == IB_LINK_LAYER_ETHERNET)
  635. wc->sl = be16_to_cpu(cqe->sl_vid) >> 13;
  636. else
  637. wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
  638. }
  639. return 0;
  640. }
  641. int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  642. {
  643. struct mlx4_ib_cq *cq = to_mcq(ibcq);
  644. struct mlx4_ib_qp *cur_qp = NULL;
  645. unsigned long flags;
  646. int npolled;
  647. int err = 0;
  648. spin_lock_irqsave(&cq->lock, flags);
  649. for (npolled = 0; npolled < num_entries; ++npolled) {
  650. err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
  651. if (err)
  652. break;
  653. }
  654. mlx4_cq_set_ci(&cq->mcq);
  655. spin_unlock_irqrestore(&cq->lock, flags);
  656. if (err == 0 || err == -EAGAIN)
  657. return npolled;
  658. else
  659. return err;
  660. }
  661. int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
  662. {
  663. mlx4_cq_arm(&to_mcq(ibcq)->mcq,
  664. (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
  665. MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
  666. to_mdev(ibcq->device)->uar_map,
  667. MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
  668. return 0;
  669. }
  670. void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
  671. {
  672. u32 prod_index;
  673. int nfreed = 0;
  674. struct mlx4_cqe *cqe, *dest;
  675. u8 owner_bit;
  676. /*
  677. * First we need to find the current producer index, so we
  678. * know where to start cleaning from. It doesn't matter if HW
  679. * adds new entries after this loop -- the QP we're worried
  680. * about is already in RESET, so the new entries won't come
  681. * from our QP and therefore don't need to be checked.
  682. */
  683. for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
  684. if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
  685. break;
  686. /*
  687. * Now sweep backwards through the CQ, removing CQ entries
  688. * that match our QP by copying older entries on top of them.
  689. */
  690. while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
  691. cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
  692. if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
  693. if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
  694. mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
  695. ++nfreed;
  696. } else if (nfreed) {
  697. dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
  698. owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
  699. memcpy(dest, cqe, sizeof *cqe);
  700. dest->owner_sr_opcode = owner_bit |
  701. (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
  702. }
  703. }
  704. if (nfreed) {
  705. cq->mcq.cons_index += nfreed;
  706. /*
  707. * Make sure update of buffer contents is done before
  708. * updating consumer index.
  709. */
  710. wmb();
  711. mlx4_cq_set_ci(&cq->mcq);
  712. }
  713. }
  714. void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
  715. {
  716. spin_lock_irq(&cq->lock);
  717. __mlx4_ib_cq_clean(cq, qpn, srq);
  718. spin_unlock_irq(&cq->lock);
  719. }