dev-usb.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238
  1. /*
  2. * Atheros AR7XXX/AR9XXX USB Host Controller device
  3. *
  4. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  5. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  6. *
  7. * Parts of this file are based on Atheros' 2.6.15 BSP
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License version 2 as published
  11. * by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/irq.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/usb/ehci_pdriver.h>
  20. #include <linux/usb/ohci_pdriver.h>
  21. #include <asm/mach-ath79/ath79.h>
  22. #include <asm/mach-ath79/ar71xx_regs.h>
  23. #include "common.h"
  24. #include "dev-usb.h"
  25. static struct resource ath79_ohci_resources[2];
  26. static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
  27. static struct usb_ohci_pdata ath79_ohci_pdata = {
  28. };
  29. static struct platform_device ath79_ohci_device = {
  30. .name = "ohci-platform",
  31. .id = -1,
  32. .resource = ath79_ohci_resources,
  33. .num_resources = ARRAY_SIZE(ath79_ohci_resources),
  34. .dev = {
  35. .dma_mask = &ath79_ohci_dmamask,
  36. .coherent_dma_mask = DMA_BIT_MASK(32),
  37. .platform_data = &ath79_ohci_pdata,
  38. },
  39. };
  40. static struct resource ath79_ehci_resources[2];
  41. static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
  42. static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
  43. .has_synopsys_hc_bug = 1,
  44. .port_power_off = 1,
  45. };
  46. static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
  47. .caps_offset = 0x100,
  48. .has_tt = 1,
  49. .port_power_off = 1,
  50. };
  51. static struct platform_device ath79_ehci_device = {
  52. .name = "ehci-platform",
  53. .id = -1,
  54. .resource = ath79_ehci_resources,
  55. .num_resources = ARRAY_SIZE(ath79_ehci_resources),
  56. .dev = {
  57. .dma_mask = &ath79_ehci_dmamask,
  58. .coherent_dma_mask = DMA_BIT_MASK(32),
  59. },
  60. };
  61. static void __init ath79_usb_init_resource(struct resource res[2],
  62. unsigned long base,
  63. unsigned long size,
  64. int irq)
  65. {
  66. res[0].flags = IORESOURCE_MEM;
  67. res[0].start = base;
  68. res[0].end = base + size - 1;
  69. res[1].flags = IORESOURCE_IRQ;
  70. res[1].start = irq;
  71. res[1].end = irq;
  72. }
  73. #define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
  74. AR71XX_RESET_USB_PHY | \
  75. AR71XX_RESET_USB_OHCI_DLL)
  76. static void __init ath79_usb_setup(void)
  77. {
  78. void __iomem *usb_ctrl_base;
  79. ath79_device_reset_set(AR71XX_USB_RESET_MASK);
  80. mdelay(1000);
  81. ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
  82. usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
  83. /* Turning on the Buff and Desc swap bits */
  84. __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
  85. /* WAR for HW bug. Here it adjusts the duration between two SOFS */
  86. __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
  87. iounmap(usb_ctrl_base);
  88. mdelay(900);
  89. ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE,
  90. AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI);
  91. platform_device_register(&ath79_ohci_device);
  92. ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
  93. AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB);
  94. ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1;
  95. platform_device_register(&ath79_ehci_device);
  96. }
  97. static void __init ar7240_usb_setup(void)
  98. {
  99. void __iomem *usb_ctrl_base;
  100. ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
  101. ath79_device_reset_set(AR7240_RESET_USB_HOST);
  102. mdelay(1000);
  103. ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
  104. ath79_device_reset_clear(AR7240_RESET_USB_HOST);
  105. usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
  106. /* WAR for HW bug. Here it adjusts the duration between two SOFS */
  107. __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
  108. iounmap(usb_ctrl_base);
  109. ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE,
  110. AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB);
  111. platform_device_register(&ath79_ohci_device);
  112. }
  113. static void __init ar724x_usb_setup(void)
  114. {
  115. ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
  116. mdelay(10);
  117. ath79_device_reset_clear(AR724X_RESET_USB_HOST);
  118. mdelay(10);
  119. ath79_device_reset_clear(AR724X_RESET_USB_PHY);
  120. mdelay(10);
  121. ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE,
  122. AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
  123. ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
  124. platform_device_register(&ath79_ehci_device);
  125. }
  126. static void __init ar913x_usb_setup(void)
  127. {
  128. ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
  129. mdelay(10);
  130. ath79_device_reset_clear(AR913X_RESET_USB_HOST);
  131. mdelay(10);
  132. ath79_device_reset_clear(AR913X_RESET_USB_PHY);
  133. mdelay(10);
  134. ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE,
  135. AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
  136. ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
  137. platform_device_register(&ath79_ehci_device);
  138. }
  139. static void __init ar933x_usb_setup(void)
  140. {
  141. ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
  142. mdelay(10);
  143. ath79_device_reset_clear(AR933X_RESET_USB_HOST);
  144. mdelay(10);
  145. ath79_device_reset_clear(AR933X_RESET_USB_PHY);
  146. mdelay(10);
  147. ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE,
  148. AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
  149. ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
  150. platform_device_register(&ath79_ehci_device);
  151. }
  152. static void __init ar934x_usb_setup(void)
  153. {
  154. u32 bootstrap;
  155. bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
  156. if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
  157. return;
  158. ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
  159. udelay(1000);
  160. ath79_device_reset_clear(AR934X_RESET_USB_PHY);
  161. udelay(1000);
  162. ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
  163. udelay(1000);
  164. ath79_device_reset_clear(AR934X_RESET_USB_HOST);
  165. udelay(1000);
  166. ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
  167. AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
  168. ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
  169. platform_device_register(&ath79_ehci_device);
  170. }
  171. void __init ath79_register_usb(void)
  172. {
  173. if (soc_is_ar71xx())
  174. ath79_usb_setup();
  175. else if (soc_is_ar7240())
  176. ar7240_usb_setup();
  177. else if (soc_is_ar7241() || soc_is_ar7242())
  178. ar724x_usb_setup();
  179. else if (soc_is_ar913x())
  180. ar913x_usb_setup();
  181. else if (soc_is_ar933x())
  182. ar933x_usb_setup();
  183. else if (soc_is_ar934x())
  184. ar934x_usb_setup();
  185. else
  186. BUG();
  187. }