tegra20-paz00.dts 11 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "Toshiba AC100 / Dynabook AZ";
  5. compatible = "compal,paz00", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x20000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata", "atc", "atd", "ate",
  15. "dap2", "gmb", "gmc", "gmd", "spia",
  16. "spib", "spic", "spid", "spie";
  17. nvidia,function = "gmi";
  18. };
  19. atb {
  20. nvidia,pins = "atb", "gma", "gme";
  21. nvidia,function = "sdio4";
  22. };
  23. cdev1 {
  24. nvidia,pins = "cdev1";
  25. nvidia,function = "plla_out";
  26. };
  27. cdev2 {
  28. nvidia,pins = "cdev2";
  29. nvidia,function = "pllp_out4";
  30. };
  31. crtp {
  32. nvidia,pins = "crtp";
  33. nvidia,function = "crt";
  34. };
  35. csus {
  36. nvidia,pins = "csus";
  37. nvidia,function = "pllc_out1";
  38. };
  39. dap1 {
  40. nvidia,pins = "dap1";
  41. nvidia,function = "dap1";
  42. };
  43. dap3 {
  44. nvidia,pins = "dap3";
  45. nvidia,function = "dap3";
  46. };
  47. dap4 {
  48. nvidia,pins = "dap4";
  49. nvidia,function = "dap4";
  50. };
  51. ddc {
  52. nvidia,pins = "ddc";
  53. nvidia,function = "i2c2";
  54. };
  55. dta {
  56. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  57. nvidia,function = "rsvd1";
  58. };
  59. dtf {
  60. nvidia,pins = "dtf";
  61. nvidia,function = "i2c3";
  62. };
  63. gpu {
  64. nvidia,pins = "gpu", "sdb", "sdd";
  65. nvidia,function = "pwm";
  66. };
  67. gpu7 {
  68. nvidia,pins = "gpu7";
  69. nvidia,function = "rtck";
  70. };
  71. gpv {
  72. nvidia,pins = "gpv", "slxa", "slxk";
  73. nvidia,function = "pcie";
  74. };
  75. hdint {
  76. nvidia,pins = "hdint", "pta";
  77. nvidia,function = "hdmi";
  78. };
  79. i2cp {
  80. nvidia,pins = "i2cp";
  81. nvidia,function = "i2cp";
  82. };
  83. irrx {
  84. nvidia,pins = "irrx", "irtx";
  85. nvidia,function = "uarta";
  86. };
  87. kbca {
  88. nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
  89. nvidia,function = "kbc";
  90. };
  91. kbcb {
  92. nvidia,pins = "kbcb", "kbcd";
  93. nvidia,function = "sdio2";
  94. };
  95. lcsn {
  96. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  97. "ld3", "ld4", "ld5", "ld6", "ld7",
  98. "ld8", "ld9", "ld10", "ld11", "ld12",
  99. "ld13", "ld14", "ld15", "ld16", "ld17",
  100. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  101. "lhs", "lm0", "lm1", "lpp", "lpw0",
  102. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  103. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  104. "lvs";
  105. nvidia,function = "displaya";
  106. };
  107. owc {
  108. nvidia,pins = "owc";
  109. nvidia,function = "owr";
  110. };
  111. pmc {
  112. nvidia,pins = "pmc";
  113. nvidia,function = "pwr_on";
  114. };
  115. rm {
  116. nvidia,pins = "rm";
  117. nvidia,function = "i2c1";
  118. };
  119. sdc {
  120. nvidia,pins = "sdc";
  121. nvidia,function = "twc";
  122. };
  123. sdio1 {
  124. nvidia,pins = "sdio1";
  125. nvidia,function = "sdio1";
  126. };
  127. slxc {
  128. nvidia,pins = "slxc", "slxd";
  129. nvidia,function = "spi4";
  130. };
  131. spdi {
  132. nvidia,pins = "spdi", "spdo";
  133. nvidia,function = "rsvd2";
  134. };
  135. spif {
  136. nvidia,pins = "spif", "uac";
  137. nvidia,function = "rsvd4";
  138. };
  139. spig {
  140. nvidia,pins = "spig", "spih";
  141. nvidia,function = "spi2_alt";
  142. };
  143. uaa {
  144. nvidia,pins = "uaa", "uab", "uda";
  145. nvidia,function = "ulpi";
  146. };
  147. uad {
  148. nvidia,pins = "uad";
  149. nvidia,function = "spdif";
  150. };
  151. uca {
  152. nvidia,pins = "uca", "ucb";
  153. nvidia,function = "uartc";
  154. };
  155. conf_ata {
  156. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  157. "cdev1", "cdev2", "dap1", "dap2", "dtf",
  158. "gma", "gmb", "gmc", "gmd", "gme",
  159. "gpu", "gpu7", "gpv", "i2cp", "pta",
  160. "rm", "sdio1", "slxk", "spdo", "uac",
  161. "uda";
  162. nvidia,pull = <0>;
  163. nvidia,tristate = <0>;
  164. };
  165. conf_ck32 {
  166. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  167. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  168. nvidia,pull = <0>;
  169. };
  170. conf_crtp {
  171. nvidia,pins = "crtp", "dap3", "dap4", "dtb",
  172. "dtc", "dte", "slxa", "slxc", "slxd",
  173. "spdi";
  174. nvidia,pull = <0>;
  175. nvidia,tristate = <1>;
  176. };
  177. conf_csus {
  178. nvidia,pins = "csus", "spia", "spib", "spid",
  179. "spif";
  180. nvidia,pull = <1>;
  181. nvidia,tristate = <1>;
  182. };
  183. conf_ddc {
  184. nvidia,pins = "ddc", "irrx", "irtx", "kbca",
  185. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  186. "spic", "spig", "uaa", "uab";
  187. nvidia,pull = <2>;
  188. nvidia,tristate = <0>;
  189. };
  190. conf_dta {
  191. nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
  192. "spie", "spih", "uad", "uca", "ucb";
  193. nvidia,pull = <2>;
  194. nvidia,tristate = <1>;
  195. };
  196. conf_hdint {
  197. nvidia,pins = "hdint", "ld0", "ld1", "ld2",
  198. "ld3", "ld4", "ld5", "ld6", "ld7",
  199. "ld8", "ld9", "ld10", "ld11", "ld12",
  200. "ld13", "ld14", "ld15", "ld16", "ld17",
  201. "ldc", "ldi", "lhs", "lsc0", "lspi",
  202. "lvs", "pmc";
  203. nvidia,tristate = <0>;
  204. };
  205. conf_lc {
  206. nvidia,pins = "lc", "ls";
  207. nvidia,pull = <2>;
  208. };
  209. conf_lcsn {
  210. nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
  211. "lm0", "lm1", "lpp", "lpw0", "lpw1",
  212. "lpw2", "lsc1", "lsck", "lsda", "lsdi",
  213. "lvp0", "lvp1", "sdb";
  214. nvidia,tristate = <1>;
  215. };
  216. conf_ld17_0 {
  217. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  218. "ld23_22";
  219. nvidia,pull = <1>;
  220. };
  221. };
  222. };
  223. i2s@70002800 {
  224. status = "okay";
  225. };
  226. serial@70006000 {
  227. status = "okay";
  228. clock-frequency = <216000000>;
  229. };
  230. serial@70006200 {
  231. status = "okay";
  232. clock-frequency = <216000000>;
  233. };
  234. i2c@7000c000 {
  235. status = "okay";
  236. clock-frequency = <400000>;
  237. alc5632: alc5632@1e {
  238. compatible = "realtek,alc5632";
  239. reg = <0x1e>;
  240. gpio-controller;
  241. #gpio-cells = <2>;
  242. };
  243. };
  244. i2c@7000c400 {
  245. status = "okay";
  246. clock-frequency = <400000>;
  247. };
  248. nvec {
  249. compatible = "nvidia,nvec";
  250. reg = <0x7000c500 0x100>;
  251. interrupts = <0 92 0x04>;
  252. #address-cells = <1>;
  253. #size-cells = <0>;
  254. clock-frequency = <80000>;
  255. request-gpios = <&gpio 170 0>; /* gpio PV2 */
  256. slave-addr = <138>;
  257. };
  258. i2c@7000d000 {
  259. status = "okay";
  260. clock-frequency = <400000>;
  261. pmic: tps6586x@34 {
  262. compatible = "ti,tps6586x";
  263. reg = <0x34>;
  264. interrupts = <0 86 0x4>;
  265. #gpio-cells = <2>;
  266. gpio-controller;
  267. sys-supply = <&p5valw_reg>;
  268. vin-sm0-supply = <&sys_reg>;
  269. vin-sm1-supply = <&sys_reg>;
  270. vin-sm2-supply = <&sys_reg>;
  271. vinldo01-supply = <&sm2_reg>;
  272. vinldo23-supply = <&sm2_reg>;
  273. vinldo4-supply = <&sm2_reg>;
  274. vinldo678-supply = <&sm2_reg>;
  275. vinldo9-supply = <&sm2_reg>;
  276. regulators {
  277. #address-cells = <1>;
  278. #size-cells = <0>;
  279. sys_reg: regulator@0 {
  280. reg = <0>;
  281. regulator-compatible = "sys";
  282. regulator-name = "vdd_sys";
  283. regulator-always-on;
  284. };
  285. regulator@1 {
  286. reg = <1>;
  287. regulator-compatible = "sm0";
  288. regulator-name = "+1.2vs_sm0,vdd_core";
  289. regulator-min-microvolt = <1200000>;
  290. regulator-max-microvolt = <1200000>;
  291. regulator-always-on;
  292. };
  293. regulator@2 {
  294. reg = <2>;
  295. regulator-compatible = "sm1";
  296. regulator-name = "+1.0vs_sm1,vdd_cpu";
  297. regulator-min-microvolt = <1000000>;
  298. regulator-max-microvolt = <1000000>;
  299. regulator-always-on;
  300. };
  301. sm2_reg: regulator@3 {
  302. reg = <3>;
  303. regulator-compatible = "sm2";
  304. regulator-name = "+3.7vs_sm2,vin_ldo*";
  305. regulator-min-microvolt = <3700000>;
  306. regulator-max-microvolt = <3700000>;
  307. regulator-always-on;
  308. };
  309. /* LDO0 is not connected to anything */
  310. regulator@5 {
  311. reg = <5>;
  312. regulator-compatible = "ldo1";
  313. regulator-name = "+1.1vs_ldo1,avdd_pll*";
  314. regulator-min-microvolt = <1100000>;
  315. regulator-max-microvolt = <1100000>;
  316. regulator-always-on;
  317. };
  318. regulator@6 {
  319. reg = <6>;
  320. regulator-compatible = "ldo2";
  321. regulator-name = "+1.2vs_ldo2,vdd_rtc";
  322. regulator-min-microvolt = <1200000>;
  323. regulator-max-microvolt = <1200000>;
  324. };
  325. regulator@7 {
  326. reg = <7>;
  327. regulator-compatible = "ldo3";
  328. regulator-name = "+3.3vs_ldo3,avdd_usb*";
  329. regulator-min-microvolt = <3300000>;
  330. regulator-max-microvolt = <3300000>;
  331. regulator-always-on;
  332. };
  333. regulator@8 {
  334. reg = <8>;
  335. regulator-compatible = "ldo4";
  336. regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
  337. regulator-min-microvolt = <1800000>;
  338. regulator-max-microvolt = <1800000>;
  339. regulator-always-on;
  340. };
  341. regulator@9 {
  342. reg = <9>;
  343. regulator-compatible = "ldo5";
  344. regulator-name = "+2.85vs_ldo5,vcore_mmc";
  345. regulator-min-microvolt = <2850000>;
  346. regulator-max-microvolt = <2850000>;
  347. regulator-always-on;
  348. };
  349. regulator@10 {
  350. reg = <10>;
  351. regulator-compatible = "ldo6";
  352. /*
  353. * Research indicates this should be
  354. * 1.8v; other boards that use this
  355. * rail for the same purpose need it
  356. * set to 1.8v. The schematic signal
  357. * name is incorrect; perhaps copied
  358. * from an incorrect NVIDIA reference.
  359. */
  360. regulator-name = "+2.85vs_ldo6,avdd_vdac";
  361. regulator-min-microvolt = <1800000>;
  362. regulator-max-microvolt = <1800000>;
  363. };
  364. regulator@11 {
  365. reg = <11>;
  366. regulator-compatible = "ldo7";
  367. regulator-name = "+3.3vs_ldo7,avdd_hdmi";
  368. regulator-min-microvolt = <3300000>;
  369. regulator-max-microvolt = <3300000>;
  370. };
  371. regulator@12 {
  372. reg = <12>;
  373. regulator-compatible = "ldo8";
  374. regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
  375. regulator-min-microvolt = <1800000>;
  376. regulator-max-microvolt = <1800000>;
  377. };
  378. regulator@13 {
  379. reg = <13>;
  380. regulator-compatible = "ldo9";
  381. regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
  382. regulator-min-microvolt = <2850000>;
  383. regulator-max-microvolt = <2850000>;
  384. regulator-always-on;
  385. };
  386. regulator@14 {
  387. reg = <14>;
  388. regulator-compatible = "ldo_rtc";
  389. regulator-name = "+3.3vs_rtc";
  390. regulator-min-microvolt = <3300000>;
  391. regulator-max-microvolt = <3300000>;
  392. regulator-always-on;
  393. };
  394. };
  395. };
  396. adt7461@4c {
  397. compatible = "adi,adt7461";
  398. reg = <0x4c>;
  399. };
  400. };
  401. pmc {
  402. nvidia,invert-interrupt;
  403. };
  404. usb@c5000000 {
  405. status = "okay";
  406. };
  407. usb@c5004000 {
  408. status = "okay";
  409. nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
  410. };
  411. usb@c5008000 {
  412. status = "okay";
  413. };
  414. sdhci@c8000000 {
  415. status = "okay";
  416. cd-gpios = <&gpio 173 0>; /* gpio PV5 */
  417. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  418. power-gpios = <&gpio 169 0>; /* gpio PV1 */
  419. bus-width = <4>;
  420. };
  421. sdhci@c8000600 {
  422. status = "okay";
  423. bus-width = <8>;
  424. };
  425. gpio-keys {
  426. compatible = "gpio-keys";
  427. power {
  428. label = "Power";
  429. gpios = <&gpio 79 1>; /* gpio PJ7, active low */
  430. linux,code = <116>; /* KEY_POWER */
  431. gpio-key,wakeup;
  432. };
  433. };
  434. gpio-leds {
  435. compatible = "gpio-leds";
  436. wifi {
  437. label = "wifi-led";
  438. gpios = <&gpio 24 0>; /* gpio PD0 */
  439. linux,default-trigger = "rfkill0";
  440. };
  441. };
  442. regulators {
  443. compatible = "simple-bus";
  444. #address-cells = <1>;
  445. #size-cells = <0>;
  446. p5valw_reg: regulator@0 {
  447. compatible = "regulator-fixed";
  448. reg = <0>;
  449. regulator-name = "+5valw";
  450. regulator-min-microvolt = <5000000>;
  451. regulator-max-microvolt = <5000000>;
  452. regulator-always-on;
  453. };
  454. };
  455. sound {
  456. compatible = "nvidia,tegra-audio-alc5632-paz00",
  457. "nvidia,tegra-audio-alc5632";
  458. nvidia,model = "Compal PAZ00";
  459. nvidia,audio-routing =
  460. "Int Spk", "SPKOUT",
  461. "Int Spk", "SPKOUTN",
  462. "Headset Mic", "MICBIAS1",
  463. "MIC1", "Headset Mic",
  464. "Headset Stereophone", "HPR",
  465. "Headset Stereophone", "HPL",
  466. "DMICDAT", "Digital Mic";
  467. nvidia,audio-codec = <&alc5632>;
  468. nvidia,i2s-controller = <&tegra_i2s1>;
  469. nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
  470. };
  471. };