xhci.c 60 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/irq.h>
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/slab.h>
  26. #include "xhci.h"
  27. #define DRIVER_AUTHOR "Sarah Sharp"
  28. #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  29. /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
  30. static int link_quirk;
  31. module_param(link_quirk, int, S_IRUGO | S_IWUSR);
  32. MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
  33. /* TODO: copied from ehci-hcd.c - can this be refactored? */
  34. /*
  35. * handshake - spin reading hc until handshake completes or fails
  36. * @ptr: address of hc register to be read
  37. * @mask: bits to look at in result of read
  38. * @done: value of those bits when handshake succeeds
  39. * @usec: timeout in microseconds
  40. *
  41. * Returns negative errno, or zero on success
  42. *
  43. * Success happens when the "mask" bits have the specified value (hardware
  44. * handshake done). There are two failure modes: "usec" have passed (major
  45. * hardware flakeout), or the register reads as all-ones (hardware removed).
  46. */
  47. static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
  48. u32 mask, u32 done, int usec)
  49. {
  50. u32 result;
  51. do {
  52. result = xhci_readl(xhci, ptr);
  53. if (result == ~(u32)0) /* card removed */
  54. return -ENODEV;
  55. result &= mask;
  56. if (result == done)
  57. return 0;
  58. udelay(1);
  59. usec--;
  60. } while (usec > 0);
  61. return -ETIMEDOUT;
  62. }
  63. /*
  64. * Disable interrupts and begin the xHCI halting process.
  65. */
  66. void xhci_quiesce(struct xhci_hcd *xhci)
  67. {
  68. u32 halted;
  69. u32 cmd;
  70. u32 mask;
  71. mask = ~(XHCI_IRQS);
  72. halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
  73. if (!halted)
  74. mask &= ~CMD_RUN;
  75. cmd = xhci_readl(xhci, &xhci->op_regs->command);
  76. cmd &= mask;
  77. xhci_writel(xhci, cmd, &xhci->op_regs->command);
  78. }
  79. /*
  80. * Force HC into halt state.
  81. *
  82. * Disable any IRQs and clear the run/stop bit.
  83. * HC will complete any current and actively pipelined transactions, and
  84. * should halt within 16 microframes of the run/stop bit being cleared.
  85. * Read HC Halted bit in the status register to see when the HC is finished.
  86. * XXX: shouldn't we set HC_STATE_HALT here somewhere?
  87. */
  88. int xhci_halt(struct xhci_hcd *xhci)
  89. {
  90. xhci_dbg(xhci, "// Halt the HC\n");
  91. xhci_quiesce(xhci);
  92. return handshake(xhci, &xhci->op_regs->status,
  93. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  94. }
  95. /*
  96. * Reset a halted HC, and set the internal HC state to HC_STATE_HALT.
  97. *
  98. * This resets pipelines, timers, counters, state machines, etc.
  99. * Transactions will be terminated immediately, and operational registers
  100. * will be set to their defaults.
  101. */
  102. int xhci_reset(struct xhci_hcd *xhci)
  103. {
  104. u32 command;
  105. u32 state;
  106. state = xhci_readl(xhci, &xhci->op_regs->status);
  107. if ((state & STS_HALT) == 0) {
  108. xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
  109. return 0;
  110. }
  111. xhci_dbg(xhci, "// Reset the HC\n");
  112. command = xhci_readl(xhci, &xhci->op_regs->command);
  113. command |= CMD_RESET;
  114. xhci_writel(xhci, command, &xhci->op_regs->command);
  115. /* XXX: Why does EHCI set this here? Shouldn't other code do this? */
  116. xhci_to_hcd(xhci)->state = HC_STATE_HALT;
  117. return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000);
  118. }
  119. #if 0
  120. /* Set up MSI-X table for entry 0 (may claim other entries later) */
  121. static int xhci_setup_msix(struct xhci_hcd *xhci)
  122. {
  123. int ret;
  124. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  125. xhci->msix_count = 0;
  126. /* XXX: did I do this right? ixgbe does kcalloc for more than one */
  127. xhci->msix_entries = kmalloc(sizeof(struct msix_entry), GFP_KERNEL);
  128. if (!xhci->msix_entries) {
  129. xhci_err(xhci, "Failed to allocate MSI-X entries\n");
  130. return -ENOMEM;
  131. }
  132. xhci->msix_entries[0].entry = 0;
  133. ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
  134. if (ret) {
  135. xhci_err(xhci, "Failed to enable MSI-X\n");
  136. goto free_entries;
  137. }
  138. /*
  139. * Pass the xhci pointer value as the request_irq "cookie".
  140. * If more irqs are added, this will need to be unique for each one.
  141. */
  142. ret = request_irq(xhci->msix_entries[0].vector, &xhci_irq, 0,
  143. "xHCI", xhci_to_hcd(xhci));
  144. if (ret) {
  145. xhci_err(xhci, "Failed to allocate MSI-X interrupt\n");
  146. goto disable_msix;
  147. }
  148. xhci_dbg(xhci, "Finished setting up MSI-X\n");
  149. return 0;
  150. disable_msix:
  151. pci_disable_msix(pdev);
  152. free_entries:
  153. kfree(xhci->msix_entries);
  154. xhci->msix_entries = NULL;
  155. return ret;
  156. }
  157. /* XXX: code duplication; can xhci_setup_msix call this? */
  158. /* Free any IRQs and disable MSI-X */
  159. static void xhci_cleanup_msix(struct xhci_hcd *xhci)
  160. {
  161. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  162. if (!xhci->msix_entries)
  163. return;
  164. free_irq(xhci->msix_entries[0].vector, xhci);
  165. pci_disable_msix(pdev);
  166. kfree(xhci->msix_entries);
  167. xhci->msix_entries = NULL;
  168. xhci_dbg(xhci, "Finished cleaning up MSI-X\n");
  169. }
  170. #endif
  171. /*
  172. * Initialize memory for HCD and xHC (one-time init).
  173. *
  174. * Program the PAGESIZE register, initialize the device context array, create
  175. * device contexts (?), set up a command ring segment (or two?), create event
  176. * ring (one for now).
  177. */
  178. int xhci_init(struct usb_hcd *hcd)
  179. {
  180. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  181. int retval = 0;
  182. xhci_dbg(xhci, "xhci_init\n");
  183. spin_lock_init(&xhci->lock);
  184. if (link_quirk) {
  185. xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
  186. xhci->quirks |= XHCI_LINK_TRB_QUIRK;
  187. } else {
  188. xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
  189. }
  190. retval = xhci_mem_init(xhci, GFP_KERNEL);
  191. xhci_dbg(xhci, "Finished xhci_init\n");
  192. return retval;
  193. }
  194. /*
  195. * Called in interrupt context when there might be work
  196. * queued on the event ring
  197. *
  198. * xhci->lock must be held by caller.
  199. */
  200. static void xhci_work(struct xhci_hcd *xhci)
  201. {
  202. u32 temp;
  203. u64 temp_64;
  204. /*
  205. * Clear the op reg interrupt status first,
  206. * so we can receive interrupts from other MSI-X interrupters.
  207. * Write 1 to clear the interrupt status.
  208. */
  209. temp = xhci_readl(xhci, &xhci->op_regs->status);
  210. temp |= STS_EINT;
  211. xhci_writel(xhci, temp, &xhci->op_regs->status);
  212. /* FIXME when MSI-X is supported and there are multiple vectors */
  213. /* Clear the MSI-X event interrupt status */
  214. /* Acknowledge the interrupt */
  215. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  216. temp |= 0x3;
  217. xhci_writel(xhci, temp, &xhci->ir_set->irq_pending);
  218. /* Flush posted writes */
  219. xhci_readl(xhci, &xhci->ir_set->irq_pending);
  220. if (xhci->xhc_state & XHCI_STATE_DYING)
  221. xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
  222. "Shouldn't IRQs be disabled?\n");
  223. else
  224. /* FIXME this should be a delayed service routine
  225. * that clears the EHB.
  226. */
  227. xhci_handle_event(xhci);
  228. /* Clear the event handler busy flag (RW1C); the event ring should be empty. */
  229. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  230. xhci_write_64(xhci, temp_64 | ERST_EHB, &xhci->ir_set->erst_dequeue);
  231. /* Flush posted writes -- FIXME is this necessary? */
  232. xhci_readl(xhci, &xhci->ir_set->irq_pending);
  233. }
  234. /*-------------------------------------------------------------------------*/
  235. /*
  236. * xHCI spec says we can get an interrupt, and if the HC has an error condition,
  237. * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
  238. * indicators of an event TRB error, but we check the status *first* to be safe.
  239. */
  240. irqreturn_t xhci_irq(struct usb_hcd *hcd)
  241. {
  242. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  243. u32 temp, temp2;
  244. union xhci_trb *trb;
  245. spin_lock(&xhci->lock);
  246. trb = xhci->event_ring->dequeue;
  247. /* Check if the xHC generated the interrupt, or the irq is shared */
  248. temp = xhci_readl(xhci, &xhci->op_regs->status);
  249. temp2 = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  250. if (temp == 0xffffffff && temp2 == 0xffffffff)
  251. goto hw_died;
  252. if (!(temp & STS_EINT) && !ER_IRQ_PENDING(temp2)) {
  253. spin_unlock(&xhci->lock);
  254. return IRQ_NONE;
  255. }
  256. xhci_dbg(xhci, "op reg status = %08x\n", temp);
  257. xhci_dbg(xhci, "ir set irq_pending = %08x\n", temp2);
  258. xhci_dbg(xhci, "Event ring dequeue ptr:\n");
  259. xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
  260. (unsigned long long)xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
  261. lower_32_bits(trb->link.segment_ptr),
  262. upper_32_bits(trb->link.segment_ptr),
  263. (unsigned int) trb->link.intr_target,
  264. (unsigned int) trb->link.control);
  265. if (temp & STS_FATAL) {
  266. xhci_warn(xhci, "WARNING: Host System Error\n");
  267. xhci_halt(xhci);
  268. hw_died:
  269. xhci_to_hcd(xhci)->state = HC_STATE_HALT;
  270. spin_unlock(&xhci->lock);
  271. return -ESHUTDOWN;
  272. }
  273. xhci_work(xhci);
  274. spin_unlock(&xhci->lock);
  275. return IRQ_HANDLED;
  276. }
  277. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  278. void xhci_event_ring_work(unsigned long arg)
  279. {
  280. unsigned long flags;
  281. int temp;
  282. u64 temp_64;
  283. struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
  284. int i, j;
  285. xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
  286. spin_lock_irqsave(&xhci->lock, flags);
  287. temp = xhci_readl(xhci, &xhci->op_regs->status);
  288. xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
  289. if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING)) {
  290. xhci_dbg(xhci, "HW died, polling stopped.\n");
  291. spin_unlock_irqrestore(&xhci->lock, flags);
  292. return;
  293. }
  294. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  295. xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
  296. xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
  297. xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
  298. xhci->error_bitmask = 0;
  299. xhci_dbg(xhci, "Event ring:\n");
  300. xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
  301. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  302. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  303. temp_64 &= ~ERST_PTR_MASK;
  304. xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
  305. xhci_dbg(xhci, "Command ring:\n");
  306. xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
  307. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  308. xhci_dbg_cmd_ptrs(xhci);
  309. for (i = 0; i < MAX_HC_SLOTS; ++i) {
  310. if (!xhci->devs[i])
  311. continue;
  312. for (j = 0; j < 31; ++j) {
  313. struct xhci_ring *ring = xhci->devs[i]->eps[j].ring;
  314. if (!ring)
  315. continue;
  316. xhci_dbg(xhci, "Dev %d endpoint ring %d:\n", i, j);
  317. xhci_debug_segment(xhci, ring->deq_seg);
  318. }
  319. }
  320. if (xhci->noops_submitted != NUM_TEST_NOOPS)
  321. if (xhci_setup_one_noop(xhci))
  322. xhci_ring_cmd_db(xhci);
  323. spin_unlock_irqrestore(&xhci->lock, flags);
  324. if (!xhci->zombie)
  325. mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
  326. else
  327. xhci_dbg(xhci, "Quit polling the event ring.\n");
  328. }
  329. #endif
  330. /*
  331. * Start the HC after it was halted.
  332. *
  333. * This function is called by the USB core when the HC driver is added.
  334. * Its opposite is xhci_stop().
  335. *
  336. * xhci_init() must be called once before this function can be called.
  337. * Reset the HC, enable device slot contexts, program DCBAAP, and
  338. * set command ring pointer and event ring pointer.
  339. *
  340. * Setup MSI-X vectors and enable interrupts.
  341. */
  342. int xhci_run(struct usb_hcd *hcd)
  343. {
  344. u32 temp;
  345. u64 temp_64;
  346. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  347. void (*doorbell)(struct xhci_hcd *) = NULL;
  348. hcd->uses_new_polling = 1;
  349. hcd->poll_rh = 0;
  350. xhci_dbg(xhci, "xhci_run\n");
  351. #if 0 /* FIXME: MSI not setup yet */
  352. /* Do this at the very last minute */
  353. ret = xhci_setup_msix(xhci);
  354. if (!ret)
  355. return ret;
  356. return -ENOSYS;
  357. #endif
  358. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  359. init_timer(&xhci->event_ring_timer);
  360. xhci->event_ring_timer.data = (unsigned long) xhci;
  361. xhci->event_ring_timer.function = xhci_event_ring_work;
  362. /* Poll the event ring */
  363. xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
  364. xhci->zombie = 0;
  365. xhci_dbg(xhci, "Setting event ring polling timer\n");
  366. add_timer(&xhci->event_ring_timer);
  367. #endif
  368. xhci_dbg(xhci, "Command ring memory map follows:\n");
  369. xhci_debug_ring(xhci, xhci->cmd_ring);
  370. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  371. xhci_dbg_cmd_ptrs(xhci);
  372. xhci_dbg(xhci, "ERST memory map follows:\n");
  373. xhci_dbg_erst(xhci, &xhci->erst);
  374. xhci_dbg(xhci, "Event ring:\n");
  375. xhci_debug_ring(xhci, xhci->event_ring);
  376. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  377. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  378. temp_64 &= ~ERST_PTR_MASK;
  379. xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
  380. xhci_dbg(xhci, "// Set the interrupt modulation register\n");
  381. temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
  382. temp &= ~ER_IRQ_INTERVAL_MASK;
  383. temp |= (u32) 160;
  384. xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
  385. /* Set the HCD state before we enable the irqs */
  386. hcd->state = HC_STATE_RUNNING;
  387. temp = xhci_readl(xhci, &xhci->op_regs->command);
  388. temp |= (CMD_EIE);
  389. xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
  390. temp);
  391. xhci_writel(xhci, temp, &xhci->op_regs->command);
  392. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  393. xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
  394. xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
  395. xhci_writel(xhci, ER_IRQ_ENABLE(temp),
  396. &xhci->ir_set->irq_pending);
  397. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  398. if (NUM_TEST_NOOPS > 0)
  399. doorbell = xhci_setup_one_noop(xhci);
  400. temp = xhci_readl(xhci, &xhci->op_regs->command);
  401. temp |= (CMD_RUN);
  402. xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
  403. temp);
  404. xhci_writel(xhci, temp, &xhci->op_regs->command);
  405. /* Flush PCI posted writes */
  406. temp = xhci_readl(xhci, &xhci->op_regs->command);
  407. xhci_dbg(xhci, "// @%p = 0x%x\n", &xhci->op_regs->command, temp);
  408. if (doorbell)
  409. (*doorbell)(xhci);
  410. xhci_dbg(xhci, "Finished xhci_run\n");
  411. return 0;
  412. }
  413. /*
  414. * Stop xHCI driver.
  415. *
  416. * This function is called by the USB core when the HC driver is removed.
  417. * Its opposite is xhci_run().
  418. *
  419. * Disable device contexts, disable IRQs, and quiesce the HC.
  420. * Reset the HC, finish any completed transactions, and cleanup memory.
  421. */
  422. void xhci_stop(struct usb_hcd *hcd)
  423. {
  424. u32 temp;
  425. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  426. spin_lock_irq(&xhci->lock);
  427. xhci_halt(xhci);
  428. xhci_reset(xhci);
  429. spin_unlock_irq(&xhci->lock);
  430. #if 0 /* No MSI yet */
  431. xhci_cleanup_msix(xhci);
  432. #endif
  433. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  434. /* Tell the event ring poll function not to reschedule */
  435. xhci->zombie = 1;
  436. del_timer_sync(&xhci->event_ring_timer);
  437. #endif
  438. xhci_dbg(xhci, "// Disabling event ring interrupts\n");
  439. temp = xhci_readl(xhci, &xhci->op_regs->status);
  440. xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
  441. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  442. xhci_writel(xhci, ER_IRQ_DISABLE(temp),
  443. &xhci->ir_set->irq_pending);
  444. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  445. xhci_dbg(xhci, "cleaning up memory\n");
  446. xhci_mem_cleanup(xhci);
  447. xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
  448. xhci_readl(xhci, &xhci->op_regs->status));
  449. }
  450. /*
  451. * Shutdown HC (not bus-specific)
  452. *
  453. * This is called when the machine is rebooting or halting. We assume that the
  454. * machine will be powered off, and the HC's internal state will be reset.
  455. * Don't bother to free memory.
  456. */
  457. void xhci_shutdown(struct usb_hcd *hcd)
  458. {
  459. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  460. spin_lock_irq(&xhci->lock);
  461. xhci_halt(xhci);
  462. spin_unlock_irq(&xhci->lock);
  463. #if 0
  464. xhci_cleanup_msix(xhci);
  465. #endif
  466. xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
  467. xhci_readl(xhci, &xhci->op_regs->status));
  468. }
  469. /*-------------------------------------------------------------------------*/
  470. /**
  471. * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
  472. * HCDs. Find the index for an endpoint given its descriptor. Use the return
  473. * value to right shift 1 for the bitmask.
  474. *
  475. * Index = (epnum * 2) + direction - 1,
  476. * where direction = 0 for OUT, 1 for IN.
  477. * For control endpoints, the IN index is used (OUT index is unused), so
  478. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  479. */
  480. unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
  481. {
  482. unsigned int index;
  483. if (usb_endpoint_xfer_control(desc))
  484. index = (unsigned int) (usb_endpoint_num(desc)*2);
  485. else
  486. index = (unsigned int) (usb_endpoint_num(desc)*2) +
  487. (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
  488. return index;
  489. }
  490. /* Find the flag for this endpoint (for use in the control context). Use the
  491. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  492. * bit 1, etc.
  493. */
  494. unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
  495. {
  496. return 1 << (xhci_get_endpoint_index(desc) + 1);
  497. }
  498. /* Find the flag for this endpoint (for use in the control context). Use the
  499. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  500. * bit 1, etc.
  501. */
  502. unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
  503. {
  504. return 1 << (ep_index + 1);
  505. }
  506. /* Compute the last valid endpoint context index. Basically, this is the
  507. * endpoint index plus one. For slot contexts with more than valid endpoint,
  508. * we find the most significant bit set in the added contexts flags.
  509. * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
  510. * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
  511. */
  512. unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
  513. {
  514. return fls(added_ctxs) - 1;
  515. }
  516. /* Returns 1 if the arguments are OK;
  517. * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
  518. */
  519. int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
  520. struct usb_host_endpoint *ep, int check_ep, const char *func) {
  521. if (!hcd || (check_ep && !ep) || !udev) {
  522. printk(KERN_DEBUG "xHCI %s called with invalid args\n",
  523. func);
  524. return -EINVAL;
  525. }
  526. if (!udev->parent) {
  527. printk(KERN_DEBUG "xHCI %s called for root hub\n",
  528. func);
  529. return 0;
  530. }
  531. if (!udev->slot_id) {
  532. printk(KERN_DEBUG "xHCI %s called with unaddressed device\n",
  533. func);
  534. return -EINVAL;
  535. }
  536. return 1;
  537. }
  538. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  539. struct usb_device *udev, struct xhci_command *command,
  540. bool ctx_change, bool must_succeed);
  541. /*
  542. * Full speed devices may have a max packet size greater than 8 bytes, but the
  543. * USB core doesn't know that until it reads the first 8 bytes of the
  544. * descriptor. If the usb_device's max packet size changes after that point,
  545. * we need to issue an evaluate context command and wait on it.
  546. */
  547. static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
  548. unsigned int ep_index, struct urb *urb)
  549. {
  550. struct xhci_container_ctx *in_ctx;
  551. struct xhci_container_ctx *out_ctx;
  552. struct xhci_input_control_ctx *ctrl_ctx;
  553. struct xhci_ep_ctx *ep_ctx;
  554. int max_packet_size;
  555. int hw_max_packet_size;
  556. int ret = 0;
  557. out_ctx = xhci->devs[slot_id]->out_ctx;
  558. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  559. hw_max_packet_size = MAX_PACKET_DECODED(ep_ctx->ep_info2);
  560. max_packet_size = urb->dev->ep0.desc.wMaxPacketSize;
  561. if (hw_max_packet_size != max_packet_size) {
  562. xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
  563. xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
  564. max_packet_size);
  565. xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
  566. hw_max_packet_size);
  567. xhci_dbg(xhci, "Issuing evaluate context command.\n");
  568. /* Set up the modified control endpoint 0 */
  569. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  570. xhci->devs[slot_id]->out_ctx, ep_index);
  571. in_ctx = xhci->devs[slot_id]->in_ctx;
  572. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  573. ep_ctx->ep_info2 &= ~MAX_PACKET_MASK;
  574. ep_ctx->ep_info2 |= MAX_PACKET(max_packet_size);
  575. /* Set up the input context flags for the command */
  576. /* FIXME: This won't work if a non-default control endpoint
  577. * changes max packet sizes.
  578. */
  579. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  580. ctrl_ctx->add_flags = EP0_FLAG;
  581. ctrl_ctx->drop_flags = 0;
  582. xhci_dbg(xhci, "Slot %d input context\n", slot_id);
  583. xhci_dbg_ctx(xhci, in_ctx, ep_index);
  584. xhci_dbg(xhci, "Slot %d output context\n", slot_id);
  585. xhci_dbg_ctx(xhci, out_ctx, ep_index);
  586. ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
  587. true, false);
  588. /* Clean up the input context for later use by bandwidth
  589. * functions.
  590. */
  591. ctrl_ctx->add_flags = SLOT_FLAG;
  592. }
  593. return ret;
  594. }
  595. /*
  596. * non-error returns are a promise to giveback() the urb later
  597. * we drop ownership so next owner (or urb unlink) can get it
  598. */
  599. int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
  600. {
  601. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  602. unsigned long flags;
  603. int ret = 0;
  604. unsigned int slot_id, ep_index;
  605. if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, true, __func__) <= 0)
  606. return -EINVAL;
  607. slot_id = urb->dev->slot_id;
  608. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  609. if (!xhci->devs || !xhci->devs[slot_id]) {
  610. if (!in_interrupt())
  611. dev_warn(&urb->dev->dev, "WARN: urb submitted for dev with no Slot ID\n");
  612. ret = -EINVAL;
  613. goto exit;
  614. }
  615. if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
  616. if (!in_interrupt())
  617. xhci_dbg(xhci, "urb submitted during PCI suspend\n");
  618. ret = -ESHUTDOWN;
  619. goto exit;
  620. }
  621. if (usb_endpoint_xfer_control(&urb->ep->desc)) {
  622. /* Check to see if the max packet size for the default control
  623. * endpoint changed during FS device enumeration
  624. */
  625. if (urb->dev->speed == USB_SPEED_FULL) {
  626. ret = xhci_check_maxpacket(xhci, slot_id,
  627. ep_index, urb);
  628. if (ret < 0)
  629. return ret;
  630. }
  631. /* We have a spinlock and interrupts disabled, so we must pass
  632. * atomic context to this function, which may allocate memory.
  633. */
  634. spin_lock_irqsave(&xhci->lock, flags);
  635. if (xhci->xhc_state & XHCI_STATE_DYING)
  636. goto dying;
  637. ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
  638. slot_id, ep_index);
  639. spin_unlock_irqrestore(&xhci->lock, flags);
  640. } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
  641. spin_lock_irqsave(&xhci->lock, flags);
  642. if (xhci->xhc_state & XHCI_STATE_DYING)
  643. goto dying;
  644. ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
  645. slot_id, ep_index);
  646. spin_unlock_irqrestore(&xhci->lock, flags);
  647. } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
  648. spin_lock_irqsave(&xhci->lock, flags);
  649. if (xhci->xhc_state & XHCI_STATE_DYING)
  650. goto dying;
  651. ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
  652. slot_id, ep_index);
  653. spin_unlock_irqrestore(&xhci->lock, flags);
  654. } else {
  655. ret = -EINVAL;
  656. }
  657. exit:
  658. return ret;
  659. dying:
  660. xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
  661. "non-responsive xHCI host.\n",
  662. urb->ep->desc.bEndpointAddress, urb);
  663. spin_unlock_irqrestore(&xhci->lock, flags);
  664. return -ESHUTDOWN;
  665. }
  666. /*
  667. * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
  668. * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
  669. * should pick up where it left off in the TD, unless a Set Transfer Ring
  670. * Dequeue Pointer is issued.
  671. *
  672. * The TRBs that make up the buffers for the canceled URB will be "removed" from
  673. * the ring. Since the ring is a contiguous structure, they can't be physically
  674. * removed. Instead, there are two options:
  675. *
  676. * 1) If the HC is in the middle of processing the URB to be canceled, we
  677. * simply move the ring's dequeue pointer past those TRBs using the Set
  678. * Transfer Ring Dequeue Pointer command. This will be the common case,
  679. * when drivers timeout on the last submitted URB and attempt to cancel.
  680. *
  681. * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
  682. * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
  683. * HC will need to invalidate the any TRBs it has cached after the stop
  684. * endpoint command, as noted in the xHCI 0.95 errata.
  685. *
  686. * 3) The TD may have completed by the time the Stop Endpoint Command
  687. * completes, so software needs to handle that case too.
  688. *
  689. * This function should protect against the TD enqueueing code ringing the
  690. * doorbell while this code is waiting for a Stop Endpoint command to complete.
  691. * It also needs to account for multiple cancellations on happening at the same
  692. * time for the same endpoint.
  693. *
  694. * Note that this function can be called in any context, or so says
  695. * usb_hcd_unlink_urb()
  696. */
  697. int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  698. {
  699. unsigned long flags;
  700. int ret;
  701. u32 temp;
  702. struct xhci_hcd *xhci;
  703. struct xhci_td *td;
  704. unsigned int ep_index;
  705. struct xhci_ring *ep_ring;
  706. struct xhci_virt_ep *ep;
  707. xhci = hcd_to_xhci(hcd);
  708. spin_lock_irqsave(&xhci->lock, flags);
  709. /* Make sure the URB hasn't completed or been unlinked already */
  710. ret = usb_hcd_check_unlink_urb(hcd, urb, status);
  711. if (ret || !urb->hcpriv)
  712. goto done;
  713. temp = xhci_readl(xhci, &xhci->op_regs->status);
  714. if (temp == 0xffffffff) {
  715. xhci_dbg(xhci, "HW died, freeing TD.\n");
  716. td = (struct xhci_td *) urb->hcpriv;
  717. usb_hcd_unlink_urb_from_ep(hcd, urb);
  718. spin_unlock_irqrestore(&xhci->lock, flags);
  719. usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, -ESHUTDOWN);
  720. kfree(td);
  721. return ret;
  722. }
  723. if (xhci->xhc_state & XHCI_STATE_DYING) {
  724. xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
  725. "non-responsive xHCI host.\n",
  726. urb->ep->desc.bEndpointAddress, urb);
  727. /* Let the stop endpoint command watchdog timer (which set this
  728. * state) finish cleaning up the endpoint TD lists. We must
  729. * have caught it in the middle of dropping a lock and giving
  730. * back an URB.
  731. */
  732. goto done;
  733. }
  734. xhci_dbg(xhci, "Cancel URB %p\n", urb);
  735. xhci_dbg(xhci, "Event ring:\n");
  736. xhci_debug_ring(xhci, xhci->event_ring);
  737. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  738. ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
  739. ep_ring = ep->ring;
  740. xhci_dbg(xhci, "Endpoint ring:\n");
  741. xhci_debug_ring(xhci, ep_ring);
  742. td = (struct xhci_td *) urb->hcpriv;
  743. list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
  744. /* Queue a stop endpoint command, but only if this is
  745. * the first cancellation to be handled.
  746. */
  747. if (!(ep->ep_state & EP_HALT_PENDING)) {
  748. ep->ep_state |= EP_HALT_PENDING;
  749. ep->stop_cmds_pending++;
  750. ep->stop_cmd_timer.expires = jiffies +
  751. XHCI_STOP_EP_CMD_TIMEOUT * HZ;
  752. add_timer(&ep->stop_cmd_timer);
  753. xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index);
  754. xhci_ring_cmd_db(xhci);
  755. }
  756. done:
  757. spin_unlock_irqrestore(&xhci->lock, flags);
  758. return ret;
  759. }
  760. /* Drop an endpoint from a new bandwidth configuration for this device.
  761. * Only one call to this function is allowed per endpoint before
  762. * check_bandwidth() or reset_bandwidth() must be called.
  763. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  764. * add the endpoint to the schedule with possibly new parameters denoted by a
  765. * different endpoint descriptor in usb_host_endpoint.
  766. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  767. * not allowed.
  768. *
  769. * The USB core will not allow URBs to be queued to an endpoint that is being
  770. * disabled, so there's no need for mutual exclusion to protect
  771. * the xhci->devs[slot_id] structure.
  772. */
  773. int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  774. struct usb_host_endpoint *ep)
  775. {
  776. struct xhci_hcd *xhci;
  777. struct xhci_container_ctx *in_ctx, *out_ctx;
  778. struct xhci_input_control_ctx *ctrl_ctx;
  779. struct xhci_slot_ctx *slot_ctx;
  780. unsigned int last_ctx;
  781. unsigned int ep_index;
  782. struct xhci_ep_ctx *ep_ctx;
  783. u32 drop_flag;
  784. u32 new_add_flags, new_drop_flags, new_slot_info;
  785. int ret;
  786. ret = xhci_check_args(hcd, udev, ep, 1, __func__);
  787. if (ret <= 0)
  788. return ret;
  789. xhci = hcd_to_xhci(hcd);
  790. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  791. drop_flag = xhci_get_endpoint_flag(&ep->desc);
  792. if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
  793. xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
  794. __func__, drop_flag);
  795. return 0;
  796. }
  797. if (!xhci->devs || !xhci->devs[udev->slot_id]) {
  798. xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
  799. __func__);
  800. return -EINVAL;
  801. }
  802. in_ctx = xhci->devs[udev->slot_id]->in_ctx;
  803. out_ctx = xhci->devs[udev->slot_id]->out_ctx;
  804. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  805. ep_index = xhci_get_endpoint_index(&ep->desc);
  806. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  807. /* If the HC already knows the endpoint is disabled,
  808. * or the HCD has noted it is disabled, ignore this request
  809. */
  810. if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED ||
  811. ctrl_ctx->drop_flags & xhci_get_endpoint_flag(&ep->desc)) {
  812. xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
  813. __func__, ep);
  814. return 0;
  815. }
  816. ctrl_ctx->drop_flags |= drop_flag;
  817. new_drop_flags = ctrl_ctx->drop_flags;
  818. ctrl_ctx->add_flags &= ~drop_flag;
  819. new_add_flags = ctrl_ctx->add_flags;
  820. last_ctx = xhci_last_valid_endpoint(ctrl_ctx->add_flags);
  821. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  822. /* Update the last valid endpoint context, if we deleted the last one */
  823. if ((slot_ctx->dev_info & LAST_CTX_MASK) > LAST_CTX(last_ctx)) {
  824. slot_ctx->dev_info &= ~LAST_CTX_MASK;
  825. slot_ctx->dev_info |= LAST_CTX(last_ctx);
  826. }
  827. new_slot_info = slot_ctx->dev_info;
  828. xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
  829. xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  830. (unsigned int) ep->desc.bEndpointAddress,
  831. udev->slot_id,
  832. (unsigned int) new_drop_flags,
  833. (unsigned int) new_add_flags,
  834. (unsigned int) new_slot_info);
  835. return 0;
  836. }
  837. /* Add an endpoint to a new possible bandwidth configuration for this device.
  838. * Only one call to this function is allowed per endpoint before
  839. * check_bandwidth() or reset_bandwidth() must be called.
  840. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  841. * add the endpoint to the schedule with possibly new parameters denoted by a
  842. * different endpoint descriptor in usb_host_endpoint.
  843. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  844. * not allowed.
  845. *
  846. * The USB core will not allow URBs to be queued to an endpoint until the
  847. * configuration or alt setting is installed in the device, so there's no need
  848. * for mutual exclusion to protect the xhci->devs[slot_id] structure.
  849. */
  850. int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  851. struct usb_host_endpoint *ep)
  852. {
  853. struct xhci_hcd *xhci;
  854. struct xhci_container_ctx *in_ctx, *out_ctx;
  855. unsigned int ep_index;
  856. struct xhci_ep_ctx *ep_ctx;
  857. struct xhci_slot_ctx *slot_ctx;
  858. struct xhci_input_control_ctx *ctrl_ctx;
  859. u32 added_ctxs;
  860. unsigned int last_ctx;
  861. u32 new_add_flags, new_drop_flags, new_slot_info;
  862. int ret = 0;
  863. ret = xhci_check_args(hcd, udev, ep, 1, __func__);
  864. if (ret <= 0) {
  865. /* So we won't queue a reset ep command for a root hub */
  866. ep->hcpriv = NULL;
  867. return ret;
  868. }
  869. xhci = hcd_to_xhci(hcd);
  870. added_ctxs = xhci_get_endpoint_flag(&ep->desc);
  871. last_ctx = xhci_last_valid_endpoint(added_ctxs);
  872. if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
  873. /* FIXME when we have to issue an evaluate endpoint command to
  874. * deal with ep0 max packet size changing once we get the
  875. * descriptors
  876. */
  877. xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
  878. __func__, added_ctxs);
  879. return 0;
  880. }
  881. if (!xhci->devs || !xhci->devs[udev->slot_id]) {
  882. xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
  883. __func__);
  884. return -EINVAL;
  885. }
  886. in_ctx = xhci->devs[udev->slot_id]->in_ctx;
  887. out_ctx = xhci->devs[udev->slot_id]->out_ctx;
  888. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  889. ep_index = xhci_get_endpoint_index(&ep->desc);
  890. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  891. /* If the HCD has already noted the endpoint is enabled,
  892. * ignore this request.
  893. */
  894. if (ctrl_ctx->add_flags & xhci_get_endpoint_flag(&ep->desc)) {
  895. xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
  896. __func__, ep);
  897. return 0;
  898. }
  899. /*
  900. * Configuration and alternate setting changes must be done in
  901. * process context, not interrupt context (or so documenation
  902. * for usb_set_interface() and usb_set_configuration() claim).
  903. */
  904. if (xhci_endpoint_init(xhci, xhci->devs[udev->slot_id],
  905. udev, ep, GFP_NOIO) < 0) {
  906. dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
  907. __func__, ep->desc.bEndpointAddress);
  908. return -ENOMEM;
  909. }
  910. ctrl_ctx->add_flags |= added_ctxs;
  911. new_add_flags = ctrl_ctx->add_flags;
  912. /* If xhci_endpoint_disable() was called for this endpoint, but the
  913. * xHC hasn't been notified yet through the check_bandwidth() call,
  914. * this re-adds a new state for the endpoint from the new endpoint
  915. * descriptors. We must drop and re-add this endpoint, so we leave the
  916. * drop flags alone.
  917. */
  918. new_drop_flags = ctrl_ctx->drop_flags;
  919. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  920. /* Update the last valid endpoint context, if we just added one past */
  921. if ((slot_ctx->dev_info & LAST_CTX_MASK) < LAST_CTX(last_ctx)) {
  922. slot_ctx->dev_info &= ~LAST_CTX_MASK;
  923. slot_ctx->dev_info |= LAST_CTX(last_ctx);
  924. }
  925. new_slot_info = slot_ctx->dev_info;
  926. /* Store the usb_device pointer for later use */
  927. ep->hcpriv = udev;
  928. xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  929. (unsigned int) ep->desc.bEndpointAddress,
  930. udev->slot_id,
  931. (unsigned int) new_drop_flags,
  932. (unsigned int) new_add_flags,
  933. (unsigned int) new_slot_info);
  934. return 0;
  935. }
  936. static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
  937. {
  938. struct xhci_input_control_ctx *ctrl_ctx;
  939. struct xhci_ep_ctx *ep_ctx;
  940. struct xhci_slot_ctx *slot_ctx;
  941. int i;
  942. /* When a device's add flag and drop flag are zero, any subsequent
  943. * configure endpoint command will leave that endpoint's state
  944. * untouched. Make sure we don't leave any old state in the input
  945. * endpoint contexts.
  946. */
  947. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  948. ctrl_ctx->drop_flags = 0;
  949. ctrl_ctx->add_flags = 0;
  950. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  951. slot_ctx->dev_info &= ~LAST_CTX_MASK;
  952. /* Endpoint 0 is always valid */
  953. slot_ctx->dev_info |= LAST_CTX(1);
  954. for (i = 1; i < 31; ++i) {
  955. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
  956. ep_ctx->ep_info = 0;
  957. ep_ctx->ep_info2 = 0;
  958. ep_ctx->deq = 0;
  959. ep_ctx->tx_info = 0;
  960. }
  961. }
  962. static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
  963. struct usb_device *udev, int *cmd_status)
  964. {
  965. int ret;
  966. switch (*cmd_status) {
  967. case COMP_ENOMEM:
  968. dev_warn(&udev->dev, "Not enough host controller resources "
  969. "for new device state.\n");
  970. ret = -ENOMEM;
  971. /* FIXME: can we allocate more resources for the HC? */
  972. break;
  973. case COMP_BW_ERR:
  974. dev_warn(&udev->dev, "Not enough bandwidth "
  975. "for new device state.\n");
  976. ret = -ENOSPC;
  977. /* FIXME: can we go back to the old state? */
  978. break;
  979. case COMP_TRB_ERR:
  980. /* the HCD set up something wrong */
  981. dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
  982. "add flag = 1, "
  983. "and endpoint is not disabled.\n");
  984. ret = -EINVAL;
  985. break;
  986. case COMP_SUCCESS:
  987. dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
  988. ret = 0;
  989. break;
  990. default:
  991. xhci_err(xhci, "ERROR: unexpected command completion "
  992. "code 0x%x.\n", *cmd_status);
  993. ret = -EINVAL;
  994. break;
  995. }
  996. return ret;
  997. }
  998. static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
  999. struct usb_device *udev, int *cmd_status)
  1000. {
  1001. int ret;
  1002. struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
  1003. switch (*cmd_status) {
  1004. case COMP_EINVAL:
  1005. dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
  1006. "context command.\n");
  1007. ret = -EINVAL;
  1008. break;
  1009. case COMP_EBADSLT:
  1010. dev_warn(&udev->dev, "WARN: slot not enabled for"
  1011. "evaluate context command.\n");
  1012. case COMP_CTX_STATE:
  1013. dev_warn(&udev->dev, "WARN: invalid context state for "
  1014. "evaluate context command.\n");
  1015. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
  1016. ret = -EINVAL;
  1017. break;
  1018. case COMP_SUCCESS:
  1019. dev_dbg(&udev->dev, "Successful evaluate context command\n");
  1020. ret = 0;
  1021. break;
  1022. default:
  1023. xhci_err(xhci, "ERROR: unexpected command completion "
  1024. "code 0x%x.\n", *cmd_status);
  1025. ret = -EINVAL;
  1026. break;
  1027. }
  1028. return ret;
  1029. }
  1030. /* Issue a configure endpoint command or evaluate context command
  1031. * and wait for it to finish.
  1032. */
  1033. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  1034. struct usb_device *udev,
  1035. struct xhci_command *command,
  1036. bool ctx_change, bool must_succeed)
  1037. {
  1038. int ret;
  1039. int timeleft;
  1040. unsigned long flags;
  1041. struct xhci_container_ctx *in_ctx;
  1042. struct completion *cmd_completion;
  1043. int *cmd_status;
  1044. struct xhci_virt_device *virt_dev;
  1045. spin_lock_irqsave(&xhci->lock, flags);
  1046. virt_dev = xhci->devs[udev->slot_id];
  1047. if (command) {
  1048. in_ctx = command->in_ctx;
  1049. cmd_completion = command->completion;
  1050. cmd_status = &command->status;
  1051. command->command_trb = xhci->cmd_ring->enqueue;
  1052. list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
  1053. } else {
  1054. in_ctx = virt_dev->in_ctx;
  1055. cmd_completion = &virt_dev->cmd_completion;
  1056. cmd_status = &virt_dev->cmd_status;
  1057. }
  1058. init_completion(cmd_completion);
  1059. if (!ctx_change)
  1060. ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
  1061. udev->slot_id, must_succeed);
  1062. else
  1063. ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
  1064. udev->slot_id);
  1065. if (ret < 0) {
  1066. if (command)
  1067. list_del(&command->cmd_list);
  1068. spin_unlock_irqrestore(&xhci->lock, flags);
  1069. xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
  1070. return -ENOMEM;
  1071. }
  1072. xhci_ring_cmd_db(xhci);
  1073. spin_unlock_irqrestore(&xhci->lock, flags);
  1074. /* Wait for the configure endpoint command to complete */
  1075. timeleft = wait_for_completion_interruptible_timeout(
  1076. cmd_completion,
  1077. USB_CTRL_SET_TIMEOUT);
  1078. if (timeleft <= 0) {
  1079. xhci_warn(xhci, "%s while waiting for %s command\n",
  1080. timeleft == 0 ? "Timeout" : "Signal",
  1081. ctx_change == 0 ?
  1082. "configure endpoint" :
  1083. "evaluate context");
  1084. /* FIXME cancel the configure endpoint command */
  1085. return -ETIME;
  1086. }
  1087. if (!ctx_change)
  1088. return xhci_configure_endpoint_result(xhci, udev, cmd_status);
  1089. return xhci_evaluate_context_result(xhci, udev, cmd_status);
  1090. }
  1091. /* Called after one or more calls to xhci_add_endpoint() or
  1092. * xhci_drop_endpoint(). If this call fails, the USB core is expected
  1093. * to call xhci_reset_bandwidth().
  1094. *
  1095. * Since we are in the middle of changing either configuration or
  1096. * installing a new alt setting, the USB core won't allow URBs to be
  1097. * enqueued for any endpoint on the old config or interface. Nothing
  1098. * else should be touching the xhci->devs[slot_id] structure, so we
  1099. * don't need to take the xhci->lock for manipulating that.
  1100. */
  1101. int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  1102. {
  1103. int i;
  1104. int ret = 0;
  1105. struct xhci_hcd *xhci;
  1106. struct xhci_virt_device *virt_dev;
  1107. struct xhci_input_control_ctx *ctrl_ctx;
  1108. struct xhci_slot_ctx *slot_ctx;
  1109. ret = xhci_check_args(hcd, udev, NULL, 0, __func__);
  1110. if (ret <= 0)
  1111. return ret;
  1112. xhci = hcd_to_xhci(hcd);
  1113. if (!udev->slot_id || !xhci->devs || !xhci->devs[udev->slot_id]) {
  1114. xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
  1115. __func__);
  1116. return -EINVAL;
  1117. }
  1118. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  1119. virt_dev = xhci->devs[udev->slot_id];
  1120. /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
  1121. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  1122. ctrl_ctx->add_flags |= SLOT_FLAG;
  1123. ctrl_ctx->add_flags &= ~EP0_FLAG;
  1124. ctrl_ctx->drop_flags &= ~SLOT_FLAG;
  1125. ctrl_ctx->drop_flags &= ~EP0_FLAG;
  1126. xhci_dbg(xhci, "New Input Control Context:\n");
  1127. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  1128. xhci_dbg_ctx(xhci, virt_dev->in_ctx,
  1129. LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
  1130. ret = xhci_configure_endpoint(xhci, udev, NULL,
  1131. false, false);
  1132. if (ret) {
  1133. /* Callee should call reset_bandwidth() */
  1134. return ret;
  1135. }
  1136. xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
  1137. xhci_dbg_ctx(xhci, virt_dev->out_ctx,
  1138. LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
  1139. xhci_zero_in_ctx(xhci, virt_dev);
  1140. /* Install new rings and free or cache any old rings */
  1141. for (i = 1; i < 31; ++i) {
  1142. if (!virt_dev->eps[i].new_ring)
  1143. continue;
  1144. /* Only cache or free the old ring if it exists.
  1145. * It may not if this is the first add of an endpoint.
  1146. */
  1147. if (virt_dev->eps[i].ring) {
  1148. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  1149. }
  1150. virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
  1151. virt_dev->eps[i].new_ring = NULL;
  1152. }
  1153. return ret;
  1154. }
  1155. void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  1156. {
  1157. struct xhci_hcd *xhci;
  1158. struct xhci_virt_device *virt_dev;
  1159. int i, ret;
  1160. ret = xhci_check_args(hcd, udev, NULL, 0, __func__);
  1161. if (ret <= 0)
  1162. return;
  1163. xhci = hcd_to_xhci(hcd);
  1164. if (!xhci->devs || !xhci->devs[udev->slot_id]) {
  1165. xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
  1166. __func__);
  1167. return;
  1168. }
  1169. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  1170. virt_dev = xhci->devs[udev->slot_id];
  1171. /* Free any rings allocated for added endpoints */
  1172. for (i = 0; i < 31; ++i) {
  1173. if (virt_dev->eps[i].new_ring) {
  1174. xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
  1175. virt_dev->eps[i].new_ring = NULL;
  1176. }
  1177. }
  1178. xhci_zero_in_ctx(xhci, virt_dev);
  1179. }
  1180. static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
  1181. struct xhci_container_ctx *in_ctx,
  1182. struct xhci_container_ctx *out_ctx,
  1183. u32 add_flags, u32 drop_flags)
  1184. {
  1185. struct xhci_input_control_ctx *ctrl_ctx;
  1186. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  1187. ctrl_ctx->add_flags = add_flags;
  1188. ctrl_ctx->drop_flags = drop_flags;
  1189. xhci_slot_copy(xhci, in_ctx, out_ctx);
  1190. ctrl_ctx->add_flags |= SLOT_FLAG;
  1191. xhci_dbg(xhci, "Input Context:\n");
  1192. xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
  1193. }
  1194. void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
  1195. unsigned int slot_id, unsigned int ep_index,
  1196. struct xhci_dequeue_state *deq_state)
  1197. {
  1198. struct xhci_container_ctx *in_ctx;
  1199. struct xhci_ep_ctx *ep_ctx;
  1200. u32 added_ctxs;
  1201. dma_addr_t addr;
  1202. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  1203. xhci->devs[slot_id]->out_ctx, ep_index);
  1204. in_ctx = xhci->devs[slot_id]->in_ctx;
  1205. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  1206. addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
  1207. deq_state->new_deq_ptr);
  1208. if (addr == 0) {
  1209. xhci_warn(xhci, "WARN Cannot submit config ep after "
  1210. "reset ep command\n");
  1211. xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
  1212. deq_state->new_deq_seg,
  1213. deq_state->new_deq_ptr);
  1214. return;
  1215. }
  1216. ep_ctx->deq = addr | deq_state->new_cycle_state;
  1217. added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
  1218. xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
  1219. xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
  1220. }
  1221. void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
  1222. struct usb_device *udev, unsigned int ep_index)
  1223. {
  1224. struct xhci_dequeue_state deq_state;
  1225. struct xhci_virt_ep *ep;
  1226. xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
  1227. ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  1228. /* We need to move the HW's dequeue pointer past this TD,
  1229. * or it will attempt to resend it on the next doorbell ring.
  1230. */
  1231. xhci_find_new_dequeue_state(xhci, udev->slot_id,
  1232. ep_index, ep->stopped_td,
  1233. &deq_state);
  1234. /* HW with the reset endpoint quirk will use the saved dequeue state to
  1235. * issue a configure endpoint command later.
  1236. */
  1237. if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
  1238. xhci_dbg(xhci, "Queueing new dequeue state\n");
  1239. xhci_queue_new_dequeue_state(xhci, udev->slot_id,
  1240. ep_index, &deq_state);
  1241. } else {
  1242. /* Better hope no one uses the input context between now and the
  1243. * reset endpoint completion!
  1244. */
  1245. xhci_dbg(xhci, "Setting up input context for "
  1246. "configure endpoint command\n");
  1247. xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
  1248. ep_index, &deq_state);
  1249. }
  1250. }
  1251. /* Deal with stalled endpoints. The core should have sent the control message
  1252. * to clear the halt condition. However, we need to make the xHCI hardware
  1253. * reset its sequence number, since a device will expect a sequence number of
  1254. * zero after the halt condition is cleared.
  1255. * Context: in_interrupt
  1256. */
  1257. void xhci_endpoint_reset(struct usb_hcd *hcd,
  1258. struct usb_host_endpoint *ep)
  1259. {
  1260. struct xhci_hcd *xhci;
  1261. struct usb_device *udev;
  1262. unsigned int ep_index;
  1263. unsigned long flags;
  1264. int ret;
  1265. struct xhci_virt_ep *virt_ep;
  1266. xhci = hcd_to_xhci(hcd);
  1267. udev = (struct usb_device *) ep->hcpriv;
  1268. /* Called with a root hub endpoint (or an endpoint that wasn't added
  1269. * with xhci_add_endpoint()
  1270. */
  1271. if (!ep->hcpriv)
  1272. return;
  1273. ep_index = xhci_get_endpoint_index(&ep->desc);
  1274. virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  1275. if (!virt_ep->stopped_td) {
  1276. xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
  1277. ep->desc.bEndpointAddress);
  1278. return;
  1279. }
  1280. if (usb_endpoint_xfer_control(&ep->desc)) {
  1281. xhci_dbg(xhci, "Control endpoint stall already handled.\n");
  1282. return;
  1283. }
  1284. xhci_dbg(xhci, "Queueing reset endpoint command\n");
  1285. spin_lock_irqsave(&xhci->lock, flags);
  1286. ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
  1287. /*
  1288. * Can't change the ring dequeue pointer until it's transitioned to the
  1289. * stopped state, which is only upon a successful reset endpoint
  1290. * command. Better hope that last command worked!
  1291. */
  1292. if (!ret) {
  1293. xhci_cleanup_stalled_ring(xhci, udev, ep_index);
  1294. kfree(virt_ep->stopped_td);
  1295. xhci_ring_cmd_db(xhci);
  1296. }
  1297. virt_ep->stopped_td = NULL;
  1298. virt_ep->stopped_trb = NULL;
  1299. spin_unlock_irqrestore(&xhci->lock, flags);
  1300. if (ret)
  1301. xhci_warn(xhci, "FIXME allocate a new ring segment\n");
  1302. }
  1303. /*
  1304. * This submits a Reset Device Command, which will set the device state to 0,
  1305. * set the device address to 0, and disable all the endpoints except the default
  1306. * control endpoint. The USB core should come back and call
  1307. * xhci_address_device(), and then re-set up the configuration. If this is
  1308. * called because of a usb_reset_and_verify_device(), then the old alternate
  1309. * settings will be re-installed through the normal bandwidth allocation
  1310. * functions.
  1311. *
  1312. * Wait for the Reset Device command to finish. Remove all structures
  1313. * associated with the endpoints that were disabled. Clear the input device
  1314. * structure? Cache the rings? Reset the control endpoint 0 max packet size?
  1315. */
  1316. int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
  1317. {
  1318. int ret, i;
  1319. unsigned long flags;
  1320. struct xhci_hcd *xhci;
  1321. unsigned int slot_id;
  1322. struct xhci_virt_device *virt_dev;
  1323. struct xhci_command *reset_device_cmd;
  1324. int timeleft;
  1325. int last_freed_endpoint;
  1326. ret = xhci_check_args(hcd, udev, NULL, 0, __func__);
  1327. if (ret <= 0)
  1328. return ret;
  1329. xhci = hcd_to_xhci(hcd);
  1330. slot_id = udev->slot_id;
  1331. virt_dev = xhci->devs[slot_id];
  1332. if (!virt_dev) {
  1333. xhci_dbg(xhci, "%s called with invalid slot ID %u\n",
  1334. __func__, slot_id);
  1335. return -EINVAL;
  1336. }
  1337. xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
  1338. /* Allocate the command structure that holds the struct completion.
  1339. * Assume we're in process context, since the normal device reset
  1340. * process has to wait for the device anyway. Storage devices are
  1341. * reset as part of error handling, so use GFP_NOIO instead of
  1342. * GFP_KERNEL.
  1343. */
  1344. reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  1345. if (!reset_device_cmd) {
  1346. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  1347. return -ENOMEM;
  1348. }
  1349. /* Attempt to submit the Reset Device command to the command ring */
  1350. spin_lock_irqsave(&xhci->lock, flags);
  1351. reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
  1352. list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
  1353. ret = xhci_queue_reset_device(xhci, slot_id);
  1354. if (ret) {
  1355. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1356. list_del(&reset_device_cmd->cmd_list);
  1357. spin_unlock_irqrestore(&xhci->lock, flags);
  1358. goto command_cleanup;
  1359. }
  1360. xhci_ring_cmd_db(xhci);
  1361. spin_unlock_irqrestore(&xhci->lock, flags);
  1362. /* Wait for the Reset Device command to finish */
  1363. timeleft = wait_for_completion_interruptible_timeout(
  1364. reset_device_cmd->completion,
  1365. USB_CTRL_SET_TIMEOUT);
  1366. if (timeleft <= 0) {
  1367. xhci_warn(xhci, "%s while waiting for reset device command\n",
  1368. timeleft == 0 ? "Timeout" : "Signal");
  1369. spin_lock_irqsave(&xhci->lock, flags);
  1370. /* The timeout might have raced with the event ring handler, so
  1371. * only delete from the list if the item isn't poisoned.
  1372. */
  1373. if (reset_device_cmd->cmd_list.next != LIST_POISON1)
  1374. list_del(&reset_device_cmd->cmd_list);
  1375. spin_unlock_irqrestore(&xhci->lock, flags);
  1376. ret = -ETIME;
  1377. goto command_cleanup;
  1378. }
  1379. /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
  1380. * unless we tried to reset a slot ID that wasn't enabled,
  1381. * or the device wasn't in the addressed or configured state.
  1382. */
  1383. ret = reset_device_cmd->status;
  1384. switch (ret) {
  1385. case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
  1386. case COMP_CTX_STATE: /* 0.96 completion code for same thing */
  1387. xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
  1388. slot_id,
  1389. xhci_get_slot_state(xhci, virt_dev->out_ctx));
  1390. xhci_info(xhci, "Not freeing device rings.\n");
  1391. /* Don't treat this as an error. May change my mind later. */
  1392. ret = 0;
  1393. goto command_cleanup;
  1394. case COMP_SUCCESS:
  1395. xhci_dbg(xhci, "Successful reset device command.\n");
  1396. break;
  1397. default:
  1398. if (xhci_is_vendor_info_code(xhci, ret))
  1399. break;
  1400. xhci_warn(xhci, "Unknown completion code %u for "
  1401. "reset device command.\n", ret);
  1402. ret = -EINVAL;
  1403. goto command_cleanup;
  1404. }
  1405. /* Everything but endpoint 0 is disabled, so free or cache the rings. */
  1406. last_freed_endpoint = 1;
  1407. for (i = 1; i < 31; ++i) {
  1408. if (!virt_dev->eps[i].ring)
  1409. continue;
  1410. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  1411. last_freed_endpoint = i;
  1412. }
  1413. xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
  1414. xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
  1415. ret = 0;
  1416. command_cleanup:
  1417. xhci_free_command(xhci, reset_device_cmd);
  1418. return ret;
  1419. }
  1420. /*
  1421. * At this point, the struct usb_device is about to go away, the device has
  1422. * disconnected, and all traffic has been stopped and the endpoints have been
  1423. * disabled. Free any HC data structures associated with that device.
  1424. */
  1425. void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
  1426. {
  1427. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1428. struct xhci_virt_device *virt_dev;
  1429. unsigned long flags;
  1430. u32 state;
  1431. int i;
  1432. if (udev->slot_id == 0)
  1433. return;
  1434. virt_dev = xhci->devs[udev->slot_id];
  1435. if (!virt_dev)
  1436. return;
  1437. /* Stop any wayward timer functions (which may grab the lock) */
  1438. for (i = 0; i < 31; ++i) {
  1439. virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
  1440. del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
  1441. }
  1442. spin_lock_irqsave(&xhci->lock, flags);
  1443. /* Don't disable the slot if the host controller is dead. */
  1444. state = xhci_readl(xhci, &xhci->op_regs->status);
  1445. if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING)) {
  1446. xhci_free_virt_device(xhci, udev->slot_id);
  1447. spin_unlock_irqrestore(&xhci->lock, flags);
  1448. return;
  1449. }
  1450. if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
  1451. spin_unlock_irqrestore(&xhci->lock, flags);
  1452. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1453. return;
  1454. }
  1455. xhci_ring_cmd_db(xhci);
  1456. spin_unlock_irqrestore(&xhci->lock, flags);
  1457. /*
  1458. * Event command completion handler will free any data structures
  1459. * associated with the slot. XXX Can free sleep?
  1460. */
  1461. }
  1462. /*
  1463. * Returns 0 if the xHC ran out of device slots, the Enable Slot command
  1464. * timed out, or allocating memory failed. Returns 1 on success.
  1465. */
  1466. int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
  1467. {
  1468. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1469. unsigned long flags;
  1470. int timeleft;
  1471. int ret;
  1472. spin_lock_irqsave(&xhci->lock, flags);
  1473. ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
  1474. if (ret) {
  1475. spin_unlock_irqrestore(&xhci->lock, flags);
  1476. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1477. return 0;
  1478. }
  1479. xhci_ring_cmd_db(xhci);
  1480. spin_unlock_irqrestore(&xhci->lock, flags);
  1481. /* XXX: how much time for xHC slot assignment? */
  1482. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  1483. USB_CTRL_SET_TIMEOUT);
  1484. if (timeleft <= 0) {
  1485. xhci_warn(xhci, "%s while waiting for a slot\n",
  1486. timeleft == 0 ? "Timeout" : "Signal");
  1487. /* FIXME cancel the enable slot request */
  1488. return 0;
  1489. }
  1490. if (!xhci->slot_id) {
  1491. xhci_err(xhci, "Error while assigning device slot ID\n");
  1492. return 0;
  1493. }
  1494. /* xhci_alloc_virt_device() does not touch rings; no need to lock */
  1495. if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_KERNEL)) {
  1496. /* Disable slot, if we can do it without mem alloc */
  1497. xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
  1498. spin_lock_irqsave(&xhci->lock, flags);
  1499. if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
  1500. xhci_ring_cmd_db(xhci);
  1501. spin_unlock_irqrestore(&xhci->lock, flags);
  1502. return 0;
  1503. }
  1504. udev->slot_id = xhci->slot_id;
  1505. /* Is this a LS or FS device under a HS hub? */
  1506. /* Hub or peripherial? */
  1507. return 1;
  1508. }
  1509. /*
  1510. * Issue an Address Device command (which will issue a SetAddress request to
  1511. * the device).
  1512. * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
  1513. * we should only issue and wait on one address command at the same time.
  1514. *
  1515. * We add one to the device address issued by the hardware because the USB core
  1516. * uses address 1 for the root hubs (even though they're not really devices).
  1517. */
  1518. int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
  1519. {
  1520. unsigned long flags;
  1521. int timeleft;
  1522. struct xhci_virt_device *virt_dev;
  1523. int ret = 0;
  1524. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1525. struct xhci_slot_ctx *slot_ctx;
  1526. struct xhci_input_control_ctx *ctrl_ctx;
  1527. u64 temp_64;
  1528. if (!udev->slot_id) {
  1529. xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
  1530. return -EINVAL;
  1531. }
  1532. virt_dev = xhci->devs[udev->slot_id];
  1533. /* If this is a Set Address to an unconfigured device, setup ep 0 */
  1534. if (!udev->config)
  1535. xhci_setup_addressable_virt_dev(xhci, udev);
  1536. /* Otherwise, assume the core has the device configured how it wants */
  1537. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  1538. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  1539. spin_lock_irqsave(&xhci->lock, flags);
  1540. ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
  1541. udev->slot_id);
  1542. if (ret) {
  1543. spin_unlock_irqrestore(&xhci->lock, flags);
  1544. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1545. return ret;
  1546. }
  1547. xhci_ring_cmd_db(xhci);
  1548. spin_unlock_irqrestore(&xhci->lock, flags);
  1549. /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
  1550. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  1551. USB_CTRL_SET_TIMEOUT);
  1552. /* FIXME: From section 4.3.4: "Software shall be responsible for timing
  1553. * the SetAddress() "recovery interval" required by USB and aborting the
  1554. * command on a timeout.
  1555. */
  1556. if (timeleft <= 0) {
  1557. xhci_warn(xhci, "%s while waiting for a slot\n",
  1558. timeleft == 0 ? "Timeout" : "Signal");
  1559. /* FIXME cancel the address device command */
  1560. return -ETIME;
  1561. }
  1562. switch (virt_dev->cmd_status) {
  1563. case COMP_CTX_STATE:
  1564. case COMP_EBADSLT:
  1565. xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
  1566. udev->slot_id);
  1567. ret = -EINVAL;
  1568. break;
  1569. case COMP_TX_ERR:
  1570. dev_warn(&udev->dev, "Device not responding to set address.\n");
  1571. ret = -EPROTO;
  1572. break;
  1573. case COMP_SUCCESS:
  1574. xhci_dbg(xhci, "Successful Address Device command\n");
  1575. break;
  1576. default:
  1577. xhci_err(xhci, "ERROR: unexpected command completion "
  1578. "code 0x%x.\n", virt_dev->cmd_status);
  1579. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  1580. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  1581. ret = -EINVAL;
  1582. break;
  1583. }
  1584. if (ret) {
  1585. return ret;
  1586. }
  1587. temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
  1588. xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
  1589. xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
  1590. udev->slot_id,
  1591. &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
  1592. (unsigned long long)
  1593. xhci->dcbaa->dev_context_ptrs[udev->slot_id]);
  1594. xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
  1595. (unsigned long long)virt_dev->out_ctx->dma);
  1596. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  1597. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  1598. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  1599. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  1600. /*
  1601. * USB core uses address 1 for the roothubs, so we add one to the
  1602. * address given back to us by the HC.
  1603. */
  1604. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
  1605. udev->devnum = (slot_ctx->dev_state & DEV_ADDR_MASK) + 1;
  1606. /* Zero the input context control for later use */
  1607. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  1608. ctrl_ctx->add_flags = 0;
  1609. ctrl_ctx->drop_flags = 0;
  1610. xhci_dbg(xhci, "Device address = %d\n", udev->devnum);
  1611. /* XXX Meh, not sure if anyone else but choose_address uses this. */
  1612. set_bit(udev->devnum, udev->bus->devmap.devicemap);
  1613. return 0;
  1614. }
  1615. /* Once a hub descriptor is fetched for a device, we need to update the xHC's
  1616. * internal data structures for the device.
  1617. */
  1618. int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
  1619. struct usb_tt *tt, gfp_t mem_flags)
  1620. {
  1621. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1622. struct xhci_virt_device *vdev;
  1623. struct xhci_command *config_cmd;
  1624. struct xhci_input_control_ctx *ctrl_ctx;
  1625. struct xhci_slot_ctx *slot_ctx;
  1626. unsigned long flags;
  1627. unsigned think_time;
  1628. int ret;
  1629. /* Ignore root hubs */
  1630. if (!hdev->parent)
  1631. return 0;
  1632. vdev = xhci->devs[hdev->slot_id];
  1633. if (!vdev) {
  1634. xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
  1635. return -EINVAL;
  1636. }
  1637. config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
  1638. if (!config_cmd) {
  1639. xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
  1640. return -ENOMEM;
  1641. }
  1642. spin_lock_irqsave(&xhci->lock, flags);
  1643. xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
  1644. ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
  1645. ctrl_ctx->add_flags |= SLOT_FLAG;
  1646. slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
  1647. slot_ctx->dev_info |= DEV_HUB;
  1648. if (tt->multi)
  1649. slot_ctx->dev_info |= DEV_MTT;
  1650. if (xhci->hci_version > 0x95) {
  1651. xhci_dbg(xhci, "xHCI version %x needs hub "
  1652. "TT think time and number of ports\n",
  1653. (unsigned int) xhci->hci_version);
  1654. slot_ctx->dev_info2 |= XHCI_MAX_PORTS(hdev->maxchild);
  1655. /* Set TT think time - convert from ns to FS bit times.
  1656. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  1657. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  1658. */
  1659. think_time = tt->think_time;
  1660. if (think_time != 0)
  1661. think_time = (think_time / 666) - 1;
  1662. slot_ctx->tt_info |= TT_THINK_TIME(think_time);
  1663. } else {
  1664. xhci_dbg(xhci, "xHCI version %x doesn't need hub "
  1665. "TT think time or number of ports\n",
  1666. (unsigned int) xhci->hci_version);
  1667. }
  1668. slot_ctx->dev_state = 0;
  1669. spin_unlock_irqrestore(&xhci->lock, flags);
  1670. xhci_dbg(xhci, "Set up %s for hub device.\n",
  1671. (xhci->hci_version > 0x95) ?
  1672. "configure endpoint" : "evaluate context");
  1673. xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
  1674. xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
  1675. /* Issue and wait for the configure endpoint or
  1676. * evaluate context command.
  1677. */
  1678. if (xhci->hci_version > 0x95)
  1679. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  1680. false, false);
  1681. else
  1682. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  1683. true, false);
  1684. xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
  1685. xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
  1686. xhci_free_command(xhci, config_cmd);
  1687. return ret;
  1688. }
  1689. int xhci_get_frame(struct usb_hcd *hcd)
  1690. {
  1691. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1692. /* EHCI mods by the periodic size. Why? */
  1693. return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
  1694. }
  1695. MODULE_DESCRIPTION(DRIVER_DESC);
  1696. MODULE_AUTHOR(DRIVER_AUTHOR);
  1697. MODULE_LICENSE("GPL");
  1698. static int __init xhci_hcd_init(void)
  1699. {
  1700. #ifdef CONFIG_PCI
  1701. int retval = 0;
  1702. retval = xhci_register_pci();
  1703. if (retval < 0) {
  1704. printk(KERN_DEBUG "Problem registering PCI driver.");
  1705. return retval;
  1706. }
  1707. #endif
  1708. /*
  1709. * Check the compiler generated sizes of structures that must be laid
  1710. * out in specific ways for hardware access.
  1711. */
  1712. BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
  1713. BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
  1714. BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
  1715. /* xhci_device_control has eight fields, and also
  1716. * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
  1717. */
  1718. BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
  1719. BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
  1720. BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
  1721. BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
  1722. BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
  1723. /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
  1724. BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
  1725. BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
  1726. return 0;
  1727. }
  1728. module_init(xhci_hcd_init);
  1729. static void __exit xhci_hcd_cleanup(void)
  1730. {
  1731. #ifdef CONFIG_PCI
  1732. xhci_unregister_pci();
  1733. #endif
  1734. }
  1735. module_exit(xhci_hcd_cleanup);